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- Log -----------------------------------------------------------------
commit 1fba55a9b62118ac102c161bb8efcd2ceed379a1
Author: Marc Schink <de...@za...>
Date:   Sat Jun 1 10:41:29 2024 +0200

    flash/nor/tcl: Fix memory leak of flash bank name
    
    Change-Id: I54cd1ee479a0570ae849a71be47c82eebd1ae454
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8303
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 720fb60a1..6ac932be7 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -1298,6 +1298,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
 	if (retval != ERROR_OK) {
 		LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT
 				"; usage: %s", driver_name, c->base, driver->usage);
+		free(c->name);
 		free(c);
 		return retval;
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/tcl.c | 1 +
 1 file changed, 1 insertion(+)


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commit 0a3217b8ff34043e6c59850e5d7667edf97ec447
Author: Marc Schink <de...@za...>
Date:   Sat May 25 18:57:10 2024 +0200

    tcl/board: Add config for NXP FRDM-KV31F
    
    Change-Id: I4d7cd1bcadd8159e4830107c2788708aef02add0
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8299
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/board/nxp/frdm-kv31f-jlink.cfg b/tcl/board/nxp/frdm-kv31f-jlink.cfg
new file mode 100644
index 000000000..e55a01cd7
--- /dev/null
+++ b/tcl/board/nxp/frdm-kv31f-jlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration file for NXP FRDM-KV31F development boards.
+#
+# This configuration file is only for FRDM-KV31F development boards with the
+# SEGGER J-Link OpenSDA firmware, see:
+# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/
+
+source [find interface/jlink.cfg]
+
+# Set working area size to 32 KiB.
+set WORKAREASIZE 0x8000
+
+# Set the chip name.
+set CHIPNAME kv31f
+
+transport select swd
+
+source [find target/kx.cfg]
+
+reset_config srst_only

commit 84126893ff9305060b7d481ebf50e8c7405d7eae
Author: Marc Schink <de...@za...>
Date:   Sat May 25 18:55:23 2024 +0200

    tcl/board: Add config for NXP FRDM-KV11Z
    
    Change-Id: I9cd497a085f8f9c7854ae3b96e60a73b3b050d0e
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8298
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/board/nxp/frdm-kv11z-jlink.cfg b/tcl/board/nxp/frdm-kv11z-jlink.cfg
new file mode 100644
index 000000000..725a37b9e
--- /dev/null
+++ b/tcl/board/nxp/frdm-kv11z-jlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration file for NXP FRDM-KV11Z development boards.
+#
+# This configuration file is only for FRDM-KV11Z development boards with the
+# SEGGER J-Link OpenSDA firmware, see:
+# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/
+
+source [find interface/jlink.cfg]
+
+# Set working area size to 16 KiB.
+set WORKAREASIZE 0x4000
+
+# Set the chip name.
+set CHIPNAME kv11z
+
+transport select swd
+
+source [find target/kx.cfg]
+
+reset_config srst_only

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/nxp/frdm-kv11z-jlink.cfg | 21 +++++++++++++++++++++
 tcl/board/nxp/frdm-kv31f-jlink.cfg | 21 +++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 tcl/board/nxp/frdm-kv11z-jlink.cfg
 create mode 100644 tcl/board/nxp/frdm-kv31f-jlink.cfg


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commit d382c95d57c0ad9ed2dcc83c95404babb7647708
Author: Parshintsev Anatoly <ana...@sy...>
Date:   Thu Jun 22 19:28:52 2023 +0300

    target/riscv: support for smp group manipulation
    
    this functionality allows to query if a target belongs to some smp group
    and to dynamically turn on/off smp-specific behavior
    
    Change-Id: I67bafb1817c621a38ae4a2f55e12e4143e992c4e
    Signed-off-by: Parshintsev Anatoly <ana...@sy...>
    Signed-off-by: Bernhard Rosenkränzer <be...@ba...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8296
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 87e3650b4..b782e0ba9 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11278,6 +11278,18 @@ When utilizing version 0.11 of the RISC-V Debug Specification,
 and DBUS registers, respectively.
 @end deffn
 
+@deffn {Command} {riscv smp} [on|off]
+Display, enable or disable SMP handling mode. This command is needed only if
+user wants to temporary @b{disable} SMP handling for an existing SMP group
+(see @code{aarch64 smp} for additional information). To define an SMP
+group the command @code{target smp} should be used.
+@end deffn
+
+@deffn {Command} {riscv smp_gdb} [core_id]
+Display/set the current core displayed in GDB. This is needed only if
+@code{riscv smp} was used.
+@end deffn
+
 @deffn {Command} {riscv use_bscan_tunnel} value
 Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the
 width of the DM transport TAP's instruction register to enable. Supply a
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 9cd4922d2..511a3c6c3 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -3049,6 +3049,9 @@ static const struct command_registration riscv_command_handlers[] = {
 		.usage = "",
 		.chain = semihosting_common_handlers
 	},
+	{
+		.chain = smp_command_handlers
+	},
 	COMMAND_REGISTRATION_DONE
 };
 

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi         | 12 ++++++++++++
 src/target/riscv/riscv.c |  3 +++
 2 files changed, 15 insertions(+)


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- Log -----------------------------------------------------------------
commit 2f8bb252ffb89cb2019f634230bc17b4dfccc75a
Author: Tim Newsome <ti...@si...>
Date:   Mon Sep 21 14:10:27 2020 -0700

    doc: Minimally describe the BSCAN tunnel interface.
    
    Add minimal documentation for the BSCAN tunnel interface.
    This is based on Tim Newsome <ti...@si...>'s work on
    the RISC-V fork.
    
    Change-Id: I5e0cd6972cb90649670249765e9bb30c2847eea6
    Signed-off-by: Tim Newsome <ti...@si...>
    Signed-off-by: Bernhard Rosenkränzer <be...@ba...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8297
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 5eef81e40..87e3650b4 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11279,8 +11279,22 @@ and DBUS registers, respectively.
 @end deffn
 
 @deffn {Command} {riscv use_bscan_tunnel} value
-Enable or disable use of a BSCAN tunnel to reach DM.  Supply the width of
-the DM transport TAP's instruction register to enable.  Supply a value of 0 to disable.
+Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the
+width of the DM transport TAP's instruction register to enable. Supply a
+value of 0 to disable.
+
+This BSCAN tunnel interface is specific to SiFive IP. Anybody may implement
+it, but currently there is no good documentation on it. In a nutshell, this
+feature scans USER4 into a Xilinx TAP to select the tunnel device (assuming
+hardware is present and it is hooked up to the Xilinx USER4 IR) and
+encapsulates a tunneled scan directive into a DR scan into the Xilinx TAP. A
+tunneled DR scan consists of:
+@enumerate
+@item 1 bit that selects IR when 0, or DR when 1
+@item 7 bits that encode the width of the desired tunneled scan
+@item A width+1 stream of bits for the tunneled TDI. The plus one is because there is a one-clock skew between TDI of Xilinx chain and TDO from tunneled chain.
+@item 3 bits of zero that the tunnel uses to go back to idle state.
+@end enumerate
 @end deffn
 
 @deffn {Command} {riscv set_ebreakm} on|off

commit 9623069e8090fbbf80250836e82feaecdb65233e
Author: Mark Featherston <ma...@em...>
Date:   Thu May 23 13:24:32 2024 -0700

    jtag/drivers/ftdi: Use command_print instead of LOG_USER for get_signal
    
    LOG_USER only outputs to user interfaces, but leaves no way to get the
    FTDI inputs over the RPC interface. Switch to command_print so this
    string goes to both logs and the RPC interface.
    
    Change-Id: I99024194b6687b88d354ef278aa25f372c862c22
    Signed-off-by: Mark Featherston <ma...@em...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8294
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>

diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c
index 58f83af59..661300506 100644
--- a/src/jtag/drivers/ftdi.c
+++ b/src/jtag/drivers/ftdi.c
@@ -852,7 +852,7 @@ COMMAND_HANDLER(ftdi_handle_get_signal_command)
 	uint16_t sig_data = 0;
 	sig = find_signal_by_name(CMD_ARGV[0]);
 	if (!sig) {
-		LOG_ERROR("interface configuration doesn't define signal '%s'", CMD_ARGV[0]);
+		command_print(CMD, "interface configuration doesn't define signal '%s'", CMD_ARGV[0]);
 		return ERROR_FAIL;
 	}
 
@@ -860,7 +860,7 @@ COMMAND_HANDLER(ftdi_handle_get_signal_command)
 	if (ret != ERROR_OK)
 		return ret;
 
-	LOG_USER("Signal %s = %#06x", sig->name, sig_data);
+	command_print(CMD, "%#06x", sig_data);
 
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi        | 18 ++++++++++++++++--
 src/jtag/drivers/ftdi.c |  4 ++--
 2 files changed, 18 insertions(+), 4 deletions(-)


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commit 72b39088ee1772a65e74004fdc096db09edf8c0c
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Apr 8 17:42:52 2024 +0200

    target: reset examine after assert_reset
    
    For some target, the API assert_reset() checks if the target has
    been examined, with target_was_examined(), to perform conditional
    operations like:
    - assert adapter's srst;
    - write some register to catch the reset vector;
    - invalidate the register cache.
    
    Targets created with -defer-examine gets the examine flag reset
    right before entering in their assert_reset(), disrupting the
    actions above.
    
    For targets created with -defer-examine, move the reset examine
    after the assert_reset().
    
    Change-Id: If96e7876dcace8905165115292deb93a3e45cb36
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8293
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/target.c b/src/target/target.c
index efc168903..7d4947a6e 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -5365,17 +5365,19 @@ COMMAND_HANDLER(handle_target_reset)
 		return ERROR_FAIL;
 	}
 
-	if (target->defer_examine)
-		target_reset_examined(target);
-
 	/* determine if we should halt or not. */
 	target->reset_halt = (a != 0);
 	/* When this happens - all workareas are invalid. */
 	target_free_all_working_areas_restore(target, 0);
 
 	/* do the assert */
-	if (n->value == NVP_ASSERT)
-		return target->type->assert_reset(target);
+	if (n->value == NVP_ASSERT) {
+		int retval = target->type->assert_reset(target);
+		if (target->defer_examine)
+			target_reset_examined(target);
+		return retval;
+	}
+
 	return target->type->deassert_reset(target);
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)


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commit b5e7118048250a4ffc589fd8b82a11de05132d23
Author: Noah Moroze <noa...@gm...>
Date:   Wed May 15 22:50:58 2024 -0400

    src/helper/startup: fix syntax errors
    
    The missing closing brackets were caught by tclint v0.2.5
    (https://github.com/nmoroze/tclint):
    
    ```
    tclint src/helper/startup.tcl | grep "syntax error"
    ```
    
    The improperly escaped backslash was caught by manual inspection during
    code review.
    
    Change-Id: I8cd44e58040d4627f6b2fc8b88ca8a930cda0ba6
    Signed-off-by: Noah Moroze <noa...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8282
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl
index 5a0d479f5..e6e76e68f 100644
--- a/src/helper/startup.tcl
+++ b/src/helper/startup.tcl
@@ -11,10 +11,10 @@ proc find {filename} {
 	if {[catch {ocd_find $filename} t]==0} {
 		return $t
 	}
-	if {[catch {ocd_find [string map {\ /} $filename} t]==0} {
+	if {[catch {ocd_find [string map {\\ /} $filename]} t]==0} {
 		return $t
 	}
-	if {[catch {ocd_find [string map {/ \\} $filename} t]==0} {
+	if {[catch {ocd_find [string map {/ \\} $filename]} t]==0} {
 		return $t
 	}
 	# make sure error message matches original input string

commit 7050cade9dcea77dd9882669ea97fddc6a8084d4
Author: Noah Moroze <noa...@gm...>
Date:   Wed May 15 22:49:23 2024 -0400

    tcl/chip/st/spear: fix syntax errors
    
    While the current jimtcl does not consider this an error, the Tcl
    dodekalogue states that strings terminate at the second double quote
    character (see https://www.tcl.tk/man/tcl/TclCmd/Tcl.htm#M8).
    
    These syntax errors were caught by tclint v0.2.5
    (https://github.com/nmoroze/tclint):
    
    ```
    tclint tcl/chip/st/spear/spear3xx_ddr.tcl | grep "syntax error"
    ```
    
    Change-Id: I2763d93095e3db7590644652f16b7b24939d6cae
    Signed-off-by: Noah Moroze <noa...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8281
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl
index 59925672d..06962215b 100644
--- a/tcl/chip/st/spear/spear3xx_ddr.tcl
+++ b/tcl/chip/st/spear/spear3xx_ddr.tcl
@@ -10,7 +10,7 @@
 
 proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
 	if { $ddr_chips != 1 && $ddr_chips != 2 } {
-		error "Only 1 or 2 DDR chips permitted. Wrong value "$ddr_chips
+		error "Only 1 or 2 DDR chips permitted. Wrong value $ddr_chips"
 	}
 
 	if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
@@ -21,7 +21,7 @@ proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
 	#	????? $ddr_chips
 	#	set ddr_size 0x?????
 	} else {
-		error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type
+		error "sp3xx_ddr_init: unrecognized DDR type $ddr_type"
 	}
 
 	# MPMC START

-----------------------------------------------------------------------

Summary of changes:
 src/helper/startup.tcl             | 4 ++--
 tcl/chip/st/spear/spear3xx_ddr.tcl | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)


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- Log -----------------------------------------------------------------
commit 223e3d8fe76d86f01111bbe37f83a19d719ac81a
Author: Noah Moroze <noa...@gm...>
Date:   Wed May 15 22:47:53 2024 -0400

    tcl/target/c100helper: fix syntax errors
    
    Fixes: 64d89d5ee1a5 ("tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change")
    
    These syntax errors were caught by tclint v0.2.5
    (https://github.com/nmoroze/tclint):
    
    ```
    tclint tcl/target/c100helper.tcl | grep "syntax error"
    ```
    
    Change-Id: I511c54353c4853560adca6b4852d48df2aade283
    Signed-off-by: Noah Moroze <noa...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8280
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index d1d3f258b..ba0e4fe0a 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -176,7 +176,7 @@ proc setupAmbaClk {} {
     mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
     # wait for PLL to lock
     echo "Waiting for Amba PLL to lock"
-    while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 }
+    while {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK == 0} { sleep 1 }
     # remove the internal PLL bypass
     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
     # remove PLL from BYPASS mode using MUX
@@ -250,7 +250,7 @@ proc setupArmClk {} {
     mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
     # wait for PLL to lock
     echo "Waiting for Amba PLL to lock"
-    while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 }
+    while {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK == 0} { sleep 1 }
     # remove the internal PLL bypass
     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
     # remove PLL from BYPASS mode using MUX

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/c100helper.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit eecba412cd8a6d515c925d87fe53e79881305517
Author: Noah Moroze <noa...@gm...>
Date:   Wed May 15 22:39:12 2024 -0400

    tcl/memory: fix syntax errors
    
    Using a command in an expression requires a bracketed command
    substitution.
    
    These syntax errors were caught by tclint v0.2.5
    (https://github.com/nmoroze/tclint):
    
    ```
    tclint tcl/memory.tcl | grep "syntax error"
    ```
    
    Change-Id: I510d46222f4fb02d6ef73121b231d5b2df77e5c0
    Signed-off-by: Noah Moroze <noa...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8279
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/memory.tcl b/tcl/memory.tcl
index b11174995..8b93b515e 100644
--- a/tcl/memory.tcl
+++ b/tcl/memory.tcl
@@ -66,10 +66,10 @@ proc iswithin { ADDRESS BASE LEN } {
 proc address_info { ADDRESS } {
 
     foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
-	if { info exists $WHERE } {
+	if { [info exists $WHERE] } {
 	    set lmt [set N_[set WHERE]]
 	    for { set region 0 } { $region < $lmt } { incr region } {
-		if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } {
+		if { [iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN)] } {
 		    return  "$WHERE $region";
 		}
 	    }

-----------------------------------------------------------------------

Summary of changes:
 tcl/memory.tcl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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commit c7c4d4d48c63c1048414779f633641ea4e9657c8
Author: Marc Schink <de...@za...>
Date:   Mon May 20 11:32:19 2024 +0200

    contrib: Drop 'coresight-trace.txt'
    
    This document is outdated and has broken text formatting. It also
    provides no useful information to users nor developers, at worst it
    causes confusion. For that reason, drop this file.
    
    Change-Id: Id5ee1f6e74d1a641c60d897f114bb97f5fd48e5b
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8292
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/coresight-trace.txt b/contrib/coresight-trace.txt
deleted file mode 100644
index 517119b6f..000000000
--- a/contrib/coresight-trace.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-+OpenOCD and CoreSight Tracing
-+
-Many recent ARM chips  (Using e..g. Cortex-M3 and
-Cortex-M4 cores) support CoreSight debug/trace.
-This note sketches an approach currently planned for those cores
-with OpenOCD.
-
- This tracing data can help debug and tune ARM software, but not
-all cores support tracing.  Some support more extensive tracing
-other cores with trace support +should be able to use the same
-approach and maybe some of the same analysis code.
-
-+the Cortex-M3 is assumed here to be the
-+core in use, for simplicity and to reflect current OpenOCD users.
-
-
-This note summarizes a software model to generate, collect, and
-analyze such trace data .  That is not fully implemented as of early
-January 2011, +and thus is not *yet* usable.
-+
-+
-+Some microcontroller cores support a low pin-count Single-wire trace,
-with a mode where +trace data is emitted (usually to a UART.  To use
-this mode, +SWD must be in use.
-+At this writing, OpenOCD SWD support is not yet complete either.
-
-(There are also multi-wire trace ports requiring more complex debug
-adapters than OpenOCD currently supports, and offering richer data.
-+
-+
-+* ENABLING involves activating  SWD and (single wire) trace.
-+
-+current expectations are that OpenOCD itself will handle enabling;
-activating single wire trace involves a debug adapter interaction, and
-collecting that trace data requires particular (re)wiring.
-+
-+* CONFIGURATION involves setting up ITM  and/or ETM modules to emit the
-+desired data from the Cortex core.  (This might include dumping
-+event counters printf-style messages; code profiling; and more.  Not all
-+cores offer the same trace capabilities.
-+
-+current expectations are that Tcl scripts will be used to configure these
-+modules for the desired tracing, by direct writes to registers.  In some
-+cases (as with RTOS event tracking and similar messaging, this might
-+be  augmented or replaced by user code running on the ARM core.
-+
-+COLLECTION involves reading that trace data, probably through UART, and
-+saving it in a useful format to analyse  For now, deferred analysis modes
-are assumed, not than real-time or interactive ones.
-+
-+
-+current expectations are to to dump data in text using contrib/itmdump.c
-+or derived tools, and to post-process it into reports.  Such reports might
-+include program messaging (such as application data streams via ITM, maybe
-+using printf type messaging; code coverage analysis or so forth.  Recent
-+versions of CMSIS software reserve some ITM codespace for RTOS  event
-tracing and include ITM messaging support.
-Clearly some of that data would be valuable for interactive debugging.
-+
-+Should someone get ambitious, GUI reports should be possible.  GNU tools
-+for simpler reports like gprof may be simpler to support at first.
-+In any case, OpenOCD is not currently GUI-oriented.  Accordingly, we now
-+expect any such graphics to come from postprocessing.
-
- measurements for RTOS event timings should also be easy to collect.
-+Examples include context and message switch times, as well as times
-for application interactions.
-+

-----------------------------------------------------------------------

Summary of changes:
 contrib/coresight-trace.txt | 68 ---------------------------------------------
 1 file changed, 68 deletions(-)
 delete mode 100644 contrib/coresight-trace.txt


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- Log -----------------------------------------------------------------
commit 71013521d7b195022616284aabc5e072a60c52bf
Author: Antonio Borneo <bor...@gm...>
Date:   Fri May 3 23:04:46 2024 +0200

    server: gdb: respect command gdb_report_register_access_error
    
    Commit 236c54c94a53 ("server/gdb_server.c: support unavailable
    registers") correctly returns a string of 'x' when the register is
    not available in the current target.
    
    While implementing this, it incorrectly drops the pre-existing
    feature of optionally ignoring errors while reading a register.
    This feature has a real use case documented in the OpenOCD manual
    in chapter 'Using GDB as a non-intrusive memory inspector', where
    GDB attaches to a target without halting it. For targets that need
    to be halted to read its registers, we need to hack the values of
    the registers returned to GDB; either returning 'xxxx' or an error
    causes GDB to drop the connection.
    
    Re-add the check on 'gdb_report_register_access_error' to keep the
    pre-existing behavior when a register error has to be ignored:
    - return a string of '0';
    - drop a debug message.
    
    Change-Id: Ie65c92f259f92502e688914f334655b635874179
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: 236c54c94a53 ("server/gdb_server.c: support unavailable registers")
    Reviewed-on: https://review.openocd.org/c/openocd/+/8228
    Tested-by: jenkins

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 5052bf43b..7c2f41e41 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1233,6 +1233,8 @@ static int gdb_get_reg_value_as_str(struct target *target, char *tstr, struct re
 			tstr[len] = '\0';
 			return ERROR_OK;
 	}
+	memset(tstr, '0', len);
+	tstr[len] = '\0';
 	return ERROR_FAIL;
 }
 
@@ -1277,7 +1279,9 @@ static int gdb_get_registers_packet(struct connection *connection,
 	for (i = 0; i < reg_list_size; i++) {
 		if (!reg_list[i] || reg_list[i]->exist == false || reg_list[i]->hidden)
 			continue;
-		if (gdb_get_reg_value_as_str(target, reg_packet_p, reg_list[i]) != ERROR_OK) {
+		retval = gdb_get_reg_value_as_str(target, reg_packet_p, reg_list[i]);
+		if (retval != ERROR_OK && gdb_report_register_access_error) {
+			LOG_DEBUG("Couldn't get register %s.", reg_list[i]->name);
 			free(reg_packet);
 			free(reg_list);
 			return gdb_error(connection, retval);
@@ -1395,7 +1399,9 @@ static int gdb_get_register_packet(struct connection *connection,
 
 	reg_packet = calloc(DIV_ROUND_UP(reg_list[reg_num]->size, 8) * 2 + 1, 1); /* plus one for string termination null */
 
-	if (gdb_get_reg_value_as_str(target, reg_packet, reg_list[reg_num]) != ERROR_OK) {
+	retval = gdb_get_reg_value_as_str(target, reg_packet, reg_list[reg_num]);
+	if (retval != ERROR_OK && gdb_report_register_access_error) {
+		LOG_DEBUG("Couldn't get register %s.", reg_list[reg_num]->name);
 		free(reg_packet);
 		free(reg_list);
 		return gdb_error(connection, retval);

-----------------------------------------------------------------------

Summary of changes:
 src/server/gdb_server.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)


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commit 2c8376b79d104a855bd3a559e59edf330309bcad
Author: Ian Thompson <ia...@ca...>
Date:   Wed Jan 31 15:14:25 2024 -0800

    target/xtensa: avoid IHI for writes to non-executable memory
    
    For MPU configs, determine memory access rights
    by probing protection TLB.  Issuing IHI without execute
    permissions can trigger an exception.
    
    No new clang static analyzer warnings.
    
    Change-Id: Iea8eab5c2113df3f954285c3b9a79e96d41aa941
    Signed-off-by: Ian Thompson <ia...@ca...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8080
    Reviewed-by: Erhan Kurubas <erh...@es...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index fb7748aa2..f7c82efed 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -158,6 +158,12 @@
 #define XT_INS_RFWU(X) (XT_ISBE(X) ? 0x005300 << 8 : 0x003500)
 #define XT_INS_RFWO_RFWU_MASK(X)   (XT_ISBE(X) ? 0xFFFFFF << 8 : 0xFFFFFF)
 
+/* Read Protection TLB Entry Info */
+#define XT_INS_PPTLB(X, S, T) _XT_INS_FORMAT_RRR(X, 0x500000, ((S) << 4) | (T), 0xD)
+
+#define XT_TLB1_ACC_SHIFT		8
+#define XT_TLB1_ACC_MSK			0xF
+
 #define XT_WATCHPOINTS_NUM_MAX  2
 
 /* Special register number macro for DDR, PS, WB, A3, A4 registers.
@@ -298,6 +304,27 @@ enum xtensa_mem_region_type {
 	XTENSA_MEM_REGS_NUM
 };
 
+/**
+ * Types of access rights for MPU option
+ * The first block is kernel RWX ARs; the second block is user rwx ARs.
+ */
+enum xtensa_mpu_access_type {
+	XTENSA_ACC_00X_000 = 0x2,
+	XTENSA_ACC_000_00X,
+	XTENSA_ACC_R00_000,
+	XTENSA_ACC_R0X_000,
+	XTENSA_ACC_RW0_000,
+	XTENSA_ACC_RWX_000,
+	XTENSA_ACC_0W0_0W0,
+	XTENSA_ACC_RW0_RWX,
+	XTENSA_ACC_RW0_R00,
+	XTENSA_ACC_RWX_R0X,
+	XTENSA_ACC_R00_R00,
+	XTENSA_ACC_R0X_R0X,
+	XTENSA_ACC_RW0_RW0,
+	XTENSA_ACC_RWX_RWX
+};
+
 /* Register definition as union for list allocation */
 union xtensa_reg_val_u {
 	xtensa_reg_val_t val;
@@ -521,6 +548,44 @@ static void xtensa_queue_exec_ins_wide(struct xtensa *xtensa, uint8_t *ops, uint
 	}
 }
 
+/* NOTE: Assumes A3 has already been saved and marked dirty; A3 will be clobbered */
+static inline bool xtensa_region_ar_exec(struct target *target, target_addr_t start, target_addr_t end)
+{
+	struct xtensa *xtensa = target_to_xtensa(target);
+	if (xtensa->core_config->mpu.enabled) {
+		/* For cores with the MPU option, issue PPTLB on start and end addresses.
+		 * Parse access rights field, and confirm both have execute permissions.
+		 */
+		for (int i = 0; i <= 1; i++) {
+			uint32_t at, acc;
+			uint8_t at_buf[4];
+			bool exec_acc;
+			target_addr_t addr = i ? end : start;
+			xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addr);
+			xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
+			xtensa_queue_exec_ins(xtensa, XT_INS_PPTLB(xtensa, XT_REG_A3, XT_REG_A3));
+			xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
+			xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, at_buf);
+			int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
+			if (res != ERROR_OK)
+				LOG_TARGET_ERROR(target, "Error queuing PPTLB: %d", res);
+			res = xtensa_core_status_check(target);
+			if (res != ERROR_OK)
+				LOG_TARGET_ERROR(target, "Error issuing PPTLB: %d", res);
+			at = buf_get_u32(at_buf, 0, 32);
+			acc = (at >> XT_TLB1_ACC_SHIFT) & XT_TLB1_ACC_MSK;
+			exec_acc = ((acc == XTENSA_ACC_00X_000) || (acc == XTENSA_ACC_R0X_000) ||
+						(acc == XTENSA_ACC_RWX_000) || (acc == XTENSA_ACC_RWX_R0X) ||
+						(acc == XTENSA_ACC_R0X_R0X) || (acc == XTENSA_ACC_RWX_RWX));
+			LOG_TARGET_DEBUG(target, "PPTLB(" TARGET_ADDR_FMT ") -> 0x%08" PRIx32 " exec_acc %d",
+				addr, at, exec_acc);
+			if (!exec_acc)
+				return false;
+		}
+	}
+	return true;
+}
+
 static int xtensa_queue_pwr_reg_write(struct xtensa *xtensa, unsigned int reg, uint32_t data)
 {
 	struct xtensa_debug_module *dm = &xtensa->dbg_mod;
@@ -2176,11 +2241,13 @@ int xtensa_write_memory(struct target *target,
 		}
 	} else {
 		/* Invalidate ICACHE, writeback DCACHE if present */
-		uint32_t issue_ihi = xtensa_is_icacheable(xtensa, address);
-		uint32_t issue_dhwb = xtensa_is_dcacheable(xtensa, address);
-		if (issue_ihi || issue_dhwb) {
+		bool issue_ihi = xtensa_is_icacheable(xtensa, address) &&
+						 xtensa_region_ar_exec(target, addrstart_al, addrend_al);
+		bool issue_dhwbi = xtensa_is_dcacheable(xtensa, address);
+		LOG_TARGET_DEBUG(target, "Cache OPs: IHI %d, DHWBI %d", issue_ihi, issue_dhwbi);
+		if (issue_ihi || issue_dhwbi) {
 			uint32_t ilinesize = issue_ihi ?  xtensa->core_config->icache.line_size : UINT32_MAX;
-			uint32_t dlinesize = issue_dhwb ? xtensa->core_config->dcache.line_size : UINT32_MAX;
+			uint32_t dlinesize = issue_dhwbi ? xtensa->core_config->dcache.line_size : UINT32_MAX;
 			uint32_t linesize = MIN(ilinesize, dlinesize);
 			uint32_t off = 0;
 			adr = addrstart_al;
@@ -2193,7 +2260,7 @@ int xtensa_write_memory(struct target *target,
 				}
 				if (issue_ihi)
 					xtensa_queue_exec_ins(xtensa, XT_INS_IHI(xtensa, XT_REG_A3, off));
-				if (issue_dhwb)
+				if (issue_dhwbi)
 					xtensa_queue_exec_ins(xtensa, XT_INS_DHWBI(xtensa, XT_REG_A3, off));
 				off += linesize;
 				if (off > 1020) {
@@ -2205,7 +2272,11 @@ int xtensa_write_memory(struct target *target,
 
 			/* Execute cache WB/INV instructions */
 			res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
-			xtensa_core_status_check(target);
+			if (res != ERROR_OK)
+				LOG_TARGET_ERROR(target,
+					"Error queuing cache writeback/invaldate instruction(s): %d",
+					res);
+			res = xtensa_core_status_check(target);
 			if (res != ERROR_OK)
 				LOG_TARGET_ERROR(target,
 					"Error issuing cache writeback/invaldate instruction(s): %d",
@@ -2367,7 +2438,8 @@ int xtensa_poll(struct target *target)
 static int xtensa_update_instruction(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
 {
 	struct xtensa *xtensa = target_to_xtensa(target);
-	unsigned int issue_ihi = xtensa_is_icacheable(xtensa, address);
+	unsigned int issue_ihi = xtensa_is_icacheable(xtensa, address) &&
+							 xtensa_region_ar_exec(target, address, address + size);
 	unsigned int issue_dhwbi = xtensa_is_dcacheable(xtensa, address);
 	uint32_t icache_line_size = issue_ihi ? xtensa->core_config->icache.line_size : UINT32_MAX;
 	uint32_t dcache_line_size = issue_dhwbi ? xtensa->core_config->dcache.line_size : UINT32_MAX;
@@ -2385,7 +2457,8 @@ static int xtensa_update_instruction(struct target *target, target_addr_t addres
 		/* Write start address to A3 and invalidate */
 		xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, address);
 		xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
-		LOG_TARGET_DEBUG(target, "DHWBI, IHI for address "TARGET_ADDR_FMT, address);
+		LOG_TARGET_DEBUG(target, "IHI %d, DHWBI %d for address " TARGET_ADDR_FMT,
+			issue_ihi, issue_dhwbi, address);
 		if (issue_dhwbi) {
 			xtensa_queue_exec_ins(xtensa, XT_INS_DHWBI(xtensa, XT_REG_A3, 0));
 			if (!same_dc_line) {

-----------------------------------------------------------------------

Summary of changes:
 src/target/xtensa/xtensa.c | 89 +++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 81 insertions(+), 8 deletions(-)


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- Log -----------------------------------------------------------------
commit 22ddf62d759b10a89e9c4c3f3929a66c9d72572d
Author: Parshintsev Anatoly <ana...@sy...>
Date:   Fri May 3 00:28:33 2024 +0300

    gdb_server: enable keep-alive packets for qCRC packet
    
    Change-Id: Ia384179bb83ad6b70bf385cc9d575e9ec58f76c7
    Signed-off-by: Parshintsev Anatoly <ana...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8227
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index c1ee4aa2a..dfd7cd520 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2845,7 +2845,9 @@ static int gdb_query_packet(struct connection *connection,
 
 			len = strtoul(separator + 1, NULL, 16);
 
+			gdb_connection->output_flag = GDB_OUTPUT_NOTIF;
 			retval = target_checksum_memory(target, addr, len, &checksum);
+			gdb_connection->output_flag = GDB_OUTPUT_NO;
 
 			if (retval == ERROR_OK) {
 				snprintf(gdb_reply, 10, "C%8.8" PRIx32 "", checksum);

-----------------------------------------------------------------------

Summary of changes:
 src/server/gdb_server.c | 2 ++
 1 file changed, 2 insertions(+)


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- Log -----------------------------------------------------------------
commit 126d8a0972ab6031588eb2f0e1fc3957bd3ccc6b
Author: Antonio Borneo <bor...@gm...>
Date:   Sat May 4 19:13:51 2024 +0200

    cortex_a: drop cortex_a_dap_write_memap_register_u32()
    
    Historically, the function cortex_a_dap_write_memap_register_u32()
    was used to discriminate the register write in APB-AP CPU debug
    against the complex memory access in AHB-AP memory bus.
    
    It has no sense to keep the function and its comment.
    Plus, by forcing atomic write it impacts the debug performance.
    
    Drop it!
    A further rework to enqueue sequence of atomic writes is needed.
    
    Change-Id: I2f5e9015f0e27fa5a6d8337a1ae25e753e2e1d26
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8231
    Reviewed-by: Oleksij Rempel <li...@re...>
    Tested-by: jenkins

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index a23540463..2de77c960 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -314,19 +314,6 @@ static int cortex_a_exec_opcode(struct target *target,
 	return retval;
 }
 
-/* Write to memory mapped registers directly with no cache or mmu handling */
-static int cortex_a_dap_write_memap_register_u32(struct target *target,
-	uint32_t address,
-	uint32_t value)
-{
-	int retval;
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-
-	retval = mem_ap_write_atomic_u32(armv7a->debug_ap, address, value);
-
-	return retval;
-}
-
 /*
  * Cortex-A implementation of Debug Programmer's Model
  *
@@ -611,11 +598,11 @@ static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 	LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
 		(unsigned) vr, (unsigned) cr);
 
-	retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
+	retval = mem_ap_write_atomic_u32(a->armv7a_common.debug_ap,
 			vr, addr);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
+	retval = mem_ap_write_atomic_u32(a->armv7a_common.debug_ap,
 			cr, control);
 	return retval;
 }
@@ -641,7 +628,7 @@ static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
 	LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
 
 	/* clear control register */
-	return cortex_a_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
+	return mem_ap_write_atomic_u32(a->armv7a_common.debug_ap, cr, 0);
 }
 
 static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
@@ -1323,13 +1310,13 @@ static int cortex_a_set_breakpoint(struct target *target,
 		brp_list[brp_i].used = true;
 		brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
 		brp_list[brp_i].control = control;
-		retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-				+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
+		retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+				armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
 				brp_list[brp_i].value);
 		if (retval != ERROR_OK)
 			return retval;
-		retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-				+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
+		retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+				armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
 				brp_list[brp_i].control);
 		if (retval != ERROR_OK)
 			return retval;
@@ -1415,13 +1402,13 @@ static int cortex_a_set_context_breakpoint(struct target *target,
 	brp_list[brp_i].used = true;
 	brp_list[brp_i].value = (breakpoint->asid);
 	brp_list[brp_i].control = control;
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
 			brp_list[brp_i].value);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
 			brp_list[brp_i].control);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1481,13 +1468,13 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
 	brp_list[brp_1].used = true;
 	brp_list[brp_1].value = (breakpoint->asid);
 	brp_list[brp_1].control = control_ctx;
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_BVR_BASE + 4 * brp_list[brp_1].brpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].brpn,
 			brp_list[brp_1].value);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_BCR_BASE + 4 * brp_list[brp_1].brpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].brpn,
 			brp_list[brp_1].control);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1499,13 +1486,13 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
 	brp_list[brp_2].used = true;
 	brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
 	brp_list[brp_2].control = control_iva;
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_BVR_BASE + 4 * brp_list[brp_2].brpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].brpn,
 			brp_list[brp_2].value);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_BCR_BASE + 4 * brp_list[brp_2].brpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].brpn,
 			brp_list[brp_2].control);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1538,13 +1525,13 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
 			brp_list[brp_i].used = false;
 			brp_list[brp_i].value = 0;
 			brp_list[brp_i].control = 0;
-			retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-					+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
+			retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+					armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
 					brp_list[brp_i].control);
 			if (retval != ERROR_OK)
 				return retval;
-			retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-					+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
+			retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+					armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
 					brp_list[brp_i].value);
 			if (retval != ERROR_OK)
 				return retval;
@@ -1557,13 +1544,13 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
 			brp_list[brp_j].used = false;
 			brp_list[brp_j].value = 0;
 			brp_list[brp_j].control = 0;
-			retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-					+ CPUDBG_BCR_BASE + 4 * brp_list[brp_j].brpn,
+			retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+					armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].brpn,
 					brp_list[brp_j].control);
 			if (retval != ERROR_OK)
 				return retval;
-			retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-					+ CPUDBG_BVR_BASE + 4 * brp_list[brp_j].brpn,
+			retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+					armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].brpn,
 					brp_list[brp_j].value);
 			if (retval != ERROR_OK)
 				return retval;
@@ -1582,13 +1569,13 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
 			brp_list[brp_i].used = false;
 			brp_list[brp_i].value = 0;
 			brp_list[brp_i].control = 0;
-			retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-					+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
+			retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+					armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
 					brp_list[brp_i].control);
 			if (retval != ERROR_OK)
 				return retval;
-			retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-					+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
+			retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+					armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
 					brp_list[brp_i].value);
 			if (retval != ERROR_OK)
 				return retval;
@@ -1783,14 +1770,14 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat
 	wrp_list[wrp_i].value = address;
 	wrp_list[wrp_i].control = control;
 
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
 			wrp_list[wrp_i].value);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
 			wrp_list[wrp_i].control);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1832,13 +1819,13 @@ static int cortex_a_unset_watchpoint(struct target *target, struct watchpoint *w
 	wrp_list[wrp_i].used = false;
 	wrp_list[wrp_i].value = 0;
 	wrp_list[wrp_i].control = 0;
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
 			wrp_list[wrp_i].control);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
-			+ CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
+	retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+			armv7a->debug_base + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
 			wrp_list[wrp_i].value);
 	if (retval != ERROR_OK)
 		return retval;

commit caabdd4a6627a86be43cd91e09f127173eb9e692
Author: Antonio Borneo <bor...@gm...>
Date:   Sat May 4 20:09:51 2024 +0200

    cortex_a: drop the command 'cache auto'
    
    The command 'cache auto' was introduced with commit cd440bd32a12
    ("add armv7a_cache handlers") in 2015 to allow disabling the cache
    handling done automatically by OpenOCD.
    This was probably a way to test the cache handling when there were
    still the two independent accesses for APB-AP CPU debug and for
    AHB-AP memory bus.
    
    The handling of cache for cortex_a is robust and there is no more
    reason to disable it.
    The command 'cache auto' is not used in any upstream script.
    On target aarch64 this command has never been introduced as the
    cache is always handled automatically by OpenOCD.
    
    Drop the command 'cache auto' and add it in the deprecated list.
    Drop the flag 'auto_cache_enabled' by considering it as true.
    Rename the function 'armv7a_cache_auto_flush_all_data()' as
    'armv7a_cache_flush_all_data()' and, while there, fix the error
    propagation in SMP case.
    
    Change-Id: I0399f1081b08c4929e0795b76f4a686630f41d56
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8230
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 82f4be5a0..dc3752e0b 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -473,7 +473,7 @@ int armv7a_identify_cache(struct target *target)
 	/*  if no l2 cache initialize l1 data cache flush function function */
 	if (!armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache) {
 		armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
-			armv7a_cache_auto_flush_all_data;
+			armv7a_cache_flush_all_data;
 	}
 
 	armv7a->armv7a_mmu.armv7a_cache.info = 1;
@@ -525,7 +525,6 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
 	armv7a->armv7a_mmu.armv7a_cache.info = -1;
 	armv7a->armv7a_mmu.armv7a_cache.outer_cache = NULL;
 	armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
-	armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = 1;
 	return ERROR_OK;
 }
 
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 6b9c2a68f..8943f1c69 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -65,8 +65,6 @@ struct armv7a_cache_common {
 	struct armv7a_arch_cache arch[6];	/* cache info, L1 - L7 */
 	int i_cache_enabled;
 	int d_u_cache_enabled;
-	int auto_cache_enabled;			/* openocd automatic
-						 * cache handling */
 	/* outer unified cache if some */
 	void *outer_cache;
 	int (*flush_all_data_cache)(struct target *target);
diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c
index 681c06aff..f2f1097c5 100644
--- a/src/target/armv7a_cache.c
+++ b/src/target/armv7a_cache.c
@@ -118,20 +118,19 @@ done:
 	return retval;
 }
 
-int armv7a_cache_auto_flush_all_data(struct target *target)
+int armv7a_cache_flush_all_data(struct target *target)
 {
 	int retval = ERROR_FAIL;
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-
-	if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled)
-		return ERROR_OK;
 
 	if (target->smp) {
 		struct target_list *head;
 		foreach_smp_target(head, target->smp_targets) {
 			struct target *curr = head->target;
-			if (curr->state == TARGET_HALTED)
-				retval = armv7a_l1_d_cache_clean_inval_all(curr);
+			if (curr->state == TARGET_HALTED) {
+				int retval1 = armv7a_l1_d_cache_clean_inval_all(curr);
+				if (retval1 != ERROR_OK)
+					retval = retval1;
+			}
 		}
 	} else
 		retval = armv7a_l1_d_cache_clean_inval_all(target);
@@ -472,28 +471,6 @@ COMMAND_HANDLER(arm7a_l1_i_cache_inval_virt_cmd)
 	return armv7a_l1_i_cache_inval_virt(target, virt, size);
 }
 
-COMMAND_HANDLER(arm7a_cache_disable_auto_cmd)
-{
-	struct target *target = get_current_target(CMD_CTX);
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-
-	if (CMD_ARGC == 0) {
-		command_print(CMD, "auto cache is %s",
-			armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled ? "enabled" : "disabled");
-		return ERROR_OK;
-	}
-
-	if (CMD_ARGC == 1) {
-		uint32_t set;
-
-		COMMAND_PARSE_ENABLE(CMD_ARGV[0], set);
-		armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = !!set;
-		return ERROR_OK;
-	}
-
-	return ERROR_COMMAND_SYNTAX_ERROR;
-}
-
 static const struct command_registration arm7a_l1_d_cache_commands[] = {
 	{
 		.name = "flush_all",
@@ -563,13 +540,6 @@ static const struct command_registration arm7a_l1_di_cache_group_handlers[] = {
 };
 
 static const struct command_registration arm7a_cache_group_handlers[] = {
-	{
-		.name = "auto",
-		.handler = arm7a_cache_disable_auto_cmd,
-		.mode = COMMAND_ANY,
-		.help = "disable or enable automatic cache handling.",
-		.usage = "(1|0)",
-	},
 	{
 		.name = "l1",
 		.mode = COMMAND_ANY,
diff --git a/src/target/armv7a_cache.h b/src/target/armv7a_cache.h
index 3e3eae55c..c4637c5d3 100644
--- a/src/target/armv7a_cache.h
+++ b/src/target/armv7a_cache.h
@@ -20,7 +20,7 @@ int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
 int armv7a_l1_i_cache_inval_all(struct target *target);
 int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt,
 					uint32_t size);
-int armv7a_cache_auto_flush_all_data(struct target *target);
+int armv7a_cache_flush_all_data(struct target *target);
 int armv7a_cache_flush_virt(struct target *target, uint32_t virt,
 				uint32_t size);
 extern const struct command_registration arm7a_cache_command_handlers[];
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index f90c02a95..a23540463 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1362,10 +1362,8 @@ static int cortex_a_set_breakpoint(struct target *target,
 			return retval;
 
 		/* make sure data cache is cleaned & invalidated down to PoC */
-		if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) {
-			armv7a_cache_flush_virt(target, breakpoint->address,
+		armv7a_cache_flush_virt(target, breakpoint->address,
 						breakpoint->length);
-		}
 
 		retval = target_write_memory(target,
 				breakpoint->address & 0xFFFFFFFE,
@@ -1600,10 +1598,8 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
 	} else {
 
 		/* make sure data cache is cleaned & invalidated down to PoC */
-		if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled) {
-			armv7a_cache_flush_virt(target, breakpoint->address,
+		armv7a_cache_flush_virt(target, breakpoint->address,
 						breakpoint->length);
-		}
 
 		/* restore original instruction (kept in target endianness) */
 		if (breakpoint->length == 4) {
diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 75e0edc77..e9646097f 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -294,3 +294,25 @@ proc "mips_m4k smp_off" {args} {
 	echo "DEPRECATED! use 'mips_m4k smp off' not 'mips_m4k smp_off'"
 	eval mips_m4k smp off $args
 }
+
+lappend _telnet_autocomplete_skip _post_init_target_cortex_a_cache_auto
+proc _post_init_target_cortex_a_cache_auto {} {
+	set cortex_a_found 0
+
+	foreach t [target names] {
+		if { [$t cget -type] != "cortex_a" } { continue }
+		set cortex_a_found 1
+		lappend ::_telnet_autocomplete_skip "$t cache auto"
+		proc "$t cache auto" { enable } {
+			echo "DEPRECATED! Don't use anymore '[dict get [info frame 0] proc] $enable' as it's always enabled"
+		}
+	}
+
+	if { $cortex_a_found } {
+		lappend ::_telnet_autocomplete_skip "cache auto"
+		proc "cache auto" { enable } {
+			echo "DEPRECATED! Don't use anymore 'cache auto $enable' as it's always enabled"
+		}
+	}
+}
+lappend post_init_commands _post_init_target_cortex_a_cache_auto

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv7a.c       |  3 +-
 src/target/armv7a.h       |  2 -
 src/target/armv7a_cache.c | 42 +++-----------------
 src/target/armv7a_cache.h |  2 +-
 src/target/cortex_a.c     | 99 ++++++++++++++++++++---------------------------
 src/target/startup.tcl    | 22 +++++++++++
 6 files changed, 71 insertions(+), 99 deletions(-)


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commit dbef02789fb1f30ae77020754b1468549fd16510
Author: Antonio Borneo <bor...@gm...>
Date:   Thu May 2 15:24:57 2024 +0200

    cortex_a: drop useless cache invalidate on mem write
    
    The initial OpenOCD code for Cortex-A (ARMv7a) [1] was merged in
    2009 but, due to lack of public documentation for ARMv7a, it was
    almost a simple copy/paste from the existing code for Cortex-M
    (ARMv7m).
    
    On Cortex-M the same AP provides access to both CPU debug and CPU
    memory. This feature is not present on ARMv7a.
    To still keep some communality with ARMv7m code, the change [2]
    splits the CPU debug access from the CPU memory access by using
    two independent AP; this is copied from the system architecture of
    TI OMAP3530 which provides to DAP a direct AHB-AP memory bus on
    AP#0, separated from AP#1 for the APB-AP CPU debug.
    But the direct memory access through the system bus breaks the
    coherency between memory and CPU caches, so change [3] added some
    cache invalidation to avoid issues.
    
    The code to allow ARMv7a CPU to really read/write in CPU memory
    was added by change [4] in 2011. Such still not optimized
    implementation was very slow, so it did not replace the access
    through the system bus. A selection through DAP's 'apsel" command
    was used to select between the two modes.
    
    Only in 2015, with change [5], the speed of CPU read/write was
    improved using the DCC_FAST_MODE. But the direct access to the
    memory through the system bus remained.
    
    Finally, with change [6] in 2018 the system bus access was dropped
    for good, as the new virtual target "mem_ap" could implement such
    access in a more clean way.
    Only memory access through CPU remained for ARMv7a.
    Nevertheless, a useless cache invalidation remained in the code,
    decreasing the speed of the write access.
    
    Drop the useless cache invalidate on CPU memory write and the
    associated comment, not anymore valid.
    Drop the now unused function armv7a_cache_auto_flush_on_write().
    
    This provides a speedup of between 4 and 8, depending on adapter
    and JTAG/SWD speed.
    
    Link: [1] 7a93100c2dfe ("Add minimalist Cortex A8 file")
    Link: [2] 1d0b276c9f75 ("The rest of the Cortex-A8 support from Magnus: ...")
    Link: [3] d4e4d65d284f ("Cache invalidation when writing to memory")
    Link: [4] 05ab8bdb813a ("cortex_a9: implement read/write memory through APB-AP")
    Link: [5] 0228f8e8274d ("Cortex A: fix extra memory read and non-word sizes")
    Link: [6] fac9be64d944 ("target/cortex_a: remove buggy memory AP accesses")
    
    Change-Id: Ifa3c7ddf2698b2c87037fb48f783844034a7140e
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8229
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c
index e1f0dfafb..681c06aff 100644
--- a/src/target/armv7a_cache.c
+++ b/src/target/armv7a_cache.c
@@ -391,27 +391,6 @@ int armv7a_cache_flush_virt(struct target *target, uint32_t virt,
 	return ERROR_OK;
 }
 
-/*
- * We assume that target core was chosen correctly. It means if same data
- * was handled by two cores, other core will loose the changes. Since it
- * is impossible to know (FIXME) which core has correct data, keep in mind
- * that some kind of data lost or corruption is possible.
- * Possible scenario:
- *  - core1 loaded and changed data on 0x12345678
- *  - we halted target and modified same data on core0
- *  - data on core1 will be lost.
- */
-int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt,
-					uint32_t size)
-{
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-
-	if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled)
-		return ERROR_OK;
-
-	return armv7a_cache_flush_virt(target, virt, size);
-}
-
 COMMAND_HANDLER(arm7a_l1_cache_info_cmd)
 {
 	struct target *target = get_current_target(CMD_CTX);
diff --git a/src/target/armv7a_cache.h b/src/target/armv7a_cache.h
index 17ec5e6de..3e3eae55c 100644
--- a/src/target/armv7a_cache.h
+++ b/src/target/armv7a_cache.h
@@ -20,8 +20,6 @@ int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
 int armv7a_l1_i_cache_inval_all(struct target *target);
 int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt,
 					uint32_t size);
-int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt,
-					uint32_t size);
 int armv7a_cache_auto_flush_all_data(struct target *target);
 int armv7a_cache_flush_virt(struct target *target, uint32_t virt,
 				uint32_t size);
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 78fd4482c..f90c02a95 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2791,9 +2791,6 @@ static int cortex_a_write_memory(struct target *target, target_addr_t address,
 	LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
 		address, size, count);
 
-	/* memory writes bypass the caches, must flush before writing */
-	armv7a_cache_auto_flush_on_write(target, address, size * count);
-
 	cortex_a_prep_memaccess(target, 0);
 	retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
 	cortex_a_post_memaccess(target, 0);

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv7a_cache.c | 21 ---------------------
 src/target/armv7a_cache.h |  2 --
 src/target/cortex_a.c     |  3 ---
 3 files changed, 26 deletions(-)


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commit bc9ca5f4a82ccbbdbe07108a83f7979b53e89889
Author: Daniel Anselmi <dan...@gm...>
Date:   Sun Mar 17 01:15:16 2024 +0100

    ipdbg: fix double free of virtual-ir data
    
    Fix possible double free and possible
    memory leak while creating an ipdbg hub.
    
    Change-Id: I6254663c27c4f38d46008c4dbff11aa27b84f399
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8085
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/server/ipdbg.c b/src/server/ipdbg.c
index e7eb96e13..859fdb035 100644
--- a/src/server/ipdbg.c
+++ b/src/server/ipdbg.c
@@ -285,6 +285,7 @@ static struct ipdbg_hub *ipdbg_allocate_hub(uint8_t data_register_length, struct
 {
 	struct ipdbg_hub *new_hub = calloc(1, sizeof(struct ipdbg_hub));
 	if (!new_hub) {
+		free(virtual_ir);
 		LOG_ERROR("Out of memory");
 		return NULL;
 	}
@@ -292,6 +293,7 @@ static struct ipdbg_hub *ipdbg_allocate_hub(uint8_t data_register_length, struct
 	new_hub->name = strdup(name);
 	if (!new_hub->name) {
 		free(new_hub);
+		free(virtual_ir);
 		LOG_ERROR("Out of memory");
 		return NULL;
 	}
@@ -304,8 +306,10 @@ static struct ipdbg_hub *ipdbg_allocate_hub(uint8_t data_register_length, struct
 	new_hub->scratch_memory.fields = calloc(IPDBG_SCRATCH_MEMORY_SIZE, sizeof(struct scan_field));
 	new_hub->connections = calloc(max_tools, sizeof(struct connection *));
 
-	if (virtual_ir)
+	if (virtual_ir) {
+		new_hub->virtual_ir = virtual_ir;
 		new_hub->scratch_memory.vir_out_val = calloc(1, DIV_ROUND_UP(virtual_ir->length, 8));
+	}
 
 	if (!new_hub->scratch_memory.dr_out_vals || !new_hub->scratch_memory.dr_in_vals ||
 		!new_hub->scratch_memory.fields || (virtual_ir && !new_hub->scratch_memory.vir_out_val) ||
@@ -997,7 +1001,6 @@ static int ipdbg_create_hub(struct jtag_tap *tap, uint32_t user_instruction, uin
 	new_hub->xoff_mask            = BIT(data_register_length - 2);
 	new_hub->tool_mask            = (new_hub->xoff_mask - 1) >> 8;
 	new_hub->last_dn_tool         = new_hub->tool_mask;
-	new_hub->virtual_ir           = virtual_ir;
 	new_hub->max_tools            = ipdbg_max_tools_from_data_register_length(data_register_length);
 	new_hub->using_queue_size     = IPDBG_SCRATCH_MEMORY_SIZE;
 
@@ -1123,11 +1126,7 @@ COMMAND_HANDLER(handle_ipdbg_create_hub_command)
 		return ERROR_FAIL;
 	}
 
-	int retval = ipdbg_create_hub(tap, user_instruction, data_register_length, virtual_ir, hub_name, cmd);
-	if (retval != ERROR_OK)
-		free(virtual_ir);
-
-	return retval;
+	return ipdbg_create_hub(tap, user_instruction, data_register_length, virtual_ir, hub_name, cmd);
 }
 
 static const struct command_registration ipdbg_config_command_handlers[] = {

-----------------------------------------------------------------------

Summary of changes:
 src/server/ipdbg.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)


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commit a84d1b5f5e2754680c12c1595db9d296eec7d45c
Author: Sean Anderson <sea...@se...>
Date:   Thu Feb 22 12:18:36 2024 -0500

    tcl/target: Add helpers for booting Xilinx ZynqMP from JTAG
    
    Add some helpers for booting ZynqMPs over JTAG. Normally, the CSU ROM
    will load boot.bin from the boot medium. However, when booting from JTAG
    we have to do this ourselves. There are generally two parts to this.
    First, we need to load the PMU firmware. Xilinx's tools do this by
    attaching to the PMU (a Microblaze CPU) over JTAG. However, the TAP is
    undocumented and we don't have any microblaze support in-tree. So
    instead we do it the same way FSBL does it:
    
    - We ask the PMU to halt
    - We load the firmware into the PMU RAM
    - We ask the PMU to resume
    
    The second thing we need to do is start one of the APU cores. When an
    APU is released from reset, it starts executing at the value of its
    RVBARADDR. While we could load the APU firmware over the AXI target,
    it is faster to load it over the APU target. To do this, we put the APU
    into an infinite loop before halting it. As an aside, I chose to use the
    "APU" terminology as opposed to "core" to make it clear that these
    commands operate on the A53 cores and not the R5F cores.
    
    Typical usage of these commands could look something like
    
            targets uscale.axi
            boot_pmu /path/to/pmu-firmware.bin
            boot_apu /path/to/u-boot-spl.bin
    
    But of course there is always the option to call lower-level commands
    individually if your boot process is more unusual.
    
    Signed-off-by: Sean Anderson <sea...@se...>
    Change-Id: I816940c2022ccca0fabb489aa75d682edd0f6138
    Reviewed-on: https://review.openocd.org/c/openocd/+/8133
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg
index 9734a1837..e8224be04 100644
--- a/tcl/target/xilinx_zynqmp.cfg
+++ b/tcl/target/xilinx_zynqmp.cfg
@@ -104,3 +104,137 @@ proc core_up { args } {
         $_TARGETNAME.$core arp_examine
     }
 }
+
+proc BIT {n} {
+	return [expr {1 << $n}]
+}
+
+set IPI_BASE			0xff300000
+set IPI_PMU_0_TRIG		[expr {$IPI_BASE + 0x30000}]
+set IPI_PMU_0_IER		[expr {$IPI_BASE + 0x30018}]
+set IPI_PMU_0					[BIT 16]
+
+set CRF_APB_BASE		0xfd1a0000
+set CRF_APB_RST_FPD_APU		[expr {$CRF_APB_BASE + 0x104}]
+set CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET	[BIT 10]
+set CRF_APB_RST_FPD_APU_L2_RESET		[BIT  8]
+set CRF_APB_RST_FPD_APU_ACPU0_RESET		[BIT  0]
+
+set APU_BASE			0xfd5c0000
+set APU_RVBARADDR_BASE		[expr {$APU_BASE + 0x40}]
+
+set PMU_BASE			0xffd80000
+set PMU_GLOBAL			$PMU_BASE
+set PMU_GLOBAL_MB_SLEEP				[BIT 16]
+set PMU_GLOBAL_FW_IS_PRESENT			[BIT  4]
+set PMU_GLOBAL_DONT_SLEEP			[BIT  0]
+
+set PMU_RAM_BASE		0xffdc0000
+
+set OCM_RAM_BASE		0xfffc0000
+
+rename BIT {}
+
+add_help_text halt_pmu "Halt the PMU in preparation for loading new firmware.\
+	This should be matched with a call to resume_pmu."
+proc halt_pmu {} {
+	set axi $::_CHIPNAME.axi
+	set val [$axi read_memory $::IPI_PMU_0_IER 32 1]
+	$axi write_memory $::IPI_PMU_0_IER 32 [expr {$val | $::IPI_PMU_0}]
+
+	set val [$axi read_memory $::IPI_PMU_0_TRIG 32 1]
+	$axi write_memory $::IPI_PMU_0_TRIG 32 [expr {$val | $::IPI_PMU_0}]
+
+	set start [ms]
+	while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_MB_SLEEP)} {
+		if {[ms] - $start > 1000} {
+			error "Timed out waiting for PMU to halt"
+		}
+	}
+}
+
+add_help_text resume_pmu "Resume the PMU after loading new firmware. This\
+	should be matched with a call to halt_pmu."
+proc resume_pmu {} {
+	set axi $::_CHIPNAME.axi
+	set val [$axi read_memory $::PMU_GLOBAL 32 1]
+	$axi write_memory $::PMU_GLOBAL 32 [expr {$val | $::PMU_GLOBAL_DONT_SLEEP}]
+
+	set start [ms]
+	while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_FW_IS_PRESENT)} {
+		if {[ms] - $start > 5000} {
+			error "Timed out waiting for PMU firmware"
+		}
+	}
+}
+
+add_usage_text release_apu {apu}
+add_help_text release_apu "Release an APU from reset. It will start executing\
+	at RVBARADDR. You probably want resume_apu or start_apu instead."
+proc release_apu {apu} {
+	set axi $::_CHIPNAME.axi
+	set val [$axi read_memory $::CRF_APB_RST_FPD_APU 32 1]
+	set mask [expr {
+		(($::CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET | \
+		  $::CRF_APB_RST_FPD_APU_ACPU0_RESET) << $apu) | \
+		$::CRF_APB_RST_FPD_APU_L2_RESET
+	}]
+	$axi write_memory $::CRF_APB_RST_FPD_APU 32 [expr {$val & ~$mask}]
+
+	core_up $apu
+	$::_TARGETNAME.$apu aarch64 dbginit
+}
+
+proc _rvbaraddr {apu} {
+	return [expr {$::APU_RVBARADDR_BASE + 8 * $apu}]
+}
+
+add_usage_text resume_apu {apu addr}
+add_help_text resume_apu "Resume an APU at a given address."
+proc resume_apu {apu addr} {
+	set addrl [expr {$addr & 0xffffffff}]
+	set addrh [expr {$addr >> 32}]
+	$::_CHIPNAME.axi write_memory [_rvbaraddr $apu] 32 [list $addrl $addrh]
+
+	release_apu $apu
+}
+
+add_usage_text start_apu {apu}
+add_help_text start_apu "Start an APU and put it into an infinite loop at\
+	RVBARADDR. This can be convenient if you just want to halt the APU\
+	(since it won't execute anything unusual)."
+proc start_apu {apu} {
+	set axi $::_CHIPNAME.axi
+	foreach {addrl addrh} [$axi read_memory [_rvbaraddr $apu] 32 2] {
+		set addr [expr {($addrh << 32) | $addrl}]
+	}
+	# write the infinite loop instruction
+	$axi write_memory $addr 32 0x14000000
+
+	release_apu $apu
+}
+
+add_usage_text boot_pmu {image}
+add_help_text boot_pmu "Boot the PMU with a given firmware image, loading it\
+	to the beginning of PMU RAM. The PMU ROM will jump to this location\
+	after we resume it."
+proc boot_pmu {image} {
+	halt_pmu
+	echo "Info : Loading PMU firmware $image to $::PMU_RAM_BASE"
+	load_image $image $::PMU_RAM_BASE
+	resume_pmu
+}
+
+add_usage_text boot_apu "image \[apu=0 \[addr=$OCM_RAM_BASE\]\]"
+add_help_text boot_apu "Boot an APU with a given firmware image. The default\
+	address is the beginning of OCM RAM. Upon success, the default target\
+	will be changed to the (running) apu."
+proc boot_apu [list image {apu 0} [list addr $OCM_RAM_BASE]] {
+	start_apu $apu
+	targets $::_TARGETNAME.$apu
+	halt
+
+	echo "Info : Loading APU$apu firmware $image to $addr"
+	load_image $image $addr
+	resume $addr
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/xilinx_zynqmp.cfg | 134 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 134 insertions(+)


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commit 3eba7b53bf067508197e2455b81fc1375b1d945e
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Apr 15 17:42:12 2024 +0200

    smp: fix SIGSEGV for "smp off" during target examine
    
    The gdb subsystem is initialized after the first target examine,
    so the field struct target::gdb_service is NULL during examine.
    
    A command "smp off" in the examine event handler causes a SIGSEGV
    during OpenOCD startup.
    
    Check for pointer not NULL before dereferencing it.
    
    Change-Id: Id115e28be23a957fef1b97ab66d7273f0ea0dce4
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8216
    Tested-by: jenkins

diff --git a/src/target/smp.c b/src/target/smp.c
index 50b19d01a..41ca880d4 100644
--- a/src/target/smp.c
+++ b/src/target/smp.c
@@ -119,7 +119,7 @@ COMMAND_HANDLER(default_handle_smp_command)
 			head->target->smp = 0;
 
 		/* fixes the target display to the debugger */
-		if (!list_empty(target->smp_targets))
+		if (!list_empty(target->smp_targets) && target->gdb_service)
 			target->gdb_service->target = target;
 
 		return ERROR_OK;

-----------------------------------------------------------------------

Summary of changes:
 src/target/smp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit c72afedce794a7251fd9c822e3bfc89f870b9fc1
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Apr 13 18:54:12 2024 +0200

    target: cortex_a: fix regs invalidation when -defer-examine
    
    The code for cortex_a allocates the register cache during the very
    first examine of the target.
    To prevent a segmentation fault in assert_reset(), the call to
    register_cache_invalidate() is guarded by target_was_examined().
    
    But for targets with -defer-examine, the target is set as not
    examined in handle_target_reset() just before entering in
    assert_reset().
    
    This causes registers to not be invalidated while reset a target
    examined but with -defer-examine.
    
    Change the condition and invalidate the register cache if it has
    been already allocated.
    
    Change-Id: I81ae782ddce07431d5f2c1bea3e2f19dfcd6d1ce
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8215
    Tested-by: jenkins

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 7fa0c4e8b..78fd4482c 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1932,7 +1932,7 @@ static int cortex_a_assert_reset(struct target *target)
 	}
 
 	/* registers are now invalid */
-	if (target_was_examined(target))
+	if (armv7a->arm.core_cache)
 		register_cache_invalidate(armv7a->arm.core_cache);
 
 	target->state = TARGET_RESET;

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_a.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit 42e31d75b443e369597669b5ff7901de902ad35e
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Apr 13 18:46:11 2024 +0200

    target: aarch64: fix regs invalidation when -defer-examine
    
    The code for aarch64 allocates the register cache during the very
    first examine of the target.
    To prevent a segmentation fault in assert_reset(), the call to
    register_cache_invalidate() is guarded by target_was_examined().
    
    But for targets with -defer-examine, the target is set as not
    examined in handle_target_reset() just before entering in
    assert_reset().
    
    This causes registers to not be invalidated while reset a target
    examined but with -defer-examine.
    
    Change the condition and invalidate the register cache if it has
    been already allocated.
    
    Change-Id: Ie13abb0ae2cc28fc3295d678c4ad1691024eb7b8
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8214
    Tested-by: jenkins

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 2e4d0b5c0..6a70b2ddf 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1983,7 +1983,7 @@ static int aarch64_assert_reset(struct target *target)
 	}
 
 	/* registers are now invalid */
-	if (target_was_examined(target)) {
+	if (armv8->arm.core_cache) {
 		register_cache_invalidate(armv8->arm.core_cache);
 		register_cache_invalidate(armv8->arm.core_cache->next);
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit 89d881c19ae89712652f17962b8b7d2e79e25ca3
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Apr 8 17:40:09 2024 +0200

    cortex_m: don't try to halt not-examined targets
    
    Prevent a segmentation fault by preventing to try to halt a target
    that has not been examined yet.
    
    Change-Id: I5d344e7fbdb5422f7c5e2c39bdd48cbc6c2a3e58
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8213
    Tested-by: jenkins

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index a26df2e5a..c225b1aa9 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1109,6 +1109,11 @@ static int cortex_m_halt_one(struct target *target)
 	int retval;
 	LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
 
+	if (!target_was_examined(target)) {
+		LOG_TARGET_ERROR(target, "target non examined yet");
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
 	if (target->state == TARGET_HALTED) {
 		LOG_TARGET_DEBUG(target, "target was already halted");
 		return ERROR_OK;

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_m.c | 5 +++++
 1 file changed, 5 insertions(+)


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- Log -----------------------------------------------------------------
commit 8667a726532604afab099881779a4b898539dabf
Author: Marc Schink <de...@za...>
Date:   Sat Nov 18 12:48:33 2023 +0100

    target/target: Add 'debug_reason' to current target
    
    Change-Id: Ie35b13b3e06411b4866ffeada47b3262493dbf2e
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8021
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 52a51c196..55e6e7680 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9191,6 +9191,18 @@ read_memory 0x20000000 32 2
 @end example
 @end deffn
 
+@deffn {Command} {debug_reason}
+Displays the current debug reason:
+@code{debug-request},
+@code{breakpoint},
+@code{watchpoint},
+@code{watchpoint-and-breakpoint},
+@code{single-step},
+@code{target-not-halted},
+@code{program-exit},
+@code{exception-catch} or @code{undefined}.
+@end deffn
+
 @deffn {Command} {halt} [ms]
 @deffnx {Command} {wait_halt} [ms]
 The @command{halt} command first sends a halt request to the target,
diff --git a/src/target/target.c b/src/target/target.c
index 45698a66c..5168305de 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -6736,6 +6736,13 @@ static const struct command_registration target_exec_command_handlers[] = {
 		.help = "Write Tcl list of 8/16/32/64 bit numbers to target memory",
 		.usage = "address width data ['phys']",
 	},
+	{
+		.name = "debug_reason",
+		.mode = COMMAND_EXEC,
+		.handler = handle_target_debug_reason,
+		.help = "displays the debug reason of this target",
+		.usage = "",
+	},
 	{
 		.name = "reset_nag",
 		.handler = handle_target_reset_nag,

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi    | 12 ++++++++++++
 src/target/target.c |  7 +++++++
 2 files changed, 19 insertions(+)


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commit ac6b00c3cae5def9c1b3f08fae68703abc494109
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Apr 6 00:26:38 2024 +0200

    target: cortex_m: fix display of DWT registers
    
    Commit 16b4b8cf5453 ("Cortex-M3: expose most DWT registers") added
    the DWT registers to the list of CPU registers.
    The commit message from 2009 reports the reason behind this odd
    mixing of CPU and DWT registers.
    This feature got broken in 2017 with the introduction of the field
    struct reg::exist and its further use in the code. As result, the
    command 'reg' on a target Cortex-M reports only the core registers
    and then the header line
            ===== Cortex-M DWT registers
    not anymore followed by the DWT registers.
    
    Fix it by tagging each DWT registers as existing.
    
    Change-Id: Iab026e7da8d6b8ba052514c3fd3b5cdfe301f330
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: b5964191f0d2 ("register: support non-existent registers")
    Reviewed-on: https://review.openocd.org/c/openocd/+/8198
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 4894cabf8..a26df2e5a 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2351,6 +2351,7 @@ static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dw
 	r->value = state->value;
 	r->arch_info = state;
 	r->type = &dwt_reg_type;
+	r->exist = true;
 }
 
 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_m.c | 1 +
 1 file changed, 1 insertion(+)


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commit a9e8ca55a6f44cf6edef7ea5ca66927fa02f3cca
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Apr 7 12:28:55 2024 +0200

    jtag: linuxgpiod: minor alignment to coding style
    
    Avoid double TAB in 'then' block by increasing indentation of the
    multi-line condition.
    
    Change-Id: I7f5a4437fe4f74228f1b0d98e5c5921af4fd36b8
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8200
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/src/jtag/drivers/linuxgpiod.c b/src/jtag/drivers/linuxgpiod.c
index 2f3d64454..1926ed9ae 100644
--- a/src/jtag/drivers/linuxgpiod.c
+++ b/src/jtag/drivers/linuxgpiod.c
@@ -378,12 +378,12 @@ static int linuxgpiod_init(void)
 			goto out_error;
 		}
 
-		if (helper_get_line(ADAPTER_GPIO_IDX_TDO) != ERROR_OK ||
-			helper_get_line(ADAPTER_GPIO_IDX_TDI) != ERROR_OK ||
-			helper_get_line(ADAPTER_GPIO_IDX_TCK) != ERROR_OK ||
-			helper_get_line(ADAPTER_GPIO_IDX_TMS) != ERROR_OK ||
-			helper_get_line(ADAPTER_GPIO_IDX_TRST) != ERROR_OK)
-				goto out_error;
+		if (helper_get_line(ADAPTER_GPIO_IDX_TDO) != ERROR_OK
+				|| helper_get_line(ADAPTER_GPIO_IDX_TDI) != ERROR_OK
+				|| helper_get_line(ADAPTER_GPIO_IDX_TCK) != ERROR_OK
+				|| helper_get_line(ADAPTER_GPIO_IDX_TMS) != ERROR_OK
+				|| helper_get_line(ADAPTER_GPIO_IDX_TRST) != ERROR_OK)
+			goto out_error;
 	}
 
 	if (transport_is_swd()) {
@@ -413,9 +413,9 @@ static int linuxgpiod_init(void)
 			goto out_error;
 	}
 
-	if (helper_get_line(ADAPTER_GPIO_IDX_SRST) != ERROR_OK ||
-		helper_get_line(ADAPTER_GPIO_IDX_LED) != ERROR_OK)
-			goto out_error;
+	if (helper_get_line(ADAPTER_GPIO_IDX_SRST) != ERROR_OK
+			|| helper_get_line(ADAPTER_GPIO_IDX_LED) != ERROR_OK)
+		goto out_error;
 
 	return ERROR_OK;
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/linuxgpiod.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)


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- Log -----------------------------------------------------------------
commit 495311d2067e85ee1fb53593a4671ef0ec09c6f1
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Apr 7 12:41:48 2024 +0200

    doc: style: report indentation of multi-line condition
    
    To help readability and discriminate the 'then' block from the
    multi-line condition, suggest to increase the indentation of the
    condition.
    
    Change-Id: I02e3834be3001e7ecf24349ad3cefe94b27b79c8
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8199
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/doc/manual/style.txt b/doc/manual/style.txt
index 1d3ec6748..a1e6b8f01 100644
--- a/doc/manual/style.txt
+++ b/doc/manual/style.txt
@@ -97,6 +97,21 @@ OpenOCD project.
       x = 0;
   }
   @endcode
+- on <tt> if </tt> statements where the condition is split among multiple
+  lines, increase the indentation of the condition to prevent it to match
+  to the indentation of the <tt> then </tt> block due to length of 'if ('
+  being same of the TAB width of 4 characters. Use:
+  @code
+  if (CMD_ARGC < 3
+          || CMD_ARGC > 8)
+      return ERROR_COMMAND_SYNTAX_ERROR;
+  @endcode
+  instead of:
+  @code
+  if (CMD_ARGC < 3 ||
+      CMD_ARGC > 8)
+      return ERROR_COMMAND_SYNTAX_ERROR;
+  @endcode
 
 Finally, try to avoid lines of code that are longer than 72-80 columns:
 

-----------------------------------------------------------------------

Summary of changes:
 doc/manual/style.txt | 15 +++++++++++++++
 1 file changed, 15 insertions(+)


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commit 04154af5d6cd5fe76a2583778379bdacb5aa6fb0
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Mar 24 22:57:52 2024 +0100

    jtag: linuxgpiod: drop extra parenthesis
    
    Checkpatch complains for extra parenthesis not required.
    
    Drop them.
    
    Change-Id: I311409f5732acf10a4910de5dcf0fb05f43e21b5
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8187
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/jtag/drivers/linuxgpiod.c b/src/jtag/drivers/linuxgpiod.c
index 3ca452357..2f3d64454 100644
--- a/src/jtag/drivers/linuxgpiod.c
+++ b/src/jtag/drivers/linuxgpiod.c
@@ -157,7 +157,7 @@ static int linuxgpiod_swd_write(int swclk, int swdio)
 	int retval;
 
 	if (!swdio_input) {
-		if (!last_stored || (swdio != last_swdio)) {
+		if (!last_stored || swdio != last_swdio) {
 			retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO], swdio);
 			if (retval < 0)
 				LOG_WARNING("Fail set swdio");
@@ -165,7 +165,7 @@ static int linuxgpiod_swd_write(int swclk, int swdio)
 	}
 
 	/* write swclk last */
-	if (!last_stored || (swclk != last_swclk)) {
+	if (!last_stored || swclk != last_swclk) {
 		retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWCLK], swclk);
 		if (retval < 0)
 			LOG_WARNING("Fail set swclk");

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/linuxgpiod.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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