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From: BERTRAND J. <joe...@sy...> - 2022-09-15 08:06:25
|
Hello,
I'm looking for a CTP spice model that runs fine with ngspice. I have
found MF-RM040-Tamb23C-SPICE.lib that contains :
*Steady State Model of 0.4Amp PTC at 23C
*May 24,Cathal Sheehan
.SUBCKT MF-RM040-Tamb23 I O
V2 I N004 0
BdTemp 0 dTemp I=I(BIcorr)*I(BIcorr)*R0*(1+ALPHA*V(dTemp))
R_th1 dTemp N001 {R_TH1}
C_th1 dTemp 0 {C_TH1}
S1 N004 O N006 0 SW1
R_th2 N001 N002 {R_TH2}
C_th2 N001 0 {C_TH2}
A1 set_break set_nobreak 0 0 0 N006 0 0 SRFLOP td=0.1u
C_th3 N002 0 {C_TH3}
BIcorr 0 Icorr I=Table(I(BIabs), 0, 0.0, 2,2.0, 3,3.3, 5.5,5.50, 1e4, 1.0e4)
R1 Icorr 0 1
BIabs 0 Iabs I=abs(I(V2))
R2 Iabs 0 1
BIabs1 0 set_break I=IF(abs(V(dTemp))>{dT_sw}, 1, 0)
R3 set_break 0 1
I2 0 set_nobreak PULSE(0 1 1u 1u 1u 2u 1 1)
R5 set_nobreak 0 1
R_th3 N002 N003 {R_TH3}
V1 N003 0 {T_AMB}
.MODEL SW1 SW(Ron=1u Roff=1G Vt=0.5 Vh=-0.4)
* Reset at the beginning
.param I_NOM=0.40 ; current rating of the fuse
.param R0=0.6 ; R_fuse at no current
.param R100=1.9 ; R_fuse at 100% current
.param R_BREAK=1.9 ; the same as R100%
*
.param TAU1=0.7
.param TAU2=50
.param TAU3=220
*
.param dT_MAX=1000 ; Melting temperature
.param T_AMB=23 ; Ambient temperature
.param dT_sw=180;Temperature at which polymer changes state
*
.param I_BREAK=I_NOM*2.5
.param P_BREAK=R_BREAK*I_BREAK*I_BREAK
.param R_TH=(dT_MAX/P_BREAK)
.param ALPHA=(R_BREAK-R0)/R0/dT_MAX
*
.param R_TH1=R_TH*0.02
.param R_TH2=R_TH*0.3
.param R_TH3=R_TH*0.68
*
.param C_TH1=TAU1/R_TH1
.param C_TH2=TAU2/R_TH2
.param C_TH3=TAU3/R_TH3
.backanno
.end
.ENDS
but ngspice complains about table function. I have tried to replace
table by pwl but now, it stops at :
A1 set_break set_nobreak 0 0 0 N006 0 0 SRFLOP td=0.1u
with :
Error on line 0 or its substitute:
a.xrv1.a1 xrv1.set_break xrv1.set_nobreak 0 0 0 xrv1.n006 0 0 srflop
MIF-ERROR - unable to find definition of model srflop
Simulation interrupted due to error!
Does someone have a ngspice compatible CTP generic CTP model ? Or is it
possible to fix mine ?
Best regards,
JB
|
|
From: BERTRAND J. <joe...@sy...> - 2022-09-15 08:06:24
|
Hello,
I'm looking for a CTP spice model that runs fine with ngspice. I have
found MF-RM040-Tamb23C-SPICE.lib that contains :
BdTemp 0 dTemp I=I(BIcorr)*I(BIcorr)*R0*(1+ALPHA*V(dTemp))
R_th1 dTemp N001 {R_TH1}
C_th1 dTemp 0 {C_TH1}
S1 N004 O N006 0 SW1
R_th2 N001 N002 {R_TH2}
C_th2 N001 0 {C_TH2}
A1 set_break set_nobreak 0 0 0 N006 0 0 SRFLOP td=0.1u
C_th3 N002 0 {C_TH3}
BIcorr 0 Icorr I=Table(I(BIabs), 0, 0.0, 2,2.0, 3,3.3, 5.5,5.50, 1e4, 1.0e4)
R1 Icorr 0 1
BIabs 0 Iabs I=abs(I(V2))
R2 Iabs 0 1
BIabs1 0 set_break I=IF(abs(V(dTemp))>{dT_sw}, 1, 0)
R3 set_break 0 1
I2 0 set_nobreak PULSE(0 1 1u 1u 1u 2u 1 1)
R5 set_nobreak 0 1
R_th3 N002 N003 {R_TH3}
V1 N003 0 {T_AMB}
.MODEL SW1 SW(Ron=1u Roff=1G Vt=0.5 Vh=-0.4)
* Reset at the beginning
.param I_NOM=0.40 ; current rating of the fuse
.param R0=0.6 ; R_fuse at no current
.param R100=1.9 ; R_fuse at 100% current
.param R_BREAK=1.9 ; the same as R100%
*
.param TAU1=0.7
.param TAU2=50
.param TAU3=220
*
.param dT_MAX=1000 ; Melting temperature
.param T_AMB=23 ; Ambient temperature
.param dT_sw=180;Temperature at which polymer changes state
*
.param I_BREAK=I_NOM*2.5
.param P_BREAK=R_BREAK*I_BREAK*I_BREAK
.param R_TH=(dT_MAX/P_BREAK)
.param ALPHA=(R_BREAK-R0)/R0/dT_MAX
*
.param R_TH1=R_TH*0.02
.param R_TH2=R_TH*0.3
.param R_TH3=R_TH*0.68
*
.param C_TH1=TAU1/R_TH1
.param C_TH2=TAU2/R_TH2
.param C_TH3=TAU3/R_TH3
.backanno
.end
.ENDS
but ngspice complains about table function. I have tried to replace
table by pwl but now, it stops at :
A1 set_break set_nobreak 0 0 0 N006 0 0 SRFLOP td=0.1u
with :
Error on line 0 or its substitute:
a.xrv1.a1 xrv1.set_break xrv1.set_nobreak 0 0 0 xrv1.n006 0 0 srflop
MIF-ERROR - unable to find definition of model srflop
Simulation interrupted due to error!
Does someone have a ngspice compatible CTP generic CTP model ? Or is it
possible to fix mine ?
Best regards,
JB
|
|
From: Holger V. <hol...@un...> - 2022-08-26 12:18:13
|
This may be a ngspice installation problem. What is your operating system? What is your ngspice version? Where did you get ngspice? Finding the VSWITCH model does require the XSPICE code models. We have to check if they are available. Their location is depending on the operating system. And it will require a suitable spinit (ngspice initialization) file, which is part of the installation. |
|
From: Anthony L. <tla...@gm...> - 2022-08-24 23:20:58
|
Hi all, I'm trying to run a simulation with a spice netlist from the manufacturer's website for the AD8000 and AD8099 op-amps. The links to the datasheets and spice models are https://www.analog.com/en/products/ad8000.html and https://www.analog.com/en/products/ad8099.html. I've also attached the file for the AD8099 as an example. When trying to run a simulation, I first run into the problem where I get the following error: > Ngspice started... > warning, model type mismatch in line > s6 97 96 1020 1030 sswitch > warning, model type mismatch in line > s1 98 1030 106 113 switch > warning, model type mismatch in line > s2 1 100 106 113 switch > warning, model type mismatch in line > s3 9 101 106 113 switch > warning, model type mismatch in line > s5 81 82 83 113 switch > warning, model type mismatch in line > s4 104 313 106 113 switch > Simulation interrupted due to error! > Note: No ".plot", ".print", or ".fourier" lines; no simulations run > Note: Compatibility modes selected: ps > Circuit: * qucs 0.0.24 /home/tlatorre/crosstalk_prj/ad8099.sch > Error on line 0 or its substitute: > s.x1.s6 x1.97 x1.96 x1.1020 x1.1030 x1:sswitch > Unable to find definition of model x1:sswitch > Simulation finished I'm a total noob at using this software, but looking at the file it seems like ngspice maybe doesn't like the fact that the model for sswitch is defined at the end of the file rather than the beginning? So, I tried moving the sswitch model and the others to the beginning of the file and reran it. Then I get the message: > Ngspice started... [same warnings as before] > Warning: Model issue on line 0 : > .model x1:switch vswitch(von=0.105,voff=0.095,ron=0.001,roff=1e6) ... > Unknown model type vswitch - ignored > Warning: Model issue on line 0 : > .model x1:sswitch vswitch(von=2.3,voff=0.1,ron=1000,roff=1e6) ... > Unknown model type vswitch - ignored > Warning: Model issue on line 0 : > .model x1:rideal res(t_abs=-273) ... > unrecognized parameter (t_abs) - ignored > Error on line 0 or its substitute: > s.x1.s6 x1.97 x1.96 x1.1020 x1.1030 x1:sswitch > Unable to find definition of model x1:sswitch > Simulation finished Here it seems like it doesn't understand the vswitch function? I tried looking online and only found that this was standard pspice syntax (this is why I set ngbehavior=ps). But I'm kind of lost here. Does anybody have any suggestions or can point me to somewhere I can learn more about why the simulation doesn't work? Thanks, Tony |
|
From: Carsten S. <c.s...@t-...> - 2022-07-31 08:00:40
|
Hello vidnyankendra, the topic of your email talks about Debian 9, within the context than you talk from Debian 8! Am 31.07.22 um 08:10 schrieb vidnyankendra via Ngspice-users: > Hi, > I wish to use an old computer with debian 8 (jessie) installed. > I was able to install latest versions of softaware like gnu-octave on this machine. > Is it possible to install one of the latest version of ngspice on this machine? > If yes, which version, and how should I proceed? Both releases, Debian 8 and 9, are out of support by the Debian project itself. https://wiki.debian.org/LTS So you should at least update to the buster release (Debian 10). Here you can get version 34+ds-1~bpo10+1 from the old-backports archive. The latest version for Debian 9 is 32.2+ds-1~bpo9+1 from oldold-backports-sloppy. https://tracker.debian.org/pkg/ngspice If you really need to stay on Debian 8 or 9 you can contact the (commercial) ETLS support and ask if a backport of a recent NGSpice version is possible. Please note that this service isn't free of costs. https://wiki.debian.org/LTS/Extended -- Regards Carsten |
|
From: vidnyankendra <vid...@di...> - 2022-07-31 06:11:11
|
Hi, I wish to use an old computer with debian 8 (jessie) installed. I was able to install latest versions of softaware like gnu-octave on this machine. Is it possible to install one of the latest version of ngspice on this machine? If yes, which version, and how should I proceed? Thanks. --vk -- vidnyankendra <vid...@di...> |
|
From: BERTRAND J. <joe...@sy...> - 2022-07-11 07:46:08
|
Holger Vogt a écrit : > I guess you have to work on your digital output stage. > > > The circuit > ~~~ > .title Toggle Flip-Flop and Output > .include "CD74HCT11.lib" > .include "SN74LVC74APWR.LIB" > > VC VCC 0 5 > Vclock /Vct 0 dc 0 pulse (0 5 0 1n 1n 5u 10u) > > XU4 /C1 /Q1 /Vct VCC VCC 0 CD74HCT11 > XU5 /C2 /Q2 /Vct VCC VCC 0 CD74HCT11 > * CLRZ D CLK PREZ Q QZ VCC GND > XU3 VCC /Q2 /Vct VCC /Q1 /Q2 VCC 0 SN74LVC74APWR_DFF > > .options method=gear reltol=5m minbreak=200ps gmin=1E-12 chgtol=1e-11 > .control > tran 1u 1m > run > set xbrushwidth=2 > plot v(/Vct) v(/C1)+6 v(/C2)+12 v(/Q1)+18 v(/Q2)+24 > .endc > .end > > ~~~ > will work only when the clock (v(/ct) rise time is 1ns (which is > completely unrealistic). With 10ns rise time the circuit ceases > functioning, probably due to severe race conditions. A toggle flip-flop > made by Q2 feedback probably is not working reliably. Thanks for you test. This output stage perfectly runs as expected (with of course real components). I use similar designs for very long time without trouble. Issue seems to be between ngspice and flip-flop model. That being said, when I run your circuit with Vclock /Vct 0 dc 0 pulse (0 5 0 10n 10n 5u 10u), Q1 and Q2 are faulty but I don't see artefacts I see in my simulation where flip-flop outputs can change even if there is no positive edge on clock input !). Can you test your circuit with another spice engine ? PSpice ou LTSpice ? Best regards, JKB |
|
From: Holger V. <hol...@un...> - 2022-07-10 14:24:14
|
I guess you have to work on your digital output stage. The circuit ~~~ .title Toggle Flip-Flop and Output .include "CD74HCT11.lib" .include "SN74LVC74APWR.LIB" VC VCC 0 5 Vclock /Vct 0 dc 0 pulse (0 5 0 1n 1n 5u 10u) XU4 /C1 /Q1 /Vct VCC VCC 0 CD74HCT11 XU5 /C2 /Q2 /Vct VCC VCC 0 CD74HCT11 * CLRZ D CLK PREZ Q QZ VCC GND XU3 VCC /Q2 /Vct VCC /Q1 /Q2 VCC 0 SN74LVC74APWR_DFF .options method=gear reltol=5m minbreak=200ps gmin=1E-12 chgtol=1e-11 .control tran 1u 1m run set xbrushwidth=2 plot v(/Vct) v(/C1)+6 v(/C2)+12 v(/Q1)+18 v(/Q2)+24 .endc .end ~~~ will work only when the clock (v(/ct) rise time is 1ns (which is completely unrealistic). With 10ns rise time the circuit ceases functioning, probably due to severe race conditions. A toggle flip-flop made by Q2 feedback probably is not working reliably. |
|
From: BERTRAND J. <joe...@sy...> - 2022-07-09 20:45:39
|
Holger Vogt a écrit : > If I relax chgtol a bit, the simulation with input file > SIM_CONVERTISSEUR_HT_WITH_FF.CIR converges and runs up to the end (MS > Windows, branch pre-master, i9 9900K). > > Excerpt from the netlist: > > .options method=gear reltol=5m minbreak=200ps gmin=1E-12 chgtol=1e-11 > .control > tran 1u .1s > run Thanks, I will try with chgtol=1e-11. But flip flop output is faulty with tran 1u .1s. To obtain a realist output, I have to reduce tstep to .5n and a simulation should take more than 2 days... Server : Linux Debian, 64 GB, i9-10900F CPU @ 2.80GHz, but constantly runs @4,8 GHz (60°C max). Best regards, JKB |
|
From: BERTRAND J. <joe...@sy...> - 2022-07-09 20:45:37
|
Holger Vogt a écrit : > If I relax chgtol a bit, the simulation with input file > SIM_CONVERTISSEUR_HT_WITH_FF.CIR converges and runs up to the end (MS > Windows, branch pre-master, i9 9900K). > > Excerpt from the netlist: > > .options method=gear reltol=5m minbreak=200ps gmin=1E-12 chgtol=1e-11 > .control > tran 1u .1s > run Thanks a lot, I will try with chgtol=1e-11. But flip flop output is faulty and I have to reduce tstep to .5ns to obtain a realist output. I think a simulation should take more than two days (i9-10900F @ 4.8 GHz [60°C] when simation is running) ... Compilation option : hilbert:[~/git/ngspice-build-exe] > head config.log This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. It was created by ngspice configure 37+, which was generated by GNU Autoconf 2.71. Invocation command line was $ ../ngspice/configure --without-ngshared --enable-nobypass --enable-xspice --enable-cider --enable-pss --enable-ndev --enable-openmp --with-x --no-create --no-recursion branch master. Best regards, JKB |
|
From: Holger V. <hol...@un...> - 2022-07-09 14:53:07
|
Simulation time 8130 s |
|
From: Holger V. <hol...@un...> - 2022-07-09 14:01:56
|
If I relax chgtol a bit, the simulation with input file SIM_CONVERTISSEUR_HT_WITH_FF.CIR converges and runs up to the end (MS Windows, branch pre-master, i9 9900K). Excerpt from the netlist: .options method=gear reltol=5m minbreak=200ps gmin=1E-12 chgtol=1e-11 .control tran 1u .1s run Btw. the run command is redundant, in a .control section tran is sufficient. If .tran was given outside of the .control section, then 'run' would start the simulation. Holger |
|
From: Holger V. <hol...@un...> - 2022-07-08 07:45:31
|
File LM6172.lib is empty. |
|
From: BERTRAND J. <joe...@sy...> - 2022-07-06 21:11:55
|
mh...@ia... a écrit : > Specualtion: it is easy to set up a simulation such that NGSPICE misses an > asynchronous event. It is almost guaranteed to happen when there > is no reasonable STEPMAX defined (or implied) on the .TRAN line. > >> But for example, at 48 µs, there is a transition >> on flip flop output without any positive edge on clock input. > > Adding gain in a feedback loop can create an algebraic loop. Some delay > (but also not too much) must be explicitly added to prevent the timestep > to go to zero. As you said, I have replaced tran 1u 100ms by tran .1n 100ms and D-flip flop runs better. But simulation aborts with doAnalyses: TRAN: Timestep too small; time = 0.000554392, timestep = 1.25e-22: trouble with j113-instance jq1 Without flip flop, it runs as expected. Regards, JB |
|
From: BERTRAND J. <joe...@sy...> - 2022-07-06 18:58:18
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mh...@ia... a écrit : > On 2022-07-06 17:44, BERTRAND Joël wrote: > [..] >> TR is a triangle signal, Vph1 and Vph2 are used to limit duty >> cycle on >> push-pull output. U1 and U6 are used as error amplifier. Vct is as I >> expect. Q1 is an automatic gain control to constrain TR amplitude. >> Results seem to be good. >> > [..] >> Using transient initial conditions >> doAnalyses: TRAN: Timestep too small; time = 0.000248895, timestep = >> 1.25e-18: trouble with node "v.xu2.v1#branch" >> >> I only show Vct (clock of flip flop, active on positive edge), Q1 and >> Q2. Q1 = not(Q2). Well. But for example, at 48 µs, there is a transition >> on flip flop output without any positive edge on clock input. >> At 19 µs, Q2 == 0. Thus, after positive edge, Q1 should be null... >> >> Simple question: is there a mistake in my schematic, is there a >> bug in >> 74HCT74 model or a issue with ngspice ? > > Specualtion: it is easy to set up a simulation such that NGSPICE misses an > asynchronous event. It is almost guaranteed to happen when there > is no reasonable STEPMAX defined (or implied) on the .TRAN line. I will try. >> But for example, at 48 µs, there is a transition >> on flip flop output without any positive edge on clock input. > > Adding gain in a feedback loop can create an algebraic loop. Some delay > (but also not too much) must be explicitly added to prevent the timestep > to go to zero. > > Your ftp server is not accessible from my browser, so that is as far > as I can go. Do you have error message ? I can send to you in private netlist and schematic if you want. Regards, JB |
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From: <mh...@ia...> - 2022-07-06 18:05:31
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On 2022-07-06 17:44, BERTRAND Joël wrote: [..] > TR is a triangle signal, Vph1 and Vph2 are used to limit duty cycle on > push-pull output. U1 and U6 are used as error amplifier. Vct is as I > expect. Q1 is an automatic gain control to constrain TR amplitude. > Results seem to be good. > [..] > Using transient initial conditions > doAnalyses: TRAN: Timestep too small; time = 0.000248895, timestep = > 1.25e-18: trouble with node "v.xu2.v1#branch" > > I only show Vct (clock of flip flop, active on positive edge), Q1 and > Q2. Q1 = not(Q2). Well. But for example, at 48 µs, there is a > transition > on flip flop output without any positive edge on clock input. > At 19 µs, Q2 == 0. Thus, after positive edge, Q1 should be null... > > Simple question: is there a mistake in my schematic, is there a bug in > 74HCT74 model or a issue with ngspice ? Specualtion: it is easy to set up a simulation such that NGSPICE misses an asynchronous event. It is almost guaranteed to happen when there is no reasonable STEPMAX defined (or implied) on the .TRAN line. > But for example, at 48 µs, there is a transition > on flip flop output without any positive edge on clock input. Adding gain in a feedback loop can create an algebraic loop. Some delay (but also not too much) must be explicitly added to prevent the timestep to go to zero. Your ftp server is not accessible from my browser, so that is as far as I can go. -marcel |
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From: BERTRAND J. <joe...@sy...> - 2022-07-06 15:45:04
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Hello, I'm working on a push-pull converter and I obtain strange simulation results. Files are on a anonymous ftp (ftp://fermat.systella.fr), in ngspice directory. Don't forget to use binary mode, this server runs with OpenVMS. Schematic: SIM_CONVERTISSEUR_HT.PDF You can see that U3 is disabled. Without U3, I can simulate this circuit between 0 and 100 ms (SIM_CONVERTISSEUR_HT_WO_FF.CIR and RESULTS_RAW.BZ2). Be careful if you want to simulate this netlist, this simulation takes around 3 hours on my i9@4.8 GHz (but I'm not sure that you can more quickly download RESULTS_RAW.BZ2). TR is a triangle signal, Vph1 and Vph2 are used to limit duty cycle on push-pull output. U1 and U6 are used as error amplifier. Vct is as I expect. Q1 is an automatic gain control to constrain TR amplitude. Results seem to be good. Now, I add U3 in simulation. I have tried some different models with the same result. Model I have put on ftp comes from TI (and I have tested this model with a simple circuit without any trouble). ngspice hangs with : hilbert:[~/cvs/electronique/sim_convertisseur_ht] > ngspice sim_convertisseur_ht.cir ****** ** ngspice-37+ : Circuit level simulation program ** The U. C. Berkeley CAD Group ** Copyright 1985-1994, Regents of the University of California. ** Copyright 2001-2022, The ngspice team. ** Please get your ngspice manual from http://ngspice.sourceforge.net/docs.html ** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html ** Creation Date: Tue Jul 5 14:20:33 UTC 2022 ****** ... Using transient initial conditions doAnalyses: TRAN: Timestep too small; time = 0.000248895, timestep = 1.25e-18: trouble with node "v.xu2.v1#branch" tran simulation(s) aborted Reducing trtol to 1 for xspice 'A' devices Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 Warning: v6: no DC value, transient time 0 value used Warning: v1: no DC value, transient time 0 value used binary raw file "results.raw" free(): invalid pointer Abandon hilbert:[~/cvs/electronique/sim_convertisseur_ht] > OK, I have to modify a parameter somewhere (but where ?) to run this simulation until 100 ms. That being said, I have tried to analyze this aborted simulation. You will find a screen capture in 74HCT74.PNG. I only show Vct (clock of flip flop, active on positive edge), Q1 and Q2. Q1 = not(Q2). Well. But for example, at 48 µs, there is a transition on flip flop output without any positive edge on clock input. At 19 µs, Q2 == 0. Thus, after positive edge, Q1 should be null... Simple question: is there a mistake in my schematic, is there a bug in 74HCT74 model or a issue with ngspice ? Best regards, JB |
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From: BERTRAND J. <joe...@sy...> - 2022-07-06 08:55:31
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Hello, For several days, I see at the end of simulation free(): invalid pointer or double corruption error valgrind shows Invalid free() / delete / delete[] / realloc() with the following trace : ==770496== Invalid free() / delete / delete[] / realloc() ==770496== at 0x484217B: free (vg_replace_malloc.c:872) ==770496== by 0x488D85E: cm_pswitch_callback (cfunc.c:90) ==770496== by 0x93F274: MIFdelete (mifdelete.c:92) ==770496== by 0x488869A: MIFdelete (dlmain.c:202) ==770496== by 0x9052F3: CKTdestroy (cktdest.c:53) ==770496== by 0x220D6A: if_cktfree (spiceif.c:587) ==770496== by 0x21C4BA: com_remcirc (runcoms2.c:218) ==770496== by 0x2070FB: com_quit (misccoms.c:106) ==770496== by 0x1C95BE: docommand (control.c:241) ==770496== by 0x1C9F06: doblock (control.c:535) ==770496== by 0x1CB62E: cp_evloop (control.c:870) ==770496== by 0x1E4066: inp_spsource (inp.c:1124) ==770496== Address 0x6d052a0 is 0 bytes inside a block of size 64 free'd ==770496== at 0x484217B: free (vg_replace_malloc.c:872) ==770496== by 0x488D85E: cm_pswitch_callback (cfunc.c:90) ==770496== by 0x93D9C1: MIFunsetup (mifsetup.c:551) ==770496== by 0x4888523: MIFunsetup (dlmain.c:146) ==770496== by 0x90898B: CKTunsetup (cktsetup.c:168) ==770496== by 0x9062B9: CKTdoJob (cktdojob.c:152) ==770496== by 0x220479: if_run (spiceif.c:358) ==770496== by 0x21BDCB: dosim (runcoms.c:332) ==770496== by 0x21BFBC: com_run (runcoms.c:394) ==770496== by 0x1C95BE: docommand (control.c:241) ==770496== by 0x1C9F06: doblock (control.c:535) ==770496== by 0x1CB62E: cp_evloop (control.c:870) ==770496== Block was alloc'd at ==770496== at 0x48445EF: calloc (vg_replace_malloc.c:1328) ==770496== by 0x488D9EF: cm_pswitch (cfunc.c:190) ==770496== by 0x93A4E5: MIFload (mifload.c:447) ==770496== by 0x4888553: MIFload (dlmain.c:153) ==770496== by 0x916CDB: CKTload (cktload.c:64) ==770496== by 0x9F2693: NIiter (niiter.c:40) ==770496== by 0x91719C: CKTop (cktop.c:44) ==770496== by 0x941943: EVTop (evtop.c:135) ==770496== by 0x91BDCA: DCtran (dctran.c:212) ==770496== by 0x90649B: CKTdoJob (cktdojob.c:232) ==770496== by 0x220479: if_run (spiceif.c:358) ==770496== by 0x21BDCB: dosim (runcoms.c:332) I have tried to fix this issue, but there is a lot of cfunc.c files... That being said, MIFunsetup and MIFdelete try to free the same pointer. Best regards, JB |
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From: BERTRAND J. <joe...@sy...> - 2022-05-31 07:06:22
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Holger Vogt a écrit : > According to the Vishay data sheet > https://www.vishay.com/docs/91021/irf540.pdf the on resistance of the > irf540 is below 77mOhms at 10 V VGS and 17 A pulsed. The simulation > shows a current i(V5) of max 40 A. Right. My first simulation was done with only 10A with the same result (and an IRF540N). In a second try, I have increased current (above max current in datasheet). I forgot to check Vds Vds according Ids... Sorry for the noise. Best regards, JB |
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From: Holger V. <hol...@un...> - 2022-05-31 06:24:04
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According to the Vishay data sheet https://www.vishay.com/docs/91021/irf540.pdf the on resistance of the irf540 is below 77mOhms at 10 V VGS and 17 A pulsed. The simulation shows a current i(V5) of max 40 A. 40 A x 0.077 Ohms = 3 V. The spice model probably offers a somewhat smaller on resistance, you have a higher VGS (15 V), but nevertheless there will be some voltage drop across the transistor. |
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From: BERTRAND J. <joe...@sy...> - 2022-05-30 18:57:05
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Holger Vogt a écrit :
> SIM_REDRESSEMENT_SYNCHRONE.KICAD_SCH;1 is empty?
Issue with owner... Seems to be fixed now:
$ dir /size/owner
Directory DISK$OPT:[ANONYMOUS.SYNC_RECTIFIER]
1N5245B.LIB;1 1 [TCPIP,ANONYMOUS]
IRF540.LIB;1 4 [TCPIP,ANONYMOUS]
IRF9540.LIB;1 4 [TCPIP,ANONYMOUS]
MBR40250.LIB;1 2 [TCPIP,ANONYMOUS]
RESULTS.RAW;1 29782 [TCPIP,ANONYMOUS]
SIM_REDRESSEMENT_SYNCHRONE.CIR;1
4 [TCPIP,ANONYMOUS]
SIM_REDRESSEMENT_SYNCHRONE.KICAD_PCB;1
1 [TCPIP,ANONYMOUS]
SIM_REDRESSEMENT_SYNCHRONE.KICAD_PRL;1
3 [TCPIP,ANONYMOUS]
SIM_REDRESSEMENT_SYNCHRONE.KICAD_PRO;1
12 [TCPIP,ANONYMOUS]
SIM_REDRESSEMENT_SYNCHRONE.KICAD_SCH;1
129 [TCPIP,ANONYMOUS]
SIM_REDRESSEMENT_SYNCHRONE.PDF;1
93 [TCPIP,ANONYMOUS]
Total of 11 files, 30035 blocks.
Please retry.
Best regards,
JKB
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From: Holger V. <hol...@un...> - 2022-05-30 18:16:18
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SIM_REDRESSEMENT_SYNCHRONE.KICAD_SCH;1 is empty? |
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From: BERTRAND J. <joe...@sy...> - 2022-05-30 17:50:01
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Hello, I'm trying to simulate a synchronized rectifier. All files (schematics, netlist, models and result of simulation) have been uploaded on an anonymous ftp running on fermat.systella.fr on directory SYNC_RECTIFIER. Please note that fermat runs with OpenVMS. Filenames can be strange for a Unix user, but ftp commands are similar to Unix ftp (but please use binary transfer). $ ncftp fermat.systella.fr NcFTP 3.2.5 (Feb 02, 2011) by Mike Gleason (http://www.NcFTP.com/contact/). Connecting to 192.168.10.107... fermat.systella.fr FTP Server (Version 5.3) Ready. Logging in... Anonymous User Account, please use binary transfer Guest login OK, access restrictions apply. Logged in to fermat.systella.fr. ncftp DUA2:[ANONYMOUS] > cd sync_rectifier New default directory is DUA2:[ANONYMOUS.SYNC_RECTIFIER] ncftp ...NYMOUS]/sync_rectifier > ls Directory DUA2:[ANONYMOUS.SYNC_RECTIFIER] 1N5245B.LIB;1 1/3 30-MAY-2022 19:14:37 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) IRF540.LIB;1 4/6 30-MAY-2022 19:15:09 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) IRF9540.LIB;1 4/6 30-MAY-2022 19:15:21 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) MBR40250.LIB;1 2/3 30-MAY-2022 19:16:00 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) RESULTS.RAW;1 29782/29784 30-MAY-2022 18:53:34 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) SIM_REDRESSEMENT_SYNCHRONE.CIR;1 4/6 30-MAY-2022 18:53:31 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) SIM_REDRESSEMENT_SYNCHRONE.KICAD_PCB;1 1/3 30-MAY-2022 16:19:16 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) SIM_REDRESSEMENT_SYNCHRONE.KICAD_PRL;1 3/3 30-MAY-2022 16:40:56 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) SIM_REDRESSEMENT_SYNCHRONE.KICAD_PRO;1 12/12 30-MAY-2022 18:53:31 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) SIM_REDRESSEMENT_SYNCHRONE.KICAD_SCH;1 0/129 30-MAY-2022 18:53:26 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) SIM_REDRESSEMENT_SYNCHRONE.PDF;1 93/93 30-MAY-2022 18:54:57 [TCPIP,ANONYMOUS] (RWED,RWED,RE,) Total of 11 files, 29906/30048 blocks ncftp ...NYMOUS]/sync_rectifier > get SIM_REDRESSEMENT_SYNCHRONE.PDF SIM_REDRESSEMENT_SYNCHRONE.PDF: 47551 bytes 224,93 kB/s ncftp ...NYMOUS]/sync_rectifier > quit Maybe I have done a mistake but I don't understand results of this simulation. For example, VP1 varies between 0V and 15V. But when Q2's gate is polarized, Vinm remains at -1V. I waited for 0V... Maybe my models are broken, but I have tried with three different models with the same result (of course, current are different, but Vinm remains at -1V). Help will be welcome. Best regards, JB |
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From: BERTRAND J. <joe...@sy...> - 2022-03-22 17:44:47
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John Doty a écrit : > The fact that v2#branch is identified here suggests that the root cause > is that V2 is an ideal voltage source with zero resistance, capable of > sourcing unbounded current. Thais can make convergence difficult to > achieve. I suggest adding a simulated resistor in series. The value > should represent a reasonable estimate of the resistance of your signal > source, 50Ω perhaps. Thanks a lot; With a 50R resistor on 100kHz line, simulation runs better : Warning: v2: no DC value, transient time 0 value used Using transient initial conditions %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%68.72ence value : 6.87210e-01rence value : 1.00045e-01 I hope it will continue until 100%. Best regards, JB |
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From: BERTRAND J. <joe...@sy...> - 2022-03-22 16:16:58
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Hello, I'm trying to simulate a charge pump (from 0 to 1s). Schematic contains a boost (5V to 86V) followed by a charge pump (86V to -86V). files are attached. I haven't attached BC337/327 models. $ ngspice sim_pompe_de_charge.cir ****** ** ngspice-36 : Circuit level simulation program ** The U. C. Berkeley CAD Group ** Copyright 1985-1994, Regents of the University of California. ** Copyright 2001-2020, The ngspice team. ** Please get your ngspice manual from http://ngspice.sourceforge.net/docs.html ** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html ****** Compatibility modes selected: ps a Circuit: KiCad schematic Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 Warning: v2: no DC value, transient time 0 value used Using transient initial conditions doAnalyses: TRAN: Timestep too small; time = 0.0710825, timestep = 1.25e-18: trouble with node "v2#branch" tran simulation(s) aborted Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 Warning: v2: no DC value, transient time 0 value used binary raw file "results.raw" ngspice-36 done I have tried to change gmin and some other parameters without success. How can I simulate this circuit until 1s ? Best regards, JB |
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