ngspice-users — The users mailing list for ngspice (general discussions).

Re: [Ngspice-users] Voltage/Temperature equation based capacitor device doesn't work as expected.

[Holger V. <hol...@un...>]

Within your post there are two files included named cap_compare.ipynb.

I do not have a tool to process them.

What are your expectations in relation to the results you have sent?

Holger

Re: [Ngspice-users] Voltage/Temperature equation based capacitor device doesn't work as expected.

[Holger V. <hol...@un...>]

Postings with attachments beyond a certain size require moderator approval.

Done.

[Ngspice-users] Voltage/Temperature equation based capacitor device doesn't work as expected.

[Amro T. <amr...@ma...>]

Dear NG-Spice Developers,
 
I'm Amro Tork. I'm the Founder of Mabrains. We are the ones who migrated the model cards to ngspice and tested it and made sure they work for GF180MCU PDK.
 
We have a problem with one of the models that we are working on.
We see that the equation based voltage dependent or temperature dependent capacitor doesn't work as expected when the equation has voltages or temper or temp variables.. I'm not sure why.
 
Mohamed Monem, here from Mabrains, has created multiple test cases that demonstrate that behavior. I would really appreciate if you can take a look at the test cases.
 
Best Regards,
Amro Tork
 
Founder
 
Email: amr...@ma... mailto:amr...@ma...
Website:http://www.mabrains.com
 
 

---------------------------------------------
Mabrains
www.mabrains.com https://www.mabrains.com/
 
CONFIDENTIAL COMMUNICATION: This email and any attachments thereto may contain private and confidential material for the sole use of the intended recipient. Any review, copying, or distribution of this email (or any attachments thereto) by others is strictly prohibited. If you are not the intended recipient, please contact the sender immediately and permanently delete the original and any copies of this email and any attachments thereto.
 

Re: [Ngspice-users] Finfet inverter fails

[Holger V. <hol...@un...>]

I do not understand your circuit.

xdriverA vdd vss in_A _eA driver
seems to be o.k.

In
.subckt invx3_asap7_75t_r vss vdd a y
there are 6 transistors. All of their drain coonections n_m0_d to n_m5_d 
are floating as the connecting resistors are commented out. So
x vss vdd a y invx3_asap7_75t_r m=1
cannot work correctly.

Holger

[Ngspice-users] Finfet inverter fails

[Mehmet C. <ma...@li...>]

I have attached a test circuit for ngspice 40, no mpi. It is using finfet
models and cells from openpdk asal7. OSDI file is generated using openvaf
23.2.0.  I changed 'm' devices to 'n' device type in the netlist.
In the model files I have replaced nmos level 72 with BSIMCMG_va type=1,
and pmos with
BSIMCMG_va type=-1. The example model file uses type=0 for pmos, while the
original modes had no such variable. Changing type to 0 or -1
make a little bit difference in the numbers, but it still is not functional.

I tried with two different .tran lines changing the first argument.
There is a min step size issue with both, in one case it completes
simulation, it aborts in the second case.

Openvaf test suite reports illegal instruction core dumps for some models.
In this case, it did not.

There may be a false transient convergence issue or there may be a problem
with OSDI. This circuit works with Xyce.

Regards


-- 
http://www.linkedin.com/in/mehmetcirit

Dr. Mehmet A. Cirit                    Phone:  (408) 647-6025
<http://voice.google.com/calls?a=nc,%2B14086476025>
Library Technologies, Inc.        Cell:       (408) 647-6025
<http://voice.google.com/calls?a=nc,%2B14086476025>
19959 Lanark Lane                   http://www.libtech.com
Saratoga, CA 95070                 Email: ma...@li...

Re: [Ngspice-users] Users list

[Holger V. <hol...@un...>]

You have to do it yourself, I do not have any means to put somebody onto 
the list.

[Ngspice-users] Users list

[Richard A. <ric...@ya...>]

Hello,

        I would like to be put on the User's list, Thank you.

Re: [Ngspice-users] strange error: no such vector

[David <bou...@gm...>]

On Wed, 24 May 2023 at 07:31, Holger Vogt <hol...@un...> wrote:

> No problem to run this netlist with or without tran command (ngspice-40,
> Windows10).

Also no problem with or without tran command
on Debian 11 with
$ apt list ngspice
ngspice/stable,now 34+ds-1 amd64 [installed]
$ ngspice --version
[david@kablamm ~]$ ngspice --version
******
** ngspice-34 : Circuit level simulation program
[...]
** Creation Date: Sun Jan 31 11:43:30 UTC 2021
******

Re: [Ngspice-users] strange error: no such vector

[Holger V. <hol...@un...>]

No problem to run this netlist with or without tran command (ngspice-40, 
Windows10).

Re: [Ngspice-users] strange error: no such vector

[<rs...@di...>]

On 2023-05-23 20:16, Holger Vogt wrote:

> This is an issue of vectors and plots, global and local availability of 
> vectors.
> 
> You may have a look at 
> https://ngspice.sourceforge.io/ngspice-control-language-tutorial.html#plots 
> or at the manual, chapt. 17.3 Plots.

I actually closely followed the tutorial you mention...


> Your simplified netlist probably does not show the root cause (is 
> vector 'a' residing in plot 'const' (globally available) or generated 
> in another plot (then 'a' is local to that specific plot).

The full netlist (still simplifies, but showing the issue anyhow) is:
------------------------------
* MWPC simulation
Q1 NC1 NB1 0 0 2N3904
Q2 NC3 NB2 NE2 0 2N3904
Q3 NC3 NB3 NC1 0 2N3906
R1 0 NB2 3k
R2 NB2 NVEE 3k
R3 NE2 NVEE 3k
R4 NVCC NC1 6k
R5 NVCC NB3 8.2k
R6 NB3 0 4.3k
R7 NVCC NB1 1Meg
V1 0 NVEE 12
V2 NVCC 0 12
Q5 NVEE NC3 NE5 0 2N3906
R8 NE5 NVCC 6.2k
V3 NV3 0 0 SINE(0 1m 10meg)
R10 NV3 NV3R 1k
C1 NB1 NV3R 4n
C2 0 NC3 4n
C3 NC3 NB1 20p
R9 NC3 NB1 200k
.model 2N3904 NPN
.model 2N3906 PNP
*
.control
let a = 1e3
alter R4 $&a
*tran 10n 10u 1u
let a =  a + 1e3
echo $&a
.endc
.end
------------------------------

which makes me believe the 'a' is global and there should not be the 
problem...
Or where am I wrong?

Thank you for any further comments.

Best regards,
Ruda

Re: [Ngspice-users] strange error: no such vector

[Holger V. <hol...@un...>]

This is an issue of vectors and plots, global and local availability of 
vectors.

You may have a look at 
https://ngspice.sourceforge.io/ngspice-control-language-tutorial.html#plots 
or at the manual, chapt. 17.3 Plots.

Your simplified netlist probably does not show the root cause (is vector 
'a' residing in plot 'const' (globally available) or generated in 
another plot (then 'a' is local to that specific plot).

[Ngspice-users] strange error: no such vector

[Rudolf S. <rud...@gm...>]

Dear list,


I have a control section like (simplified)

.control
let a = 1e3
alter R4 $&a
* tran 10n 10u 1u
let a =  a + 1e3
echo $&a
.endc

and this works ok, ie, with no error.
If I uncomment the 'tran' line, I get

Error(parse.c--checkvalid): a: no such vector.
Error: RHS "a + 1e3" invalid
Error: &a: no such variable.

I do not understand why.
Thanks for any comments.


Best regards,
Ruda

[Ngspice-users] Question about use and right citation for a book

[Miguel E. F. G. <mef6772@g.rit.edu>]

Hi,
I want to write a book about electronics and Open EDA tools, so  I wanted
to know if I could use ngspice netlist, graphs, and results in my book.
Also, I wanted to know the right way to cite it.

Thanks in advance.

Regards.

MEF

Re: [Ngspice-users] Ngspice - Query

[<mh...@ia...>]

On 2023-03-09 10:21, ALAM Md Moktarul wrote:
[..]
> 1.            IS THERE ANY WAY TO SUPPLY INPUT VECTOR TO THE SIMULATOR
> AT EACH TIME STEP?

When you insert your own XSPICE device (it does not need to actually
do anything) in a netlist, it will automatically be called at every
timestep. If your device has outputs, you can connect these outputs
to any node of the main circuit. See also my answer to #2.

BTW: a subcircuit would also work, but then you have much less
powerful ways of reacting to the events/time steps.

> 2.            IS IT POSSIBLE TO CHANGE THE NETLIST DYNAMICALLY AT EACH
> TIME STEP?

This is essentially what happens in a switched-mode powersupply. IOW,
you can add switches to any circuit to discontinuously change it to a
completely or partially different topology. If the resultant circuit
is not physical (does not conserve energy and/or charge), NGSPICE will
have problems simulating it, just as it has with 'real' SMPS circuitry.
But it is perfectly doable.

It would be easier if you just gave an example of what you are trying
to do.

-marcel

Re: [Ngspice-users] Ngspice - Query

[Giles A. <ga...@bt...>]

Actually, I think the answer to question 1 is "yes".  I believe there is a callback to the enclosing program at each step when using the shared library version, and the program could then supply new values to EXTERNAL voltage sources.  Or one could write a dedicated XSPICE model.

Giles

On 17 Mar 2023, at 17:31, Kevin Zheng wrote:

> Hi there,
> 
> Could you explain in a bit more detail what you're trying to do? That might help us suggest a better way to accomplish your goal.
> 
> On 3/9/23 1:21 AM, ALAM Md Moktarul wrote:
>> *1. Is there any way to supply input vector to the simulator at each
>> time step?*
> 
> No, ngspice decides when to take each time step.
> 
> However, you can use a piece-wise linear independent voltage (or current) source to supply fixed time-varying inputs into your circuit.
> 
>> *2. Is it possible to change the netlist dynamically at each time
>> step?*
> 
> Also generally no. Some devices and device parameters can be changed between simulations using the ALTER command, but you cannot generally change your netlist "dynamically" while your simulation is running.
> 
> However, you *can* simulate switched capacitor or other multi-phased circuits by putting the appropriate switches in your netlist.
> 
> Regards,
> Kevin
> 
> 
> _______________________________________________
> Ngspice-users mailing list
> Ngs...@li...
> https://lists.sourceforge.net/lists/listinfo/ngspice-users

Re: [Ngspice-users] Ngspice - Query

[Kevin Z. <kev...@gm...>]

Hi there,

Could you explain in a bit more detail what you're trying to do? That 
might help us suggest a better way to accomplish your goal.

On 3/9/23 1:21 AM, ALAM Md Moktarul wrote:
> *1. Is there any way to supply input vector to the simulator at each
> time step?*

No, ngspice decides when to take each time step.

However, you can use a piece-wise linear independent voltage (or 
current) source to supply fixed time-varying inputs into your circuit.

> *2. Is it possible to change the netlist dynamically at each time
> step?*

Also generally no. Some devices and device parameters can be changed 
between simulations using the ALTER command, but you cannot generally 
change your netlist "dynamically" while your simulation is running.

However, you *can* simulate switched capacitor or other multi-phased 
circuits by putting the appropriate switches in your netlist.

Regards,
Kevin

[Ngspice-users] Question about using NGspice in a book

[Miguel E. F. G. <mig...@ud...>]

Hi,
I want to write a book about electronics and Open EDA tools, so  I wanted
to know if I could use ngspice netlist, graphs, and results in my book.
Also, I wanted to know the right way to cite it.

Thanks in advance.

Regards.

Miguel E. Flores
Ingeniero en Electrónica / Electronic engineer
Máster en Manufactura Microelectrónica / M.E. Microelectronic Manufacturing
Docente/Professor.
Universidad Don Bosco / Don Bosco University
Phone +(503) 2251-8200 ext. 1752
https://orcid.org/0000-0003-0514-6239
SCOPUS 57216866683
*- Carpe Diem*
*- *La prédica más eficaz es el buen ejemplo. San Juan Bosco.
 (The most effective preaching is a good example, St Juan Bosco)

-- 
*AVISO DE CONFIDENCIALIDAD:* Este mensaje y cualquier archivo adjunto al 
mismo, se dirige exclusivamente a su(s) destinatario(s), y no puede ser 
compartido o reenviado a un tercero sin autorización del remitente. Solo 
puede ser utilizado por las personas o entidades a las cuales está 
dirigido. 
Si usted no es el destinatario al que ha sido remitida esta 
información, queda prohibida, cualquier modificación, retención, difusión o 
copia total o parcial, y no puede emprender con ella ningún tipo de acción. 
Le rogamos que lo comunique inmediatamente por esta misma vía y proceda a 
su eliminación.
Si es miembro de la Comunidad Educativa de la UDB y viola 
lo anterior será sujeto a sanción disciplinaria conforme al Art.134, 
literales “r”, “s”, y “t” del Reglamento General Administrativo-Académico. 

*CONFIDENTIALITY NOTICE:* The content of this email and any attachments 
are intended solely for the addressee(s). The information cannot be shared 
without the authorization of the sender. It can only be used by the 
intended recipients.
If you are not the intended recipient, you are hereby 
notified that any modification, dissemination, full or partial copy of this 
email is forbidden. You must not take any kind of action in reliance on it. 
Please, notify the sender by replying to this email and delete the message 
without copying or disclosing it.
If you are a member of the UDB community 
and were to violate the foregoing, you will be subject to disciplinary 
actions in accordance to Article 134, literal “r”, “s”, and “t” of the 
General Administrative-Academic Regulations.

[Ngspice-users] Ngspice - Query

[ALAM Md M. <mdm...@es...>]

Dear Sir/Madam, Good morning,

My name is Md Moktarul Alam, PhD student at the ESEO School of Engineering in France. I'm currently working with Ngspice, and since I could not find a clear answer to the two following questions in the user manual, I would greatly appreciate if you could help me with that.

1.            Is there any way to supply input vector to the simulator at each time step?
2.            Is it possible to change the netlist dynamically at each time step?

I'm eager to receive your feedback.

Thank you.
Md Moktarul Alam

Re: [Ngspice-users] Enquire about L-UTSOI model support on Ngspice

[Holger V. <hol...@un...>]

Hi Jeff,

thanks for your inquiery.

Today there are two methods to integrate a compact model into ngspice:

Take a spice-compatible C coded model and compile it into ngspice.

Compile a Verilog-A coded model with OpenVAF into a shared library and 
add this model to ngspice at runtime.

As the first route requires a C coded model, and nobody today is 
offering such a model version, this is no longer adequate for adding new 
models.

Since ngspice-39 the second road is strongly preferred:
- Grab a Verilog-A model (e.g. L-UTSOI)
- Compile it with OpenVAF (once only) into a shared library
- At ngspice start-up load load this shared lib into ngspice 
(automatically or manually)
- Prepare the netlist (with suitable N devices)
- Grab adequate model parameters
- Run the simulation as usual

A short intro is available at https://ngspice.sourceforge.io/osdi.html

Please have a look at the ngspice manual, chapter 13 
(https://ngspice.sourceforge.io/docs/ngspice-manual.pdf) for a detailed 
description of the procedure.

Examples are shown at 
https://sourceforge.net/p/ngspice/ngspice/ci/master/tree/examples/osdi/

Verilog-A compact models are available from 
https://github.com/dwarning/VA-Models or from CMC or the original 
developers.

OpenVAF is described in detail and made available at 
https://openvaf.semimod.de/.

MS Windows users will get some of the Verilog-A models compiled and 
ready for usage with the current downloads at 
https://sourceforge.net/projects/ngspice/files/ng-spice-rework/39/ngspice-39_64.7z/download 
. We may add L-UTSOI, but would need some support from users (model 
parameters, test cases).

Linux users may have to compile the models themselves, but only once in 
the beginning, then they may simulate as usual.

macOS is currently not supported by OpenVAF. Please enquire art semimod 
(https://semimod.de/projects/) if this is urgently needed.

Adaption to commercial PDKs may be still necessary, and can only be done 
with the support of users (as the ngspice developers typically don't 
have access to such PDKs).

Regards

Holger

[Ngspice-users] Enquire about L-UTSOI model support on Ngspice

[Jeff L. <jl...@pr...>]

Dear Ngspice Developer,

I am looking forward to running some circuit simulations on Ngspice with the L-UTSOI model.

L-UTSOI is based on PSP model, but it fits SOI technology better. It was used by Global Foundry and STMicroelectronics in their SOI PDK. It is a standard open-source model verified by CMC.
Si2 Compact Model Coalition to Support CEA-Leti SPICE Simulation Model - Silicon Integration Initiative<https://si2.org/2020/03/10/lutsol/>
L-UTSOI Support - Welcome (cea.fr)<https://www.cea.fr/cea-tech/leti/l-utsoisupport>
As this model is becoming more and more popular for the FD-SOI technology, is there any chance to add this model to the default model list? Rather than use the L-UTSOI Verilog-A code each time?

It would help Non-profit organizations (Students or Researchers) to do more circuit design.

Thanks for your open-source Ngspice developing works again, it lowers the bar to study and develop microelectronics!


Best regards,

Xinjie(Jeff) Liu

Disclaimer: This email and files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error, please let us know by replying to the sender and immediately deleting this email from your system. Please note that in these circumstances the use, disclosure, distribution or copying of the information contained within this email is strictly prohibited. PragmatIC does not accept any responsibility for the accuracy or completeness of this message. If you suspect that the message may have been intercepted or amended please contact the sender. PragmatIC is trading name and a trademark of PragmatIC Semiconductor Limited, a company registered in England and Wales with company number 07423954.

[Ngspice-users] Warning: temperature adjusted grading coefficient too large

[Francis T. <frt...@gm...>]

Hi,

When running a circuit that includes the HCNR200 model, which can be 
found here 
(https://www.broadcom.com/products/optocouplers/industrial-plastic/specific-function/high-linearity-analog/hcnr200), 
ngspice gives the following warnings:

Warning: d.xu1.dpd2: temperature adjusted grading coefficient too large, 
limited to 0.9

Warning: d.xu1.dpd1: temperature adjusted grading coefficient too large, 
limited to 0.9

Note: I have also copied a "cleaned up" version of the model here: 
https://gist.github.com/auxym/6d68b6d72a54f150fb1d3921eb2d46ee

When using the same model in LTSpice for example, I do not get these 
warnings.

Thank you

Francis

Re: [Ngspice-users] Is the temperature eqution in manual 1.3 section correct?

[Holger V. <hol...@un...>]

Many thanks for your input.
A fix is uploaded to ngspice manuals branch.

[Ngspice-users] Is the temperature eqution in manual 1.3 section correct?

[Shuo C. <gia...@gm...>]

NgSpice manual version 39, page 43, equation 1.1 and 1.3.
https://ngspice.sourceforge.io/docs/ngspice-39-manual.pdf
looks wrong because when T0 = T1, Is(T1) should be the same as Is(T0).
But the 2nd factor of exp[T1 * T0 / (T1 - T0)] diverges.

I think those equations are from the original SPICE3f5 manual:
http://bwrcs.eecs.berkeley.edu/Classes/IcBook/SPICE/UserGuide/overview_fr.html

>From the actual code (assuming correct), I believe the formula in the
doc swapped numerator and denominator.

https://github.com/ngspice/ngspice/blob/master/src/spicelib/devices/dio/diotemp.c#L152

The 2nd factor should be exp[Eg * q * (T1 - T0) / (N * k * T1 * T0)]
When T1 = T0, this factor becomes 1.

Regards,
Shuo Chen

[Ngspice-users] Errors/Glitches in the Documentation

[tobias f. <wie...@gm...>]

Dear NgSpice Team,

while working with the 
Documentation(https://ngspice.sourceforge.io/docs/ngspice-38-manual.pdf) 
for I found two errors/glitches, the first is on page 130, here the 
tabple goes over the page and the second one page 132, here the 
Parameter TM1 and TM2 are a second time in the table.

Greetings

Tobias Falk

Re: [Ngspice-users] ngspice model for rearmable fuse (CTP)

[Holger V. <hol...@un...>]

~~~
A1 set_break set_nobreak 0 0 0 N006 0 0 SRFLOP td=0.1u
~~~
is a LTSPICE specific call to a SR flip-flop (see 
https://ltwiki.org/index.php?title=Undocumented_LTspice#A-Devices for 
more information).

You may try to replace this call by a XSPICE SR flip-flop (see manual 
chapter 12.4.15 or 12.4.17).