Dietmar Warning

I like the paranoia tests - and initiated first version long time ago. But would it not better to shift paranoia_parallel to one hierarchy down, e.g. below tests? Only from logical POV.

set noise values to 0 in case no separate sidewall diode

stop adding nominal temperature to a temperature difference

stop adding nominal temperature to a temperature difference

Your contribution is welcome! Direct from conference in Ljubljana: One point missing is the paramset block command from Verilog-A Language Reference Manual LRM v2.4. To have this feature in PDK model libraries will drastically reduce our parse time, which is actual very large compared to other simulators. Beside this there are other benefits. But as Holger said we should prepare a list of missing things afterwards. KR Dietmar

Hi Diarmuid, we just told about new capabilities of IHP PDK for statistical simulation. I confused something: New (since March 26) is the feature to make MC global + local simulation with resistors. The entry is named res_stat_mismatch. For transistors we have only the shown corner + mismatch entries. Question is: How important is this feature for this kind of projects as yours? KR Dietmar Am Di., 17. März 2026 um 18:32 Uhr schrieb dick freebird dfreebird@users.sourceforge.net: Easiest way would...

Extracted circuits with not proper layout or insufficient extraction setup contain often ton´s of dangling capacitors. I could sing a song about ...

Not in a circuit description, but a equivalent case: We are using a voltage source in VDMOS thermal model to apply ckt temperature to the case node. It is direct stamped into the model MNA stamp together with a series resistor RTHCA. This branch is often in parallel to an external thermal network containing similar structure. Under appropriate parameter constellation we have two voltage sources nearly parallel only separated by their series resistors.