myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] Modelsim cosim.do do script file for testing missing

[Euripedes R. F. <roc...@gm...>]

Hi,
I'm running the cosimulation tests using modelsim and the comi.do file is
missing.
I fixed it using tha same code found in:
https://bitbucket.org/mattip/myhdl_fork/src/884f52072d3e?at=0.8-dev

Just pointing for some one with the same issue.

Another question is where are the right place to fork myhdl for start to
help on the development and place issues. I found some repos in github,
bitbucket and sourceforge.

Regards

Euripedes

Re: [myhdl-list] Using lists for repetitive signal routing. Code sample

[Jan C. <ja...@mu...>]

On 06/01/14 17:53, Christopher Felton wrote:
>    . . .
> This sounds to be a debug problem?  ...
Yes, thanks for the help, it must be a debug problem, but it will 
take me some time to find because the finished, but incompletely 
tested code is now rather complex.  I will have to try much harder 
to respect the freedom of interpreted code, and write the tests 
_first_ .

Below is sample test code for a bi-directional shift register, 
derived from the code you posted.  This shows that my debugged code 
will work, and I hope that it might be useful to someone else.

Jan Coombs.
-- 

#       BiDirSR_intbv.py

from myhdl import *

def BiDirShiftReg(q, u,d,u2q,clk):
   '''  '''
   @always(clk.posedge)
   def rtl():
     if u2q: q.next = u
     else:   q.next = d
   return rtl

u2q,clk = [Signal(bool(0)) for i in range(2)]
N = 4
ql = [Signal(intbv(8,max=15,min=0)[4:]) for i in range(N+2)]

def printQl():
   for ip in range(N+2):print ql[ip],
   print

bdsr = [None] * N
for i in range(N):
   bdsr[i] = BiDirShiftReg(ql[i+1], ql[i+2],ql[i],u2q,clk)

@instance
def tbstim():
   for i0 in range(2):
     u2q.next = i0
     clk.next = 0
     ql[0].next = 1
     ql[N+1].next = 0
     ql[0].next = 9
     ql[N+1].next = 4
     yield delay(10)
     printQl()
     for i1 in range(N):
       clk.next = 1; yield delay(10)
       clk.next = 0; yield delay(10)
       printQl()
     print

Simulation((tbstim,bdsr,)).run()

Re: [myhdl-list] modelsim co-simulation

[Euripedes R. F. <arq...@gm...>]

Yes The first answer was correct, Thank you! I also had to regenerate the
.so for 32 bit. Now I'm getting

invalid command name "cosim.do"

Will try to solve this now.

Thank you.



2014/1/6 Marcel Hellwig <1he...@in...>

> On 06.01.2014 20:01, Euripedes Rocha Filho wrote:
> > # ** Error: (vsim-3197) Load of "myhdl_vpi.so" failed: myhdl_vpi.so:
> > cannot open shared object file: No such file or directory.
> this is an import error ;) have you tried my first answer, namely adding
> the path of myhdl_vpi.so to LD_LIBRARY_PATH?
>
>
>
>
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>


-- 
Euripedes R. Filho

Re: [myhdl-list] modelsim co-simulation

[Marcel H. <1he...@in...>]

On 06.01.2014 20:01, Euripedes Rocha Filho wrote:
> # ** Error: (vsim-3197) Load of "myhdl_vpi.so" failed: myhdl_vpi.so:
> cannot open shared object file: No such file or directory.
this is an import error ;) have you tried my first answer, namely adding
the path of myhdl_vpi.so to LD_LIBRARY_PATH?

Re: [myhdl-list] modelsim co-simulation

[Euripedes R. F. <roc...@gm...>]

The complete error message for the first test

testSingleBitChange (test_bin2gray.TestGrayCodeProperties)
Check that only one bit changes in successive codewords ... Reading
/opt/mentor/modelsim_dlx/tcl/vsim/pref.tcl

# 10.1b

# vsim -do cosim.do -c -pli myhdl_vpi.so -quiet dut_bin2gray
# ** Error: (vsim-3197) Load of "myhdl_vpi.so" failed: myhdl_vpi.so: cannot
open shared object file: No such file or directory.
# ** Error: (vsim-PLI-3002) Failed to load PLI object file "myhdl_vpi.so".
#         Region: /
# //  ModelSim DE 10.1b Apr 26 2012 Linux 3.2.0-23-generic
# //
# //  Copyright 1991-2012 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Error loading design
Error loading design

I ad the x64 option in the make file uncomented.

It's x86_64 Ubuntu system.

 Euripedes


2014/1/6 Marcel Hellwig <1he...@in...>

> On 06.01.2014 19:43, Marcel Hellwig wrote:
> > myhdl_vpi.so: cannot open shared object file:
> maybe I have to correct myself :) does the shared object file has the x
> attribute? (chmod + x myhdl_vpi.so)
>
> Is it for the correct tar platform (x86_64 vs i686)?
> What does ``file'' say to myhdl_vpi.so? Is it a valid shared object?
>
> Greetings
>
>
>
> ------------------------------------------------------------------------------
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> organizations don't have a clear picture of how application performance
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>
>

Re: [myhdl-list] modelsim co-simulation

[Marcel H. <1he...@in...>]

On 06.01.2014 19:43, Marcel Hellwig wrote:
> myhdl_vpi.so: cannot open shared object file:
maybe I have to correct myself :) does the shared object file has the x
attribute? (chmod + x myhdl_vpi.so)

Is it for the correct tar platform (x86_64 vs i686)?
What does ``file'' say to myhdl_vpi.so? Is it a valid shared object?

Greetings

Re: [myhdl-list] modelsim co-simulation

[Marcel H. <1he...@in...>]

On 06.01.2014 19:36, Euripedes Rocha Filho wrote:
> myhdl_vpi.so: cannot open shared object file:
try this one:

http://stackoverflow.com/questions/15729137/setting-ld-library-path-environment-variable-for-loading-a-shared-library-at-run

Greetings

[myhdl-list] modelsim co-simulation

[Euripedes R. F. <arq...@gm...>]

Hi,
I'm trying to improve the test approach for a module under development and
after some consideration I follow the try myhdl.

I had the instalation for the 0.8 version done and I'm trying to cosimulate
unsig modelsim.

After instalation I run the test suite for the core and that pass, now I'm
trying to test the cosimulation with modelsim, the compilation was ok but
the tests do not pass.

First time I run  I have an error with the absence of the work library, I
manually created it using vlib amd now I'm getting the following error:

myhdl_vpi.so: cannot open shared object file:

Obviously it's a path issue but I don't know how to correct it and didn't
found the info in a web search.

My next task will be try to simulate a simple VHDL module wrapped in
verilog.

Anyone know how to fix the problem?

After the start of the simulation I'm planning to spend some time helping
to improve myhdl in any ways I can, since I'm advocating python as a high
level simulation language for some time here.


Regards

 --
Euripedes R. Filho

Re: [myhdl-list] Using lists for repetitive signal routing

[Christopher F. <chr...@gm...>]

On 1/5/2014 4:00 PM, Jan Coombs wrote:
> I am trying to connect a series of code blocks using
> lists.  The boolean signal lists are working, but the
> intbv list seem not to.

This sounds to be a debug problem?  I believe
you are describing a scenario similar to the
following:

     N = 4
     x = [Signal(intbv(ii)[32:]) for ii in range(N)]
     g = []
     for xx,yy in zip(x[:-1],x[1:]):
         g.append(m_something(xx,yy))

Where /m_something/ is the module that I am passing
one of the Signals from the list to (complete example
is at the end).

Is this what you are trying to achieve (or something
like it)?

Regards,
Chris

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     def m_something(x,y):
         @always_comb
         def rtl():
             y.next = x + 1
         return rtl

     N = 4
     x = [Signal(intbv(ii)[32:]) for ii in range(N)]
     g = []
     for xx,yy in zip(x[:-1],x[1:]):
         g.append(m_something(xx,yy))
     @instance
     def tbstim():
         x[0].next = 1
         yield delay(10)
         print(x)
         assert int(x[-1]) == int(x[0]) + N-1
     Simulation((tbstim,g,)).run()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

[myhdl-list] Using lists for repetitive signal routing

[Jan C. <jen...@mu...>]

I am trying to connect a series of code blocks using
lists.  The boolean signal lists are working, but the
intbv list seem not to.

The 4-12 instantiated code blocks are interconnected
partly like FIFOs.  A single bit shift type function is
working in both directions using a single list.

The intbv signal seems to get lost.  In myhdl simulation
I can see the signal changing on the module out port,
just before it is assigned to the list.  When assigning
list item content to a debug signal  I can only get zeros.

Does what I'm trying to do have any odd gotyas?  Is
there any sample pattern code available other than
Jan's myhdl RosettaCode adder demo?

It is very frustrating to be debugging 300 lines of code,
and not knowing clearly how it should be laid out.
Perhaps I _will_ write the tests first next time :)

Jan Coombs.
-- 

Re: [myhdl-list] emulate always_seq decorator

[Jan D. <ja...@ja...>]

On 12/27/2013 07:54 PM, Marcel Hellwig wrote:

> As you might see, I use @instance atm. But the problem is, that I have a
> reset signal and a clk signal, I want to use them both.

The yield statement is general:

http://www.myhdl.org/doc/current/manual/reference.html#myhdl-generators-and-trigger-objects

> Also, why is there the restriction, that you cannot use a generator
> function for @always... ?

Python generator functions are quite different than
normal functions in terms of behavior and usage.

Moreover, I don't think mixing implicit sensitity (in
an arguent list of a decorator) with explicit
sensitivity (with yield) is a good concept. This
concept is the same in VHDL.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] emulate always_seq decorator

[Marcel H. <ke...@co...>]

On 27.12.2013 17:25, Jan Decaluwe wrote:
> On 12/27/2013 09:01 AM, Marcel Hellwig wrote:
>> Hi everyone,
>>
>> one of my devices is using yield a lot (state machine), but the
>> decorators don't support generator functions.
> 
> The @instance decorator does. Why not simply use that?
> 
> Also, dynamic sensitivity lists are not supported in conversion.
> 
> Jan
As you might see, I use @instance atm. But the problem is, that I have a
reset signal and a clk signal, I want to use them both. But how does the
orignal always_seq is translated to vhdl code?
Also, why is there the restriction, that you cannot use a generator
function for @always... ?

Marcel

Re: [myhdl-list] emulate always_seq decorator

[Jan D. <ja...@ja...>]

On 12/27/2013 09:01 AM, Marcel Hellwig wrote:
> Hi everyone,
>
> one of my devices is using yield a lot (state machine), but the
> decorators don't support generator functions.

The @instance decorator does. Why not simply use that?

Also, dynamic sensitivity lists are not supported in conversion.

Jan

  So I looked up in the
> source and wrote my own 'always_seq' decorator.
>
>> @instance
>>      def genFunction():
>>          #we emulate a @always_seq(clk.posedge)
>>          senslist = [clk.posedge]
>>
>>          if reset.async:
>>              if reset.active:
>>                  senslist.append(reset.posedge)
>>              else:
>>                  senslist.append(reset.negedge)
>>
>>          while True:
>>              yield senslist
>>
>>              if reset == reset.active:
>>                  presetSignals()
>>                  state.next = tState.FETCH
>>              else:
>>                  yield logic()
>
>
> the problem is, that toVHDL is now complaining about a lof ot things
>
>> myhdl.ConversionError: in file /home/marcel/studium/WISE1314/Projekt/hardware/cpu.py, line 254:
>>      Not supported: list
> this is the senslist = [clk.posedge] line. And also
>> myhdl.ConversionError: in file /home/marcel/studium/WISE1314/Projekt/hardware/cpu.py, line 266:
>>      Unsupported attribute: active
>
> (if reset == reset.active).
>
> How do I tell myhdl that he should translate this as usual?! Or tell me
> a different method to use yield inside a always_seq decorated function.
>
> Greetings,
> Marcel
>
>
>
> ------------------------------------------------------------------------------
> Rapidly troubleshoot problems before they affect your business. Most IT
> organizations don't have a clear picture of how application performance
> affects their revenue. With AppDynamics, you get 100% visibility into your
> Java,.NET, & PHP application. Start your 15-day FREE TRIAL of AppDynamics Pro!
> http://pubads.g.doubleclick.net/gampad/clk?id=84349831&iu=/4140/ostg.clktrk
>
>
>
> _______________________________________________
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

[myhdl-list] emulate always_seq decorator

[Marcel H. <1he...@in...>]

Hi everyone,

one of my devices is using yield a lot (state machine), but the
decorators don't support generator functions. So I looked up in the
source and wrote my own 'always_seq' decorator.

> @instance
>     def genFunction():
>         #we emulate a @always_seq(clk.posedge)
>         senslist = [clk.posedge]
> 
>         if reset.async:
>             if reset.active:
>                 senslist.append(reset.posedge)
>             else:
>                 senslist.append(reset.negedge)
> 
>         while True:
>             yield senslist
> 
>             if reset == reset.active:
>                 presetSignals()
>                 state.next = tState.FETCH
>             else:
>                 yield logic()


the problem is, that toVHDL is now complaining about a lof ot things

> myhdl.ConversionError: in file /home/marcel/studium/WISE1314/Projekt/hardware/cpu.py, line 254:
>     Not supported: list
this is the senslist = [clk.posedge] line. And also
> myhdl.ConversionError: in file /home/marcel/studium/WISE1314/Projekt/hardware/cpu.py, line 266:
>     Unsupported attribute: active

(if reset == reset.active).

How do I tell myhdl that he should translate this as usual?! Or tell me
a different method to use yield inside a always_seq decorated function.

Greetings,
Marcel

[myhdl-list] tristate trace

[Marcel H. <1he...@in...>]

Hello *,

for a project at my university I use myhdl and need tristate signals.
The problem is/was that I cannot trace them, because they have a None
value, so I wrote a little fix.
This is far away from being perfect, but you may can discuss it and give
feedback.

Greetings
Marcel

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

>
> I pushed a couple changes last night to the
> repo.  Think I fixed (finally?) the VHDL build
> and added a work around for the UCF file.  I
> simply delete the project file every time and
> create a new one.  I did limited testing, I hope
> to test more tonight and any luck will release
> 0.0.3.
>

Little later than anticipated but I pushed out
0.0.3 [1][2].

Note on revisioning - I am using the major.minor.patch
revision scheme but considering 0.0 alpha and all
updates as patches till 0.1 :)

Regards,
Chris

[1] https://bitbucket.org/cfelton/myhdl_tools/downloads
[2] pip install myhdl_tools

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

On 12/3/2013 2:10 PM, Alexander Hungenberg wrote:
> Hi Chris
>
> well, at least I am glad you released it! :-)
> I also added some small improvements which made life easier for me
> with these tools and hope you like them (bitbucket pull request).
>
> Regarding the .ucf file: I can absolutely confirm the behaviour Thomas
> described. If I add the .ucf file myself using
>> brd.hdl_file_list.append('pone.ucf')
> it works the first time and fails afterwards (Ubuntu 13.10 64bit, ISE 14.5).
>
> Maybe a possible solution would be to find out in which config file
> Xilinx stores the used project source files and modify this directly?
> Alternatively, just deleting and recreating the xilinx directory every
> time one does a run() should work, too!
>
> Best,
> Alex
>

Alex,

Thanks for the pull request!  The changes
are great!  I merged them yesterday.

I pushed a change to simply delete the project
file on each invocation, hopefully that is a
suitable workaround.

Regards,
Chris

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

Thomas,

I pushed a couple changes last night to the
repo.  Think I fixed (finally?) the VHDL build
and added a work around for the UCF file.  I
simply delete the project file every time and
create a new one.  I did limited testing, I hope
to test more tonight and any luck will release
0.0.3.

Thanks again for all the feedback, this has been
fun collaborating!
Chris


On Tue, Dec 3, 2013 at 2:18 PM, Thomas Heller <th...@ct...> wrote:

> Am 03.12.2013 20:42, schrieb Christopher Felton:
> > Ugh, one of the reasons I hesitate and was uncertain
> > if I wanted to release this project or not,
> > compatibility and version issues can be difficult to
> > resolve :)
>
> I also find it great that yo released it.
>
> Software releases are done so that customers find the bugs,
> or maybe even submit patches.
>
> Thanks,
> Thomas
>
>
>
>
> ------------------------------------------------------------------------------
> Sponsored by Intel(R) XDK
> Develop, test and display web and hybrid apps with a single code base.
> Download it for free now!
>
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> _______________________________________________
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Thomas H. <th...@ct...>]

Am 03.12.2013 20:42, schrieb Christopher Felton:
> Ugh, one of the reasons I hesitate and was uncertain
> if I wanted to release this project or not,
> compatibility and version issues can be difficult to
> resolve :)

I also find it great that yo released it.

Software releases are done so that customers find the bugs,
or maybe even submit patches.

Thanks,
Thomas

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Alexander H. <ale...@gm...>]

Hi Chris

well, at least I am glad you released it! :-)
I also added some small improvements which made life easier for me
with these tools and hope you like them (bitbucket pull request).

Regarding the .ucf file: I can absolutely confirm the behaviour Thomas
described. If I add the .ucf file myself using
> brd.hdl_file_list.append('pone.ucf')
it works the first time and fails afterwards (Ubuntu 13.10 64bit, ISE 14.5).

Maybe a possible solution would be to find out in which config file
Xilinx stores the used project source files and modify this directly?
Alternatively, just deleting and recreating the xilinx directory every
time one does a run() should work, too!

Best,
Alex

2013/12/3 Christopher Felton <chr...@gm...>:
> <snip>
>>
>> Here is what I observe:
>>
>> Using fpga.run() to run synthesis, the ucf file is not used.
>> Starting the ISE GUI, I add the ucf-file to the sources file list,
>> and running fpga.run() again, the ucf file is used, and the pins are
>> located.  Starting fpga.run() again gies the same result.
>>
>> Remove the xilinx subdirectory completely.
>> I add 'xfile add myfile.ucf' to the code that generates the tcl
>> script, start fpga.run(), then everything works.
>> Starting fpga.run() a second time, I get an error that 'myfile.ucf'
>> is already part of the projects and sysnthesis fails.
>> I have to remove the xilinx subdirectory completely, then fpga.run()
>> works again.
>>
>> Whatever this means.
>>
>> Thomas
>>
>
> Ugh, one of the reasons I hesitate and was uncertain
> if I wanted to release this project or not,
> compatibility and version issues can be difficult to
> resolve :)
>
> I have some confidence that it the UCF is applied, at
> least on some version of ISE and some version of OS,
> otherwise this would have never worked:
> https://twitter.com/FeltonChris/status/360587567718080514
>
> I will play around and see if there is a better
> solution.  I do remember running into the the xfile
> add issue.  Maybe similar to the Altera TCL scripts,
> there is a way to force a *new* project every run - then
> the xfile would work.
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> Rapidly troubleshoot problems before they affect your business. Most IT
> organizations don't have a clear picture of how application performance
> affects their revenue. With AppDynamics, you get 100% visibility into your
> Java,.NET, & PHP application. Start your 15-day FREE TRIAL of AppDynamics Pro!
> http://pubads.g.doubleclick.net/gampad/clk?id=84349351&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

<snip>
>
> Here is what I observe:
>
> Using fpga.run() to run synthesis, the ucf file is not used.
> Starting the ISE GUI, I add the ucf-file to the sources file list,
> and running fpga.run() again, the ucf file is used, and the pins are
> located.  Starting fpga.run() again gies the same result.
>
> Remove the xilinx subdirectory completely.
> I add 'xfile add myfile.ucf' to the code that generates the tcl
> script, start fpga.run(), then everything works.
> Starting fpga.run() a second time, I get an error that 'myfile.ucf'
> is already part of the projects and sysnthesis fails.
> I have to remove the xilinx subdirectory completely, then fpga.run()
> works again.
>
> Whatever this means.
>
> Thomas
>

Ugh, one of the reasons I hesitate and was uncertain
if I wanted to release this project or not,
compatibility and version issues can be difficult to
resolve :)

I have some confidence that it the UCF is applied, at
least on some version of ISE and some version of OS,
otherwise this would have never worked:
https://twitter.com/FeltonChris/status/360587567718080514

I will play around and see if there is a better
solution.  I do remember running into the the xfile
add issue.  Maybe similar to the Altera TCL scripts,
there is a way to force a *new* project every run - then
the xfile would work.

Regards,
Chris

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Thomas H. <th...@ct...>]

Am 03.12.2013 03:51, schrieb Christopher Felton:
> On 12/2/13 12:38 PM, Thomas Heller wrote:
>> Am 02.12.2013 16:48, schrieb Christopher Felton:
>>> Thanks for the feedback!  I have fixed these
>>> issues and will push a new release, 0.0.2
>>> ASAP.
>>
>> Not so quick :-)
>>
>> Here are two other issues I found:
>>
>> 1. The ucf file is not added to the project file, so the pin mappings
>> are not used.
>>
>
> I don't observe the same behavior, if you look
> at the <proj>.tcl file in the xilinx directory
> you should see something like the following:
>
>       cd ./xilinx/
>       # set ucf file:
>       set constraints_file xula.ucf

True, but the pin mappings (or the timing constraints) from the ucf-file
are not used by the synthesis.  Looking into the .csv file that is
created, I don't see located pins.

Here is what I observe:

Using fpga.run() to run synthesis, the ucf file is not used.
Starting the ISE GUI, I add the ucf-file to the sources file list,
and running fpga.run() again, the ucf file is used, and the pins are 
located.  Starting fpga.run() again gies the same result.

Remove the xilinx subdirectory completely.
I add 'xfile add myfile.ucf' to the code that generates the tcl
script, start fpga.run(), then everything works.
Starting fpga.run() a second time, I get an error that 'myfile.ucf'
is already part of the projects and sysnthesis fails.
I have to remove the xilinx subdirectory completely, then fpga.run()
works again.

Whatever this means.

Thomas

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Thomas H. <th...@ct...>]

Am 03.12.2013 04:41, schrieb Christopher Felton:
>
> I uploaded version 0.0.2 to pypi and to
> bitbucket [1].  Thanks again for the feedback.
>
Thanks for the quick fixes.

Thomas

Re: [myhdl-list] MEP 107 Initial support

[David H. <da...@ad...>]

Yeah, the down-side is for some of my parameterizable IP (coded in MyHDL)
where **kwargs is a natural fit, I currently have to write out a silly
temporary .py file just for MyHDL to analyze to extract the top-level port
names.
So, being able to relax the restriction on **kwargs (in exchange for the
caller must .portmap prior to export), would hopefully eliminate this
ugliness.

(example IP blocks: an N-port arbiter for AXI4-S streams...  Or a PCIe BAR
interface that auto-creates software input/output bits for hardware control
from an OS driver...)




On Tue, Dec 3, 2013 at 12:05 AM, Christopher Felton
<chr...@gm...>wrote:

> On 12/2/13 9:06 PM, David Holl wrote:
> > If you go this route with the dict, I'd encourage the use of an
> > OrderedDict, so that argument order may be preserved.  Then the top
> > level restriction that prevents **kwargs can be relaxed because the top
> > function wouldn't need to be analyzed to get at the signal names.
>
> Other than complexity, is there is downside
> to analyzing the top function to get the signal
> names?
>
> Regards,
> Chris
>
> >
> > On Dec 2, 2013 6:12 PM, "Christopher Felton" <chr...@gm...
> > <mailto:chr...@gm...>> wrote:
> >
> >     On 10/2/2013 2:45 PM, Keerthan jai.c wrote:
> >      > toVerilog returns whatever would be returned if you called the
> >     function
> >      > directly, usually a tuple of generators. So, someone could
> >     hypothetically
> >      > have been passing the return value of toVerilog to a
> myhdl.Simulation
> >      > object. Returning the portmap alongside the previous return value
> >     would
> >      > break their code.
> >      >
> >      > toVerilog.portmap seems reasonable.
> >      >
> >      >
> >
> >     How about the /portmap/ is tied to the module
> >     (the function being passed) instead of the toV*?
> >
> >     Because of another request I was thinking - it
> >     could be useful to define the "default" port
> >     types in a /portmap/ function attribute.
> >
> >     Couple benefits:
> >
> >     Â  Â  1. Top-level modules often are specific, there
> >     Â  Â  Â  Â is only one mapping that makes sense
> >
> >     Â  Â  2. removes the need to re-declare the port
> >     Â  Â  Â  Â (simulation and conversion)
> >
> >     Example:
> >
> >     Â  Â  Â def m_adder(a,b,c):
> >     Â  Â  Â  Â  Â @always_comb
> >     Â  Â  Â  Â  Â def rtl():
> >     Â  Â  Â  Â  Â  Â  Â c.next = a + b
> >     Â  Â  Â  Â  Â return rtl
> >
> >     Â  Â  Â iot = intbv(0, min=-8, max=8)
> >     Â  Â  Â m_adder.portmap = {"a":Signal(iot),
> >     Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  "b":Signal(iot),
> >     Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  "c":Signal(iot)}
> >
> >     A /vportmap/ (or something similar) function attribute
> >     could be used to contain the expanded names. Â The port
> >     definitions would be tied to the top-level function.
> >
> >     .chris
> >
> >
> >
> >
> >
> ------------------------------------------------------------------------------
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> IT
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> >     <mailto:myh...@li...>
> >     https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
> >
> >
> >
> ------------------------------------------------------------------------------
> > Rapidly troubleshoot problems before they affect your business. Most IT
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> >
>
>
>
>
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> Rapidly troubleshoot problems before they affect your business. Most IT
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Re: [myhdl-list] MEP 107 Initial support

[Christopher F. <chr...@gm...>]

On 12/2/13 9:06 PM, David Holl wrote:
> If you go this route with the dict, I'd encourage the use of an
> OrderedDict, so that argument order may be preserved.  Then the top
> level restriction that prevents **kwargs can be relaxed because the top
> function wouldn't need to be analyzed to get at the signal names.

Other than complexity, is there is downside
to analyzing the top function to get the signal
names?

Regards,
Chris

>
> On Dec 2, 2013 6:12 PM, "Christopher Felton" <chr...@gm...
> <mailto:chr...@gm...>> wrote:
>
>     On 10/2/2013 2:45 PM, Keerthan jai.c wrote:
>      > toVerilog returns whatever would be returned if you called the
>     function
>      > directly, usually a tuple of generators. So, someone could
>     hypothetically
>      > have been passing the return value of toVerilog to a myhdl.Simulation
>      > object. Returning the portmap alongside the previous return value
>     would
>      > break their code.
>      >
>      > toVerilog.portmap seems reasonable.
>      >
>      >
>
>     How about the /portmap/ is tied to the module
>     (the function being passed) instead of the toV*?
>
>     Because of another request I was thinking - it
>     could be useful to define the "default" port
>     types in a /portmap/ function attribute.
>
>     Couple benefits:
>
>     Â  Â  1. Top-level modules often are specific, there
>     Â  Â  Â  Â is only one mapping that makes sense
>
>     Â  Â  2. removes the need to re-declare the port
>     Â  Â  Â  Â (simulation and conversion)
>
>     Example:
>
>     Â  Â  Â def m_adder(a,b,c):
>     Â  Â  Â  Â  Â @always_comb
>     Â  Â  Â  Â  Â def rtl():
>     Â  Â  Â  Â  Â  Â  Â c.next = a + b
>     Â  Â  Â  Â  Â return rtl
>
>     Â  Â  Â iot = intbv(0, min=-8, max=8)
>     Â  Â  Â m_adder.portmap = {"a":Signal(iot),
>     Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  "b":Signal(iot),
>     Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  Â  "c":Signal(iot)}
>
>     A /vportmap/ (or something similar) function attribute
>     could be used to contain the expanded names. Â The port
>     definitions would be tied to the top-level function.
>
>     .chris
>
>
>
>
>     ------------------------------------------------------------------------------
>     Rapidly troubleshoot problems before they affect your business. Most IT
>     organizations don't have a clear picture of how application performance
>     affects their revenue. With AppDynamics, you get 100% visibility
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>     Java,.NET, & PHP application. Start your 15-day FREE TRIAL of
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>
>
>
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> organizations don't have a clear picture of how application performance
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