myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] EDA playground

[Angel E. <ang...@gm...>]

On Sat, Oct 12, 2013 at 11:46 PM, Christopher Felton
<chr...@gm...> wrote:
> They added basic support for MyHDL simulation
> (w/o cosimulations).  If you have an example you
> want to share its not a bad place to post an
> example, you can see it run :)
> http://www.edaplayground.com/s/130/229
>
> Regards,
> Chris
>
> On 10/10/13 10:07 PM, Christopher Felton wrote:
>> I added a request to add myhdl to the EDAPlayground [1].
>>
>> If you think MyHLD support @ EDAPlayground is a good
>> idea go to:
>> https://github.com/getvictor/eda-playground/issues/7
>>
>> and watch the request and/or add a comment indicating
>> interest in the support.  Any help providing information
>> to the developers if questions arise would be useful
>> (responsive feedback).
>>
>> Regards,
>> Chris Felton
>>
>> [1] http://www.edaplayground.com/

Wow! That was fast! I didn't even have the time to vote for this issue!

Cheers,

Angel

Re: [myhdl-list] EDA playground

[Christopher F. <chr...@gm...>]

They added basic support for MyHDL simulation
(w/o cosimulations).  If you have an example you
want to share its not a bad place to post an
example, you can see it run :)
http://www.edaplayground.com/s/130/229

Regards,
Chris

On 10/10/13 10:07 PM, Christopher Felton wrote:
> I added a request to add myhdl to the EDAPlayground [1].
>
> If you think MyHLD support @ EDAPlayground is a good
> idea go to:
> https://github.com/getvictor/eda-playground/issues/7
>
> and watch the request and/or add a comment indicating
> interest in the support.  Any help providing information
> to the developers if questions arise would be useful
> (responsive feedback).
>
> Regards,
> Chris Felton
>
> [1] http://www.edaplayground.com/
>

[myhdl-list] fixed-point thoughts : part three

[Christopher F. <chr...@gm...>]

First, I have the start of a reference implementation
available here:

https://bitbucket.org/cfelton/myhdl_09dev/src/tip/myhdl/_fixbv.py?at=0.9-dev

This reference implementation covers most of the
discussions from part 1 and 2 excluding the /resize/
function.  The /resize/ function implementation is
the topic to be discussed in the rest of this post.

resize function
----------------
In part two the conversation focused around fixed-point
operations and the need for a /resize/ function.

I proposed the /resize/ function as:

    resize(val, format,
           [,round_mode='convergent']
           [,overflow_mode='saturate']

A use case might look like ::

    x = Signal(fixbv(0,min=-8,max=8,res=1/16.))
    y = Signal(fixbv(0,min=-1,max=1,res=2**-15))
    z = Signal(fixbv(0)[x.W+y.W])

    @always_seq(clock.posedge, reset=reset)
    def rtl():
       z.next = resize(resize(x, x.W+y.W) + y, z)

and/or:

    @always_seq(clock.posedge,reset=reset)
    def rtl():
       tmp = a*b
       c.next = resize(tmp, c, round_mode="round")

Above I used an attribute not yet discussed, the /W/
attribute.  I call this the W-format.  It is an object
that represents the format of the fixed-point type.  The
formats can be added, subtracted, multiplied, etc to handle
the elaboration (programatic) handling of types.  There are
two attributes for the format

    W - FixedPointFormat ojbect
    format - (wl,iwl,fwl) tuple (just a short-cut for W.format)

Before getting to the /resize/ function details, lets review
function conversion.  MyHDL supports converting functions calls
within a convertible generator if the function is part of an
assignment and is found on the right-hand side.  The function
will be convert to a similar Verilog/VHDL function.  Just
like Verilog and VHDL the function represents combinatorial
logic (stateless).

An example of a function conversion is:

     def simple_add(a,b,):
         c = a + b
         return c

     def top(clock,reset,a,b,c):
         @always_seq(clock.posedge, reset=reset)
         def rtl():
             c.next = simple_add(a,b)
         return rtl

the conversion can be viewed here:
https://gist.github.com/cfelton/6788096

I believe, the function conversion is limited to a single
level - that is there cannot be a function call in the
function.

Ok, at this point I have created a dilemma for myself.
I have proposed a function type that isn't supported for
conversion.  The proposed /resize/ function would require
considerable elaboration to programatically handle the
alignment, different rounding modes, and overflow.

I haven't thought of another way to achieve the same
goals.  At this point we could explore function conversion
that supports similar elaboration as a myhdl module
(a python function that has myhdl generators)?

    def resize(val,
               format, round_mode='floor',
               overflow_mode='saturate'):
	 # ...
	 if round_mode == 'floor':
	    rfunc = _resize_floor(...)
	 # ...

       return rfunc()


Is this the wrong approach?  Or does an "enhanced"
function conversion need to be considered?

Regards,
Chris Felton

[myhdl-list] EDA playground

[Christopher F. <chr...@gm...>]

I added a request to add myhdl to the EDAPlayground [1].

If you think MyHLD support @ EDAPlayground is a good
idea go to:
https://github.com/getvictor/eda-playground/issues/7

and watch the request and/or add a comment indicating
interest in the support.  Any help providing information
to the developers if questions arise would be useful
(responsive feedback).

Regards,
Chris Felton

[1] http://www.edaplayground.com/

Re: [myhdl-list] always_comb exception

[Steve V. <ste...@ea...>]

Thanks very much - that also seems to work well.

-----Original Message-----
>From: Norbo <Nor...@gm...>
>Sent: Oct 9, 2013 4:10 PM
>To: myh...@li...
>Subject: Re: [myhdl-list] always_comb exception
>
>Am 09.10.2013, 20:16 Uhr, schrieb Per Karlsson <bas...@gm...>:
>
>> I suspect you are running from the interpreter.
>> That won't work, because MyHDL uses inspection.
>> Every piece of MyHDL code has to be written to an actual file somewhere  
>> (or
>> at least that's how I understand it).
>>
>> Cheers
>> Per
>>
>>
>> On Wed, Oct 9, 2013 at 7:48 PM, Steve Vejcik  
>> <ste...@ea...>wrote:
>>
>>> Hi Folks - I'm just wetting my feet with myhdl and have run into a  
>>> problem
>>> running the simple latch example from the wiki. I'm running python 2.7  
>>> with
>>> myhdl v0.8. If anyone can offer some insight I'd appreciate it. Here's a
>>> variant of the problem:
>>>
>>> def Mux(z, a, b, sel):
>>>    @always_comb
>>>    def muxLogic():
>>>      if sel == 1:
>>>        z.next = a
>>>      else:
>>>        z.next = b
>>>    return muxLogic
>>> >>> z, a, b, sel = [Signal(0) for i in range(4)]
>>> >>> mux_1 = Mux(z,a,b,sel)
>>>
>>> Traceback (most recent call last):
>>>   File "<stdin>", line 1, in <module>
>>>   File "<stdin>", line 2, in Mux
>>>   File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py",  
>>> line
>>> 64, in always_comb
>>>     c = _AlwaysComb(func, symdict)
>>>   File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py",  
>>> line
>>> 185, in __init__
>>>     s = inspect.getsource(func)
>>>   File "/usr/lib/python2.7/inspect.py", line 701, in getsource
>>>     lines, lnum = getsourcelines(object)
>>>   File "/usr/lib/python2.7/inspect.py", line 690, in getsourcelines
>>>     lines, lnum = findsource(object)
>>>   File "/usr/lib/python2.7/inspect.py", line 538, in findsource
>>>     raise IOError('could not get source code')
>>> IOError: could not get source code
>>>
>>> Steve
>
>
>Yes,a file is needed, you could also write it into a file for the  
>interpreter,
>then it should definitly work.
>for example like this:
>
>
> from myhdl import *
>
>source_text="""def Mux(z, a, b, sel):
>    @always_comb
>    def muxLogic():
>      if sel == 1:
>        z.next = a
>      else:
>        z.next = b
>    return muxLogic
>z, a, b, sel = [Signal(0) for i in range(4)]
>mux_1 = Mux(z,a,b,sel)"""
>
>source_file=open("sourcetext.txt","w")
>source_file.write(source_text)
>source_file.close()
>dd=compile(source_text,"sourcetext.txt","exec")
>exec(dd)
>
>
>greetings
>Norbo
>
>
>
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>https://lists.sourceforge.net/lists/listinfo/myhdl-list


Steve

Re: [myhdl-list] always_comb exception

[Christopher F. <chr...@gm...>]

<snip>
> And got this dump from ipython:
>
<snip>
> ---------------------------------------------------------------------------
> IOError                                   Traceback (most recent call last)
>
<snip>

That is odd, I receive no such error.

Python 2.7.3 |EPD 7.3-2 (64-bit)| (default, Apr 11 2012, 17:52:16)
Type "copyright", "credits" or "license" for more information.

IPython 0.12.1 -- An enhanced Interactive Python.

In [3]: from myhdl import *
    ...: def Mux(z, a, b, sel):
    ...:    @always_comb
    ...:    def muxLogic():
    ...:      if sel == 1:
    ...:        z.next = a
    ...:      else:
    ...:        z.next = b
    ...:    return muxLogic
    ...: z, a, b, sel = [Signal(0) for i in range(4)]
    ...: mux_1 = Mux(z,a,b,sel)
    ...: print(z,a,b,sel,mux_1)
    ...:
(Signal(0), Signal(0), Signal(0), Signal(0), 
<myhdl._always_comb._AlwaysComb object at 0x0000000006383278>)


I also tried it on ipython 1.0.0 on windoze and no error, hmmm.
I am also running myhdl 0.8.1 with the above.

.chris

Re: [myhdl-list] always_comb exception

[Norbo <Nor...@gm...>]

Am 09.10.2013, 20:16 Uhr, schrieb Per Karlsson <bas...@gm...>:

> I suspect you are running from the interpreter.
> That won't work, because MyHDL uses inspection.
> Every piece of MyHDL code has to be written to an actual file somewhere  
> (or
> at least that's how I understand it).
>
> Cheers
> Per
>
>
> On Wed, Oct 9, 2013 at 7:48 PM, Steve Vejcik  
> <ste...@ea...>wrote:
>
>> Hi Folks - I'm just wetting my feet with myhdl and have run into a  
>> problem
>> running the simple latch example from the wiki. I'm running python 2.7  
>> with
>> myhdl v0.8. If anyone can offer some insight I'd appreciate it. Here's a
>> variant of the problem:
>>
>> def Mux(z, a, b, sel):
>>    @always_comb
>>    def muxLogic():
>>      if sel == 1:
>>        z.next = a
>>      else:
>>        z.next = b
>>    return muxLogic
>> >>> z, a, b, sel = [Signal(0) for i in range(4)]
>> >>> mux_1 = Mux(z,a,b,sel)
>>
>> Traceback (most recent call last):
>>   File "<stdin>", line 1, in <module>
>>   File "<stdin>", line 2, in Mux
>>   File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py",  
>> line
>> 64, in always_comb
>>     c = _AlwaysComb(func, symdict)
>>   File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py",  
>> line
>> 185, in __init__
>>     s = inspect.getsource(func)
>>   File "/usr/lib/python2.7/inspect.py", line 701, in getsource
>>     lines, lnum = getsourcelines(object)
>>   File "/usr/lib/python2.7/inspect.py", line 690, in getsourcelines
>>     lines, lnum = findsource(object)
>>   File "/usr/lib/python2.7/inspect.py", line 538, in findsource
>>     raise IOError('could not get source code')
>> IOError: could not get source code
>>
>> Steve


Yes,a file is needed, you could also write it into a file for the  
interpreter,
then it should definitly work.
for example like this:


 from myhdl import *

source_text="""def Mux(z, a, b, sel):
    @always_comb
    def muxLogic():
      if sel == 1:
        z.next = a
      else:
        z.next = b
    return muxLogic
z, a, b, sel = [Signal(0) for i in range(4)]
mux_1 = Mux(z,a,b,sel)"""

source_file=open("sourcetext.txt","w")
source_file.write(source_text)
source_file.close()
dd=compile(source_text,"sourcetext.txt","exec")
exec(dd)


greetings
Norbo

Re: [myhdl-list] always_comb exception

[David H. <da...@ad...>]

This fails with both "ipython" and plain "python" (in interactive mode) on
Mac OS X 10.8.5 using prerelease MyHDL 0.8.1 from the repo.

I pasted this text:
from myhdl import *
def Mux(z, a, b, sel):
   @always_comb
   def muxLogic():
     if sel == 1:
       z.next = a
     else:
       z.next = b
   return muxLogic

z, a, b, sel = [Signal(0) for i in range(4)]
mux_1 = Mux(z,a,b,sel)


And got this dump from ipython:

subspace(ttys002):~> ipython
Leopard libedit detected.
Python 2.7.2 (default, Oct 11 2012, 20:14:37)
Type "copyright", "credits" or "license" for more information.

IPython 0.10.1 -- An enhanced Interactive Python.
?         -> Introduction and overview of IPython's features.
%quickref -> Quick reference.
help      -> Python's own help system.
object?   -> Details about 'object'. ?object also works, ?? prints more.

In [1]: from myhdl import *

In [2]: def Mux(z, a, b, sel):
   ...:    @always_comb
   ...:    def muxLogic():
   ...:      if sel == 1:
   ...:        z.next = a
   ...:      else:
   ...:        z.next = b
   ...:    return muxLogic
   ...:

In [3]: z, a, b, sel = [Signal(0) for i in range(4)]

In [4]: mux_1 = Mux(z,a,b,sel)
---------------------------------------------------------------------------
IOError                                   Traceback (most recent call last)

/Users/dholl/<ipython console> in <module>()

/Users/dholl/<ipython console> in Mux(z, a, b, sel)

/Users/dholl/Library/Python/2.7/lib/python/site-packages/myhdl/_always_comb.pyc
in always_comb(func)
     62             except NameError:
     63                 raise NameError(n)
---> 64     c = _AlwaysComb(func, symdict)
     65     return c
     66

/Users/dholl/Library/Python/2.7/lib/python/site-packages/myhdl/_always_comb.pyc
in __init__(self, func, symdict)
    193         self.func = func
    194         self.symdict = symdict
--> 195         s = inspect.getsource(func)
    196         s = _dedent(s)
    197         tree = ast.parse(s)

/System/Library/Frameworks/Python.framework/Versions/2.7/lib/python2.7/inspect.py
in getsource(object)
    697     or code object.  The source code is returned as a single
string.  An
    698     IOError is raised if the source code cannot be retrieved."""
--> 699     lines, lnum = getsourcelines(object)
    700     return string.join(lines, '')
    701

/System/Library/Frameworks/Python.framework/Versions/2.7/lib/python2.7/inspect.py
in getsourcelines(object)
    686     original source file the first line of code was found.  An
IOError is
    687     raised if the source code cannot be retrieved."""
--> 688     lines, lnum = findsource(object)
    689
    690     if ismodule(object): return lines, 0

/Users/dholl/Library/Python/2.7/lib/python/site-packages/IPython/ultraTB.pyc
in findsource(object)
    143     lines = linecache.getlines(file, globals_dict)
    144     if not lines:
--> 145         raise IOError('could not get source code')
    146
    147     if ismodule(object):

IOError: could not get source code

In [5]:


For completeness, the dump form python is:
Last login: Wed Oct  9 15:24:05 on ttys002
subspace(ttys003):~> python
Python 2.7.2 (default, Oct 11 2012, 20:14:37)
[GCC 4.2.1 Compatible Apple Clang 4.0 (tags/Apple/clang-418.0.60)] on darwin
Type "help", "copyright", "credits" or "license" for more information.
>>> from myhdl import *
>>> def Mux(z, a, b, sel):
...    @always_comb
...    def muxLogic():
...      if sel == 1:
...        z.next = a
...      else:
...        z.next = b
...    return muxLogic
...
>>> z, a, b, sel = [Signal(0) for i in range(4)]
>>> mux_1 = Mux(z,a,b,sel)
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "<stdin>", line 2, in Mux
  File
"/Users/dholl/Library/Python/2.7/lib/python/site-packages/myhdl/_always_comb.py",
line 64, in always_comb
    c = _AlwaysComb(func, symdict)
  File
"/Users/dholl/Library/Python/2.7/lib/python/site-packages/myhdl/_always_comb.py",
line 195, in __init__
    s = inspect.getsource(func)
  File
"/System/Library/Frameworks/Python.framework/Versions/2.7/lib/python2.7/inspect.py",
line 699, in getsource
    lines, lnum = getsourcelines(object)
  File
"/System/Library/Frameworks/Python.framework/Versions/2.7/lib/python2.7/inspect.py",
line 688, in getsourcelines
    lines, lnum = findsource(object)
  File
"/System/Library/Frameworks/Python.framework/Versions/2.7/lib/python2.7/inspect.py",
line 529, in findsource
    raise IOError('source code not available')
IOError: source code not available
>>>





On Wed, Oct 9, 2013 at 2:44 PM, Christopher Felton
<chr...@gm...>wrote:

> On 10/9/2013 1:16 PM, Per Karlsson wrote:
> > I suspect you are running from the interpreter.
> > That won't work, because MyHDL uses inspection.
> > Every piece of MyHDL code has to be written to an actual file somewhere
> (or
> > at least that's how I understand it).
> >
> > Cheers
> > Per
> >
>
> Don't know about the base Python interpreter-shell
> but from the ipython console it works fine.
>
> In [2]: from myhdl import *
>     ...: def Mux(z, a, b, sel):
>     ...:    @always_comb
>     ...:    def muxLogic():
>     ...:      if sel == 1:
>     ...:        z.next = a
>     ...:      else:
>     ...:        z.next = b
>     ...:    return muxLogic
>     ...: z, a, b, sel = [Signal(0) for i in range(4)]
>     ...: mux_1 = Mux(z,a,b,sel)
>     ...:
>
> I can never type it all correct to use the base-shell
> for multiline input, e.g. function definitions :)
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> October Webinars: Code for Performance
> Free Intel webinars can help you accelerate application performance.
> Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most
> from
> the latest Intel processors and coprocessors. See abstracts and register >
> http://pubads.g.doubleclick.net/gampad/clk?id=60134071&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] always_comb exception

[Christopher F. <chr...@gm...>]

On 10/9/2013 1:16 PM, Per Karlsson wrote:
> I suspect you are running from the interpreter.
> That won't work, because MyHDL uses inspection.
> Every piece of MyHDL code has to be written to an actual file somewhere (or
> at least that's how I understand it).
>
> Cheers
> Per
>

Don't know about the base Python interpreter-shell
but from the ipython console it works fine.

In [2]: from myhdl import *
    ...: def Mux(z, a, b, sel):
    ...:    @always_comb
    ...:    def muxLogic():
    ...:      if sel == 1:
    ...:        z.next = a
    ...:      else:
    ...:        z.next = b
    ...:    return muxLogic
    ...: z, a, b, sel = [Signal(0) for i in range(4)]
    ...: mux_1 = Mux(z,a,b,sel)
    ...:

I can never type it all correct to use the base-shell
for multiline input, e.g. function definitions :)

Regards,
Chris

Re: [myhdl-list] always_comb exception

[Steve V. <ste...@ea...>]

<head><style>body{font-size:10pt;font-family:arial,sans-serif;background-color:#ffffff;color:black;}p{margin:0px;}</style></head><body><font color="#000000"><font size="2"><font face="arial,sans-serif">Hi<font size="2"> <br><font size="2">&nbsp;&nbsp; Thanks very much<font size="2"> !</font></font><br></font></font></font></font><blockquote style="PADDING-LEFT: 5px; MARGIN-LEFT: 0px; BORDER-LEFT: #0000ff 2px solid">-----Original Message-----
<br>From: Per Karlsson <bas...@gm...>
<br>Sent: Oct 9, 2013 1:16 PM
<br>To: Steve Vejcik <ste...@ea...>, General discussions on MyHDL <myh...@li...>
<br>Subject: Re: [myhdl-list] always_comb exception

<br><br><div dir="ltr">I suspect you are running from the interpreter.&nbsp;<div>That won't work, because MyHDL uses inspection.&nbsp;</div><div>Every piece of MyHDL code has to be written to an actual file somewhere (or at least that's how I understand it).</div>

<div><br></div><div>Cheers</div><div>Per</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, Oct 9, 2013 at 7:48 PM, Steve Vejcik <span dir="ltr">&lt;<a target="_blank" href="mailto:ste...@ea...">ste...@ea...</a>&gt;</span> wrote:<br>

<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Folks - I'm just wetting my feet with myhdl and have run into a problem<br>
running the simple latch example from the wiki. I'm running python 2.7 with<br>
myhdl v0.8. If anyone can offer some insight I'd appreciate it. Here's a<br>
variant of the problem:<br>
<br>
def Mux(z, a, b, sel):<br>
&nbsp; &nbsp;@always_comb<br>
&nbsp; &nbsp;def muxLogic():<br>
&nbsp; &nbsp; &nbsp;if sel == 1:<br>
&nbsp; &nbsp; &nbsp; &nbsp;z.next = a<br>
&nbsp; &nbsp; &nbsp;else:<br>
&nbsp; &nbsp; &nbsp; &nbsp;z.next = b<br>
&nbsp; &nbsp;return muxLogic<br>
&gt;&gt;&gt; z, a, b, sel = [Signal(0) for i in range(4)]<br>
&gt;&gt;&gt; mux_1 = Mux(z,a,b,sel)<br>
<br>
Traceback (most recent call last):<br>
&nbsp; File "&lt;stdin&gt;", line 1, in &lt;module&gt;<br>
&nbsp; File "&lt;stdin&gt;", line 2, in Mux<br>
&nbsp; File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py", line<br>
64, in always_comb<br>
&nbsp; &nbsp; c = _AlwaysComb(func, symdict)<br>
&nbsp; File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py", line<br>
185, in __init__<br>
&nbsp; &nbsp; s = inspect.getsource(func)<br>
&nbsp; File "/usr/lib/python2.7/inspect.py", line 701, in getsource<br>
&nbsp; &nbsp; lines, lnum = getsourcelines(ZZZobject)<br>
&nbsp; File "/usr/lib/python2.7/inspect.py", line 690, in getsourcelines<br>
&nbsp; &nbsp; lines, lnum = findsource(ZZZobject)<br>
&nbsp; File "/usr/lib/python2.7/inspect.py", line 538, in findsource<br>
&nbsp; &nbsp; raise IOError('could not get source code')<br>
IOError: could not get source code<br>
<br>
Steve<br>
<br>
------------------------------------------------------------------------------<br>
October Webinars: Code for Performance<br>
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</blockquote></div><br></div>
</myh...@li...></ste...@ea...></bas...@gm...></blockquote></body><pre>

Steve</pre>

Re: [myhdl-list] always_comb exception

[Per K. <bas...@gm...>]

I suspect you are running from the interpreter.
That won't work, because MyHDL uses inspection.
Every piece of MyHDL code has to be written to an actual file somewhere (or
at least that's how I understand it).

Cheers
Per


On Wed, Oct 9, 2013 at 7:48 PM, Steve Vejcik <ste...@ea...>wrote:

> Hi Folks - I'm just wetting my feet with myhdl and have run into a problem
> running the simple latch example from the wiki. I'm running python 2.7 with
> myhdl v0.8. If anyone can offer some insight I'd appreciate it. Here's a
> variant of the problem:
>
> def Mux(z, a, b, sel):
>    @always_comb
>    def muxLogic():
>      if sel == 1:
>        z.next = a
>      else:
>        z.next = b
>    return muxLogic
> >>> z, a, b, sel = [Signal(0) for i in range(4)]
> >>> mux_1 = Mux(z,a,b,sel)
>
> Traceback (most recent call last):
>   File "<stdin>", line 1, in <module>
>   File "<stdin>", line 2, in Mux
>   File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py", line
> 64, in always_comb
>     c = _AlwaysComb(func, symdict)
>   File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py", line
> 185, in __init__
>     s = inspect.getsource(func)
>   File "/usr/lib/python2.7/inspect.py", line 701, in getsource
>     lines, lnum = getsourcelines(object)
>   File "/usr/lib/python2.7/inspect.py", line 690, in getsourcelines
>     lines, lnum = findsource(object)
>   File "/usr/lib/python2.7/inspect.py", line 538, in findsource
>     raise IOError('could not get source code')
> IOError: could not get source code
>
> Steve
>
>
> ------------------------------------------------------------------------------
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> from
> the latest Intel processors and coprocessors. See abstracts and register >
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>

[myhdl-list] always_comb exception

[Steve V. <ste...@ea...>]

Hi Folks - I'm just wetting my feet with myhdl and have run into a problem
running the simple latch example from the wiki. I'm running python 2.7 with
myhdl v0.8. If anyone can offer some insight I'd appreciate it. Here's a
variant of the problem:

def Mux(z, a, b, sel):
   @always_comb
   def muxLogic():
     if sel == 1:
       z.next = a
     else:
       z.next = b
   return muxLogic 
>>> z, a, b, sel = [Signal(0) for i in range(4)]
>>> mux_1 = Mux(z,a,b,sel)

Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "<stdin>", line 2, in Mux
  File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py", line
64, in always_comb
    c = _AlwaysComb(func, symdict)
  File "/usr/local/lib/python2.7/dist-packages/myhdl/_always_comb.py", line
185, in __init__
    s = inspect.getsource(func)
  File "/usr/lib/python2.7/inspect.py", line 701, in getsource
    lines, lnum = getsourcelines(object)
  File "/usr/lib/python2.7/inspect.py", line 690, in getsourcelines
    lines, lnum = findsource(object)
  File "/usr/lib/python2.7/inspect.py", line 538, in findsource
    raise IOError('could not get source code')
IOError: could not get source code

Steve

Re: [myhdl-list] MEP - keep hierarchy in conversion

[Christopher F. <chr...@gm...>]

On 10/4/2013 4:14 PM, Jan Decaluwe wrote:
> On 10/03/2013 11:48 PM, Angel Ezquerra wrote:
>
>> This may be one of those "folklore things" that get told from engineer
>> to engineer, without a proper backup. It may even have been true once,
>> but perhaps it is no longer the case?
>
> [About the need for floorplanning FPGAs]
>
> I have now checked this with competent people that I trust
> and that regularly do large layouts.
>
> They tell me that with current state-of-the-art tools,
> floorplanning within the digital HDL flow doesn't make
> much sense, not for ASICs and not for FPGAs.
>
> On the contrary: "flat" layout tools can do intelligent
> placement automatically, and global placement optimization
> (no artificial boundaries) is advantageous, just like for
> synthesis.
>
> The condition however is a clean design methodology, in
> particular solid conservative synchronous design practices.
>
> Therefore, my hypothesis is that people who claim that
> "floorplanning is essential", like Mr. Karlsson and his
> anynomous "expert", really use it as a workaround for a
> messy methodology.
>

Some additional comments on the need for floorplanning
specifically for FPGAs.  Here are three more opinions [1]
that support the *no* floorplanning (usenet comp.arch.fpga)
At least one commenter suggests restricting (preventing
flattening) causes lower QoR.

[1] 
http://www.fpgarelated.com/comp.arch.fpga/thread/109993/granularity-of-components-for-fpga-synthesis.php

Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/05/2013 12:07 AM, Angel Ezquerra wrote:

> That makes sense when you put it like that. That being said, do you
> know if your colleagues would consider the Xilinx tools (ISE and/or
> Vivado) "state of the art" in this regard?

Those colleagues have experience with a wide variety of targets
and tools, including lots of ASIC work and both Xilinx and Altera
tool sets.

> Do you have any blog post or some other material where you describe
> what you would consider "solid conservative synchronous design
> practices"? I'd be really interested in what you would have to say on
> that topic.

 From my web site you will find a number of blogs that I believe
clearly represent my line of thinking.

I have not written a blog about this specific topic. If I would,
I think I would present it as an application of sound principles:
separation of concerns (such as functional vs physical and timing),
minimization of dependencies, understand what your compilers
(synthesis and layout tools) can do and what tasks you can
leave to them.

This would lead to concrete methodology guidelines, e.g.
* keep HDL source target independent and plan for that
* don't use clock gating for functional behavior; use logic
instead (you have it anyway)
(clock gating for power management is fine and an increasingly
important requirement)
* register interfaces between blocks systematically (minimize
timing dependencies)

It's unlikely I will write such a blog though as this way
of thinking has become second nature to me, and "not interesting
enough" to blog about. A blog is lots of work and there
is a pile of more interesting and innovative topics.

Let me add that I co-founded a company, Easics, that has been
putting this type of methodology into practice since 1992. Easics
is a like a lean design factory that turns over succesful projects
back-to-back.

The interesting point is that occasionally we (at Easics) get the
opportunity to compare design methodologies, unlike most companies.
And the evidence points all in the same direction: this type of
methodology leads to *better* QoR and *much* smaller compilation
times.

Therefore, when someone says he "needs" floorplanning, and my
evidence says we don't, I'm not questioning his methodology in
vain. Time and time again, we have seen that basic methodology
choices, that are seldom talked about, cause major differences
in QoR and compilation time.

> Also, do you think that making it easy to split the generated code a
> into multiple files has real benefits other than floorplanning?

Yes - as I have reported I do that myself regularly.

Good reasons I can think of: code clarity (certainly), support
incremental synthesis (likely), easy extraction of reusable IP
in VHDL/Verilog format, enable floorplanning support (if you
need it).

I repeat that I support efforts for a clean way to support
hierarchical output from the convertor. Suggested lines of work:

* study top-level convertibility restrictions and how to
relax them if possible
* bring Oscar's changesets over to mercurial and align
with the MyHDL development, so that they can be reviewed
and discussed there (see Keerthan's changesets about
interfaces, I'm quite happy how that works)
* other creative ideas in line with the project's spirit,
which means Verilog is *not* the inspiration or the norm

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/04/2013 01:39 AM, David Holl wrote:

> Folks will argue when they're passionate about something.  I
> interpret the ongoing discussions as a sign that Jan's MyHDL has
> developed quite a following.  :)

I interprete them as a big waste of time and energy.
If this means "success", it's quite depressing actually.

I developed MyHDL because I want to change the way the
mainstream thinks about HDL design - away from low-level,
misguided "hardware thinking" and towards higher abstraction
levels, sound software-like development techniques, focus
on verification.

What we are seeing is the flip-side of python and open
source. The barrier of entry is so low that people with
zero interest and respect for the project goals and
origins can "participate" just like those that
understand and contribute.

Instead of the project changing the way they think, they
want to impose their way of thinking upon the project.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MEP - keep hierarchy in conversion

[Angel E. <ang...@gm...>]

El 04/10/2013 23:14, "Jan Decaluwe" <ja...@ja...> escribió:
>
> On 10/03/2013 11:48 PM, Angel Ezquerra wrote:
>
> > This may be one of those "folklore things" that get told from engineer
> > to engineer, without a proper backup. It may even have been true once,
> > but perhaps it is no longer the case?
>
> [About the need for floorplanning FPGAs]
>
> I have now checked this with competent people that I trust
> and that regularly do large layouts.
>
> They tell me that with current state-of-the-art tools,
> floorplanning within the digital HDL flow doesn't make
> much sense, not for ASICs and not for FPGAs.
>
> On the contrary: "flat" layout tools can do intelligent
> placement automatically, and global placement optimization
> (no artificial boundaries) is advantageous, just like for
> synthesis.

That makes sense when you put it like that. That being said, do you know if
your colleagues would consider the Xilinx tools (ISE and/or Vivado) "state
of the art" in this regard?

> The condition however is a clean design methodology, in
> particular solid conservative synchronous design practices.

Do you have any blog post or some other material where you describe what
you would consider "solid conservative synchronous design practices"? I'd
be really interested in what you would have to say on that topic.

> Therefore, my hypothesis is that people who claim that
> "floorplanning is essential", like Mr. Karlsson and his
> anynomous "expert", really use it as a workaround for a
> messy methodology.

Or maybe they use tools which are not state of the art? The tools you use
often frame your way of thinking (as many MyHDL users have probably
discovered).

Also, do you think that making it easy to split the generated code a into
multiple files has real benefits other than floorplanning? If you do, which
ones? Off the top of my head I can think of improved interaction with
version control (when that is necessary) and perhaps making it easier to
understand/find synthesis errors...

Cheers,

Angel

Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/03/2013 11:48 PM, Angel Ezquerra wrote:

> This may be one of those "folklore things" that get told from engineer
> to engineer, without a proper backup. It may even have been true once,
> but perhaps it is no longer the case?

[About the need for floorplanning FPGAs]

I have now checked this with competent people that I trust
and that regularly do large layouts.

They tell me that with current state-of-the-art tools,
floorplanning within the digital HDL flow doesn't make
much sense, not for ASICs and not for FPGAs.

On the contrary: "flat" layout tools can do intelligent
placement automatically, and global placement optimization
(no artificial boundaries) is advantageous, just like for
synthesis.

The condition however is a clean design methodology, in
particular solid conservative synchronous design practices.

Therefore, my hypothesis is that people who claim that
"floorplanning is essential", like Mr. Karlsson and his
anynomous "expert", really use it as a workaround for a
messy methodology.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/03/2013 11:48 PM, Angel Ezquerra wrote:
> On Thu, Oct 3, 2013 at 6:20 PM, Jan Decaluwe <ja...@ja...> wrote:

> I know that I've been told this by a couple of times, by different
> Xilinx instructors, when I did some training classes on the Xilinx ISE
> tools a few years ago. Next time we get some Xilinx guys to visit us I
> will ask them if this is still the case.

Be careful with what Xilinx tells you - they may sell workarounds
for their own problems and limitations as "general FPGA recommendations".

For example, there is this guy (Ken Chapman), a Xilinx fellow, who
recommends fine-grained reset control to reduce resets to a
minimum. An important reason mentioned is saving on routing resources
and avoiding congestion.

The implications for the coding style I'm advocating
and trying to promote with MyHDL would be horribe and scary -
process partitioning just for reset control.

The fact that few complain about this must mean that many
designers work at a fairly low-level - the kind of typical
Verilog-inspired coding that I find horrible.

Now, Altera doesn't have such a recommendation afaik. And guess what,
in their newest architecture it seems that Xilinx will increase
global routing resources drastically. To me, this is evidence
that they recognize that something was wrong with their previous one.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/03/2013 11:48 PM, Angel Ezquerra wrote:

[About the need for floorplanning FPGAs]

> This may be one of those "folklore things" that get told from engineer
> to engineer, without a proper backup.

Sometimes it seems that the HDL design world, especially the Verilog side,
is *only* folklore. Like the absurd recommendation that one
"should not mix blocking and nonblocking assignments". (No problem
at all with local blocking assignments.) I suspect 95+% of the Verilog
world still believes this complete bullshit, at a great cost in good coding
pratices.

Verilog as a language is bad enough, but the real problem is that it
attracts a particular kind of hardware engineer, fond of low-level
thinking and unaware of good programming practices. And the larger
the company, the worse it gets, like with Ericsson and ARM for
example, because then mediocrity (of the hardware designers, not
the company) gets coupled with arrogance.

ARM actually claims that one shouldn't use if-then-else clauses in
HDL code. Instead of questioning the hypotheses that lead to this
obviously absurd conclusion, they make it a recommendation and
a requirement for subcontractors.

Such companies are also full of mediocre engineers that think they
are geniuses just because they have fought Verilog long enough to
get something to work. Then they make Verilog the norm of all things,
no matter how absurd, as the best example of the digital Stockholm
syndrome I know of. And of course, they feel too good to enter into
a rational discussion with those who actually know something about
this stuff, as we just saw. Those are the people that I really
hate in this profession.

> It may even have been true once,
> but perhaps it is no longer the case?

Or it may be true for one vendor and not for another.

Or for one family and not for another.

That's why I ask for evidence: an independent study by
a credible source that compares alternative flows based
on experiments.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MEP - keep hierarchy in conversion

[David H. <da...@ad...>]

Digging up a few docs for general edification in the realm of FPGA's,
hierarchical design, partitions, and constraints...


This Altera doc doesn't concisely claim it improves map/plan/route results:
 (in fact, it warns of the contrary...)

"Quartus II Incremental Compilation for Hierarchical and Team-Based Design"
http://www.altera.com/literature/hb/qts/qts_qii51015.pdf

But on the 2nd and 3rd pages, it does intro the trade-offs of "Flat
Compilation Flow with No Design Partitions" vs "Incremental Compilation
Flow With Design Partitions", and the rest of the document is interesting
as well.


And similar docs from Xilinx:

"Vivado Design Suite User Guide: Hierarchical Design"
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug905-vivado-hierarchical-design.pdf
page 4: "Users can iterate on a specific section of a design, achieving
timing closure and other specific goals, then reuse those exact results
while turning their attention to other parts of the design."

"Hierarchical Design Methodology Guide" [for ISE, not Vivado]
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/Hierarchical_Design_Methodology_Guide.pdf
page 53:  (block quote)

Design preservation:
• Reduces the number of implementation iterations during timing closure.
Once a portion of the design meets timing, the implementation results
(placement and routing) are used in the next iteration.
• Prevents portions of the design that are complete, and that meet timing,
from being affected by changes in other parts of the design.
• Uses partitions to preserve the previous implementation results for a
module instance.

Using partitions carefully:
• Reduces the number of design iterations.
• Shortens timing closure.
• Eliminates re-verification of unchanged instances.



Also, these appear relevant:
"Advanced Strategies for Improving Performance"
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/ise_c_imp_strategies.htm#styler-id1.1.1.12.4.6.3.3.8

"Timing Constraints Recommendations"
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/ise_c_imp_strategies.htm#styler-id1.1.1.12.4.6.3.3.9.1


(general impression:  Tools sometimes need a bit of guidance to get the job
done.)

- David


On Thu, Oct 3, 2013 at 5:48 PM, Angel Ezquerra <ang...@gm...>wrote:

> On Thu, Oct 3, 2013 at 6:20 PM, Jan Decaluwe <ja...@ja...> wrote:
> > On 10/02/2013 12:44 AM, Angel Ezquerra wrote:
> >> I cannot comment on the ASIC side, but on the FPGA side it is a common
> >> recommendation to properly organize your code into entities to improve
> >> the map and/or plan and route results.
> >
> > I have briefly checked the Xilinx docs and I haven't found
> > such a recommendation.
>
> This may be one of those "folklore things" that get told from engineer
> to engineer, without a proper backup. It may even have been true once,
> but perhaps it is no longer the case?
>
> I know that I've been told this by a couple of times, by different
> Xilinx instructors, when I did some training classes on the Xilinx ISE
> tools a few years ago. Next time we get some Xilinx guys to visit us I
> will ask them if this is still the case.
>

Re: [myhdl-list] MEP - keep hierarchy in conversion

[David H. <da...@ad...>]

A vendor neutral standard would be fantastic.  I notice a number of
references to Synopsys (.sdc) files from both Altera and Xilinx, but I'm
not sure how consistent that is.  [Anyone else have perspective here?]  Not
very vendor neutral, but just yet-another-vendor.  In the case of Xilinx,
their old [ISE] tools offer a variety of (disjoint) formats to specify
timing constraints.  I tend to use .ucf files, since they're simple text
files and easier on my eyes versus the clutter of .xml.  (and very simple
to export from a Python script...)

Personally I'm attracted to the latter approach -- of "generating all the
required files from MyHDL *.py + physical conf *.py depending on the target".
 :)  And for now, leaving the responsibility of dealing with vendor
specific file formats to the end-user --- such as they might generate from
their "physical conf *.py" files.

It would be nice if MyHDL could assist in auto-exporting some of the
assigned net names...  oh... I have another dirty code idea coming on...  I
could have the _convert_filter invoke user callback functions for any
requested signal, memory, or generator.  At that point in the process, all
the names are assigned, so the user can extract whatever names [or other
info?] as necessary to assist with generating constraint files.  Yep,
nasty.  [But then I can assign a "TIG" on that net w/out the nuisance of
manually sync'ing my constraints (.ucf) file when the occasional name
happens...]


On Thu, Oct 3, 2013 at 4:15 PM, Jan Decaluwe <ja...@ja...> wrote:

> On 10/03/2013 09:48 PM, David Holl wrote:
> > <snip>
> > Since this HDL is already in Python, and Python is pretty darn
> > flexible...  Could Python fill that higher role, and perhaps be
> > capable of doing such end-to-end design control?  (ie, in a
> > collection of .py files, some files are just for describing the logic
> > design, while others manage the resource assignment but assisted with
> > a few [as needed] hierarchical names from the logic design?)
>
> A reasonable suggestion. However, if there is already
> a standard, even de facto (I don't know) then reusing it
> might be considered. (I seemed to understand that Xilinx
> uses an xml input format). Alternatively, generating
> all the required files from MyHDL *.py + physical conf *.py
> depending on the target might be quite attractive too.
>
>

Re: [myhdl-list] MEP - keep hierarchy in conversion

[David H. <da...@ad...>]

Howdy Angel --- I finished implementing a switch which ought to help with
situations where predictable output ordering would be desired.  What do you
think?

Proposed Implementation:

Every signal and generator is assigned a unique number that is incremented
after each assignment.  During just prior to output conversion, a
_convert_filter sorts siglist, memlist and genlist:

    siglist.sort(key=lambda x: x._extData['sort_order'])
    memlist.sort(key=lambda x: x.elObj._extData['sort_order'])
    genlist.sort(key=lambda x: x._extData['sort_order'])

To enable, set
    toVerilog.sorted_output = True # default is False, to match usual
semi-random output

There are no other changes required to your MyHDL design aside from
setting toVerilog.sorted_output for conversion.

It is in the repo at https://dh...@bi.../dholl/myhdl-partition
available under two branches:
The "outputsort" branch supports only the sorted_output extension.
The "partition" branch supports both partitioned_output and sorted_output
extensions, so you could simultaneously enable:
    toVerilog.partitioned_output = True
    toVerilog.separate_files = True
    toVerilog.sorted_output = True
    toVerilog(the_top, clk, rst, ...)

(Implementation Note:  This extension required no additional modifications
to MyHDL beyond those contained in my "extension_hooks" branch.  A little
monkey-patching is involved, but by keeping a small footprint for the
underlying hooks, I hope to keep pace with MyHDL's development while
maintaining the extensions for my own work.)

- David


On Thu, Oct 3, 2013 at 10:13 AM, David Holl <da...@ad...> wrote:

> On Tue, Oct 1, 2013 at 6:44 PM, Angel Ezquerra <ang...@gm...>wrote:
>
>> <snip> If multiple files were generated,
>> only some of those files would usually change, making it easier to
>> tell what changed in a given version.
>>
>> So I think that there are a few sensible reasons for wanting the
>> ability to split the generated design into files and entities.
>>
> <snip>
> Additional idea:
>
> <snip> Preserve the order of signals and generators, according to the
> order in which you originally declared them in your code ---- not the order
> that MyHDL happens to traverse your netlist.
>

Re: [myhdl-list] MEP - keep hierarchy in conversion

[David H. <da...@ad...>]

>
> <snip>
> It's really easy to misinterpret one-another on internet boards (or so
> I've heard). Can't we just all focus on the technical stuff, and ignore the
> rest? It feels like we do the opposite on this board sometimes, and it is
> getting us nowhere.
>

Folks will argue when they're passionate about something.  I interpret the
ongoing discussions as a sign that Jan's MyHDL has developed quite the
following.  :)  [not just the recent few days, but over the history in the
mail archives]

Jan et al., Thank you for MyHDL!  We like it, and care.  :)

- David

Re: [myhdl-list] MEP - keep hierarchy in conversion

[Per K. <bas...@gm...>]

Are we reading the same text?

He described what happens when you run back-end tools without floorplanning
(which is what we wanted to know), and then questioned what those who have
not actually tried it have to bring to the discussion--which I think is a
fair point.

In my reading nobody's intelligence or character was brought into question,
only their knowledge.

It's really easy to misinterpret one-another on internet boards (or so I've
heard). Can't we just all focus on the technical stuff, and ignore the
rest? It feels like we do the opposite on this board sometimes, and it is
getting us nowhere.

Sorry, this was reeeeaaaaally my last post on the subject. :) (But it
doesn't count because it was actually not on the subject as such.)


On Thu, Oct 3, 2013 at 11:12 PM, Christopher Felton
<chr...@gm...>wrote:

> On 10/3/2013 3:40 PM, Per Karlsson wrote:
> > I considered censoring that last remark, since I suspected it might
> agitate
> > you. I'm sorry I didn't.
> > That said, it seems to me he was not cowardly but wise to stay anonymous.
> >
>
> It does suck when folks reduce a technical argument to
> "if you don't get it you are dumb".  If it is that simple,
> can't it be explained simply?  Instead of calling someone
> unintelligent just state the simple argument?
>
> It is easier to say outlandish things or be disrespectful
> if you don't have to own up to the words.
>
> .chris
>
>
>
>
>
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Re: [myhdl-list] MEP - keep hierarchy in conversion

[Angel E. <ang...@gm...>]

On Thu, Oct 3, 2013 at 6:20 PM, Jan Decaluwe <ja...@ja...> wrote:
> On 10/02/2013 12:44 AM, Angel Ezquerra wrote:
>> I cannot comment on the ASIC side, but on the FPGA side it is a common
>> recommendation to properly organize your code into entities to improve
>> the map and/or plan and route results.
>
> I have briefly checked the Xilinx docs and I haven't found
> such a recommendation.
>

This may be one of those "folklore things" that get told from engineer
to engineer, without a proper backup. It may even have been true once,
but perhaps it is no longer the case?

I know that I've been told this by a couple of times, by different
Xilinx instructors, when I did some training classes on the Xilinx ISE
tools a few years ago. Next time we get some Xilinx guys to visit us I
will ask them if this is still the case.

Cheers,

Angel