myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] myhdl.org website migration

[Jan D. <ja...@ja...>]

On 02/17/2014 08:37 PM, Angel Ezquerra wrote:

> I think I miss some kind graphical element like in the bootstrap page
> to give the landing page a bit more "oomph".

Added some icons from font-awesome - idea borrowed from bootswatch.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] myhdl.org website migration

[Angel E. <ang...@gm...>]

On Mon, Feb 17, 2014 at 5:18 PM, Jan Decaluwe <ja...@ja...> wrote:
> On 02/16/2014 07:44 PM, Angel Ezquerra wrote:
>
>>
>> That it's great! You should definitely shoot for something like that.
>> That is exactly the kind of thing that I had in mind when I wrote my
>> previous email.
>
> I have just pushed something up based on highlights from
> the old site and inspired by the bootstrap design style.

That is much better! You _did_ explain the gist of MyHDL with just a
few lines :-)

I think I miss some kind graphical element like in the bootstrap page
to give the landing page a bit more "oomph". That being said this is
already quite nice.

Cheers,

Angel

Re: [myhdl-list] myhdl.org website migration

[Angel E. <ang...@gm...>]

On Mon, Feb 17, 2014 at 5:17 PM, Jan Decaluwe <ja...@ja...> wrote:
> On 02/16/2014 07:08 PM, Angel Ezquerra wrote:
>
>>> Now we have the name and a tagline. I see the value
>>> of adding a one or two liner description, and perhaps
>>> the latest "News" item.
>>
>> For what is worth, I agree with Chris.
>>
>> My first thought upon seeing the new web page was:
>>
>> "This looks nice and modern"
>>
>> quickly followed by:
>>
>> "This looks quite empty".
>>
>> Personally whenever I go to a new web page, I like to be able to
>> understand what it is about by reading what is shown to me on the
>> landing page. I think a lot of people feel the same. Currently I just
>> see the "tag line" which is nice, but I don't really see how MyHDL
>> helps me go "From Python to Silicon".
>>
>> What is the point of the landing page if I _must_ go to some other
>> page to see what the whole thing is about?
>
> I don't understand your reply. I have just said that I
> see the value of more info, like a 2 liner description and
> the latest News item.

Yes, that is what you said and IMHO it may not be enough. I don't
think you can explain what MyHDL is in a couple of lines.

> *Of course* it looks empty now, this is work in progress,
> which has not been "released" yet!

I was referring to the feel of the landing page in particular. Your
comment led me to think that you did not want to put much more in
there. Maybe I was wrong.

> I was just warning agains my own tendency (as an engineer
> that doesn't know much about good visual design), to try
> to say or link everything everywhere.

That is a good idea, but it is also way too easy to go overboard with
the minimalism.

> I'm impressed by the
> bootstrap guys, both technically and design-wise, and
> I would like a landing page like they have:
>
> http://getbootstrap.com/

That it's great! You should definitely shoot for something like that.
That is exactly the kind of thing that I had in mind when I wrote my
previous email.

Cheers,

Angel

Re: [myhdl-list] myhdl.org website migration

[Angel E. <ang...@gm...>]

On Mon, Feb 17, 2014 at 5:23 PM, Jan Decaluwe <ja...@ja...> wrote:
> Sorry, I made the mistake to reply only to you instead
> of to the list, so that the rest of this very interesting
> conversation :-) fell off the list.
>
> I have just posted my replies to the list using "Edit message as new",
> if it is possible for you to do the same everyone can follow.
>
> Jan

OK, I will do so in a minute. I will try to reply to the emails that
you just resent to the list, as if I were reply to them for the first
time.

Cheers,

Angel


> On 02/16/2014 07:08 PM, Angel Ezquerra wrote:
>> On Sun, Feb 16, 2014 at 6:29 PM, Jan Decaluwe <ja...@ja...> wrote:
>>> On 02/14/2014 02:47 PM, Christopher Felton wrote:
>>>
>>>> Couple (minor) comments on the new site.
>>>>
>>>> Is there a way to easily link back to the site from
>>>> the manual?  I found it a little frustrating jumping
>>>> to the manual and back to the site.
>>>
>>> The manual link is to the manual generated with readthedocs.org,
>>> which looks like a convenient automatic method for the future.
>>>
>>> Anyone knows how include return links in readthedocs
>>> manuals?
>>>
>>>> I realize the menu system has the links to get started,
>>>> etc.  But I think having some more content on the landing
>>>> page would be beneficial for new visitors, etc.  I can
>>>> create a pull-request with some ideas.
>>>
>>> I suggest to discuss this first. I want to learn from
>>> good examples (bootstrap) and keep the landing page
>>> as "to the point" and short as possible.
>>>
>>> Now we have the name and a tagline. I see the value
>>> of adding a one or two liner description, and perhaps
>>> the latest "News" item.
>>
>> For what is worth, I agree with Chris.
>>
>> My first thought upon seeing the new web page was:
>>
>> "This looks nice and modern"
>>
>> quickly followed by:
>>
>> "This looks quite empty".
>>
>> Personally whenever I go to a new web page, I like to be able to
>> understand what it is about by reading what is shown to me on the
>> landing page. I think a lot of people feel the same. Currently I just
>> see the "tag line" which is nice, but I don't really see how MyHDL
>> helps me go "From Python to Silicon".
>>
>> What is the point of the landing page if I _must_ go to some other
>> page to see what the whole thing is about?
>>
>>>> Also, my contribution plan to the new site is adding
>>>> examples.  In the past I experimented with adding the
>>>> examples to the manual and using doctest to verify the
>>>> examples when a new version of the manual was created.
>>>> I think this would be good as release tests (that is
>>>> verifying the examples on the site still work).  Now,
>>>> that the new website is in a repository, I propose we
>>>> add a little (as little as possible) formality to the
>>>> examples so we can leverage this code collection for
>>>> release testing, e.g. all examples should have:
>>>>
>>>>        1. description write up
>>>>        2. .py file with working example
>>>>        3. test for the example
>>>>
>>>> In addition, there are ways to embedded the code from
>>>> bitbucket in the example write-up, the write-up can
>>>> always have the latest code (easy to maintain the examples),
>>>> thoughts?
>>>
>>> Mm, I don't think we want to do repo accesses over the
>>> net on every build. Of course, you could add a script
>>> to pull the sources automatically on demand.
>>>
>>> The straightforward way would be to have some "include"
>>> facility in the markdown format - however markdown doesn't
>>> support this :-( No doubt we can find a workaround or add
>>> support ourselves, but I propose to delay that for a
>>> future optimization.
>>
>> What Markdown variant are you using? I am partial to pandoc's variant
>> (http://johnmacfarlane.net/pandoc/demo/example9/pandocs-markdown.html)
>> which I think is very nice.
>>
>> Cheers,
>>
>> Angel
>>
>> ------------------------------------------------------------------------------
>> Android apps run on BlackBerry 10
>> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
>> Now with support for Jelly Bean, Bluetooth, Mapview and more.
>> Get your Android app in front of a whole new audience.  Start now.
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>> _______________________________________________
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>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
> ------------------------------------------------------------------------------
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Re: [myhdl-list] myhdl.org website migration

[Jan D. <ja...@ja...>]

Sorry, I made the mistake to reply only to you instead
of to the list, so that the rest of this very interesting
conversation :-) fell off the list.

I have just posted my replies to the list using "Edit message as new",
if it is possible for you to do the same everyone can follow.

Jan

On 02/16/2014 07:08 PM, Angel Ezquerra wrote:
> On Sun, Feb 16, 2014 at 6:29 PM, Jan Decaluwe <ja...@ja...> wrote:
>> On 02/14/2014 02:47 PM, Christopher Felton wrote:
>>
>>> Couple (minor) comments on the new site.
>>>
>>> Is there a way to easily link back to the site from
>>> the manual?  I found it a little frustrating jumping
>>> to the manual and back to the site.
>>
>> The manual link is to the manual generated with readthedocs.org,
>> which looks like a convenient automatic method for the future.
>>
>> Anyone knows how include return links in readthedocs
>> manuals?
>>
>>> I realize the menu system has the links to get started,
>>> etc.  But I think having some more content on the landing
>>> page would be beneficial for new visitors, etc.  I can
>>> create a pull-request with some ideas.
>>
>> I suggest to discuss this first. I want to learn from
>> good examples (bootstrap) and keep the landing page
>> as "to the point" and short as possible.
>>
>> Now we have the name and a tagline. I see the value
>> of adding a one or two liner description, and perhaps
>> the latest "News" item.
>
> For what is worth, I agree with Chris.
>
> My first thought upon seeing the new web page was:
>
> "This looks nice and modern"
>
> quickly followed by:
>
> "This looks quite empty".
>
> Personally whenever I go to a new web page, I like to be able to
> understand what it is about by reading what is shown to me on the
> landing page. I think a lot of people feel the same. Currently I just
> see the "tag line" which is nice, but I don't really see how MyHDL
> helps me go "From Python to Silicon".
>
> What is the point of the landing page if I _must_ go to some other
> page to see what the whole thing is about?
>
>>> Also, my contribution plan to the new site is adding
>>> examples.  In the past I experimented with adding the
>>> examples to the manual and using doctest to verify the
>>> examples when a new version of the manual was created.
>>> I think this would be good as release tests (that is
>>> verifying the examples on the site still work).  Now,
>>> that the new website is in a repository, I propose we
>>> add a little (as little as possible) formality to the
>>> examples so we can leverage this code collection for
>>> release testing, e.g. all examples should have:
>>>
>>>        1. description write up
>>>        2. .py file with working example
>>>        3. test for the example
>>>
>>> In addition, there are ways to embedded the code from
>>> bitbucket in the example write-up, the write-up can
>>> always have the latest code (easy to maintain the examples),
>>> thoughts?
>>
>> Mm, I don't think we want to do repo accesses over the
>> net on every build. Of course, you could add a script
>> to pull the sources automatically on demand.
>>
>> The straightforward way would be to have some "include"
>> facility in the markdown format - however markdown doesn't
>> support this :-( No doubt we can find a workaround or add
>> support ourselves, but I propose to delay that for a
>> future optimization.
>
> What Markdown variant are you using? I am partial to pandoc's variant
> (http://johnmacfarlane.net/pandoc/demo/example9/pandocs-markdown.html)
> which I think is very nice.
>
> Cheers,
>
> Angel
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] myhdl.org website migration

[Jan D. <ja...@ja...>]

On 02/17/2014 11:09 AM, Angel Ezquerra wrote:

> I think I miss some kind graphical element like in the bootstrap page
> to give the landing page a bit more "oomph". That being said this is
> already quite nice.

Ok, but note that bootstrap itself doesn't even have a
real logo (just a letter B with a border): the graphical
elements refer to other tools or illustrate concepts.

I think I would like a logo for MyHDL, but I also think
we need a more modern (minimalistic? :-)) one than the
current one on MyHDL.org.

And again, I think this is something for design professionals,
not electronic engineers. It seems there are such services on the
internet - no idea whether this is worthwhile.

Anyone with suggestions?

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] myhdl.org website migration

[Jan D. <ja...@ja...>]

On 02/16/2014 07:44 PM, Angel Ezquerra wrote:

>
> That it's great! You should definitely shoot for something like that.
> That is exactly the kind of thing that I had in mind when I wrote my
> previous email.

I have just pushed something up based on highlights from
the old site and inspired by the bootstrap design style.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] myhdl.org website migration

[Jan D. <ja...@ja...>]

On 02/16/2014 07:08 PM, Angel Ezquerra wrote:

>> Now we have the name and a tagline. I see the value
>> of adding a one or two liner description, and perhaps
>> the latest "News" item.
>
> For what is worth, I agree with Chris.
>
> My first thought upon seeing the new web page was:
>
> "This looks nice and modern"
>
> quickly followed by:
>
> "This looks quite empty".
>
> Personally whenever I go to a new web page, I like to be able to
> understand what it is about by reading what is shown to me on the
> landing page. I think a lot of people feel the same. Currently I just
> see the "tag line" which is nice, but I don't really see how MyHDL
> helps me go "From Python to Silicon".
>
> What is the point of the landing page if I _must_ go to some other
> page to see what the whole thing is about?

I don't understand your reply. I have just said that I
see the value of more info, like a 2 liner description and
the latest News item.

*Of course* it looks empty now, this is work in progress,
which has not been "released" yet!

I was just warning agains my own tendency (as an engineer
that doesn't know much about good visual design), to try
to say or link everything everywhere. I'm impressed by the
bootstrap guys, both technically and design-wise, and
I would like a landing page like they have:

http://getbootstrap.com/


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] myhdl.org website migration

[Angel E. <ang...@gm...>]

On Sun, Feb 16, 2014 at 6:29 PM, Jan Decaluwe <ja...@ja...> wrote:
> On 02/14/2014 02:47 PM, Christopher Felton wrote:
>
>> Couple (minor) comments on the new site.
>>
>> Is there a way to easily link back to the site from
>> the manual?  I found it a little frustrating jumping
>> to the manual and back to the site.
>
> The manual link is to the manual generated with readthedocs.org,
> which looks like a convenient automatic method for the future.
>
> Anyone knows how include return links in readthedocs
> manuals?
>
>> I realize the menu system has the links to get started,
>> etc.  But I think having some more content on the landing
>> page would be beneficial for new visitors, etc.  I can
>> create a pull-request with some ideas.
>
> I suggest to discuss this first. I want to learn from
> good examples (bootstrap) and keep the landing page
> as "to the point" and short as possible.
>
> Now we have the name and a tagline. I see the value
> of adding a one or two liner description, and perhaps
> the latest "News" item.

For what is worth, I agree with Chris.

My first thought upon seeing the new web page was:

"This looks nice and modern"

quickly followed by:

"This looks quite empty".

Personally whenever I go to a new web page, I like to be able to
understand what it is about by reading what is shown to me on the
landing page. I think a lot of people feel the same. Currently I just
see the "tag line" which is nice, but I don't really see how MyHDL
helps me go "From Python to Silicon".

What is the point of the landing page if I _must_ go to some other
page to see what the whole thing is about?

>> Also, my contribution plan to the new site is adding
>> examples.  In the past I experimented with adding the
>> examples to the manual and using doctest to verify the
>> examples when a new version of the manual was created.
>> I think this would be good as release tests (that is
>> verifying the examples on the site still work).  Now,
>> that the new website is in a repository, I propose we
>> add a little (as little as possible) formality to the
>> examples so we can leverage this code collection for
>> release testing, e.g. all examples should have:
>>
>>       1. description write up
>>       2. .py file with working example
>>       3. test for the example
>>
>> In addition, there are ways to embedded the code from
>> bitbucket in the example write-up, the write-up can
>> always have the latest code (easy to maintain the examples),
>> thoughts?
>
> Mm, I don't think we want to do repo accesses over the
> net on every build. Of course, you could add a script
> to pull the sources automatically on demand.
>
> The straightforward way would be to have some "include"
> facility in the markdown format - however markdown doesn't
> support this :-( No doubt we can find a workaround or add
> support ourselves, but I propose to delay that for a
> future optimization.

What Markdown variant are you using? I am partial to pandoc's variant
(http://johnmacfarlane.net/pandoc/demo/example9/pandocs-markdown.html)
which I think is very nice.

Cheers,

Angel

Re: [myhdl-list] myhdl.org website migration

[Jan D. <ja...@ja...>]

On 02/14/2014 02:47 PM, Christopher Felton wrote:

> Couple (minor) comments on the new site.
>
> Is there a way to easily link back to the site from
> the manual?  I found it a little frustrating jumping
> to the manual and back to the site.

The manual link is to the manual generated with readthedocs.org,
which looks like a convenient automatic method for the future.

Anyone knows how include return links in readthedocs
manuals?

> I realize the menu system has the links to get started,
> etc.  But I think having some more content on the landing
> page would be beneficial for new visitors, etc.  I can
> create a pull-request with some ideas.

I suggest to discuss this first. I want to learn from
good examples (bootstrap) and keep the landing page
as "to the point" and short as possible.

Now we have the name and a tagline. I see the value
of adding a one or two liner description, and perhaps
the latest "News" item.

> Also, my contribution plan to the new site is adding
> examples.  In the past I experimented with adding the
> examples to the manual and using doctest to verify the
> examples when a new version of the manual was created.
> I think this would be good as release tests (that is
> verifying the examples on the site still work).  Now,
> that the new website is in a repository, I propose we
> add a little (as little as possible) formality to the
> examples so we can leverage this code collection for
> release testing, e.g. all examples should have:
>
>       1. description write up
>       2. .py file with working example
>       3. test for the example
>
> In addition, there are ways to embedded the code from
> bitbucket in the example write-up, the write-up can
> always have the latest code (easy to maintain the examples),
> thoughts?

Mm, I don't think we want to do repo accesses over the
net on every build. Of course, you could add a script
to pull the sources automatically on demand.

The straightforward way would be to have some "include"
facility in the markdown format - however markdown doesn't
support this :-( No doubt we can find a workaround or add
support ourselves, but I propose to delay that for a
future optimization.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] @always_comb - Conversion Error

[Jan D. <ja...@ja...>]

Did you simulate this?

I don't think so. But you should:

http://www.myhdl.org/doc/current/manual/conversion.html#simulate-first

Any operation on a Signal, including slicing, operates on the
underlying value. In particular, slicing a Signal of an intbv
returns an intbv, not a Signal.

In other words, the "signal" aspect of your inputs is gone
and I don't see how this can work. And if it doesn't work,
conclusions about convertibility are meaningless.

On 02/11/2014 02:29 AM, Carlos Silva wrote:
> Hi,
>
> I´ve had been using MyHDL to generate dynamic Verilog code directly from a
> python program. Leaving apart some natural difficulties due to my need of
> dynamic number of inputs and input widths, I´m facing a problem with an
> instance that I thought will be simple to implement, but returned me an
> unexpected error.
>
> Im trying to implement a simple 8x3 multiplexer and I receive the following
> error:
>
> Traceback (most recent call last):
>    File "C:\ECLIPSE\Scales_verilog\DYN\average_hw.py", line 624, in <module>
>      N_TRUNC, N_CALIB)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_toVerilog.py", line
> 135, in __call__
>      genlist = _analyzeGens(arglist, h.absnames)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_analyze.py", line
> 168, in _analyzeGens
>      raise ConversionError(_error.UnsupportedType, n, info)
> myhdl.ConversionError: File C:\ECLIPSE\Scales_verilog\DYN\HDW.py, line 182:
> Object type is not supported in this context: in4
>
> The related parts of my code are:
>
>      n0 = Signal(intbv(15))[12:0]
>      n1 = Signal(intbv(31))[12:0]
>      n2 = Signal(intbv(63))[12:0]
>      n3 = Signal(intbv(127))[12:0]
>      n4 = Signal(intbv(255))[12:0]
>      n5 = Signal(intbv(511))[12:0]
>      n6 = Signal(intbv(1023))[12:0]
>      n7 = Signal(intbv(2047))[12:0]
>      db6 = Signal(intbv(0)[12:0])
>      n = Signal(intbv(0)[3:0])
>      U_25 = Mux_8(n0, n1, n2, n3, n4, n5, n6, n7, db6, n)
>
> # Multiplexer (8 inputs, 3 bits selector)
> def Mux_8(in0, in1, in2, in3, in4, in5, in6, in7, out, sel):
>      @always_comb
>      def logic():
>          if sel == 0x0:
>              out.next = in0
>          elif sel == 0x1:
>              out.next = in1
>          elif sel == 0x2:
>              out.next = in2
>          elif sel == 0x3:
>              out.next = in3
>          elif sel == 0x4:
>              out.next = in4
>          elif sel == 0x5:
>              out.next = in5
>          elif sel == 0x6:
>              out.next = in6
>          else:
>              out.next = in7
>      return instances()
>
>
> I have edited manually the code of "_extractHierarchy" with some print
> statements to obtain the types for each input, and it stops at in4, with the
> following sequence of prints:
>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._intbv.intbv'>
>
>
> The original type of all the inputs is <class 'myhdl._intbv.intbv'>.
>
> Using python 2.7 under Eclipse with Pydev and MyHDL 0.8.
>
>
> Any sugestions?
>
>
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

[myhdl-list] Website migration clarification

[Jan D. <ja...@ja...>]

After some feedback, I'd like to clarify some points
about the myhdl.org website migration.

1) 2 websites
The old myhdl.org will be split into two: dev.myhdl.org
for development info and a new myhdl.org for users. The
new myhdl.org is currently developed under new.myhdl.org.

2) *No content will be lost*
A snapshot of all content has been checked in in the mercurial
repo for the new website under _ori.

3) No one is forced to use the new system, not even
to migrate his old content.

If you don't have time or don't want to use the new
system, but still want your content migrated, no
problem: just let me know in private mail. I or someone
else will migrate it eventually.

Because of 2) there is no time constraint for migration:
as everything is in the repo, old content can be
ressurected at any time.

4) Migration is a good time for review and edits.

This is an opportunity to review all content, bring
it up to date, remove dead links, and discard clearly
outdated content.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MEP 107 need for portmap

[Keerthan jai.c <jck...@gm...>]

I'm not sure which approach is more pythonic in this scenario. However,
currently the only interface to the conversion functions are through toV*
attributes. I think it is more 'consistent' to use toVerilog.portmap,
unless we make the other parameters(such as toVerilog.name) exposed through
top level function attributes too.


On Fri, Feb 14, 2014 at 8:50 AM, Christopher Felton
<chr...@gm...>wrote:

> Previously, we had a short discussion that the MEP107
> interface conversion for top-levels (e.g modules being
> converted) introduced a need for a generated /portmap/ [1].
>
> The main uses case, given a module:
>
>      def m_some_mod(ifc1, ifc2):
>          # ...
>
> If I am verifying the above module via co-simulation,
> without a /portmap/ I would need to manually write a
> wrapper or manually breakout all the interface /Signals/
> when building the /Cosimulation/, example:
>
>      Cosimualation(simcmd, ifc1_di=ifc1.di, ifc1_do=ifc1.do ...
>
> In this case it defeats the purpose of the interfaces.
> To address this complication Keerthan proposed a /portmap/
> be generated in the conversion functions, the above would
> then become:
>
>      Cosimulation(simcmd, **portmap)
>
> Ahhh, much better :)
>
> The /toV*/ functions already return a list generators in
> the module.  The /portmap/ can't be returned from the
> /toV*/ functions without breaking backwards compatibility.
>
> The current proposal is to attach a function attribute to the
> /toV*/ functions, e.g:
>
>      toVerilog.portmap
>
> The /toV*.portmap/ would be the dictionary of the converted
> portmap (interface expanded names).
>
> I would like to propose and discuss attaching the /portmap/
> attribute to the function being converted and not the
> conversion functions.  To me this is a more natural (I don't
> know if this is generally pythonic (accepted) to have other
> functions modify and/or add attributes to other functions).
>
> In addition, I would propose that generated portmap saved
> in the /vportmap/ attribute and the /portmap/ attribute
> to be used as a user defined default port definition.
>
> Keerthan has done an amazing job implementing MEP-107, many
> thanks!  He has also created a pull-request for the
> /toVerilog.portmap/, I wanted to have a short discussion
> and make sure this is the most flexible path moving forward.
> Once we finalize the portmap I can update the MEP.
>
> Regards,
> Chris
>
> [1] http://thread.gmane.org/gmane.comp.python.myhdl/3223/focus=3318
>
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
>
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] Dynamic ports

[Carlos S. <car...@sa...>]

Yes, I confirm that the first method didn´t solve the problem (the design 
was built without ports, this time, as the ports were not recognized 
automatically by Verilog Converter).

I will try this second approach and give you feedback.

I also found another article posted by you:
http://www.fpgarelated.com/showarticle/544.php
That presents a new feature available in future MyHDL 0.9 version that seems 
to be a good solution to my problem. But I can´t wait for the new version of 
MyHDL.

Re: [myhdl-list] Dynamic ports

[Christopher F. <chr...@gm...>]

I am dazed and confused - my previous response is only
partial.  When your top-level function (myhdl module) is
evaluated the "ports" (function arguments) are determined.
In other-words, you do need to explicitly state them.

One method to work around (hack) is to create a string
and evaluate it, example:

     top_template = \
     """
     def m_outer_top(%s):
         portmap = {%s}
         return m_top_vargs(**portmap)
     """ % (", ".join(portmap.keys()),
            ", ".join(["'%s':%s"%(k,k) for k,v in portmap.items()]))

     exec(top_template)
     toVerilog(m_outer_top, *x, y=y, sel=sel)

If you dynamically build the "outer top" you can then use
the generic "inner top" and that might work.

Regards,
Chris

On 2/14/14 10:25 AM, Christopher Felton wrote:
> I would try something like the following - I have
> not tested this thoroughly but something like this
> should get you where you need to be.
>
> In [116]: def m_top_vargs(**portmap):
>        ...:     # need a method to locally reference all the
>        ...:     # ports passed, example
>        ...:     xcnt = sum([1 for k in portmap if 'x' in k])
>        ...:     locallist = [Signal(intbv(0)[12:]) for _ in range(xcnt)]
>        ...:     sel = portmap['sel']
>        ...:     y = portmap['y']
>        ...:     xi = 0
>        ...:     for k,v in portmap.iteritems():
>        ...:         if 'x' in k:
>        ...:             locallist[ii].assign(v)
>        ...:             xi += 1
>        ...:     print(locallist)
>        ...:
>
> In [117]: portmap = {'sel': Signal(intbv(0)[4:]),'y': Signal(intbv(0)[21:])}
>        ...: for ii in range(8):  # for the number of inputs
>        ...:     portmap['x%d'%ii] = Signal(intbv(0)[21:])
>        ...: m_top_vargs(**portmap)
>        ...:
> [Signal(intbv(0L)), Signal(intbv(0L)), Signal(intbv(0L)),
> Signal(intbv(0L)), Signal(intbv(0L)), Signal(intbv(0L)),
> Signal(intbv(0L)), Signal(intbv(0L))]
>
>
> On 2/14/2014 9:57 AM, Carlos Silva wrote:
>> Hi,
>>
>> As I mentioned in a previous post, I´m using MyHDL to generate Verilog code
>> directly from an ADC simulation program written in Python.
>>
>> ADC´s can be generated with different number of stages and different
>> resolutions per stage, so, my actual approach is based on the maximum number
>> of ports that can be used, and if they aren´t used, they stay disconnected.
>>
>> But this is not the perfect solution. Ports that are not used appear in final
>> design, disconnected, but I need them to be discarded during conversion, to
>> build a cleaner final design.
>>
>> I can generate N different files to generate N different configurations, but
>> it is certainly an ugly and heavy solution.
>>
>> Is it possible to discard disconnected ports during conversion to Verilog?
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Android apps run on BlackBerry 10
>> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
>> Now with support for Jelly Bean, Bluetooth, Mapview and more.
>> Get your Android app in front of a whole new audience.  Start now.
>> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Dynamic ports

[Christopher F. <chr...@gm...>]

I would try something like the following - I have
not tested this thoroughly but something like this
should get you where you need to be.

In [116]: def m_top_vargs(**portmap):
      ...:     # need a method to locally reference all the
      ...:     # ports passed, example
      ...:     xcnt = sum([1 for k in portmap if 'x' in k])
      ...:     locallist = [Signal(intbv(0)[12:]) for _ in range(xcnt)]
      ...:     sel = portmap['sel']
      ...:     y = portmap['y']
      ...:     xi = 0
      ...:     for k,v in portmap.iteritems():
      ...:         if 'x' in k:
      ...:             locallist[ii].assign(v)
      ...:             xi += 1
      ...:     print(locallist)
      ...:

In [117]: portmap = {'sel': Signal(intbv(0)[4:]),'y': Signal(intbv(0)[21:])}
      ...: for ii in range(8):  # for the number of inputs
      ...:     portmap['x%d'%ii] = Signal(intbv(0)[21:])
      ...: m_top_vargs(**portmap)
      ...:
[Signal(intbv(0L)), Signal(intbv(0L)), Signal(intbv(0L)), 
Signal(intbv(0L)), Signal(intbv(0L)), Signal(intbv(0L)), 
Signal(intbv(0L)), Signal(intbv(0L))]


On 2/14/2014 9:57 AM, Carlos Silva wrote:
> Hi,
>
> As I mentioned in a previous post, I´m using MyHDL to generate Verilog code
> directly from an ADC simulation program written in Python.
>
> ADC´s can be generated with different number of stages and different
> resolutions per stage, so, my actual approach is based on the maximum number
> of ports that can be used, and if they aren´t used, they stay disconnected.
>
> But this is not the perfect solution. Ports that are not used appear in final
> design, disconnected, but I need them to be discarded during conversion, to
> build a cleaner final design.
>
> I can generate N different files to generate N different configurations, but
> it is certainly an ugly and heavy solution.
>
> Is it possible to discard disconnected ports during conversion to Verilog?
>
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] Dynamic ports

[Carlos S. <car...@sa...>]

Hi,

As I mentioned in a previous post, I´m using MyHDL to generate Verilog code 
directly from an ADC simulation program written in Python.

ADC´s can be generated with different number of stages and different 
resolutions per stage, so, my actual approach is based on the maximum number 
of ports that can be used, and if they aren´t used, they stay disconnected.

But this is not the perfect solution. Ports that are not used appear in final 
design, disconnected, but I need them to be discarded during conversion, to 
build a cleaner final design.

I can generate N different files to generate N different configurations, but 
it is certainly an ugly and heavy solution.

Is it possible to discard disconnected ports during conversion to Verilog?

Re: [myhdl-list] <at> always_comb - Conversion Error

[Carlos S. <car...@sa...>]

Thanks, Chris

I apreciate your help.

That solved my problem. :)

Re: [myhdl-list] @always_comb - Conversion Error

[Christopher F. <chr...@gm...>]

I didn't debug your example but the following is an
alternative approach.

A flexible mux:

     def m_mux(sigin, sigout, sel):
         @always_comb
         def rtl():
             sigout.next = sigin[sel]
         return rtl

A top-level wrapper (to convert) with the values you
previously provided:

     def m_mux_top(y, sel):
         # in this example, x has no drivers. make x constant
         x = (15, 31, 63, 127, 255, 511, 1023, 2047,)
         gmux = m_mux(x, y, sel)
         return gmux

When including the mux in a design, you can create
a list of signals and pass it to the mux.  The following
illustrates using the mux with a list of signals.  Note,
you have to jump through some hoops for conversion.  It
only makes sense to convert discrete top-level ports.  This
would not need to be completed (an intermediate list of
signals if top-level ports are not included)


     def m_mux_top8(x0, x1, x2, x3, x4, x5, x6, x7, y, sel):
         inputs = (x0,x1,x2,x3,x4,x5,x6,x7,)
         locallist = [Signal(xx.val) for xx in inputs]
         for xx,ll in zip(inputs,locallist):
             ll.assign(xx)
         print(ll)
         gmux = m_mux(locallist, y, sel)
         return gmux

And finally a short test and conversion:

     # ---[Simple Testbench and Conversion]---
     x = [Signal(intbv(init)[12:])
          for init in (15, 31, 63, 127, 255, 511, 1023, 2047,)]
     y = Signal(intbv(0)[12:])
     sel = Signal(intbv(0, min=0, max=len(x)))
     tbdut = m_mux_top(y, sel)
     def test(tbdut):
         @instance
         def tbstim():
             for ii in range(len(x)):
                 sel.next = ii
                 yield delay(4)
                 assert y == x[ii], " x[%d] %d, y %d" % \
                                    (ii,int(x[ii]),int(y))
         return tbstim, tbdut

     Simulation(test(m_mux_top(y,sel))).run()
     Simulation(test(m_mux_top8(*x, y=y, sel=sel))).run()
     toVerilog(m_mux_top, y=y, sel=sel)
     toVerilog(m_mux_top8, *x, y=y, sel=sel)

Regards,
Chris

----------------------------------------------------------------
The converted Verilog
----------------------------------------------------------------
%less m_mux_top.v
// File: m_mux_top.v
// Generated by MyHDL 0.9dev
// Date: Fri Feb 14 08:33:37 2014

`timescale 1ns/10ps

module m_mux_top8 (
     y,
     sel
);

output [11:0] y;
reg [11:0] y;
input [2:0] sel;

always @(sel) begin: M_MUX_TOP_GMUX_RTL
     case (sel)
         0: y = 15;
         1: y = 31;
         2: y = 63;
         3: y = 127;
         4: y = 255;
         5: y = 511;
         6: y = 1023;
         default: y = 2047;
     endcase
end

endmodule

In [109]: %less m_mux_top8.v
// File: m_mux_top8.v
// Generated by MyHDL 0.9dev
// Date: Fri Feb 14 08:33:37 2014

`timescale 1ns/10ps

module m_mux_top8 (
     x0,
     x1,
     x2,
     x3,
     x4,
     x5,
     x6,
     x7,
     y,
     sel
);

input [11:0] x0;
input [11:0] x1;
input [11:0] x2;
input [11:0] x3;
input [11:0] x4;
input [11:0] x5;
input [11:0] x6;
input [11:0] x7;
output [11:0] y;
wire [11:0] y;
input [2:0] sel;

wire [11:0] locallist [0:8-1];

assign y = locallist[sel];

endmodule


On 2/10/2014 7:29 PM, Carlos Silva wrote:
> Hi,
>
> I´ve had been using MyHDL to generate dynamic Verilog code directly from a
> python program. Leaving apart some natural difficulties due to my need of
> dynamic number of inputs and input widths, I´m facing a problem with an
> instance that I thought will be simple to implement, but returned me an
> unexpected error.
>
> Im trying to implement a simple 8x3 multiplexer and I receive the following
> error:
>
> Traceback (most recent call last):
>    File "C:\ECLIPSE\Scales_verilog\DYN\average_hw.py", line 624, in <module>
>      N_TRUNC, N_CALIB)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_toVerilog.py", line
> 135, in __call__
>      genlist = _analyzeGens(arglist, h.absnames)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_analyze.py", line
> 168, in _analyzeGens
>      raise ConversionError(_error.UnsupportedType, n, info)
> myhdl.ConversionError: File C:\ECLIPSE\Scales_verilog\DYN\HDW.py, line 182:
> Object type is not supported in this context: in4
>
> The related parts of my code are:
>
>      n0 = Signal(intbv(15))[12:0]
>      n1 = Signal(intbv(31))[12:0]
>      n2 = Signal(intbv(63))[12:0]
>      n3 = Signal(intbv(127))[12:0]
>      n4 = Signal(intbv(255))[12:0]
>      n5 = Signal(intbv(511))[12:0]
>      n6 = Signal(intbv(1023))[12:0]
>      n7 = Signal(intbv(2047))[12:0]
>      db6 = Signal(intbv(0)[12:0])
>      n = Signal(intbv(0)[3:0])
>      U_25 = Mux_8(n0, n1, n2, n3, n4, n5, n6, n7, db6, n)
>
> # Multiplexer (8 inputs, 3 bits selector)
> def Mux_8(in0, in1, in2, in3, in4, in5, in6, in7, out, sel):
>      @always_comb
>      def logic():
>          if sel == 0x0:
>              out.next = in0
>          elif sel == 0x1:
>              out.next = in1
>          elif sel == 0x2:
>              out.next = in2
>          elif sel == 0x3:
>              out.next = in3
>          elif sel == 0x4:
>              out.next = in4
>          elif sel == 0x5:
>              out.next = in5
>          elif sel == 0x6:
>              out.next = in6
>          else:
>              out.next = in7
>      return instances()
>
>
> I have edited manually the code of "_extractHierarchy" with some print
> statements to obtain the types for each input, and it stops at in4, with the
> following sequence of prints:
>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._intbv.intbv'>
>
>
> The original type of all the inputs is <class 'myhdl._intbv.intbv'>.
>
> Using python 2.7 under Eclipse with Pydev and MyHDL 0.8.
>
>
> Any sugestions?
>
>
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] MEP 107 need for portmap

[Christopher F. <chr...@gm...>]

Previously, we had a short discussion that the MEP107
interface conversion for top-levels (e.g modules being
converted) introduced a need for a generated /portmap/ [1].

The main uses case, given a module:

     def m_some_mod(ifc1, ifc2):
         # ...

If I am verifying the above module via co-simulation,
without a /portmap/ I would need to manually write a
wrapper or manually breakout all the interface /Signals/
when building the /Cosimulation/, example:

     Cosimualation(simcmd, ifc1_di=ifc1.di, ifc1_do=ifc1.do ...

In this case it defeats the purpose of the interfaces.
To address this complication Keerthan proposed a /portmap/
be generated in the conversion functions, the above would
then become:

     Cosimulation(simcmd, **portmap)

Ahhh, much better :)

The /toV*/ functions already return a list generators in
the module.  The /portmap/ can't be returned from the
/toV*/ functions without breaking backwards compatibility.

The current proposal is to attach a function attribute to the
/toV*/ functions, e.g:

     toVerilog.portmap

The /toV*.portmap/ would be the dictionary of the converted
portmap (interface expanded names).

I would like to propose and discuss attaching the /portmap/
attribute to the function being converted and not the
conversion functions.  To me this is a more natural (I don't
know if this is generally pythonic (accepted) to have other
functions modify and/or add attributes to other functions).

In addition, I would propose that generated portmap saved
in the /vportmap/ attribute and the /portmap/ attribute
to be used as a user defined default port definition.

Keerthan has done an amazing job implementing MEP-107, many
thanks!  He has also created a pull-request for the
/toVerilog.portmap/, I wanted to have a short discussion
and make sure this is the most flexible path moving forward.
Once we finalize the portmap I can update the MEP.

Regards,
Chris

[1] http://thread.gmane.org/gmane.comp.python.myhdl/3223/focus=3318

Re: [myhdl-list] myhdl.org website migration

[Christopher F. <chr...@gm...>]

<snip>
>
> http://new.myhdl.org/
>
> Site development and deployment happens in a
> natural way from mercurial repositories on bitbucket.
>
> Of course, I don't want to force noone to move to
> the new system. However, all those that have
> made significant contributions in the past may
> email me privately if they would like to become
> a contributor to the new websites.

Couple (minor) comments on the new site.

Is there a way to easily link back to the site from
the manual?  I found it a little frustrating jumping
to the manual and back to the site.

I realize the menu system has the links to get started,
etc.  But I think having some more content on the landing
page would be beneficial for new visitors, etc.  I can
create a pull-request with some ideas.

Also, my contribution plan to the new site is adding
examples.  In the past I experimented with adding the
examples to the manual and using doctest to verify the
examples when a new version of the manual was created.
I think this would be good as release tests (that is
verifying the examples on the site still work).  Now,
that the new website is in a repository, I propose we
add a little (as little as possible) formality to the
examples so we can leverage this code collection for
release testing, e.g. all examples should have:

     1. description write up
     2. .py file with working example
     3. test for the example

In addition, there are ways to embedded the code from
bitbucket in the example write-up, the write-up can
always have the latest code (easy to maintain the examples),
thoughts?

Regard,
Chris

Re: [myhdl-list] myhdl.org website migration

[Tom D. <TD...@Di...>]

Jan,

That looks great. Good to get some tips to try and keep up with the kids.

Tom




On Wed, Feb 12, 2014 at 11:16 AM, Jan Decaluwe <ja...@ja...> wrote:

> On 02/12/2014 12:36 AM, Tom Dillon wrote:
> > Jan,
> >
> > Thanks for sharing Urubu. Have you started a discussion list for it?
>
> Not yet.
>
> I want to keep this as light-weight and "modern" as possible,
> so I checked what the GitHub kids are doing.
>
> Related market-leader projects such as bootstrap and jekyll
> apparently don't even have separate discussion lists.
> Everything is being done with GitHub Issues. You can
> define labels such as Discussion, Question and Suggestion
> for generic, open-ended Issues.
>
> I think I like this, because it keeps everything in one
> place and close to the reality of the code. I looked up
> the most common labels in Jekyll, and came up with
> this initial setup for Urubu:
>
> https://github.com/jandecaluwe/urubu/issues?labels=duplicate&state=open
>
> What do people think?
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
>
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] myhdl.org website migration

[Jan D. <ja...@ja...>]

On 02/12/2014 12:36 AM, Tom Dillon wrote:
> Jan,
>
> Thanks for sharing Urubu. Have you started a discussion list for it?

Not yet.

I want to keep this as light-weight and "modern" as possible,
so I checked what the GitHub kids are doing.

Related market-leader projects such as bootstrap and jekyll
apparently don't even have separate discussion lists.
Everything is being done with GitHub Issues. You can
define labels such as Discussion, Question and Suggestion
for generic, open-ended Issues.

I think I like this, because it keeps everything in one
place and close to the reality of the code. I looked up
the most common labels in Jekyll, and came up with
this initial setup for Urubu:

https://github.com/jandecaluwe/urubu/issues?labels=duplicate&state=open

What do people think?

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] myhdl.org website migration

[Tom D. <TD...@Di...>]

Jan,

Thanks for sharing Urubu. Have you started a discussion list for it?

Tom



On Mon, Feb 10, 2014 at 2:12 PM, Jan Decaluwe <ja...@ja...> wrote:

> For a long time and for various reasons, I was no longer
> happy with myhdl.org. I have blogged about some of
> the issues here:
>
> http://www.jandecaluwe.com/blog/wikis-dont-work.html
>
> Eventually, I have decided to move to a static approach.
> There are many systems, but noone that suited my needs.
> I have blogged about this there:
>
> http://www.jandecaluwe.com/blog/i-dont-like-blogs.html
>
> Therefore, I decided to write my own tool:
>
> http://urubu.jandecaluwe.com/
>
> I have migrated my own websites, and the migration
> of myhdl.org is underway. I have decided to split
> in into a "development" site and a "main" site.
>
> Migration of the development site is well underway:
>
> http://dev.myhdl.org/
>
> For the new myhdl.org, I have a skeleton proposal
> here:
>
> http://new.myhdl.org/
>
> Site development and deployment happens in a
> natural way from mercurial repositories on bitbucket.
>
> Of course, I don't want to force noone to move to
> the new system. However, all those that have
> made significant contributions in the past may
> email me privately if they would like to become
> a contributor to the new websites.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Androi apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
>
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] myhdl.org website migration

[Keerthan jai.c <jck...@gm...>]

I love the new design, it's beautiful!
I also would like to contribute to the new site.


On Tue, Feb 11, 2014 at 11:26 AM, Jan Decaluwe <ja...@ja...> wrote:

> On 02/11/2014 12:37 PM, Jan Coombs wrote:
> > On 10/02/14 20:12, Jan Decaluwe wrote:
> >> For a long time and for various reasons, ...
> > All excellent changes, thanks.   I'd not heard of 'markdown',
>
> Really ?? It's used everywhere :-)
>
> > this appeals to me as ideal, and would be my tool of preference for
> > writing manuals.
>
> For truee manuals, asciidoc or restructuredText is probably
> better. I will keep the MyHDL manual in rst format. But for
> websites, things have to be straightforward
> and easy and I believe markdown is optimal.
>
> > I would like to move about half of my tiny contribution into the
> > new framework, and hope to have much more to post later this year.
>
> Please send me a peronsal email with your bitbucket account.
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
>
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck