myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Simplifying Interfaces

[Wesley N. <we...@sk...>]

Did anyone ever come up with a good example of this?

Wesley New
South African SKA Project
+2721 506 7365
www.ska.ac.za



On Fri, Jul 6, 2012 at 4:56 AM, Christopher Felton <chr...@gm...>
wrote:

> On 7/5/12 11:29 AM, Tom Dillon wrote:
> >
> > On 07/04/2012 02:22 PM, Christopher Felton wrote:
> >> <snip>
> >>>> Anyone else have an idea for an example?  I think for the example to
> be
> >>>> useful, you would want a design that you would use multiple modules
> and
> >>>> have some interface between.  But the interface would be small
> (limited
> >>>> number of signals in the class) so the the example would be
> digestible.
> >>> Maybe something based on complex numbers, as Tom D has
> >>> hinted. One could represent them as a class instance,
> >>> or even as a tuple.
> >>>
> >>>
> >> I was worried if the complex number example was used some
> >> might expect operator overload.  I have been waffling if
> >> this would be a good example.
> >
> > I think the example would have to show why we would not try to overload
> > operators.
> >
>
> I agree, which, IMO, requires a little bit of *ART*.
> There are many concepts that need to pulled together and
> succinctly explained.  I do not want set incorrect
> expectations.
>
> I don't know if I see a good way to explain that operator
> overloading is appropriate for a sequence of instructions
> but not for a hardware description (concurrent processes).
> Or if it is absent if it will raise questions.
>
> I don't if a plain "signal container" example would be a
> better fit.
>
> Regards,
> Chris
>
>
>
>
>
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Re: [myhdl-list] Using existing HDL modules - part 2

[Mike G. <mj...@gi...>]

Chris,

Re earlier comments, this might be useful:

There is a complete verilog parser (verilogParse.py) in the examples from
the pyparsing distribution (not in the binaries)

http://sourceforge.net/project/showfiles.php?group_id=97203

Regards,

Mike

Re: [myhdl-list] Using existing HDL modules - part 2

[Christopher F. <chr...@gm...>]

On 11/5/2014 12:09 PM, Mike Gill wrote:
> Chris,
>
> Many thanks for response.
>
> I'm getting out of my depth, and as I've found out enough to use MyHDL for
> what I need, I'll back off any further commenting.
>

It is always good to hear where folks have issues
or what might make their lives easier.  But the
reality is sometimes it is a great idea, sometimes
not, sometimes it is a resource issues, etc.

Always feel free to comment but also be prepared
for direct responses and also a lack of interest
because it might be out of scope or not enough
cycles to implement / investigate.

If you feel like some light reading, here is a thread
on the same subject from a couple years ago:
http://thread.gmane.org/gmane.comp.python.myhdl/2850/focus=2878

And this thread also touches on some of the same
items:
http://www.alteraforum.com/forum/showthread.php?t=43867

Regards,
Chris

Re: [myhdl-list] Using existing HDL modules - part 2

[Mike G. <mj...@gi...>]

Chris,

Many thanks for response.

I'm getting out of my depth, and as I've found out enough to use MyHDL for
what I need, I'll back off any further commenting.

Regards

Mike

Re: [myhdl-list] Using existing HDL modules - part 2

[Christopher F. <chr...@gm...>]

On 11/5/2014 5:57 AM, Mike Gill wrote:
> Thanks to all for the responses to my post of 3rd Nov. I feel a fraud
> because shortly after posting I was able to instantiate an external
> primitive with user defined code by actually reading the manual.
>
> Thanks to Guy for the presentation. I replicated the example in slide 43.
>
> It looks like this example is intended to be simulated but I don't think the
> defined logic function is recognized in MyHDL. The same VHDL file and the
> same "ToVHDLWarning: Port is not used: O" is generated if the logic function
> is replaced with "pass". In
> http://docs.myhdl.org/en/latest/manual/conversion_examples.html#user-defined-code
> it says "...conversion of the ..... function is bypassed..."

Correct, the user-defined code will not be
interpreted, analyzed, etc. by MyHDL.  If you
want to simulate, in MyHDL, you need to define
logic that represents the behavior (no small task
for large IP) or do co-simulation.

>
> I think this topic is important. MyHDL is attractive for algorithm
> development (my personal interest) but I don't see how it could possibly be
> considered for development of a whole fpga project where it controls the top
> level module. It is vital to be able to readily use not only chip primitives
> but also soft IP cores generated by the chip vendor's tool suite, and it
> can't be relied on that everyone involved will know Python.
>

As mentioned the difficulty will be simulation, it
would be a large task (project) to build a fully
compliant Verilog or VHDL simulator in Python that
could read, parse, compile, and simulate the IP.

> Is it possible to have a wrapper function for the user-defined code feature
> along the lines of:
>
> module_inst = include('module_file.v/.vhd', signal_list,  property_list=None)

There is a beta feature where you define the module
to be a Verilog of VHDL instance:

     def VHDL_ENTITY(clock, reset, x, y, z):
         z.driven = True
         @always(clock, reset, x, y)
         def logic():
             pass
         return logic
     VHDL_ENTITY.vhdl_instance = "VHDL_INSTANCE_NAME"

     def m_top(clock, reset, x, y, z):
         g = VHDL_ENTITY(clock, reset, x, y, z)
         return g

     clock = Signal(bool(0))
     reset = ResetSignal(0, 0, True)
     x,y,z = [Signal(intbv(0)[8:]) for _ in range(3)]
     toVHDL(m_top, clock, reset, x, y, z)


https://gist.github.com/cfelton/0792c5823d418afee604

Verilog is the same.  Your MyHDL module will need to have
the same port list but it simplifies, some.  It would
be an unreasonable task to parse the VHDL or Verilog and
determine the ports automatically.

Note, I agree tools to help realize the current state of FPGA
development aren't bad but I don't know if this falls under
the current MyHDL goals (might be an external tool) or if there
are enough developers to generate such tools.

In summary, I don't believe there are any show stoppers but
integration with FPGA IP and 3rd party IP is interesting
when it comes to simulation / verification.


Regards,
Chris

Re: [myhdl-list] VHDL Records

[Christopher F. <chr...@gm...>]

On 11/5/2014 5:27 AM, Wesley New wrote:
> Hi All,
>
> We are sitting with a problem where we wish to use existing VHDL code that
> uses records and wish to pull it into our MyHDL designs with using user
> defined code. Unfortunately it would seem that MyHDL does not support this.
> Is this correct or is there some way to create records out of signals?
>
> Thanks
>

In the user-defined code, any valid HDL can exist.
But the MyHDL converter will not convert anything
to VHDL records.  The converter, for the most part,
attempts to use basic common constructs between Verilog
and VHDL.

The best option is to write a wrapper in  VHDL that
breaks out the signals.


Regards,
Chris

[myhdl-list] Using existing HDL modules - part 2

[Mike G. <mj...@gi...>]

Thanks to all for the responses to my post of 3rd Nov. I feel a fraud
because shortly after posting I was able to instantiate an external
primitive with user defined code by actually reading the manual.

Thanks to Guy for the presentation. I replicated the example in slide 43.

It looks like this example is intended to be simulated but I don't think the
defined logic function is recognized in MyHDL. The same VHDL file and the
same "ToVHDLWarning: Port is not used: O" is generated if the logic function
is replaced with "pass". In
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#user-defined-code
it says "...conversion of the ..... function is bypassed..."

I think this topic is important. MyHDL is attractive for algorithm
development (my personal interest) but I don't see how it could possibly be
considered for development of a whole fpga project where it controls the top
level module. It is vital to be able to readily use not only chip primitives
but also soft IP cores generated by the chip vendor's tool suite, and it
can't be relied on that everyone involved will know Python.

Is it possible to have a wrapper function for the user-defined code feature
along the lines of:

module_inst = include('module_file.v/.vhd', signal_list,  property_list=None)

If a module is given it can be parsed for signal types and have the signal
names (given as a strings maybe in a list) assigned to these in sequence.
Properties would be needed if an instantiation template has to be given
where a module is not available. module_inst is a dummy generator function
containing a set of signal.read/driven assignments and the user code
assignment (which, vitally, appears to work inside the function but I don't
understand why)

It does not look too ambitious to parse a module for the external signals,
but I don't know enough about the syntax. I was going to attempt something
very basic from looking at sample files.

Comments welcome. What are other's assessments of MyHDL?

Regards

Mike

[myhdl-list] VHDL Records

[Wesley N. <we...@sk...>]

Hi All,

We are sitting with a problem where we wish to use existing VHDL code that
uses records and wish to pull it into our MyHDL designs with using user
defined code. Unfortunately it would seem that MyHDL does not support this.
Is this correct or is there some way to create records out of signals?

Thanks

Wesley New
South African SKA Project
+2721 506 7365
www.ska.ac.za

Re: [myhdl-list] Using existing HDL modules

[Jan C. <jen...@mu...>]

On 03/11/14 14:59, Mike Gill wrote:
> Hi
>
> How do you access chip primitives and hard IP blocks in MyHDL? The chip
> vendor supplies modules and instantiation templates in Verilog or VHDL. Is
> there any way of including or importing these without having to edit the
> Verilog or VHDL file generated by MyHDL? I can't work out whether the
> user-defined code facility can do this.
I have a MyHDL RAM (model?) with content initialisation code which 
simulates in MyHDL and is accepted by the Lattice (Ex Silicon Blue) 
toolchain.

This puts the RAM image into Verilog defparam statements in MyHDL 
user-defined code for the synth tools, and initialises the MyHDL 
RAM model for simulation.

AFAICT the same technique will allow direct access to the all of 
chip primitives.   Haven't looked at IP blocks.

Let me know if you'd like me to send or post code.

Jan Combs.

Re: [myhdl-list] Using existing HDL modules

[Henry G. <he...@ca...>]

On 04/11/14 07:42, Guy Eschemann wrote:
> what this means is that you cannot generate VHDL code that is
> parameterizable using VHDL generics (think of a FIFO that has a "depth"
> generic for example). The parametrization has to be done in MyHDL before
> the actual VHDL code is generated.
Oh, I understand - so you mean you can't pass around a parameterizable 
v* block for others to use. Not as problematic as I interpreted your 
point as being. :)

Cheers,

Henry

Re: [myhdl-list] Using existing HDL modules

[Guy E. <gu...@no...>]

Hello Henry,

what this means is that you cannot generate VHDL code that is 
parameterizable using VHDL generics (think of a FIFO that has a "depth" 
generic for example). The parametrization has to be done in MyHDL before 
the actual VHDL code is generated.

As far as I know, this limitation applies to all all high-level design 
solutions (C-based HLS, Bluespec SV, etc.). It may or may not be an 
issue for you.

Regards,
Guy.

Am 03.11.2014 19:04, schrieb Henry Gomersall:
> On 03/11/14 17:52, Guy Eschemann wrote:
>> I have an example showing how to instantiate an IBUFDS component from
>> the Xilinx Unisim library with user-defined code. You'll find it on
>> the slide number 43 of my presentation on "FPGA Design with Python and
>> MyHDL"
>> (http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python).
> Hi Guy, that's a great presentation.
>
> One question though: you say on page 45 that MyHDL cannot generate
> parameterizable HDL. What do you mean by this?
>
> My understanding is that with the flexibility of python, parameterizable
> HDL (or indeed almost any kind of metaprogramming niceness) is a
> wonderful thing to be doing with MyHDL. Have I missed something?
>
> Cheers,
>
> Henry
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

-- 
Guy Eschemann
FPGA Consultant, CEO
noasic GmbH
Auenheimer Str. 26a
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
Mobile: +49 (0) 173 72 51 886
gu...@no...
Follow me on Twitter: @geschema
http://noasic.com
http://fpga-news.de
USt-IdNr.: DE296246015
HRB 711881, Amtsgericht Freiburg i. Br.

Re: [myhdl-list] Using existing HDL modules

[Christopher F. <chr...@gm...>]

On 11/3/2014 12:04 PM, Henry Gomersall wrote:
> On 03/11/14 17:52, Guy Eschemann wrote:
>> I have an example showing how to instantiate an IBUFDS component from
>> the Xilinx Unisim library with user-defined code. You'll find it on
>> the slide number 43 of my presentation on "FPGA Design with Python and
>> MyHDL"
>> (http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python).
>
> Hi Guy, that's a great presentation.
>
> One question though: you say on page 45 that MyHDL cannot generate
> parameterizable HDL. What do you mean by this?
>
> My understanding is that with the flexibility of python, parameterizable
> HDL (or indeed almost any kind of metaprogramming niceness) is a
> wonderful thing to be doing with MyHDL. Have I missed something?
>
> Cheers,
>
> Henry
>

The HDL in Python (the MyHDL) is very parameterizable,
modular, scalable, etc.  But the generated Verilog/VHDL
is not.  The generated Verilog/VHDL is an convenient
intermediate format.

Hope that helps,
Chris

Re: [myhdl-list] Using existing HDL modules

[Henry G. <he...@ca...>]

On 03/11/14 17:52, Guy Eschemann wrote:
> I have an example showing how to instantiate an IBUFDS component from 
> the Xilinx Unisim library with user-defined code. You'll find it on 
> the slide number 43 of my presentation on "FPGA Design with Python and 
> MyHDL" 
> (http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python).

Hi Guy, that's a great presentation.

One question though: you say on page 45 that MyHDL cannot generate 
parameterizable HDL. What do you mean by this?

My understanding is that with the flexibility of python, parameterizable 
HDL (or indeed almost any kind of metaprogramming niceness) is a 
wonderful thing to be doing with MyHDL. Have I missed something?

Cheers,

Henry

Re: [myhdl-list] Using existing HDL modules

[Guy E. <guy...@gm...>]

Hello Mike,

I have an example showing how to instantiate an IBUFDS component from the
Xilinx Unisim library with user-defined code. You'll find it on the slide
number 43 of my presentation on "FPGA Design with Python and MyHDL" (
http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python
).

Hope this helps,
Guy.


Guy Eschemann
FPGA Consultant, CEO
noasic GmbH
Sundheimer Feld 6
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
Mobile: +49 (0) 173 72 51 886
gu...@no... <Guy...@gm...>
Follow me on Twitter: @geschema <http://twitter.com/geschema>
Skype: guy.eschemann
http://noasic.com
http://fpga-news.de
USt-IdNr.: DE296246015
HRB 711881, Amtsgericht Freiburg i. Br.

On Mon, Nov 3, 2014 at 3:59 PM, Mike Gill <mj...@gi...> wrote:

> Hi
>
> How do you access chip primitives and hard IP blocks in MyHDL? The chip
> vendor supplies modules and instantiation templates in Verilog or VHDL. Is
> there any way of including or importing these without having to edit the
> Verilog or VHDL file generated by MyHDL? I can't work out whether the
> user-defined code facility can do this.
>
> My knowledge of Verilog and VHDL is very limited.
>
> Many thanks
>
> Mike
>
>
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Using existing HDL modules

[Henry G. <he...@ca...>]

On 03/11/14 17:11, Christopher Felton wrote:
> co-simulate with existing V*
> models.

The potential problem with this being the paranoid encryption that seems 
to be de rigueur among IP authors. This is an issue if you want to use 
Icarus verilog, but Aldec and Modelsim should be ok.

Cheers,

Henry

Re: [myhdl-list] Using existing HDL modules

[Christopher F. <chr...@gm...>]

On 11/3/2014 8:59 AM, Mike Gill wrote:
> Hi
>
> How do you access chip primitives and hard IP blocks in MyHDL? The chip
> vendor supplies modules and instantiation templates in Verilog or VHDL. Is
> there any way of including or importing these without having to edit the
> Verilog or VHDL file generated by MyHDL? I can't work out whether the
> user-defined code facility can do this.
>
> My knowledge of Verilog and VHDL is very limited.
>
> Many thanks
>
> Mike
>

In short, user-defined code is used to instantiate
third party IP provided in Verilog of VHDL (including
hard IP).  For simulation you will need to created
a functional model or co-simulate with existing V*
models.

http://docs.myhdl.org/en/latest/manual/conversion.html#user-defined-code

Regards,
Chris

[myhdl-list] Using existing HDL modules

[Mike G. <mj...@gi...>]

Hi

How do you access chip primitives and hard IP blocks in MyHDL? The chip
vendor supplies modules and instantiation templates in Verilog or VHDL. Is
there any way of including or importing these without having to edit the
Verilog or VHDL file generated by MyHDL? I can't work out whether the
user-defined code facility can do this.

My knowledge of Verilog and VHDL is very limited.

Many thanks

Mike

Re: [myhdl-list] Keeping hierarchy for conversion

[Christopher L. <loz...@fr...>]

I quite agree with you that the way to learn this stuff is from the ground up. 

Start with circuit layouts and a simulator, move on to verily or vhdl. 

Maybe I do not even need python.  LOL. 

I have been hard at work on zopache.  It is a Through the web development environment on top of Grok/zope

Okay.  So I get the Object oriented concepts wrong.  You are the person who knows how to do them correctly. 

All I can hope to do is to help you verbalize what the critical concepts are.  Why did you not use Native MyHDL. 

What is the key concept behind your approach.   What are the abstractions that you are using. What are the benefits of those abstractions.  What would it take to release a library that supports that approach in a more general fashion?

I hope that helps. 

Chris

Re: [myhdl-list] time unit in cosimulation

[Christopher F. <chr...@gm...>]

On 10/9/14, 2:56 PM, Shen Chen wrote:
<snip>
> In the co-simulation phase, we realized that the time in myHDL is 1000x
> that in verilog.
>
> It may be fine if verilog uses `timescale 1ns/1ps, and myHDL uses 1ns
> time step.
>
> However, some of the fault modes in SRAM requires higher timing
> precision, so we went for 1ps time step in myHDL.
>
> It took us quite some time to figure out that, in this case, we need to
> tell the verilog simulator to use 1 fs time step.
>
> Only after finding this out by trial and error, did I realize that the
> manual mentioned this 1000x factor for delta cycle implementation.

For others reading this, this is the section in the manual
that explains the 1000x:
http://docs.myhdl.org/en/latest/manual/cosimulation.html#delta-cycle-implementation

Maybe a cosimulation example could be added to the examples
that demonstrates the 1000x difference, to help communicate
this in the future?


Regards,
Chris

[myhdl-list] time unit in cosimulation

[Shen C. <she...@co...>]

 

Hi All, 

In our experiment of using MyHDL in an SRAM BIST design,
we used the following flow: 

myHDL RTL and testbench -> convert to
verilog rtl -> Synthesis/Place&Route -> co-simulation of myHDL testbench
with the sdf back-annotated verilog. 

Only the design (BIST module) is
converted to verilog, the SRAM is considered as a part of the testbench,
and is modeled behaviorally. 

This allows us to model some complex
fault modes in the SRAM. 

In the co-simulation phase, we realized that
the time in myHDL is 1000x that in verilog. 

It may be fine if verilog
uses `timescale 1ns/1ps, and myHDL uses 1ns time step. 

However, some
of the fault modes in SRAM requires higher timing precision, so we went
for 1ps time step in myHDL. 

It took us quite some time to figure out
that, in this case, we need to tell the verilog simulator to use 1 fs
time step. 

Only after finding this out by trial and error, did I
realize that the manual mentioned this 1000x factor for delta cycle
implementation. 

A coarse reading of the vpi source code confirmed
this. 

I hope the manual can explain the implication of the 1000x
factor from the users' perspective, hopefully saving users some time.


regards,
shenchen 

-- 

SHEN Chen General
Manager
---------------------------------
Cogenda Co Ltd
SISPARK II Room
C102-1, 1355 Jinjihu Avenue, Suzhou, Jiangsu, China
Phone(Fax): +86 512
67900636
Homepage: http://www.cogenda.com
 

Re: [myhdl-list] subtype RamWord_t

[Christopher F. <chr...@gm...>]

There is no method to define a type for the generated
VHDL.  The generator will not create types in VHDL,
if you are integrating existing VHDL components with
MyHDL generated VHDL components you will need to use
conversion functions in the VHDL.

If you are having issues on the VHDL side, you can
post the VHDL code and someone might be able to help
or try one of the VHDL specific groups.

Regards,
Chris

On 10/2/2014 2:38 PM, Edward Vidal wrote:
> Hello all,
> In the process of learning myhdl and trying to convert a vdh code snippet to myhdl.
> RAM_WIDTH_C = 16 is defined as constant
>
> subtype RamWord_t is unsigned(RAM_WIDTH_C-1 downto 0);  -- RAM word type.
>
>
> RAM_SIZE_C = 16384
> For addr I used
>
> addr_r = addr_r = Signal(intbv(0, min = 0, max = RAM_SIZE_C))
>
> which converted  addr_r: out unsigned(13 downto 0); which
> I am trying dataToRam_r = Signal(intbv(0, min = 0, max = 2**RAM_WIDTH_C - 1))
> which is correct I think but not of subtype RamWord_t
> dataToRam_r: out unsigned(15 downto 0);
>
> What is the process to make it of type RamWord_t
> Any and all help is appreciated.
>
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
>
>
>
> ------------------------------------------------------------------------------
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>
>
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>

Re: [myhdl-list] subtype RamWord_t

[Christopher F. <chr...@gm...>]

That is correct, the first creates 14bits and the second
16bits as you specified.

     In [4] : RAM_WIDTH_C = 16
              RAM_SIZE_C = 16384
              t1 = intbv(0, min=0, max=RAM_SIZE_C)
              t2 = intbv(0, min=0, max=2**RAM_WIDTH_C)
              print(len(t1), len(t2))
     (14, 16)

     Int[5]: 2**14
     Out[5]: 16384

Regards,
Chris


On 10/2/2014 2:38 PM, Edward Vidal wrote:
> Hello all,
> In the process of learning myhdl and trying to convert a vdh code snippet to myhdl.
> RAM_WIDTH_C = 16 is defined as constant
>
> subtype RamWord_t is unsigned(RAM_WIDTH_C-1 downto 0);  -- RAM word type.
>
>
> RAM_SIZE_C = 16384
> For addr I used
>
> addr_r = addr_r = Signal(intbv(0, min = 0, max = RAM_SIZE_C))
>
> which converted  addr_r: out unsigned(13 downto 0); which
> I am trying dataToRam_r = Signal(intbv(0, min = 0, max = 2**RAM_WIDTH_C - 1))
> which is correct I think but not of subtype RamWord_t
> dataToRam_r: out unsigned(15 downto 0);
>
> What is the process to make it of type RamWord_t
> Any and all help is appreciated.
>
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
>
>
>
> ------------------------------------------------------------------------------
> Meet PCI DSS 3.0 Compliance Requirements with EventLog Analyzer
> Achieve PCI DSS 3.0 Compliant Status with Out-of-the-box PCI DSS Reports
> Are you Audit-Ready for PCI DSS 3.0 Compliance? Download White paper
> Comply to PCI DSS 3.0 Requirement 10 and 11.5 with EventLog Analyzer
> http://pubads.g.doubleclick.net/gampad/clk?id=154622311&iu=/4140/ostg.clktrk
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] subtype RamWord_t

[Edward V. <dev...@sb...>]

Hello all,
In the process of learning myhdl and trying to convert a vdh code snippet to myhdl.
RAM_WIDTH_C = 16 is defined as constant 

subtype RamWord_t is unsigned(RAM_WIDTH_C-1 downto 0);  -- RAM word type.


RAM_SIZE_C = 16384
For addr I used 

addr_r = addr_r = Signal(intbv(0, min = 0, max = RAM_SIZE_C))

which converted  addr_r: out unsigned(13 downto 0); which
I am trying dataToRam_r = Signal(intbv(0, min = 0, max = 2**RAM_WIDTH_C - 1))
which is correct I think but not of subtype RamWord_t
dataToRam_r: out unsigned(15 downto 0);

What is the process to make it of type RamWord_t
Any and all help is appreciated.

Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

[myhdl-list] Result of 17-bit expression is truncated to fit in 16-bit target.

[Edward V. <dev...@sb...>]

Hello all,
I generated a Verilog file with myhdl (see below).  The jpeg.v, top_level_mod.vhd, and VHDL_LIB
generates a bit file with ISE 14.7.
I am running on XulA2-LX9 from XESS sending the flags even_odd_s & fwd_inv_s to the FPGA.
I am sending back from the FPGA res_s  left_s sam_s  right_s, which are being read from SDram
even_odd_s fwd_inv_s res_s  left_s sam_s  right_s 
1                   1        2  0x0002 0x00a3 0x00a0 0x009b
1                   0    318  0x013e 0x00a3 0x00a0 0x009b
0                   0      80  0x0050 0x00a3 0x00a0 0x009b
0                   1    240  0x00f0 0x00a3 0x00a0 0x009b
The res_s is computed on PC with Python and compares with the returned res_s values.
I am currently having problems saving res_s to SDram.  I am getting the following warnings. 

WARNING:HDLCompiler:413 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\fast_clk_jpeg\jpeg.v"
Line 50: Result of 17-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\fast_clk_jpeg\jpeg.v"
Line 53: Result of 17-bit expression is truncated to fit in 16-bit target.
output signed [15:0] res_s;
reg signed [15:0] res_s;

The lines producing the warnings are the following.
res_s <= (sam_s + $signed(((left_s + right_s) + 2) >>> 2));  line 50
res_s <= (sam_s - $signed(((left_s + right_s) + 2) >>> 2));  line 53

When I try to make the res_s 17 bit my code will not Synthesize.
The code worked with the jpeg.vhd but works better with jpeg.v.
I appreciate any and all help.
Thanks
Edward Vidal Jr.
// File: jpeg.v
// Generated by MyHDL 0.9dev
// Date: Sat Sep 20 01:39:13 2014


`timescale 1ns/10ps

module jpeg (
    clk_fast,
    left_s,
    right_s,
    sam_s,
    res_s,
    even_odd_s,
    fwd_inv_s,
    updated_s,
    noupdate_s
);


input clk_fast;
input signed [15:0] left_s;
input signed [15:0] right_s;
input signed [15:0] sam_s;
output signed [15:0] res_s;
reg signed [15:0] res_s;
input even_odd_s;
input fwd_inv_s;
input updated_s;
output noupdate_s;
reg noupdate_s;






always @(posedge clk_fast) begin: JPEG_HDL
    if (updated_s) begin
        if (even_odd_s) begin
            if (fwd_inv_s) begin
                res_s <= (sam_s - ($signed(left_s >>> 1) + $signed(right_s >>> 1)));
            end
            else begin
                res_s <= (sam_s + ($signed(left_s >>> 1) + $signed(right_s >>> 1)));
            end
        end
        else begin
            if (fwd_inv_s) begin
                res_s <= (sam_s + $signed(((left_s + right_s) + 2) >>> 2));
            end
            else begin
                res_s <= (sam_s - $signed(((left_s + right_s) + 2) >>> 2));
            end
        end
    end
    else begin
        noupdate_s <= 1;
    end
end

endmodule


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

[myhdl-list] fsm.v and fsm.vhd

[Edward V. <dev...@sb...>]

Hello all,
I am new to HDL and myhdl.  I am using Xilinx ISE 14.7.  I created a simple FSM with myhdl.  When I add the "RamCtrl.v" file.   I can create a "TB.vhd"   file and run a simulation with no problems.  


When I try with  "RamCtrl.vhd",  I also add "pck_myhd_09.vhd".  I can Synthesize, Implement Design, and  Generate Programming File no problems.   When I create a "TB.vhd" and try run the simulation I get the following errors.
  ERROR:HDLCompiler:377 - "C:/Xilinx/14.7/ISE_DS/fsm_test1/TB.vhd" Line 45: Entity port state does not match with type std_logic of component port
ERROR:HDLCompiler:377 - "C:/Xilinx/14.7/ISE_DS/fsm_test1/TB.vhd" Line 49: Entity port addrsam_r does not match with type std_logic_vector of component port
ERROR:HDLCompiler:377 - "C:/Xilinx/14.7/ISE_DS/fsm_test1/TB.vhd" Line 50: Entity port addrjpeg_r does not match with type std_logic_vector of component port
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit tb in library work failed

I believe the problem is related to the "RamCtrl.vhd" has the following.
 attribute enum_encoding: string;

    type t_enum_t_State_1 is (
    INIT,
    RD_AND_JPEG_DATA,
    WR_DATA,
    INTERLACE,
    DONE
);
attribute enum_encoding of t_enum_t_State_1: type is "00001 00010 00100 01000 10000";

 How do you fix the problem in the "TB.vhd" file this missing causes errors in other signals.
I appreciate all the help.
Thanks 


Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613