myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] OSS CVC vpi module

[Paul.Y.Zhang <yzh...@gm...>]

Yes, I wrote a different vpi mdule, wait to work around the issue. But, 
failed.

- Paul

在 2014/12/17 20:52, Christopher Felton 写道:
> On 12/17/2014 6:00 AM, Paul.Y.Zhang wrote:
>> There are two cases causing memory leak:
>>
>>     1. vpi_put_value with delay, such as:
>>
>>      vpi_put_value(handle, value_p, time_p, vpiInerialDelay);
>>      vpi_put_value(handle, value_p, time_p, vpiTransportDelay);
>> vpi_put_value(handle, value_p, time_p, vpiPureTransportDelay);
>>
>> But seems vpiNoDelay does NOT cause memory leak.
>>
>>     2. callback with reason cbAfterDelay
>>
>> These two cases will cause memory leak.
>
> Thanks for the investigation Paul!
>
> Did you use some custom code for the test?  I only see
> vpi_put_value called in one spot with vpiNoDelay:
> https://bitbucket.org/jandecaluwe/myhdl/src/tip/cosimulation/cver/myhdl_vpi.c?at=default#cl-406
>
> I believe one of the issues with VPI and different simulators
> is that it is not always defined who is supposed to release
> memory allocated (simulator or the VPI module).  Possibly in
> the delay callback something additional needs to be released
> (pure speculation at this point)?
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
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-- 
Paul

Re: [myhdl-list] OSS CVC vpi module

[Henry G. <he...@ca...>]

On 17/12/14 11:53, Paul.Y.Zhang wrote:
> What's the meaning "run the whole lot under valgrind"?
Valgrind is a hugely useful tool for (among other things) tracking down 
memory leaks. Basically it monkey patches the code to replace the 
standard allocator and checks when stuff is not freed. I've used it 
somewhat for finding leaks in my own code.

It's less easy under Python because python causes Valgrind to throw up 
no end of errors due to its memory pooling and whatnot, but it's not 
insurmountable:
http://stackoverflow.com/questions/20112989/how-to-use-valgrind-with-python

(I've done a bit of valgrind under python with reasonable success).

Cheers,

Henry

Re: [myhdl-list] OSS CVC vpi module

[Christopher F. <chr...@gm...>]

On 12/17/2014 6:00 AM, Paul.Y.Zhang wrote:
> There are two cases causing memory leak:
>
>    1. vpi_put_value with delay, such as:
>
>     vpi_put_value(handle, value_p, time_p, vpiInerialDelay);
>     vpi_put_value(handle, value_p, time_p, vpiTransportDelay);
> vpi_put_value(handle, value_p, time_p, vpiPureTransportDelay);
>
> But seems vpiNoDelay does NOT cause memory leak.
>
>    2. callback with reason cbAfterDelay
>
> These two cases will cause memory leak.


Thanks for the investigation Paul!

Did you use some custom code for the test?  I only see
vpi_put_value called in one spot with vpiNoDelay:
https://bitbucket.org/jandecaluwe/myhdl/src/tip/cosimulation/cver/myhdl_vpi.c?at=default#cl-406

I believe one of the issues with VPI and different simulators
is that it is not always defined who is supposed to release
memory allocated (simulator or the VPI module).  Possibly in
the delay callback something additional needs to be released
(pure speculation at this point)?

Regards,
Chris

Re: [myhdl-list] OSS CVC vpi module

[Paul.Y.Zhang <yzh...@gm...>]

There are two cases causing memory leak:

  1. vpi_put_value with delay, such as:

   vpi_put_value(handle, value_p, time_p, vpiInerialDelay);
   vpi_put_value(handle, value_p, time_p, vpiTransportDelay);
vpi_put_value(handle, value_p, time_p, vpiPureTransportDelay);

But seems vpiNoDelay does NOT cause memory leak.

  2. callback with reason cbAfterDelay

These two cases will cause memory leak.

- Paul


在 2014/12/17 19:53, Paul.Y.Zhang 写道:
> What's the meaning "run the whole lot under valgrind"?
>
> - Paul
>
> 在 2014/12/17 17:42, Henry Gomersall 写道:
>> On 16/12/14 23:39, Paul.Y.Zhang wrote:
>>> After some test，I found the memory leak is caused by 
>>> "vpi_put_value()".
>> What happens if you run the whole lot under valgrind?
>>
>> It's nice it's open source, because now there's a chance to fix it!
>>
>> Henry
>>
>> ------------------------------------------------------------------------------ 
>>
>> Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server
>> from Actuate! Instantly Supercharge Your Business Reports and Dashboards
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>> more
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>>
>> _______________________________________________
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>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

-- 
Paul

Re: [myhdl-list] OSS CVC vpi module

[Paul.Y.Zhang <yzh...@gm...>]

What's the meaning "run the whole lot under valgrind"?

- Paul

在 2014/12/17 17:42, Henry Gomersall 写道:
> On 16/12/14 23:39, Paul.Y.Zhang wrote:
>> After some test，I found the memory leak is caused by "vpi_put_value()".
> What happens if you run the whole lot under valgrind?
>
> It's nice it's open source, because now there's a chance to fix it!
>
> Henry
>
> ------------------------------------------------------------------------------
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-- 
Paul

Re: [myhdl-list] OSS CVC vpi module

[Henry G. <he...@ca...>]

On 16/12/14 23:39, Paul.Y.Zhang wrote:
> After some test，I found the memory leak is caused by "vpi_put_value()".
What happens if you run the whole lot under valgrind?

It's nice it's open source, because now there's a chance to fix it!

Henry

Re: [myhdl-list] OSS CVC vpi module

[Paul.Y.Zhang <yzh...@gm...>]

After some test，I found the memory leak is caused by "vpi_put_value()".

- Paul

在 2014/12/17 0:13, Christopher Felton 写道:
> On 12/16/2014 9:46 AM, Paul.Y.Zhang wrote:
>> Hi, Chris,
>>
>> Excuse me, I am not very familar with the PLI/VPI technology. I do not
>> see any tf_ functions in "myhdl_vpi.c" codes. Waiting for your progress.
>>
>> - Paul
> I didn't look ... I wonder what Steve was referring to
> then?
>
> .chris
>
>> 在 2014/12/16 22:58, Christopher Felton 写道:
>>> On 12/13/2014 7:43 PM, Paul.Y.Zhang wrote:
>>>> neccHi,
>>>>
>>>> I post the cver vpi module (cosimulation/cver/myhdl_vpi.c) to Steve
>>>> Meyer (the author of OSS CVC?), to get help of the memory leak issue.
>>>> Got the below replay:
>>>>
>>>>        I assume calltf means the PLI uses the old tf_ interface.  You need to
>>>> translate (or find) a version of your myhdl PLI coded in vpi_.  tf_ is obsolete
>>>> old 1990s Verilog XL PLI that is deprecated (removed from) IEEE 1364 2005.
>>>> The reason tf_ is removed is that it just grew in Cadence XL so nobody could
>>>> duplicate behavior.
>>> According to the 1364-2005 LRM [1] which contains the
>>> PLI/VPI definition, indicates the tf_ functions are
>>> deprecated (section 24).
>>>
>>> Wow - I am a little slow to follow this thread, I didn't
>>> realize that the Tachyon re-opened/released their
>>> simulator, originally they open-sourced GPLCVER [2] and
>>> now they open-sourced CVC [3].  This is pretty amazing
>>> because CVC is fast and a great companion with MyHDL (IMO).
>>>
>>> I will try and experiment replacing the tf_ functions
>>> with the OSS CVC and see if the leak can be resolved.
>>>
>>> Regards,
>>> Chris
>>>
>>>
>>> [1] http://ieeexplore.ieee.org/servlet/opac?punumber=10779
>>>         (probably can alos be found by googling, note "Verilog"
>>>          has been merged with SV in the 1800 standard ...)
>>>
>>> [2] http://sourceforge.net/projects/gplcver/
>>>
>>> [3] http://www.tachyon-da.com/
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server
>>> from Actuate! Instantly Supercharge Your Business Reports and Dashboards
>>> with Interactivity, Sharing, Native Excel Exports, App Integration & more
>>> Get technology previously reserved for billion-dollar corporations, FREE
>>> http://pubads.g.doubleclick.net/gampad/clk?id=164703151&iu=/4140/ostg.clktrk
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
> ------------------------------------------------------------------------------
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list

-- 
Paul

Re: [myhdl-list] OSS CVC vpi module

[Christopher F. <chr...@gm...>]

On 12/16/2014 9:46 AM, Paul.Y.Zhang wrote:
> Hi, Chris,
>
> Excuse me, I am not very familar with the PLI/VPI technology. I do not
> see any tf_ functions in "myhdl_vpi.c" codes. Waiting for your progress.
>
> - Paul

I didn't look ... I wonder what Steve was referring to
then?

.chris

>
> 在 2014/12/16 22:58, Christopher Felton 写道:
>> On 12/13/2014 7:43 PM, Paul.Y.Zhang wrote:
>>> neccHi,
>>>
>>> I post the cver vpi module (cosimulation/cver/myhdl_vpi.c) to Steve
>>> Meyer (the author of OSS CVC?), to get help of the memory leak issue.
>>> Got the below replay:
>>>
>>>       I assume calltf means the PLI uses the old tf_ interface.  You need to
>>> translate (or find) a version of your myhdl PLI coded in vpi_.  tf_ is obsolete
>>> old 1990s Verilog XL PLI that is deprecated (removed from) IEEE 1364 2005.
>>> The reason tf_ is removed is that it just grew in Cadence XL so nobody could
>>> duplicate behavior.
>> According to the 1364-2005 LRM [1] which contains the
>> PLI/VPI definition, indicates the tf_ functions are
>> deprecated (section 24).
>>
>> Wow - I am a little slow to follow this thread, I didn't
>> realize that the Tachyon re-opened/released their
>> simulator, originally they open-sourced GPLCVER [2] and
>> now they open-sourced CVC [3].  This is pretty amazing
>> because CVC is fast and a great companion with MyHDL (IMO).
>>
>> I will try and experiment replacing the tf_ functions
>> with the OSS CVC and see if the leak can be resolved.
>>
>> Regards,
>> Chris
>>
>>
>> [1] http://ieeexplore.ieee.org/servlet/opac?punumber=10779
>>        (probably can alos be found by googling, note "Verilog"
>>         has been merged with SV in the 1800 standard ...)
>>
>> [2] http://sourceforge.net/projects/gplcver/
>>
>> [3] http://www.tachyon-da.com/
>>
>>
>> ------------------------------------------------------------------------------
>> Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server
>> from Actuate! Instantly Supercharge Your Business Reports and Dashboards
>> with Interactivity, Sharing, Native Excel Exports, App Integration & more
>> Get technology previously reserved for billion-dollar corporations, FREE
>> http://pubads.g.doubleclick.net/gampad/clk?id=164703151&iu=/4140/ostg.clktrk
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] OSS CVC vpi module

[Paul.Y.Zhang <yzh...@gm...>]

Hi, Chris,

Excuse me, I am not very familar with the PLI/VPI technology. I do not 
see any tf_ functions in "myhdl_vpi.c" codes. Waiting for your progress.

- Paul

在 2014/12/16 22:58, Christopher Felton 写道:
> On 12/13/2014 7:43 PM, Paul.Y.Zhang wrote:
>> neccHi,
>>
>> I post the cver vpi module (cosimulation/cver/myhdl_vpi.c) to Steve
>> Meyer (the author of OSS CVC?), to get help of the memory leak issue.
>> Got the below replay:
>>
>>      I assume calltf means the PLI uses the old tf_ interface.  You need to
>> translate (or find) a version of your myhdl PLI coded in vpi_.  tf_ is obsolete
>> old 1990s Verilog XL PLI that is deprecated (removed from) IEEE 1364 2005.
>> The reason tf_ is removed is that it just grew in Cadence XL so nobody could
>> duplicate behavior.
> According to the 1364-2005 LRM [1] which contains the
> PLI/VPI definition, indicates the tf_ functions are
> deprecated (section 24).
>
> Wow - I am a little slow to follow this thread, I didn't
> realize that the Tachyon re-opened/released their
> simulator, originally they open-sourced GPLCVER [2] and
> now they open-sourced CVC [3].  This is pretty amazing
> because CVC is fast and a great companion with MyHDL (IMO).
>
> I will try and experiment replacing the tf_ functions
> with the OSS CVC and see if the leak can be resolved.
>
> Regards,
> Chris
>
>
> [1] http://ieeexplore.ieee.org/servlet/opac?punumber=10779
>       (probably can alos be found by googling, note "Verilog"
>        has been merged with SV in the 1800 standard ...)
>
> [2] http://sourceforge.net/projects/gplcver/
>
> [3] http://www.tachyon-da.com/
>
>
> ------------------------------------------------------------------------------
> Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server
> from Actuate! Instantly Supercharge Your Business Reports and Dashboards
> with Interactivity, Sharing, Native Excel Exports, App Integration & more
> Get technology previously reserved for billion-dollar corporations, FREE
> http://pubads.g.doubleclick.net/gampad/clk?id=164703151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

-- 
Paul

Re: [myhdl-list] OSS CVC vpi module

[Christopher F. <chr...@gm...>]

On 12/13/2014 7:43 PM, Paul.Y.Zhang wrote:
> neccHi,
>
> I post the cver vpi module (cosimulation/cver/myhdl_vpi.c) to Steve
> Meyer (the author of OSS CVC?), to get help of the memory leak issue.
> Got the below replay:
>
>     I assume calltf means the PLI uses the old tf_ interface.  You need to
> translate (or find) a version of your myhdl PLI coded in vpi_.  tf_ is obsolete
> old 1990s Verilog XL PLI that is deprecated (removed from) IEEE 1364 2005.
> The reason tf_ is removed is that it just grew in Cadence XL so nobody could
> duplicate behavior.

According to the 1364-2005 LRM [1] which contains the
PLI/VPI definition, indicates the tf_ functions are
deprecated (section 24).

Wow - I am a little slow to follow this thread, I didn't
realize that the Tachyon re-opened/released their
simulator, originally they open-sourced GPLCVER [2] and
now they open-sourced CVC [3].  This is pretty amazing
because CVC is fast and a great companion with MyHDL (IMO).

I will try and experiment replacing the tf_ functions
with the OSS CVC and see if the leak can be resolved.

Regards,
Chris


[1] http://ieeexplore.ieee.org/servlet/opac?punumber=10779
     (probably can alos be found by googling, note "Verilog"
      has been merged with SV in the 1800 standard ...)

[2] http://sourceforge.net/projects/gplcver/

[3] http://www.tachyon-da.com/

[myhdl-list] OSS CVC vpi module

[Paul.Y.Zhang <yzh...@gm...>]

neccHi,

I post the cver vpi module (cosimulation/cver/myhdl_vpi.c) to Steve 
Meyer (the author of OSS CVC?), to get help of the memory leak issue. 
Got the below replay:

   I assume calltf means the PLI uses the old tf_ interface.  You need to
translate (or find) a version of your myhdl PLI coded in vpi_.  tf_ is obsolete
old 1990s Verilog XL PLI that is deprecated (removed from) IEEE 1364 2005.
The reason tf_ is removed is that it just grew in Cadence XL so nobody could
duplicate behavior.


Is there anyone in this list has any comment for this issue?

CVC is faster 10x times than icarus!

-- 
Paul

Re: [myhdl-list] Tachyon cosimulation?

[Paul.Y.Zhang <yzh...@gm...>]

Hi, Henry

Did you tried cosim with tachyon cvc? What's going on?

Thanks.
- Paul

在 2014/12/10 2:57, Henry Gomersall 写道:
> On 09/12/14 18:40, Christopher Felton wrote:
>> On 12/9/2014 12:31 PM, Christopher Felton wrote:
>>>> On 12/9/2014 10:52 AM, Henry Gomersall wrote:
>>>>>> I just noticed that Tachyon is now open source:
>>>>>> http://www.tachyon-da.com/
>>>>>>
>>>>>> Has anyone had success using Tachyon in cosimulation with MyHDL?
>> You should be able to use the CVER VPI module without
>> modifications to run cosim with tachyon.
> Great, thanks. I'll have a play with stuff.
>
> Henry
>
> ------------------------------------------------------------------------------
> Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server
> from Actuate! Instantly Supercharge Your Business Reports and Dashboards
> with Interactivity, Sharing, Native Excel Exports, App Integration & more
> Get technology previously reserved for billion-dollar corporations, FREE
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> _______________________________________________
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-- 
Paul

Re: [myhdl-list] Tachyon cosimulation?

[Paul.Y.Zhang <yzh...@gm...>]

Hi,

I just tried the OSS CVC, the memory leak is still there.

Regards,
Paul


在 2014/12/10 2:31, Christopher Felton 写道:
> On 12/9/2014 10:52 AM, Henry Gomersall wrote:
>> I just noticed that Tachyon is now open source:
>> http://www.tachyon-da.com/
>>
>> Has anyone had success using Tachyon in cosimulation with MyHDL?
> Yes, I used it for a chip verification a couple years
> ago.  At that point there was a memory leak that occurred
> with Tachyon that we couldn't figure out but it didn't
> occur with Modelsim (VPI memory leak).
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server
> from Actuate! Instantly Supercharge Your Business Reports and Dashboards
> with Interactivity, Sharing, Native Excel Exports, App Integration & more
> Get technology previously reserved for billion-dollar corporations, FREE
> http://pubads.g.doubleclick.net/gampad/clk?id=164703151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list

-- 
Paul

Re: [myhdl-list] Tachyon cosimulation?

[Henry G. <he...@ca...>]

On 09/12/14 18:40, Christopher Felton wrote:
> On 12/9/2014 12:31 PM, Christopher Felton wrote:
>> >On 12/9/2014 10:52 AM, Henry Gomersall wrote:
>>> >>I just noticed that Tachyon is now open source:
>>> >>http://www.tachyon-da.com/
>>> >>
>>> >>Has anyone had success using Tachyon in cosimulation with MyHDL?
>> >
> You should be able to use the CVER VPI module without
> modifications to run cosim with tachyon.
Great, thanks. I'll have a play with stuff.

Henry

Re: [myhdl-list] Tachyon cosimulation?

[Christopher F. <chr...@gm...>]

On 12/9/2014 12:31 PM, Christopher Felton wrote:
> On 12/9/2014 10:52 AM, Henry Gomersall wrote:
>> I just noticed that Tachyon is now open source:
>> http://www.tachyon-da.com/
>>
>> Has anyone had success using Tachyon in cosimulation with MyHDL?
>

You should be able to use the CVER VPI module without
modifications to run cosim with tachyon.

Regards,
Chris

Re: [myhdl-list] Tachyon cosimulation?

[Christopher F. <chr...@gm...>]

On 12/9/2014 10:52 AM, Henry Gomersall wrote:
> I just noticed that Tachyon is now open source:
> http://www.tachyon-da.com/
>
> Has anyone had success using Tachyon in cosimulation with MyHDL?

Yes, I used it for a chip verification a couple years
ago.  At that point there was a memory leak that occurred
with Tachyon that we couldn't figure out but it didn't
occur with Modelsim (VPI memory leak).

Regards,
Chris

[myhdl-list] Tachyon cosimulation?

[Henry G. <he...@ca...>]

I just noticed that Tachyon is now open source:
http://www.tachyon-da.com/

Has anyone had success using Tachyon in cosimulation with MyHDL?

Cheers,

Henry

Re: [myhdl-list] ISE 14.7 and FSM

[Christopher F. <chr...@gm...>]

<snip>

Edward,

Couple suggestions, first, as you indicate, when you
add the *RamCtrl* module you encounter issues.  You
should try and debug this module independent of the
rest!

If you are unable to determine the issue, asking a
question on a smaller set of code will get a better
response.  It is a lot of work to trudge through your
600+ lines of code and try to determine what is going
on.  You NEED to reduce the issue to something
manageable, very few will walk through all of your
code to answer a question.

If you interrogate the *RamCtrl* module there are a
bunch of issues.  What is *RamCtrl* supposed to do?

If it is a state-machine it needs to be a sequential
process (@always_seq(clock ...)) and not purely a
combinatorial.  And you need to decide what are the
inputs to the state-machine and outputs (not sure
why state is in the port list).

One of the other issues is that you are missing several
".next" on assignments.

Regards,
Chris

Re: [myhdl-list] ISE 14.7 and FSM

[Edward V. <dev...@sb...>]

The python file is in the same folder as the https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/XESS_SdramSPInst/xess_jpeg_top.vhd

https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/XESS_SdramSPInst/xess_jpeg_top.py  

The FSM that works okay in a simulation is https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/jpeg_top.py with the test bed https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/simulation/jpegprocess_tb.vhd.  
This one is not using sdram.  

 I did notice that the one that is  not working has several lines without a ";" is this normal.  The steps to change the https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/jpeg_top.py to 
generate the one with the non working FSM are in the previous e-mail or at the https://github.com/develone/jpeg-2000-test/commits/master/jpeg2k/XESS_SdramSPInst/xess_jpeg_top.py history tab.
Thanks,

Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613


On Saturday, December 6, 2014 11:51 AM, Christopher Felton <chr...@gm...> wrote:
 


On 12/6/14, 10:16 AM, Edward Vidal wrote:
> Hello All,
> Fairly new to both VHDL and myhdl.
> I would appreciate any and all help. Thanks in advance.
> I have created other FSM that I used in simulation and it worked okay.
> I am using ISE 14.7 for a Spartan6 XC6SLX9.

Simulation works ok but when you try and synthesize
the design you get errors (assumes conversion works
ok?).

> If I can provide any additional information just let me know.
> Creating a project with xess_jpeg_top.vhd & pck_myhdl_09.vhd will
> synthesize okay.
> The file xess_jpeg_top.vhd is not a package and has the following RTL
> modules.

Is the original source MyHDL source?  Do you have
a link to the original MyHDL?

p.s. the IRC channel #myhdl on freenode can also
be used for real-time discussions.

Regards,
Chris





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Re: [myhdl-list] ISE 14.7 and FSM

[Christopher F. <chr...@gm...>]

On 12/6/14, 10:16 AM, Edward Vidal wrote:
> Hello All,
> Fairly new to both VHDL and myhdl.
> I would appreciate any and all help. Thanks in advance.
> I have created other FSM that I used in simulation and it worked okay.
> I am using ISE 14.7 for a Spartan6 XC6SLX9.

Simulation works ok but when you try and synthesize
the design you get errors (assumes conversion works
ok?).

> If I can provide any additional information just let me know.
> Creating a project with xess_jpeg_top.vhd & pck_myhdl_09.vhd will
> synthesize okay.
> The file xess_jpeg_top.vhd is not a package and has the following RTL
> modules.

Is the original source MyHDL source?  Do you have
a link to the original MyHDL?

p.s. the IRC channel #myhdl on freenode can also
be used for real-time discussions.

Regards,
Chris

[myhdl-list] ISE 14.7 and FSM

[Edward V. <dev...@sb...>]

Hello All,
Fairly new to both VHDL and myhdl.
I would appreciate any and all help. Thanks in advance.
I have created other FSM that I used in simulation and it worked okay.
I am using ISE 14.7 for a Spartan6 XC6SLX9.
If I can provide any additional information just let me know.
Creating a project with xess_jpeg_top.vhd & pck_myhdl_09.vhd will synthesize okay.
The file xess_jpeg_top.vhd is not a package and has the following RTL modules.

XESS_JPEG_TOP_INSTANCE_2_MUXLOGIC
XESS_JPEG_TOP_INSTANCE_3_JPEG
XESS_JPEG_TOP_INSTANCE_4_SDRAM_RD
XESS_JPEG_TOP_INSTANCE_5_RAM2SIG
XESS_JPEG_TOP_INSTANCE_7_FSMUPDATE

Adding a FSM module see below.
XESS_JPEG_TOP_INSTANCE_6_FSM to the xess_jpeg_top.vhd now creates a package.
When I try to synthesize generates the following errors.
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 172: Syntax error near "case".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 176: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 180: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 184: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 187: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 190: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 193: Syntax error near "end".
ERROR:HDLCompiler:854 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 61: Unit <myhdl> ignored due to previous errors.
Lines 169-194
XESS_JPEG_TOP_INSTANCE_6_FSM: process (addr_r, state, even_odd_x) is
begin
    (even_odd_x <= '0')
    case state is
        when INIT =>
            addr_x <= to_unsigned(1, 24);
            (state <= ODD_SAMPLES)
        when ODD_SAMPLES =>
            if (addr_r = 1) then
                addr_x <= to_unsigned(2, 24);
                (state <= EVEN_SAMPLES)
            end if;
        when EVEN_SAMPLES =>
            addr_x <= to_unsigned(2, 24);
            (state <= WR_DATA)
        when WR_DATA =>
            addr_x <= to_unsigned(8, 24);
            (state <= INTERLACE)
        when INTERLACE =>
            addr_x <= to_unsigned(16, 24);
            (state <= DONE)
        when others => -- DONE
            addr_x <= to_unsigned(1, 24);
            (state <= INIT)
    end case;
end process XESS_JPEG_TOP_INSTANCE_6_FSM;
The file that I am using to generate the FSM is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg2k/XESS_SdramSPInst/xess_jpeg_top.vhd
The following is the checked message.
trying to add a FSM
when following 4 lines are un-commented 
def xess_jpeg_top(clk_fast, addr_r, addr_x, addr_r1, addr_r2, muxsel, dataToRam_r, dataToRam_x, sig_in, noupdate_s, res_s, jp_lf, jp_sa ,jp_rh, jp_flgs, reset_col, rdy, addr_not_reached, offset, dataFromRam_s, state, even_odd_r, even_odd_x):
instance_6 = RamCtrl(addr_r, addr_x, state, even_odd_r, even_odd_x)
return instance_2, instance_3, instance_4, instance_5, instance_6, instance_7
toVHDL(xess_jpeg_top, clk_fast, addr_r, addr_x, addr_r1, addr_r2, muxsel, dataToRam_r, dataToRam_x, sig_in, noupdate_s, res_s, jp_lf, jp_sa ,jp_rh, jp_flgs, reset_col, rdy, addr_not_reached, offset, dataFromRam_s, state, even_odd_r, even_odd_x)
the xess_jpeg_top.vhd now creates a package.

when the following 3 lines are un-commented and the line instance_6 = RamCtrl(addr_r, addr_x, state, even_odd_r, even_odd_x) is commented out
def xess_jpeg_top(clk_fast, addr_r, addr_x, addr_r1, addr_r2, muxsel, dataToRam_r, dataToRam_x, sig_in, noupdate_s, res_s, jp_lf, jp_sa ,jp_rh, jp_flgs, reset_col, rdy, addr_not_reached, offset, dataFromRam_s):
return instance_2, instance_3, instance_4, instance_5, instance_7
toVHDL(xess_jpeg_top, clk_fast, addr_r, addr_x, addr_r1, addr_r2, muxsel, dataToRam_r, dataToRam_x, sig_in, noupdate_s, res_s, jp_lf, jp_sa ,jp_rh, jp_flgs, reset_col, rdy, addr_not_reached, offset, dataFromRam_s)
The XESS_JPEG_TOP_INSTANCE_6_FSM is not generated and the file xess_jpeg_top.vhd is not a package.
Thanks,

 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

[myhdl-list] Interesting ...

[Christopher F. <chr...@gm...>]

Hmmm, I didn't know what to expect but I wasn't
expecting this:

In [22]: def m_nonlocal(clock, reset, x, y, z):
     ...:     class nonlocal:
     ...:         cnt = 0
     ...:
     ...:     @always_seq(clock.posedge, reset=reset)
     ...:     def rtl():
     ...:         nonlocal.cnt += 1
     ...:         if nonlocal.cnt > 10:
     ...:             z.next = x + y
     ...:             nonlocal.cnt = 0
     ...:     return rtl
     ...:

In [23]: from myhdl import *

In [24]: clock = Signal(bool(0))
     ...: reset = ResetSignal(0, 0, True)
     ...: x,y,z = [Signal(intbv(0, min=-80, max=80)) for _ in range(3)]
     ...: toVerilog(m_nonlocal, clock, reset, x, y, z)
     ...:
Out[24]: <myhdl._always_seq._AlwaysSeq at 0xa2e10b8>

In [25]: %less m_nonlocal.v
// File: m_nonlocal.v
// Generated by MyHDL 0.9dev
// Date: Fri Nov 21 16:32:28 2014
// <snip a bunch of stuff ... >

always @(posedge clock, negedge reset) begin: M_NONLOCAL_RTL
     reg nonlocal.cnt;
     if (reset == 0) begin
         z <= 0;
     end
     else begin
         nonlocal.cnt = nonlocal.cnt + 1;
         if ((nonlocal.cnt > 10)) begin
             z <= (x + y);
             nonlocal.cnt = 0;
         end
     end
end

endmodule

Re: [myhdl-list] Signal has multiple drivers

[Josy B. <jos...@gm...>]

The read_file_sdram definition has two return statements. The first one 
will be executed, shutting out the rest of the code. You have to make a 
single 'lumped' return after the last process, e.g. <return file_rd, 
muxLogic>
You will then get the VHDL-warning that addr_r has multiple drivers 
because you specify an <addr_r.next = ...> operation in both processes.

[myhdl-list] Signal has multiple drivers

[Edward V. <dev...@sb...>]

Hello all,
Fairly new to vhdl.  Using a structural model with 8 instances.  Everything was working okay.
Started getting a message the Signal has multiple drivers.
Found a posting http://comments.gmane.org/gmane.comp.python.myhdl/1999
from Chris Felton to use a mux.

I see in the package generated with toVHDL
signal instance_7_addr_r: unsigned(5 downto 0); which is used by JPEG_TOP_INSTANCE_1_SDRAM_RD and
JPEG_TOP_INSTANCE_7_FILE_RD.

What I do not see in the package is the code for the muxLogic.

    @always_comb
    def muxLogic():
        addr_r.next = addr_r1
        if sel == 1:
            addr_r.next = addr_r2
    return muxLogic    
which was part of JPEG_TOP_INSTANCE_7_FILE_RD.

def read_file_sdram(clk_fast, rst, eog, we_sdram, rst_file_in, addr_r1, addr_r2, sel ):
    addr_r = Signal(intbv(0)[6:])
    @always(clk_fast.negedge)
    def file_rd():
        if (rst_file_in == 0):
            rst.next = 1
            addr_r.next = 0
            we_sdram.next = 1
        else:
            if (rst == 1):
                rst.next = 0
            elif (eog == 0):
                if (addr_r <= 48):
                    
                    addr_r.next = addr_r + 1
            else:
                we_sdram.next = 0
    return file_rd
    @always_comb
    def muxLogic():
        addr_r.next = addr_r1
        if sel == 1:
            addr_r.next = addr_r2
    return muxLogic

I am trying to run a simulation using ISE 14.7 at the moment.
I know I need to use addr_r1, addr_r2, and sel for JPEG_TOP_INSTANCE_7_FILE_RD. Which is where is where
I defined the muxLogic.  JPEG_TOP_INSTANCE_7_FILE_RD and JPEG_TOP_INSTANCE_1_SDRAM_RD
both will be used in simulation.  Only JPEG_TOP_INSTANCE_1_SDRAM_RD & JPEG_TOP_INSTANCE_4_FSM will be used
in the bit file.  This uses addr_r which is not part of entity jpeg_top.
Did I put the muxLogic code in the wrong place?
Thanks in advance for any and all help.


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] Simplifying Interfaces

[Christopher F. <chr...@gm...>]

On 11/7/2014 9:05 AM, Wesley New wrote:
> Did anyone ever come up with a good example of this?
>

Interfaces have been implemented in 0.9-dev, do you
mean has a succinct example been generated as a cookbook
or tutorial?

I have a basic example here:
http://www.fpgarelated.com/showarticle/544.php

Regards,
Chris

> Wesley New
> South African SKA Project
> +2721 506 7365
> www.ska.ac.za
>
>
>
> On Fri, Jul 6, 2012 at 4:56 AM, Christopher Felton <chr...@gm...>
> wrote:
>
>> On 7/5/12 11:29 AM, Tom Dillon wrote:
>>>
>>> On 07/04/2012 02:22 PM, Christopher Felton wrote:
>>>> <snip>
>>>>>> Anyone else have an idea for an example?  I think for the example to
>> be
>>>>>> useful, you would want a design that you would use multiple modules
>> and
>>>>>> have some interface between.  But the interface would be small
>> (limited
>>>>>> number of signals in the class) so the the example would be
>> digestible.
>>>>> Maybe something based on complex numbers, as Tom D has
>>>>> hinted. One could represent them as a class instance,
>>>>> or even as a tuple.
>>>>>
>>>>>
>>>> I was worried if the complex number example was used some
>>>> might expect operator overload.  I have been waffling if
>>>> this would be a good example.
>>>
>>> I think the example would have to show why we would not try to overload
>>> operators.
>>>
>>
>> I agree, which, IMO, requires a little bit of *ART*.
>> There are many concepts that need to pulled together and
>> succinctly explained.  I do not want set incorrect
>> expectations.
>>
>> I don't know if I see a good way to explain that operator
>> overloading is appropriate for a sequence of instructions
>> but not for a hardware description (concurrent processes).
>> Or if it is absent if it will raise questions.
>>
>> I don't if a plain "signal container" example would be a
>> better fit.
>>
>> Regards,
>> Chris
>>
>>
>>
>>
>>
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