myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] std_logic_vector

[Edward V. <dev...@sb...>]

 Hello
Josy thanks for the reply. 
Is there a way to have mix of unsigned and std_logic_vector?
I have a top_level that has only 1 toVHDL statement.  For now only 1 signal needs to be std_logic_vector to match someone else code.  
When I break it up to 7 toVHDL 1 statement fails since a variable is _enumPortTypeSet AssertionError.
I am correct in thinking that toVHDL.numeric_ports = False is only for the next toVHDL statement.
Also did not understand the Qsys comment I am using a Xilinx product spartan 6.  Web search appears to be for Altera product.
Thanks
I am starting to think that I might be making progress.  

Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] Setting of enum values

[Henry G. <he...@ca...>]

On 06/01/15 20:50, Henry Gomersall wrote:
> On 29/12/14 18:26, Christopher Felton wrote:
>>>> >> >AFAICT it doesn't acquire any state from the enum function so it could
>>>> >> >just as easily be at the module level, allowing more flexible usage when
>>>> >> >needing to fit the enum to an existing definition.
>> >I am sure there are many ways to implement it, this may
>> >not have been a use case envision or desired.  We can
>> >propose a modification to have the "Enum" class public
>> >and then various custom functions can be created to
>> >implement the codedicts, etc.  I think this would provide
>> >flexibility but also maintain a minimal / logical enum.
> I'm keen on this. I don't see any reason why Enum should be so hard to
> access. I agree enum should be kept as is.
Further to this, why not just extend the existing python Enum:

https://pypi.python.org/pypi/enum34

Cheers,

Henry

Re: [myhdl-list] FW: Std_logoc_vector

[Josy B. <jos...@gm...>]

Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> ----Forwarded Message----
> From: develone <at> sbcglobal.net
> To: myhdl-list-request <at> lists.sourceforge.net
> Sent: Tue, Jan 6, 2015 4:03 PM CST
> Subject: Std_logoc_vector
> 
> Hello.
> How do you get a signal to be std_locic_vector instead of unsigned or 
signed to match others code that is
> defined as std_logic_vector. Thanks
> 
> 
Use this:
-------
        # force std_logic_vectors instead of unsigned in Interface as 
Qsys wants this
        toVHDL.numeric_ports = False
        toVHDL( ... )

------
I'm not sure whether it is documented, but it works (at least in MyHDL 
0.9)

Regards,

Josy

[myhdl-list] FW: Std_logoc_vector

[Edward V. <dev...@sb...>]

----Forwarded Message----
From: dev...@sb...
To: myh...@li...
Sent: Tue, Jan 6, 2015 4:03 PM CST
Subject: Std_logoc_vector


Hello.
How do you get a signal to be std_locic_vector instead of unsigned or signed to match others code that is defined as std_logic_vector. Thanks

Re: [myhdl-list] Setting of enum values

[Henry G. <he...@ca...>]

On 29/12/14 18:26, Christopher Felton wrote:
>> >AFAICT it doesn't acquire any state from the enum function so it could
>> >just as easily be at the module level, allowing more flexible usage when
>> >needing to fit the enum to an existing definition.
> I am sure there are many ways to implement it, this may
> not have been a use case envision or desired.  We can
> propose a modification to have the "Enum" class public
> and then various custom functions can be created to
> implement the codedicts, etc.  I think this would provide
> flexibility but also maintain a minimal / logical enum.

I'm keen on this. I don't see any reason why Enum should be so hard to 
access. I agree enum should be kept as is.

Cheers,

Henry

Re: [myhdl-list] Another typo in docs

[Henry G. <he...@ca...>]

On 06/01/15 04:23, Christopher Felton wrote:
>> >My hg-fu is low, so I've no idea what's going on with multiple heads and
>> >whatnot - I'd appreciate being enlightened. It's not exactly intuitive!
>> >
> hg multiple heads, usually need to be merged.  This is
> the default case when you are modifying your local copy
> (tip) and then pull from somewhere else.  The cure is
> typically a merge.  If you merge right after a pull all
> works.  if not you might have to specify the heads to
> merge, something like:
>
>      >> hg heads
>      >> hg merge tip ...
>
> More information here:
> http://mercurial.selenic.com/wiki/MultipleHeads
>
> This post uses nice diagrams (Directed Acyclic Graph
> (a DAG)) to show how heads are created and merged, and
> merge vs. rebase.  This might help visualize what is
> going on.
> http://softwareswirl.blogspot.com/2009/04/truce-in-merge-vs-rebase-war.html
>
> This might be helpful:
> http://mercurial.selenic.com/wiki/GitConcepts
Thanks for that.

Is my repository in a fit state for a PR? It doesn't seem to be 
complaining about multiple heads at the moment.

I can fold in any changes that come out of the current discussions about 
the best doctest strategy.

Henry

Re: [myhdl-list] Another typo in docs

[Henry G. <he...@ca...>]

On 06/01/15 20:31, Ben wrote:
>>> I had to replicate some code in the documentation for doctest to work
>>> >>(which just makes it easier to copy and paste, though potentially open
>>> >>to replication errors down the line). The issue seemed to be related to
>>> >>globals in the doctest string, though I've not tried to hard to get to
>>> >>the bottom of it.
>>> >>
>> >
>> >I did not find a work around for this.  Your approach is nice
>> >to enable doctest but I am worried the maintenance will be a
>> >pain (double code snips).
> Maybe there is a way using the ``doctest_global_setup`` config value
> [0]. The conf.py file is python so it should be possible to read (part
> of) another python file to populate that variable. That code would be
> automatically 'duplicated' on top of each file ...
I did wonder if there was some trick that could be done with defining 
functions elsewhere. I can't see how this solves it though.

Is there some way in which a global (or perhaps a hidden local) can be 
used to make sure the displayed code is correct?

I don't see how we get round the problem that a carried forward instance 
factory seems to get broken by doctest.

Henry

Re: [myhdl-list] Another typo in docs

[Ben <ben...@gm...>]

On Tue, Jan 6, 2015 at 1:10 PM, Christopher Felton
<chr...@gm...> wrote:
> On 1/4/15, 11:38 AM, Henry Gomersall wrote:
>> On 04/01/15 17:29, Henry Gomersall wrote:
>>> On 24/05/14 01:52, Christopher Felton wrote:
>>>>> Here are the merged changes - I don't know if this is
>>>>> the final version/format desired but it is a starting
>>>>> point, I merged it to the 0.9dev branch:
>>>>>
>>>>> https://bitbucket.org/cfelton/myhdl_09dev_doctest/overview
>>> Did you ever had this working?
>>>
>>> I'm getting a problem in which inspect.getsource is unable to return the
>>> correct source of the function inside always_comb.
>>>
>>> Specifically, the source of muxLogic in comb1 in rtl.rst is given as:
>>>
>>> def test():
>>>            print "z a b sel"
>>>            for i in range(8):
>>>                a.next, b.next, sel.next = randrange(8), randrange(8),
>>> randrange(2)
>>>                yield delay(10)
>>>                print "%s %s %s %s" % (z, a, b, sel)
>>>
>>> i.e. the source of test(). Clearly, this means the sensitivity list is
>>> not found properly with a resultant error raised by myhdl.
>>>
>>> The test code works fine in a standalone .py file, so it's some
>>> interaction with sphinx doctest.
>>
>> Further to this, I've got a working doctest suite for rtl.rst. This is at:
>>
>> https://bitbucket.org/heng/myhdl/branch/0.9-dev
>>
>> I had to replicate some code in the documentation for doctest to work
>> (which just makes it easier to copy and paste, though potentially open
>> to replication errors down the line). The issue seemed to be related to
>> globals in the doctest string, though I've not tried to hard to get to
>> the bottom of it.
>>
>
> I did not find a work around for this.  Your approach is nice
> to enable doctest but I am worried the maintenance will be a
> pain (double code snips).

Maybe there is a way using the ``doctest_global_setup`` config value
[0]. The conf.py file is python so it should be possible to read (part
of) another python file to populate that variable. That code would be
automatically 'duplicated' on top of each file ...

Just my 2c.

Ben.

[0] http://sphinx-doc.org/ext/doctest.html#confval-doctest_global_setup

Re: [myhdl-list] Another typo in docs

[Henry G. <he...@ca...>]

On 06/01/15 12:10, Christopher Felton wrote:
>> I had to replicate some code in the documentation for doctest to work
>> >(which just makes it easier to copy and paste, though potentially open
>> >to replication errors down the line). The issue seemed to be related to
>> >globals in the doctest string, though I've not tried to hard to get to
>> >the bottom of it.
>> >
> I did not find a work around for this.  Your approach is nice
> to enable doctest but I am worried the maintenance will be a
> pain (double code snips).

Yeah, I can't work out how else to do it (easily).

I noticed the FSM code later on works fine in which the test suite is 
defined differently - everything is done inside a function. Perhaps this 
is a solution, though I sort of thought it's quite useful showing a few 
different ways to work.

Cheers,

Henry

Re: [myhdl-list] Another typo in docs

[Christopher F. <chr...@gm...>]

On 1/4/15, 11:38 AM, Henry Gomersall wrote:
> On 04/01/15 17:29, Henry Gomersall wrote:
>> On 24/05/14 01:52, Christopher Felton wrote:
>>>> Here are the merged changes - I don't know if this is
>>>> the final version/format desired but it is a starting
>>>> point, I merged it to the 0.9dev branch:
>>>>
>>>> https://bitbucket.org/cfelton/myhdl_09dev_doctest/overview
>> Did you ever had this working?
>>
>> I'm getting a problem in which inspect.getsource is unable to return the
>> correct source of the function inside always_comb.
>>
>> Specifically, the source of muxLogic in comb1 in rtl.rst is given as:
>>
>> def test():
>>            print "z a b sel"
>>            for i in range(8):
>>                a.next, b.next, sel.next = randrange(8), randrange(8),
>> randrange(2)
>>                yield delay(10)
>>                print "%s %s %s %s" % (z, a, b, sel)
>>
>> i.e. the source of test(). Clearly, this means the sensitivity list is
>> not found properly with a resultant error raised by myhdl.
>>
>> The test code works fine in a standalone .py file, so it's some
>> interaction with sphinx doctest.
>
> Further to this, I've got a working doctest suite for rtl.rst. This is at:
>
> https://bitbucket.org/heng/myhdl/branch/0.9-dev
>
> I had to replicate some code in the documentation for doctest to work
> (which just makes it easier to copy and paste, though potentially open
> to replication errors down the line). The issue seemed to be related to
> globals in the doctest string, though I've not tried to hard to get to
> the bottom of it.
>

I did not find a work around for this.  Your approach is nice
to enable doctest but I am worried the maintenance will be a
pain (double code snips).

Regards,
Chris

Re: [myhdl-list] Another typo in docs

[Christopher F. <chr...@gm...>]

<snip>
>
> My hg-fu is low, so I've no idea what's going on with multiple heads and
> whatnot - I'd appreciate being enlightened. It's not exactly intuitive!
>

hg multiple heads, usually need to be merged.  This is
the default case when you are modifying your local copy
(tip) and then pull from somewhere else.  The cure is
typically a merge.  If you merge right after a pull all
works.  if not you might have to specify the heads to
merge, something like:

    >> hg heads
    >> hg merge tip ...

More information here:
http://mercurial.selenic.com/wiki/MultipleHeads

This post uses nice diagrams (Directed Acyclic Graph
(a DAG)) to show how heads are created and merged, and
merge vs. rebase.  This might help visualize what is
going on.
http://softwareswirl.blogspot.com/2009/04/truce-in-merge-vs-rebase-war.html

This might be helpful:
http://mercurial.selenic.com/wiki/GitConcepts


Regards,
Chris

Re: [myhdl-list] Lost in conversion ... _error.SignalInMultipleLists

[Josy B. <jos...@gm...>]

Josy Boelen <josyboelen <at> gmail.com> writes:

> My code is rather a handful ... but I'll make a minimal project around 
the 
> conflicting module.
> <snip>

I just did that, and  the reduced code shows the identical error, so I 
must be doing something wrong. I'll have to find out ...

Regards,

Josy

Re: [myhdl-list] Which is better ??? IOPT or MyHDL ?????

[Josy B. <jos...@gm...>]

David Blubaugh <davidblubaugh2000 <at> yahoo.com> writes:

> 
> I was wondering if anyone out there has ever worked with IOPT petri net 
toolset for development for FPGAs ??? 
> I was wondering as to which is better IOPT petri nets or python 
scripting within MyHDL ??  
> 
> Has anyone ever worked with petri nets for FPGA development ???  Should 
I use a combination of both since I am
> truly amazed with the specification, verification, and validation power 
of petri nets !!!  
> 
> You can do virtually anything with using petri nets !!!
> 
> Thanks,
> 
> David Blubaugh
> 
> ------------------------------------------------------------------------
------
Hey David, get off my cloud !!!
You are welcome to start your own thread !!! You know how to do that ?????

Regards,

Josy

[myhdl-list] Which is better ??? IOPT or MyHDL ?????

[David B. <dav...@ya...>]

I was wondering if anyone out there has ever worked with IOPT petri net toolset for development for FPGAs ???  I was wondering as to which is better IOPT petri nets or python scripting within MyHDL ??  


Has anyone ever worked with petri nets for FPGA development ???  Should I use a combination of both since I am truly amazed with the specification, verification, and validation power of petri nets !!!  

You can do virtually anything with using petri nets !!!

Thanks,

David Blubaugh

Re: [myhdl-list] Lost in conversion ... _error.SignalInMultipleLists

[Josy B. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:

<snip>
> Do you have an example of the failing code?
> This is probably one of those cases where it
> will simulate ok (no restriction for a signal
> in a single list) but will not convert.
> 
> Regards,
> Chris
> 
>
Thanks Chris, 

Your example shows how to provoke the error. I'll run it through my 
'annotating' MyHDL and see what that prints out.
My code is rather a handful ... but I'll make a minimal project around the 
conflicting module.
And, yes it simulates OK.
I can reformulate the question better as:
In my printlog the offending line immediately flags a name as being used 
in a(nother) list, although the name in question hasn't been visited 
before and thus shouldn't/couldn't have the _inList flag set?

Regards,

Josy

Re: [myhdl-list] Lost in conversion ... _error.SignalInMultipleLists

[Christopher F. <chr...@gm...>]

On 1/5/2015 2:56 AM, Josy Boelen wrote:
<snip>
> ---
> Can somebody shed some light?
>

I didn't work through your print trace or what
the conversion code is trying to do.  But here
is an example that generates the same error.

     from myhdl import *

     def m_multi_list(clock, reset, x, y):
         los1 = [Signal(bool(0)) for _ in range(4)]
         sig_in_two = los1[0]
         los2 = [sig_in_two] + [Signal(bool(0)) for _ in range(3)]

         @always_seq(clock.posedge, reset=reset)
         def rtl():
             y.next = los1[x] and los2[x]

         return rtl

     clock = Signal(bool(0))
     reset = ResetSignal(0, active=0, async=True)
     x = Signal(intbv(0, min=0, max=4))
     y = Signal(bool(0))
     toVHDL(m_multi_list, clock, reset, x, y)


Do you have an example of the failing code?
This is probably one of those cases where it
will simulate ok (no restriction for a signal
in a single list) but will not convert.


Regards,
Chris

Re: [myhdl-list] Another typo in docs

[Christopher F. <chr...@gm...>]

On 1/4/2015 11:29 AM, Henry Gomersall wrote:
> On 24/05/14 01:52, Christopher Felton wrote:
>> Here are the merged changes - I don't know if this is
>> the final version/format desired but it is a starting
>> point, I merged it to the 0.9dev branch:
>>
>> https://bitbucket.org/cfelton/myhdl_09dev_doctest/overview
>
> Did you ever had this working?

I did at one point.  I originally attempted the doctest
in 0.8 but was unable to generate a PR before the 0.8
release.  Then I merged the effort to the 0.9 ...

Let me check tonight if I have my latest pushed to
bitbucket repo and see if I had similar issues as
you state.

Regards,
Chris

[myhdl-list] Lost in conversion ... _error.SignalInMultipleLists

[Josy B. <jos...@gm...>]

While converting a module I get the following:
----
  File "C:\Python27\lib\site-packages\myhdl\conversion\_analyze.py", 
line 147, in _analyzeSigs
    raise ConversionError(_error.SignalInMultipleLists, s._name)
myhdl.ConversionError: Signal in multiple list is not supported: 
pl_ple_2_enables(0)
---
The 'ofending' section in _analyze.py:
---
    # handle the case where a named signal appears in a list also by 
giving
    # priority to the list and marking the signals as unused
    print '_analyzeSigs - memlist',memlist
    for m in memlist:
        if not m._used:
            continue
#         print m
        for i, s in enumerate(m.mem):
            s._name = "%s%s%s%s" % (m.name, open, i, close)
            print m.name, s._name, s._inList,
            s._used = False
            if s._inList:
                raise ConversionError(_error.SignalInMultipleLists, 
s._name)
            s._inList = True
            if not s._nrbits:
                raise ConversionError(_error.UndefinedBitWidth, s._name)
            if type(s.val) != type(m.elObj.val):
                raise ConversionError(_error.InconsistentType, s._name)
            if s._nrbits != m.elObj._nrbits:
                raise ConversionError(_error.InconsistentBitWidth, 
s._name)
            print'->', s._name, s._inList
----
I added some print statements to _analyze.py as you can see.
The exception is raised when _inList is already set. _inList is however 
initialised to False in _Signal.py and only set to True in the above 
code.
Here is the output of these 2 print statemants:
---
pl_Enables pl_Enables(0) False -> pl_Enables(0) True
pl_Enables pl_Enables(1) False -> pl_Enables(1) True
pl_Enables pl_Enables(2) False -> pl_Enables(2) True
pl_ple_2_lenables pl_ple_2_lenables(0) False -> pl_ple_2_lenables(0) 
True
pl_ple_2_readies pl_ple_2_readies(0) False -> pl_ple_2_readies(0) True
pl_ple_2_enables pl_ple_2_enables(0) True
---
Can somebody shed some light?

Regards,

Josy

Re: [myhdl-list] Another typo in docs

[Henry G. <he...@ca...>]

On 04/01/15 17:29, Henry Gomersall wrote:
> On 24/05/14 01:52, Christopher Felton wrote:
>> >Here are the merged changes - I don't know if this is
>> >the final version/format desired but it is a starting
>> >point, I merged it to the 0.9dev branch:
>> >
>> >https://bitbucket.org/cfelton/myhdl_09dev_doctest/overview
> Did you ever had this working?
>
> I'm getting a problem in which inspect.getsource is unable to return the
> correct source of the function inside always_comb.
>
> Specifically, the source of muxLogic in comb1 in rtl.rst is given as:
>
> def test():
>           print "z a b sel"
>           for i in range(8):
>               a.next, b.next, sel.next = randrange(8), randrange(8),
> randrange(2)
>               yield delay(10)
>               print "%s %s %s %s" % (z, a, b, sel)
>
> i.e. the source of test(). Clearly, this means the sensitivity list is
> not found properly with a resultant error raised by myhdl.
>
> The test code works fine in a standalone .py file, so it's some
> interaction with sphinx doctest.

Further to this, I've got a working doctest suite for rtl.rst. This is at:

https://bitbucket.org/heng/myhdl/branch/0.9-dev

I had to replicate some code in the documentation for doctest to work 
(which just makes it easier to copy and paste, though potentially open 
to replication errors down the line). The issue seemed to be related to 
globals in the doctest string, though I've not tried to hard to get to 
the bottom of it.

My hg-fu is low, so I've no idea what's going on with multiple heads and 
whatnot - I'd appreciate being enlightened. It's not exactly intuitive!

Cheers,

Henry

Re: [myhdl-list] Another typo in docs

[Henry G. <he...@ca...>]

On 24/05/14 01:52, Christopher Felton wrote:
> Here are the merged changes - I don't know if this is
> the final version/format desired but it is a starting
> point, I merged it to the 0.9dev branch:
>
> https://bitbucket.org/cfelton/myhdl_09dev_doctest/overview

Did you ever had this working?

I'm getting a problem in which inspect.getsource is unable to return the 
correct source of the function inside always_comb.

Specifically, the source of muxLogic in comb1 in rtl.rst is given as:

def test():
         print "z a b sel"
         for i in range(8):
             a.next, b.next, sel.next = randrange(8), randrange(8), 
randrange(2)
             yield delay(10)
             print "%s %s %s %s" % (z, a, b, sel)

i.e. the source of test(). Clearly, this means the sensitivity list is 
not found properly with a resultant error raised by myhdl.

The test code works fine in a standalone .py file, so it's some 
interaction with sphinx doctest.

Cheers,

Henry

[myhdl-list] Is it time for 0.9 release?

[Christopher F. <chr...@gm...>]

I think it is time for the 0.9 release, the major
feature in 0.9 is the interfaces.  Some have been
using the interfaces for awhile and there are no
obvious issues.

I think 0.9 could be released, thoughts?

Regards,
Chris

Re: [myhdl-list] Setting of enum values

[Christopher F. <chr...@gm...>]

On 12/28/2014 11:44 AM, Henry Gomersall wrote:
> On 28/12/14 11:24, Henry Gomersall wrote:
>> Looking at the code, it seems the enum value is set by the argument
>> order, so I can't see how to do it trivially.
>
> It strikes me that the problem is that the class definition is inside
> the enum factory function. Is there a reason for this?

I don't know about the original design decision.

>
> AFAICT it doesn't acquire any state from the enum function so it could
> just as easily be at the module level, allowing more flexible usage when
> needing to fit the enum to an existing definition.

I am sure there are many ways to implement it, this may
not have been a use case envision or desired.  We can
propose a modification to have the "Enum" class public
and then various custom functions can be created to
implement the codedicts, etc.  I think this would provide
flexibility but also maintain a minimal / logical enum.

Note, I am thinking out loud here.  I don't know if there
was a design decision to limit the use - I can't think
of one ...

Regards,
Chris

Re: [myhdl-list] Setting of enum values

[Christopher F. <chr...@gm...>]

On 12/28/14, 5:24 AM, Henry Gomersall wrote:
> Is there a way to set an enum to have a specific value?

No, but you can set the "encoding" type.

     States = enum("IDLE", ..., encoding='binary')

http://docs.myhdl.org/en/latest/manual/reference.html#myhdl.enum

Regards,
Chris

Re: [myhdl-list] Setting of enum values

[Henry G. <he...@ca...>]

On 28/12/14 11:24, Henry Gomersall wrote:
> Looking at the code, it seems the enum value is set by the argument
> order, so I can't see how to do it trivially.

It strikes me that the problem is that the class definition is inside 
the enum factory function. Is there a reason for this?

AFAICT it doesn't acquire any state from the enum function so it could 
just as easily be at the module level, allowing more flexible usage when 
needing to fit the enum to an existing definition.

Cheers,

Henry

[myhdl-list] Setting of enum values

[Henry G. <he...@ca...>]

Is there a way to set an enum to have a specific value?

Looking at the code, it seems the enum value is set by the argument 
order, so I can't see how to do it trivially.

The use case is to interface with a library block that has the states 
already defined, and I don't really want to implement every enumeration 
for my usage.

I suppose the simple workaround is to wrap the library with the state 
logic and let the synthesis tools worry about any optimisations.

Cheers,

Henry