myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] [newb] traceSignals question

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> In the following simple test:
> 
> from myhdl import Signal, always, intbv, Simulation, delay, toVerilog,
> traceSignals
> 
> def ClkDriver(clk):
> 
>     halfPeriod = delay(1)
> 
>     @always(halfPeriod)
>     def driveClk():
>         clk.next = not clk
> 
>     return driveClk
> 
> def Counter (count, clock, n):
> 
>     @always (clock.posedge)
>     def cntLogic():
>         if count == n-1:
>             count.next = 0
>         else:
>             count.next = count + 1
> 
>         print count
>     return cntLogic
> 
> n = 16
> 
> count = Signal (intbv(0)[4:])
> clock = Signal (bool())
> 
> #clkdriver_inst = ClkDriver(clock)
> clkdriver_inst = traceSignals (ClkDriver, clock)
> cnt_inst = Counter (count, clock, n)
> 
> sim = Simulation (clkdriver_inst, cnt_inst)
> sim.run(50)
> 
> I assumed (it really isn't explained in the manual) that
> traceSignals (ClkDriver, clock) would only trace signals used by 'ClkDriver',
> which would only be clock.  It seems my .vcd output includes others, such as
> 'count'.  How is this determined?  Am I using traceSignals correctly?

Yes, you're just seeing some scope effects.

traceSignals() extract hierarchy below the function argument, as you
would expect. However, all signals in the scope of a module are
considered, not just the ones used inside generators. This behavior
is normally what you'd expect, but sometimes it seems too broad,
as in this case.

The issue is that count and clock are globals, and therefore they
are in anybody's scope. Global signals work fine, but for larger
designs you would probably encapsulate your design in its own
function and get rid of global signals, like so:

def bench():
     count = Signal (intbv(0)[4:])
     clock = Signal (bool())

     #clkdriver_inst = ClkDriver(clock)
     clkdriver_inst = traceSignals (ClkDriver, clock)
     cnt_inst = Counter (count, clock, n)

     return clkdriver_inst, cnt_inst

sim = Simulation(bench())
sim.run(50)


And in such a case you'd only see the signals you expect.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org

[myhdl-list] [newb] modelling question

[Neal B. <ndb...@gm...>]

Simple question.  Model an accumulator.  The accumulator has state (call it
'sum').

Most examples are an RTL style.  My imitation of this style might be: 

def accum (x, result, _sum, count, clock, n):
    @always (clock.posedge)
    def accum_logic(x):
        _sum.next += x
        if count == n-1:
            result.next = _sum
            _sum.next = 0

    return accum_logic

_sum is an internal variable.  Does it need to be one of the parameters passed
to accum, as I showed above?

Perhaps this could be:
def accum (x, result, count, clock, n):

    _sum = Signal (0)

    @always (clock.posedge)
    def accum_logic(x):
        _sum.next += x
        if count == n-1:
            result.next = _sum
            _sum.next = 0

    return accum_logic

What if I prefer object oriented style?  The manual mentions this (the fifo
examples).  I wonder if this style will work properly with the rest of myhdl? 
For example, there are some functions that 'infer' inputs and outputs.  Does
this work if I use this object-oriented style?  There must be some constraints.

[myhdl-list] [newb] traceSignals question

[Neal B. <ndb...@gm...>]

In the following simple test:

from myhdl import Signal, always, intbv, Simulation, delay, toVerilog,
traceSignals

def ClkDriver(clk):

    halfPeriod = delay(1)

    @always(halfPeriod)
    def driveClk():
        clk.next = not clk

    return driveClk

def Counter (count, clock, n):

    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

        print count
    return cntLogic

n = 16

count = Signal (intbv(0)[4:])
clock = Signal (bool())

#clkdriver_inst = ClkDriver(clock)
clkdriver_inst = traceSignals (ClkDriver, clock)
cnt_inst = Counter (count, clock, n)

sim = Simulation (clkdriver_inst, cnt_inst)
sim.run(50)

I assumed (it really isn't explained in the manual) that
traceSignals (ClkDriver, clock) would only trace signals used by 'ClkDriver',
which would only be clock.  It seems my .vcd output includes others, such as
'count'.  How is this determined?  Am I using traceSignals correctly?

[myhdl-list] Manual in pdf

[Jan D. <ja...@ja...>]

Upon request, I have added the latest version of the manual
in pdf format to the site:

     http://www.myhdl.org/doku.php/doc:pdf

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org

Re: [myhdl-list] Floating point

[Günter D. <dan...@we...>]

Sami Al Dalahmah wrote:
> Hi Guenter,
> Basically I'm testing serial to parallel block, it simply streams arrays. It
> worked fine with integers arrays, but didn't work with floating point
> arrays, because like you said intbv() deals with integers inherently. What I
> am after here is to find a short cut instead of writing a quantizer (like
> you said scale, round and truncate), i.e. is there any ready module that can
> quantize a floating point array, I tried the bin() function but it doesn't
> recognize floating points, it treats them as integers.
> 

Hmm, I am still trying to put your approach into a box. If you have
floating point numbers and use the Python build in floating point type,
that means you don't care about conversion to synthesizable HDL. So just
for simulation you would need to apply some scaling if the numbers are
not scaled appropriately yet and then can use the Python build in
round() function to do the rounding.

Guenter

Re: [myhdl-list] Floating point

[Sami Al D. <sam...@gm...>]

Hi Guenter,
Basically I'm testing serial to parallel block, it simply streams arrays. It
worked fine with integers arrays, but didn't work with floating point
arrays, because like you said intbv() deals with integers inherently. What I
am after here is to find a short cut instead of writing a quantizer (like
you said scale, round and truncate), i.e. is there any ready module that can
quantize a floating point array, I tried the bin() function but it doesn't
recognize floating points, it treats them as integers.

On Tue, Feb 10, 2009 at 6:47 AM, Günter Dannoritzer <dan...@we...>wrote:

> Sami Al Dalahmah wrote:
> > Dear all,
> > I'm trying to pass a floating point array to intbv() but normally
> couldn't,
> > is there any suggestions on how to do it elegantly or should I write a
> > function for quantization?
>
> Hi Sami,
>
> An intbv() is a data type related to the int data type in Python. So to
> assign a whole floating point array might not work that well. Could you
> explain more in detail what you are trying to do?
>
> What would make sense is to convert a floating point array to an intbv
> array. In that case you would need to scale and round/trunc the floating
> point values and then convert them to intbv.
>
> Cheers,
>
> Guenter
>
>
>
> ------------------------------------------------------------------------------
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>



-- 
Best Regards
Sami Aldalahmeh

Re: [myhdl-list] Floating point

[Günter D. <dan...@we...>]

Sami Al Dalahmah wrote:
> Dear all,
> I'm trying to pass a floating point array to intbv() but normally couldn't,
> is there any suggestions on how to do it elegantly or should I write a
> function for quantization?

Hi Sami,

An intbv() is a data type related to the int data type in Python. So to
assign a whole floating point array might not work that well. Could you
explain more in detail what you are trying to do?

What would make sense is to convert a floating point array to an intbv
array. In that case you would need to scale and round/trunc the floating
point values and then convert them to intbv.

Cheers,

Guenter

[myhdl-list] Floating point

[Sami Al D. <sam...@gm...>]

Dear all,
I'm trying to pass a floating point array to intbv() but normally couldn't,
is there any suggestions on how to do it elegantly or should I write a
function for quantization?

-- 
Best Regards
Sami Aldalahmeh

Re: [myhdl-list] toVerilog conversion question

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> All,
> 
> I am trying to create a case statement in Verilog that relies on other 
> Signals such as this:
> (THIS WOULD BE THE VERILOG AFTER CONVERSION, where dwb_mx is a Signal 
> that is 32 bits)
> 
>     4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};
>     4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};
>     4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};
>     4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
>     . . .
>     . . .
>     . . .
> 
> Is there a way to do this?  I have been struggling to get my conversion 
> to something like this and was wondering if it is possible.  All the 
> examples that I looked at online are case statements that already know 
> the values on the right side of => .  That is, when the tuple is made 
> with constants.  I guess I could do a bunch of if statements... but 
> didn't know if there was another way to do this more elegantly within MyHDL.

There are two separate cases when the convertor uses case statements:

1) to implement indexing into a tuple of constant integers
This is not what you're after here.

2) when it detects that the conditions in an if-elsif-esle control
structure are exclusive.
This is what you're after. I'm going to expand on this further.

As Python doesn't have a case statement, the straightforward way is to
map MyHDL if/elsif statements to Verilog if/elsif statements. The only
good reason to use case statements (+ pragmas) instead is because in
that way you can express exclusivity, which may result in a more
efficient implementation.

Currently, the convertor doesn't try to detect exclusivity based on
numbers. I don't think that would be very worthwhile. Instead, MyHDL
supports enumeration types, which let you express exclusive conditions
explicitly, like in VHDL.

When I look at your code, it seems it's trying to express one-hot
encoding. In my opinion, it's clearer and less error-prone to use
an enum type to represent the choices symbolically, and define
(or change!) the desired encoding at a single place in the code.
The enum type constructor has a parameter for this.

The documentation (see link below) is perhaps a little confusing.
It suggest that this optimization is only for FSMs. While that
is an important application, the optimization is actually general.
Whenever a enum type is used to indicate exclusivity in a control
structure, a case statement will be used in Verilog or VHDL.
It doesn't matter what you do inside the control structure.

http://www.myhdl.org/doc/0.6/manual/conversion_examples.html#optimizations-for-finite-state-machines

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org

Re: [myhdl-list] Another newbie question

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> All,
> 
> Is there a way to delay signals when converting to Verilog?

Not at this point.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org

Re: [myhdl-list] Support for z and x signal levels in Verilog?

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> I have searched the documentation and the wiki but was unable to find 
> anything in regards to whether or not MyHDL supports Verilog's high 
> impedance and undefined signal levels?
> 
> Does anyone know if there is a way to do this?

1) Modelling
I never quite liked X. It was originally invented for gate level
simulation, and even there I always thought it creates more problems
than it solves. I think RTL modelling and beyond (which is were
MyHDL is positioned) can do without it.

That having said, Python has a "high-level" object for undefined values,
None. It is the default value of Signals and intbv's and could be used 
for modeling.

None is also proposed to represent tristate values in the
following mep:

http://www.myhdl.org/doku.php/meps:mep-103

The distribution contains an experimental implementation of this
for modeling, but it is undocumented in the manual.

2) Conversion to Verilog
At this moment, the convertor neither writes X nor Z. I don't
think it will ever write X. For Z, it could support the mep
referenced above at some point.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org

Re: [myhdl-list] Control over output file generation

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> Eric Jonas wrote:
>> Hello! MyHDL has been a lot of fun thus far, but as I look toward
>> automating more of my design flow, I'm stuck on one question: The
>> correct way to control both the location and name of the generated
>> verilog/vhdl code. 
> 
> The file name in connection with the module name can be changed with the
> toVerilog.name or toVHDL.name attribute. See the reference document for
> that:
> 
> http://www.myhdl.org/doc/0.6/manual/reference.html#myhdl.toVerilog
> http://www.myhdl.org/doc/0.6/whatsnew/0.6.html#toVHDL
> 
> Now I am not sure whether that would also allow to add a path. You might
> have to do some additional Python tricks to do that.

No, .name merely changes the top level design name from its default.
The name is also used to define a filename, but that cannot be
further controlled at this point.

I guess we should add an additional attribute (.filename ?) to
control the desired filename.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org

[myhdl-list] Another newbie question

[Newell J. <pil...@gm...>]

All,

Is there a way to delay signals when converting to Verilog?

I want to be able to convert using toVerilog to produce something like this:

a <= #1 b;

I have tried different approaches but the best I have figured out is doing
something like this:

if something:
   yield delay(1)
   a = b
...
...

which gets converted to:

#1
a <= b;

Any other suggestions?

Thanks,

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

[myhdl-list] Support for z and x signal levels in Verilog?

[Newell J. <pil...@gm...>]

I have searched the documentation and the wiki but was unable to find
anything in regards to whether or not MyHDL supports Verilog's high
impedance and undefined signal levels?

Does anyone know if there is a way to do this?

Thanks in advance,

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] toVerilog conversion question

[Newell J. <pil...@gm...>]

Just to clarify on my last post after re-reading it.  Brendan...when I was
referring to case statements I was referring to the Verilog case statement.
I know that Python does not have case statements.

To keep it simple without getting mixed up in words I am just trying to get
a case statement like the one in my initial posting.  If anyone has clues on
how to get a toVerilog conversion that would be able to spit out....that is
what I am after.

Thanks,

On Fri, Jan 30, 2009 at 10:11 PM, Newell Jensen <pil...@gm...>wrote:

>
>
>>
>> The last I heard, Guido doesn't like case/switch statements.  :-)
>
>
> Thanks...but I am well aware of that.  Maybe you don't understand my
> question.
>
>
>>  If statements
>> and concat() are what I would use.  The converter will insert case
>> statements
>> into the Verilog where appropriate.
>
>
> Not necessarily.  I understand that if you have an enumeration or a tuple
> of hardcoded values then it will work.  However, my question is whether or
> not there is a way to update Signals with other Signals (i.e. Signals which
> change on the right side of the non-blocking assignment <=).  I have been
> having issues doing this and have not found anything in the documentation or
> cookbook.
>
> If you point me to a specific example then maybe I will see what you are
> trying to say.  Thanks for the effort though.
>
>
>
>>  I used the following LJ article to get
>> going with this sort of thing:
>>
>> http://www.linuxjournal.com/article/7542
>>
>> The CookBook and other resources on myhdl.org are also very useful
>> references.
>>
>> Cheers,
>>
>> - Brendan
>>
>>
>>
>> ------------------------------------------------------------------------------
>> This SF.net email is sponsored by:
>> SourcForge Community
>> SourceForge wants to tell your story.
>> http://p.sf.net/sfu/sf-spreadtheword
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> Newell
>
> http://www.gempillar.com
> Before enlightenment: chop wood, carry water
> After enlightenment: code, build circuits
>



-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] toVerilog conversion question

[Newell J. <pil...@gm...>]

>
>
> The last I heard, Guido doesn't like case/switch statements.  :-)


Thanks...but I am well aware of that.  Maybe you don't understand my
question.


>  If statements
> and concat() are what I would use.  The converter will insert case
> statements
> into the Verilog where appropriate.


Not necessarily.  I understand that if you have an enumeration or a tuple of
hardcoded values then it will work.  However, my question is whether or not
there is a way to update Signals with other Signals (i.e. Signals which
change on the right side of the non-blocking assignment <=).  I have been
having issues doing this and have not found anything in the documentation or
cookbook.

If you point me to a specific example then maybe I will see what you are
trying to say.  Thanks for the effort though.



>  I used the following LJ article to get
> going with this sort of thing:
>
> http://www.linuxjournal.com/article/7542
>
> The CookBook and other resources on myhdl.org are also very useful
> references.
>
> Cheers,
>
> - Brendan
>
>
>
> ------------------------------------------------------------------------------
> This SF.net email is sponsored by:
> SourcForge Community
> SourceForge wants to tell your story.
> http://p.sf.net/sfu/sf-spreadtheword
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] toVerilog conversion question

[Brendan R. <bre...@gm...>]

Newell Jensen <pillar2012 <at> gmail.com> writes:

> 
> All,I am trying to create a case statement in Verilog that relies on other
Signals such as this:(THIS WOULD BE THE VERILOG AFTER CONVERSION, where dwb_mx
is a Signal that is 32 bits)    4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};   
4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};    4'h2: mem_mx <= #1 {24'd0,
dwb_mx[15:8]};    4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
>     . . .    . . .    . . .Is there a way to do this?  I have been struggling
to get my conversion to something like this and was wondering if it is
possible.  All the examples that I looked at online are case statements that
already know the values on the right side of => .  That is, when the tuple is
made with constants.  I guess I could do a bunch of if statements... but didn't
know if there was another way to do this more elegantly within MyHDL.Thanks,--
Newellhttp://www.gempillar.comBefore enlightenment: chop wood, carry waterAfter
enlightenment: code, build circuits

The last I heard, Guido doesn't like case/switch statements.  :-)  If statements
and concat() are what I would use.  The converter will insert case statements
into the Verilog where appropriate.  I used the following LJ article to get
going with this sort of thing:

http://www.linuxjournal.com/article/7542

The CookBook and other resources on myhdl.org are also very useful references.

Cheers,

- Brendan

[myhdl-list] toVerilog conversion question

[Newell J. <pil...@gm...>]

All,

I am trying to create a case statement in Verilog that relies on other
Signals such as this:
(THIS WOULD BE THE VERILOG AFTER CONVERSION, where dwb_mx is a Signal that
is 32 bits)

    4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};
    4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};
    4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};
    4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
    . . .
    . . .
    . . .

Is there a way to do this?  I have been struggling to get my conversion to
something like this and was wondering if it is possible.  All the examples
that I looked at online are case statements that already know the values on
the right side of => .  That is, when the tuple is made with constants.  I
guess I could do a bunch of if statements... but didn't know if there was
another way to do this more elegantly within MyHDL.

Thanks,

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] Control over output file generation

[Günter D. <dan...@we...>]

Eric Jonas wrote:
> Hello! MyHDL has been a lot of fun thus far, but as I look toward
> automating more of my design flow, I'm stuck on one question: The
> correct way to control both the location and name of the generated
> verilog/vhdl code. 

The file name in connection with the module name can be changed with the
toVerilog.name or toVHDL.name attribute. See the reference document for
that:

http://www.myhdl.org/doc/0.6/manual/reference.html#myhdl.toVerilog
http://www.myhdl.org/doc/0.6/whatsnew/0.6.html#toVHDL

Now I am not sure whether that would also allow to add a path. You might
have to do some additional Python tricks to do that.

My first idea was to just do a os.chdir() ahead of the toVerilog/toVHDL
call, but that might not work as the converter will not find the code
then. Easiest way might be to create the code and then move it with a
combination of shutil.copy() and os.remove() to the path you want.

Cheers,

Guenter

[myhdl-list] Control over output file generation

[Eric J. <jo...@MI...>]

Hello! MyHDL has been a lot of fun thus far, but as I look toward
automating more of my design flow, I'm stuck on one question: The
correct way to control both the location and name of the generated
verilog/vhdl code. 

In particular, how do I tell toVerilog() to dump the output file
in /foo/bar/baz.v?  And is it at all possible to control the filenames
that the different contained modules will be generated as? I have some
code analysis and automated build tools that I'm trying to interoperate
with. 

Thanks again, 
		...Eric

Re: [myhdl-list] migrating from myHDL-0.5.1 to myHDL_0.6

[Jan D. <ja...@ja...>]

Sami Al Dalahmah wrote:
> Dear All,
> 
> Thank you for your response, it is really helpful especially Gunter's 
> approach. But for now I think I will go with the straight forward one 
> suggested by Jan. And I assume I should install the new VPI file of the 
> 0.6 for the cosimulation instead of the old one in the simulator (Icarus 
> in my case), right?

Yes.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org

Re: [myhdl-list] migrating from myHDL-0.5.1 to myHDL_0.6

[Günter D. <dan...@we...>]

Sami Al Dalahmah wrote:

...

> By the way does anyone have
> good experience in Icarus (maybe it is somehow unrelated to myHDL but it can
> be useful)? I ran into the issue when you have a python script using the
> function "os.system(*command*)" to run Icarus for compiling and simulating
> then GTKwave for showing the wave diagram, sometimes when you have a syntax
> error python just do not realize this and continue the script. Do you if
> Icarus can return a value that can be tested for errors that can help my
> script? Actually I asked the same question in the Icarus Wiki and they
> pointed to a Perl test suite that I can learn from, this requires investing
> time to learn Perl then translate it to Python, which is an option I like to
> make one my last ones.
> 
> Sorry for the long email and thank you for your time reading it.
> 

I thought there was a discussion about that last year or so on the
Icarus mailing list, but the only post I found was this from 2007:

http://www.nabble.com/gEDA-dev:-Icarus-Verilog-return-codes--td8653647.html

However, if I understand you right then you want to know when the
simulation failed, which might not be covered by that return code.

As Newell mentioned in another post, one way to solve that is not to use
os.system() but for example os.popen() instead. There you can read the
output of the application and in the test bench you can write some text
that can be search for in the calling python script.

Cheers,

Guenter

Re: [myhdl-list] migrating from myHDL-0.5.1 to myHDL_0.6

[Newell J. <pil...@gm...>]

On Mon, Jan 26, 2009 at 3:07 PM, Sami Al Dalahmah
<sam...@gm...>wrote:

> Dear All,
>
> Thank you for your response, it is really helpful especially Gunter's
> approach. But for now I think I will go with the straight forward one
> suggested by Jan. And I assume I should install the new VPI file of the 0.6
> for the cosimulation instead of the old one in the simulator (Icarus in my
> case), right?
>
> I really like the analyze/verify features, because they save me the script
> used to compile ans simulate the Verilog code. By the way does anyone have
> good experience in Icarus (maybe it is somehow unrelated to myHDL but it can
> be useful)? I ran into the issue when you have a python script using the
> function "os.system(*command*)" to run Icarus for compiling and simulating
> then


Just remember that you are simply programming in Python.  Therefore, there
are other ways of calling the command above (whether or not this would be
the right thing to do or not will depend on what you doing).  Look at Popen
in the subprocess module that comes with Python.  You can do try-except
blocks as well etc.

>>> help(os.system)

This will show you that os.system will give you an exit status.

This is the beauty of MyHDL....its in Python!

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] migrating from myHDL-0.5.1 to myHDL_0.6

[Sami Al D. <sam...@gm...>]

Dear All,

Thank you for your response, it is really helpful especially Gunter's
approach. But for now I think I will go with the straight forward one
suggested by Jan. And I assume I should install the new VPI file of the 0.6
for the cosimulation instead of the old one in the simulator (Icarus in my
case), right?

I really like the analyze/verify features, because they save me the script
used to compile ans simulate the Verilog code. By the way does anyone have
good experience in Icarus (maybe it is somehow unrelated to myHDL but it can
be useful)? I ran into the issue when you have a python script using the
function "os.system(*command*)" to run Icarus for compiling and simulating
then GTKwave for showing the wave diagram, sometimes when you have a syntax
error python just do not realize this and continue the script. Do you if
Icarus can return a value that can be tested for errors that can help my
script? Actually I asked the same question in the Icarus Wiki and they
pointed to a Perl test suite that I can learn from, this requires investing
time to learn Perl then translate it to Python, which is an option I like to
make one my last ones.

Sorry for the long email and thank you for your time reading it.

On Mon, Jan 26, 2009 at 10:38 PM, Jan Decaluwe <ja...@ja...> wrote:

> Sami Al Dalahmah wrote:
> > Dear Jan,
> >
> > Thank you for your response. Maybe I should have been more precise, what
> > I should have said was "installation guide" . I have myHDL 0.5.1 with
> > python 2.5 on Ubuntu, if I want to have the new myHDL 0.6, should I
> > remove the 0.5.1 version or remove a specific files in the bin
> > directory?
>
> There are no bin files, myhdl is installed as a directory somewhere in
> your Python path.
>
> Personally, I always use 'python setup.py install', as for all my
> Python packages. Usually I don't even bother to remove the old
> installation, although I admit that would be cleaner. (Note that
> for this to go wrong, a package's behavior should depend on the
> existence of superfluous files, which is rather strange behaviour.)
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>     Python as a hardware description language:
>     http://www.myhdl.org
>
>
>
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-- 
Best Regards
Sami Aldalahmeh

Re: [myhdl-list] migrating from myHDL-0.5.1 to myHDL_0.6

[Jan D. <ja...@ja...>]

Sami Al Dalahmah wrote:
> Dear Jan,
> 
> Thank you for your response. Maybe I should have been more precise, what 
> I should have said was "installation guide" . I have myHDL 0.5.1 with 
> python 2.5 on Ubuntu, if I want to have the new myHDL 0.6, should I 
> remove the 0.5.1 version or remove a specific files in the bin 
> directory? 

There are no bin files, myhdl is installed as a directory somewhere in
your Python path.

Personally, I always use 'python setup.py install', as for all my
Python packages. Usually I don't even bother to remove the old 
installation, although I admit that would be cleaner. (Note that
for this to go wrong, a package's behavior should depend on the
existence of superfluous files, which is rather strange behaviour.)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org