myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] [new] design flow question

[Günter D. <dan...@we...>]

Newell Jensen wrote:
...
> It would really be nice if there was a way to wrap these cores for use in
> MyHDL so that in the end I could have a Top Level MyHDL implementation with
> embedded cores from OpenCores.
> 
> Any ideas if this is possible?
> 

Have a look at this enhancement proposal:

  http://myhdl.org/doku.php/meps:mep-101

Which is implemented now and documented here:

  http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code


Sometimes subjects were already discussed on this mailing list and can
be searched here:

  http://sourceforge.net/mailarchive/forum.php?forum_name=myhdl-list


Hope this helps.

Cheers,

Guenter

Re: [myhdl-list] [new] design flow question

[Newell J. <pil...@gm...>]

I wanted to ask some questions that are similar to the ones that Neal
asked.  I am new to HDL design in general but love programming in Python.
However, I think I will be using a bunch of the open source cores that are
on OpenCores.org.

I would love to start using MyHDL on a regular basis but as of now I don't
really see how I can use MyHDL with all the OpenCores that I would be using
(I am new so if the answer is obvious than excuse me for my ignorance...I am
still learning).
It would really be nice if there was a way to wrap these cores for use in
MyHDL so that in the end I could have a Top Level MyHDL implementation with
embedded cores from OpenCores.

Any ideas if this is possible?

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] [new] design flow question

[Jan D. <ja...@ja...>]

Neal Becker wrote:
>
>>
> I'm still a bit lost.  My question is, suppose, for example,  I want to do a design targetting Xylinx.  Suppose I want to use an FIR filter, using Xylinx FIR core generator.  
> Would this work with a myhdl frontend, and if so, how would the design flow go?

MyHDL is "front-end" in a HDL-based design flow, as an alternative
to Verilog or VHDL. In the ideal case, your HDL designs are
technology-independent, which means that they contain no references
to primitives of specific target technologies. Targetting to
a specific technology is decoupled from this and is accomplished
by a synthesis tool.

The big advantage of HDL-based design like that, is that you are
not tied to a specific vendor, technology or device.

This ideal can be approached very closely, but for obvious
reasons it's not necessarily in an FPGA vendors interest
to tell you this or promote it. Consequently, one obverves
a great deal of difference in "technology independence"
between various design teams. If you want it, you have to
plan for it and keep the discipline.

I have never used any Xilinx core generator, but I assume
that its output is in terms of Xilinx primitives. If so,
this is not compatible with true HDL-based design as outlined
above.

An HDL-based solution could be as follows. Write a fully
parametrized core generator e.g. for a FIR filter in
MyHDL. (It's ideal for such work, seems easy.) Generate
your coefficients using a filter design package, fill
them in, resimulate in MyHDL, convert to Verilog/VHDL.

The output would be technology independent Verilog or
VHDL code for that filter, that you can then target
to anything using a synthesis tool: Xilinx, Altera,
Actel, ASIC implementation ...

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html

Re: [myhdl-list] [new] design flow question

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> I know only a little about Verilog - I do algorithm development and hand off to coworkers who produce verilog.
> 
> We typically do a lot of DSP work (lots of arithmetic).  Often, things like Xylinx cores are used.
> 
> Would that sort of design flow work with a myhdl frontend?  Any hints?

Sure. This seems to be exactly the case recently highlighted by Chris,
and just added to the advocacy page:

http://www.myhdl.org/doku.php/why#you_would_like_to_do_algorithm_development_and_implementation_in_the_same_environment

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html

Re: [myhdl-list] Advocacy page

[Jan D. <ja...@ja...>]

Christopher L. Felton wrote:
>> On the occasion of the new release, I decided to write a
>> page with common situations and opinions that MyHDL addresses,
>> and that people hopefully can relate to.
>>
>> I have tried to write it down as succinctly as possible -
>> hard work, takes time!
>>
>>     http://www.myhdl.org/doku.php/why
>>
>> Feedback, suggestions, improvements welcome!
> 
> Very good work!  Thanks for all the hard work, with the releases, 
> documentation, and the "Why".
> 
> 
> In addition to everything you mentioned in your write-up, the following 
> puts all those together and captures why Python and MyHDL has 
> been attractive for me.  The following isn't really new/different but 
> a combination of the points you made.  

Thanks, I think this is a very valid case that I hadn't listed yet.
I have reworded it and added to the advocacy page:

http://www.myhdl.org/doku.php/why#you_would_like_to_do_algorithm_development_and_implementation_in_the_same_environment

Thanks,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html

Re: [myhdl-list] Advocacy page

[Jan D. <ja...@ja...>]

Andrew Stone wrote:
> How about "because you can take your dev env (MyHDL/gtkwave/emacs for
> me) with you"?  I'm a noob at hardware design so maybe you all do not
> find this so advantageous but for me its a pain to use the WebPack ISE
> GUI for Xilinx chips, Flex for Cypress, and if I ever get an Altera
> device I'm going to have to learn Quartus I think?  With MyHDL I can
> do all the simulation outside of the vendor GUI and so all I have to
> learn to do in each vendor tool is how to click the "compile" button,
> assign the pins, and program the device, instead of trying to actually
> use GUIs that seem to be designed by a bunch of hardware engineers
> ;-).

I don't think we can argue that MyHDL has a clear distincitive advantage
for non-GUI based design. You can set it up for other HDL languages
and environments also. (When I was doing Verilog and VHDL, I have
basically always done it like that.)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html

Re: [myhdl-list] [new] design flow question

[David B. <dav...@ya...>]

Neal,  
 
Are you willing to share this library with the rest of us??
 
David Blubaugh 

--- On Sat, 12/20/08, Neal Becker <ndb...@gm...> wrote:

From: Neal Becker <ndb...@gm...>
Subject: Re: [myhdl-list] [new] design flow question
To: myh...@li...
Date: Saturday, December 20, 2008, 5:27 PM

Felton Christopher wrote:

>>>
>> I'm still a bit lost.  My question is, suppose, for example,  I
want
>> to do a design targetting Xylinx.  Suppose I want to use an FIR
>> filter, using Xylinx FIR core generator.  Would this work with a
>> myhdl frontend, and if so, how would the design flow go?
>>
> 
> What tool do you currently use for your DSP algorithm simulation?
> 
>
You mean high-level simulation?  I use python with a library of my own based on
boost::python and boost::ublas. 


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Re: [myhdl-list] [new] design flow question

[Neal B. <ndb...@gm...>]

Felton Christopher wrote:

>>>
>> I'm still a bit lost.  My question is, suppose, for example,  I want
>> to do a design targetting Xylinx.  Suppose I want to use an FIR
>> filter, using Xylinx FIR core generator.  Would this work with a
>> myhdl frontend, and if so, how would the design flow go?
>>
> 
> What tool do you currently use for your DSP algorithm simulation?
> 
>
You mean high-level simulation?  I use python with a library of my own based on boost::python and boost::ublas. 

Re: [myhdl-list] Advocacy page

[Martin d A. <po...@ma...>]

On Wed, 17 Dec 2008, Christopher Felton wrote:
>> use GUIs that seem to be designed by a bunch of hardware engineers
>
> That way no need to learn guis for each of the vendors.

One thing I learned quickly in ASIC design and verification is to stay 
away from vendor GUIs and always use command line tools (except for 
waveforms viewing, I don't see much choice here). I use GNU Make to 
implement the dependencies and bash to tie the pieces together. You also 
need a good load sharing/job dispatching tool.

Martin

Re: [myhdl-list] [new] design flow question

[Felton C. <chr...@gm...>]

>>
> I'm still a bit lost.  My question is, suppose, for example,  I want  
> to do a design targetting Xylinx.  Suppose I want to use an FIR  
> filter, using Xylinx FIR core generator.  Would this work with a  
> myhdl frontend, and if so, how would the design flow go?
>

What tool do you currently use for your DSP algorithm simulation?

Re: [myhdl-list] [new] design flow question

[Neal B. <ndb...@gm...>]

Felton Christopher wrote:

> On the website there are many examples, check out some of the
> following links.
> 
> http://www.myhdl.org/doku.php/publications  -- This is your one stop
> shop, the paper by Dillon Engineering (a bunch of active MyHDL
> contributors) describes exactly what you are looking for
> (http://www.myhdl.org/doku.php/publications ).
> 
> Different examples that have been contributed to the site
> http://www.myhdl.org/doku.php/cookbook:sinecomp   -- Implementation of
> the cordic
> http://www.myhdl.org/doku.php/cookbook:bitonic   	-- Sort algorithm
> implementation
> http://www.myhdl.org/doku.php/projects:cordic_calculations	-- Another
> cordic
> http://www.myhdl.org/doku.php/projects:gcicexample	-- CIC Filter
> http://www.myhdl.org/doku.php/projects:conste_encoder  --
> Constellation Encoder
> 
> Good luck
> 
I'm still a bit lost.  My question is, suppose, for example,  I want to do a design targetting Xylinx.  Suppose I want to use an FIR filter, using Xylinx FIR core generator.  Would this work with a myhdl frontend, and if so, how would the design flow go?

[myhdl-list] MICROPROCESSOR DESIGN

[David B. <dav...@ya...>]

To All, Has anyone executed a microprocessor design within MyHDL?   Thanks, David Blubaugh


      

Re: [myhdl-list] [new] design flow question

[Felton C. <chr...@gm...>]

On the website there are many examples, check out some of the  
following links.

http://www.myhdl.org/doku.php/publications  -- This is your one stop  
shop, the paper by Dillon Engineering (a bunch of active MyHDL  
contributors) describes exactly what you are looking for (http://www.myhdl.org/doku.php/publications 
).

Different examples that have been contributed to the site
http://www.myhdl.org/doku.php/cookbook:sinecomp   -- Implementation of  
the cordic
http://www.myhdl.org/doku.php/cookbook:bitonic   	-- Sort algorithm  
implementation
http://www.myhdl.org/doku.php/projects:cordic_calculations	-- Another  
cordic
http://www.myhdl.org/doku.php/projects:gcicexample	-- CIC Filter
http://www.myhdl.org/doku.php/projects:conste_encoder  --  
Constellation Encoder

Good luck


On Dec 17, 2008, at 7:34 PM, Neal Becker wrote:

> I know only a little about Verilog - I do algorithm development and  
> hand off to coworkers who produce verilog.
>
> We typically do a lot of DSP work (lots of arithmetic).  Often,  
> things like Xylinx cores are used.
>
> Would that sort of design flow work with a myhdl frontend?  Any hints?
>
>
> ------------------------------------------------------------------------------
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[myhdl-list] [new] design flow question

[Neal B. <ndb...@gm...>]

I know only a little about Verilog - I do algorithm development and hand off to coworkers who produce verilog.

We typically do a lot of DSP work (lots of arithmetic).  Often, things like Xylinx cores are used.

Would that sort of design flow work with a myhdl frontend?  Any hints?

Re: [myhdl-list] Advocacy page

[Christopher F. <cf...@uc...>]

  find this so advantageous but for me its a pain to use the WebPack
>ISE
> GUI for Xilinx chips, Flex for Cypress, and if I ever get an Altera
> device I'm going to have to learn Quartus I think?  With MyHDL I can
> do all the simulation outside of the vendor GUI and so all I have to
> learn to do in each vendor tool is how to click the "compile" 
>button,
> assign the pins, and program the device, instead of trying to 
>actually
> use GUIs that seem to be designed by a bunch of hardware engineers

I believe you can get a python script from Dillon Engineering site 
that will run the synthesis for most these FPGA tools.  If not all of 
them, the framework is there shouldn't be hard to add.  That way no 
need to learn guis for each of the vendors.

Good luck.

Re: [myhdl-list] Advocacy page

[Andrew S. <g.a...@gm...>]

How about "because you can take your dev env (MyHDL/gtkwave/emacs for
me) with you"?  I'm a noob at hardware design so maybe you all do not
find this so advantageous but for me its a pain to use the WebPack ISE
GUI for Xilinx chips, Flex for Cypress, and if I ever get an Altera
device I'm going to have to learn Quartus I think?  With MyHDL I can
do all the simulation outside of the vendor GUI and so all I have to
learn to do in each vendor tool is how to click the "compile" button,
assign the pins, and program the device, instead of trying to actually
use GUIs that seem to be designed by a bunch of hardware engineers
;-).

Now I do my MyHDL programming in Linux, and then I only pop up a
Windows VM when I want to program the device.

Andrew

On Wed, Dec 17, 2008 at 5:24 AM, Jan Decaluwe <ja...@ja...> wrote:
> On the occasion of the new release, I decided to write a
> page with common situations and opinions that MyHDL addresses,
> and that people hopefully can relate to.
>
> I have tried to write it down as succinctly as possible -
> hard work, takes time!
>
>     http://www.myhdl.org/doku.php/why
>
> Feedback, suggestions, improvements welcome!
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>     From Python to silicon:
>     http://www.myhdl.org
>
>
> ------------------------------------------------------------------------------
> SF.Net email is Sponsored by MIX09, March 18-20, 2009 in Las Vegas, Nevada.
> The future of the web can't happen without you.  Join us at MIX09 to help
> pave the way to the Next Web now. Learn more and register at
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> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] IEEE STANDARDIZATION

[Christopher L. F. <cf...@uc...>]

> When will the final release for 0.6 be ready.  In the past, I have  
> been having some issues with Mercurial.  I have been working them  
> out.  However, I may need help.  Is anyone out there willing to help?
>
> And Lastly,..............
>
> I was wondering if MyHDL can or EVER will be submitted directly to  
> the institute of Electronics and Electrical Engineers ( IEEE ) for  
> obtaining UNIVERSAL and International standardization?  Where MyHDL  
> no longer has to be converted directly to either VHDL or Verilog?  I  
> STRONGLY believe that having to finally convert MyHDL source to  
> Verilog or VHDL constrains the unique advantages of utilizing MyHDL  
> within the Python programming language framework for hardware  
> development for both FPGAs and ASICS.
>
> As an End Game Approach, the idea that I am trying to transmit is  
> that we as a collective could write a proposal to the IEEE, where  
> they will then develop a standardization for the MyHDL language.   
> The same type of standardization that has been bestowed to both  
> Verilog and VHDL.  This would allow companies like XILINX, ALTERA,  
> IBM, INTEL, Cadence to confident enough to develop synthesizers for  
> MyHDL, where there would no longer be a critical need to convert  
> MyHDL to either Verilog to VHDL.  Where a design that is not be  
> synthesized onto an ASIC or FPGA, could be become so with this  
> approach...
>
> I believe that the National Institute of Standards and Technology  
> (NIST) might be more than happy to bring about international  
> standardization for MyHDL.  There is a strong need within the  
> scientific communities to develop reconfigurable computing for  
> numerical methods.
>
> I believe that in the end that giving MyHDL the following possible  
> designations,
>


Hmmm, there is nothing stopping anyone from creating a MyHDL to gate- 
level netlist directly.  I think what Jan has done is brilliant.  He  
leveraged existing technology and tools without having to recreate a  
lot of work.  This has allowed him and others to focus on MyHDL and  
not the back end conversion.  I also think this is the correct approach.

I don't think standards are bad (not too much experience here) but I  
do think there would be a disconnect between development and the  
standardization.  Probably look at other languages for present and  
past experiences.

I think MyHDL will grow with more adoption, this requires more  
individual developers using MyHDL in their design flows and more  
success stories.

Because MyHDL outputs Verilog/VHDL it is minimal risk to add MyHDL to  
the design flow.  Personally, I like the current model.  It would be  
great to see many more developers involved and the project grow as it  
is.  As Jan has pointed out MyHDL is fully functional.  It is up to us  
developers to create some interesting works utilizing MyHDL and Python  
(I am personally working on a time reclamation tool :)

At this point there is a focal point and no competing "standards".  I  
think Jan overseeing/controlling MyHDL as the project he created is  
good.  He is very open to others comments and input.  Because of this  
MyHDL has been maturing.  There are no different/competing versions  
because company A did something different than company B.  Companies  
may become interested in MyHDL because it helps promote their tools  
(if they are good tools).


> ANSI MyHDL or ISO MyHDL, might be a benefit for the entire hadware  
> development community.
>
> So,
>
> What does everybody think about this plan.  I would love to have  
> this plan apart of my thesis endeavor at Wright State University.

As previously mentioned, I think what would help this project the most  
is more success stories and adoption.  Example for you studies if you  
were able to create a working ASIC using the MyHDL flow that would be  
very impressive (mosis education program).   You are in luck that you  
have a group of experienced developers that would help guide you in  
the usage of MyHDL.

Thanks

On Dec 17, 2008, at 6:47 AM, David Blubaugh wrote:

>
>
> Thanks to All,
>
> David Blubaugh
>
>
>
>
>
> ------------------------------------------------------------------------------
> SF.Net email is Sponsored by MIX09, March 18-20, 2009 in Las Vegas,  
> Nevada.
> The future of the web can't happen without you.  Join us at MIX09 to  
> help
> pave the way to the Next Web now. Learn more and register at
> http://ad.doubleclick.net/clk;208669438;13503038;i?http://2009.visitmix.com/_______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

[myhdl-list] IEEE STANDARDIZATION

[David B. <dav...@ya...>]

When will the final release for 0.6 be ready.  In the past, I have been having some issues with Mercurial.  I have been working them out.  However, I may need help.  Is anyone out there willing to help?
 
And Lastly,..............
 
I was wondering if MyHDL can or EVER will be submitted directly to the institute of Electronics and Electrical Engineers ( IEEE ) for obtaining UNIVERSAL and International standardization?  Where MyHDL no longer has to be converted directly to either VHDL or Verilog?  I STRONGLY believe that having to finally convert MyHDL source to Verilog or VHDL constrains the unique advantages of utilizing MyHDL within the Python programming language framework for hardware development for both FPGAs and ASICS.  
 
As an End Game Approach, the idea that I am trying to transmit is that we as a collective could write a proposal to the IEEE, where they will then develop a standardization for the MyHDL language.  The same type of standardization that has been bestowed to both Verilog and VHDL.  This would allow companies like XILINX, ALTERA, IBM, INTEL, Cadence to confident enough to develop synthesizers for MyHDL, where there would no longer be a critical need to convert MyHDL to either Verilog to VHDL.  Where a design that is not be synthesized onto an ASIC or FPGA, could be become so with this approach...
 
I believe that the National Institute of Standards and Technology (NIST) might be more than happy to bring about international standardization for MyHDL.  There is a strong need within the scientific communities to develop reconfigurable computing for numerical methods.  
 
I believe that in the end that giving MyHDL the following possible designations,
 
ANSI MyHDL or ISO MyHDL, might be a benefit for the entire hadware development community.  
 
So,
 
What does everybody think about this plan.  I would love to have this plan apart of my thesis endeavor at Wright State University.  
 
 
Thanks to All,
 
David Blubaugh
 
 
 
 


      

Re: [myhdl-list] Advocacy page

[Christopher L. F. <cf...@uc...>]

> On the occasion of the new release, I decided to write a
> page with common situations and opinions that MyHDL addresses,
> and that people hopefully can relate to.
>
> I have tried to write it down as succinctly as possible -
> hard work, takes time!
>
>     http://www.myhdl.org/doku.php/why
>
> Feedback, suggestions, improvements welcome!

Very good work!  Thanks for all the hard work, with the releases,  
documentation, and the "Why".


In addition to everything you mentioned in your write-up, the  
following puts all those together and captures why Python and MyHDL  
has been attractive for me.  The following isn't really new/different  
but a combination of the points you made.  Also, as you mentioned,  
putting together a coherent thought can take some time and work.  I  
apologize in advance if the following is a little sloppy:

HDL and Beyond
For any kind of algorithm work Python provides a single language where  
everything can be accomplished.  A problem can first be tackled at a  
very high level being an algorithm and / or model.  Because of  
Python's extensive libraries this work is no different than using any  
other tool.  Commonly this work and HDL implementation have be done by  
different engineers because the tools for both required a certain  
level of knowledge that wasn't transferrable between the domains.   
With Python / MyHDL an algorithm / model designer can explore HDL  
implementation and an HDL designer can explore algorithm / model  
design.  There are not multiple tools to learn.  MyHDL is an HDL  
language so the conversion from algorithm to model is still the same  
design procedure (this is a good thing) but it can all be accomplished  
in the same environment.  And the testing can be easily leveraged for  
both design domains.
--

As a side note, I have updated to the latest release and rerun a bunch  
of my MyHDL code and everything looks good so far.

[myhdl-list] Advocacy page

[Jan D. <ja...@ja...>]

On the occasion of the new release, I decided to write a
page with common situations and opinions that MyHDL addresses,
and that people hopefully can relate to.

I have tried to write it down as succinctly as possible -
hard work, takes time!

     http://www.myhdl.org/doku.php/why

Feedback, suggestions, improvements welcome!

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org

Re: [myhdl-list] some conversion problem with concatenated intbvs

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> Hi,
> 
> With the new intbv.signed() function in the hg repository I tried to
> implement a complex multiplier. To make it a bit more complicated than
> necessary there is only one port for each input operand and one port for
> the output. For each port the upper half of the bits are used for the
> real part of the complex value and the lower half of the bits are for
> the imaginary part.
> 
> The simulation of the multiplier works just fine, however, when I
> convert it, the output is set to 0.
> 
> This is the MyHDL code I am using to create the output:
> 
>   @always_comb
>   def add_sub_logic():
>     y_o.next = concat( intbv(ac - bd)[WIDTH+1:], intbv(bc + ad)[WIDTH+1:] )
> 
> and it gets converted to this Verilog code:
> 
>   assign y_o = {5'h0, 5'h0};
> 
> 
> Attached is the full code for multiplier and unittest. The conversion
> code is part of cplxMult.py and will be initiated if the file is executed.
> 
> Am I doing something basic wrong that I get this result?

No, it's a bug both in VHDL and Verilog. The issue is that slicing an intbv
is typically used to "declare" it and the convertor didn't make the difference
with a cast of an expression.

I have now added a test that checks whether the intbv argument is a constant
or not, to have an appropriate conversion. I have pushed this to the
repository.

I see that the expression is now "preserved" by the convertor, but I have not
yet written a unit test that verifies correctness. A unit test would be welcome :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org

Re: [myhdl-list] Custom verilog include

[Günter D. <dan...@we...>]

Eric Jonas wrote:
> Is there an easy way to get something like a verilog `include into the code
> generated by myhdl ? I'm trying to use/synthesize some vendor-supplied code, and
> need the generated code to include/reference their primitives. 
> 

Have a look at the user-defined Verilog code section in connection with
the converter:

http://www.myhdl.org/doc/0.5.1/manual/conf-usage-custom.html

With the __verilog__ string you can add user defined Verilog code inside
the myhdl code.

Cheers,

Guenter

[myhdl-list] Custom verilog include

[Eric J. <jo...@mi...>]

Is there an easy way to get something like a verilog `include into the code
generated by myhdl ? I'm trying to use/synthesize some vendor-supplied code, and
need the generated code to include/reference their primitives. 

Thanks!

[myhdl-list] some conversion problem with concatenated intbvs

[Günter D. <dan...@we...>]

Hi,

With the new intbv.signed() function in the hg repository I tried to
implement a complex multiplier. To make it a bit more complicated than
necessary there is only one port for each input operand and one port for
the output. For each port the upper half of the bits are used for the
real part of the complex value and the lower half of the bits are for
the imaginary part.

The simulation of the multiplier works just fine, however, when I
convert it, the output is set to 0.

This is the MyHDL code I am using to create the output:

  @always_comb
  def add_sub_logic():
    y_o.next = concat( intbv(ac - bd)[WIDTH+1:], intbv(bc + ad)[WIDTH+1:] )

and it gets converted to this Verilog code:

  assign y_o = {5'h0, 5'h0};


Attached is the full code for multiplier and unittest. The conversion
code is part of cplxMult.py and will be initiated if the file is executed.

Am I doing something basic wrong that I get this result?

Thanks for any help.

Cheers,

Guenter

[myhdl-list] rel_0-6dev10 and code freeze

[Jan D. <ja...@ja...>]

I have just pushed the last 0.6 dev changes (support for
conversion of intbv.signed() and added the rel_0-6dev10 tag.

In principle, I don't plan any further code changes before
the 0.6 release. Only documentation files will still be updated.

Those who track development, please check that these latest
changes don't break anything in your code.

Those interested in intbv.signed() conversion, please check
that it works as expected.

I'll make a final pass on docs in the week starting Dec 8,
and I shoot for a release on Dec 15.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org