myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] intbv improvement?

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> I would find this addition to the intbv constructor helpful:
> 
> class intbv(object):
>     __slots__ = ('_val', '_min', '_max', '_nrbits')
>     
>     def __init__(self, val=None, min=None, max=None, _nrbits=0, 
> is_signed=False):
>         if _nrbits:
>             if (is_signed):
>                self._min = -1 << (_nrbits-1)
>                self._max = ~(-1 << (_nrbits-1))
>             else:
>               self._min = 0
>               self._max = 2**_nrbits

I infer that you want to use _nrbits as an end user also?
This is not how the type is set up. _nrbits is intended
to be a private parameter of the constructor for internal
use.

One of the goals of intbv is to get rid of unsigned/signed
thinking as much as possible, and push the use of fine-grained
range control as high-level alternative.
(I'm actually writing a paper about this, almost finished.)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

[myhdl-list] intbv improvement?

[Neal B. <ndb...@gm...>]

I would find this addition to the intbv constructor helpful:

class intbv(object):
    __slots__ = ('_val', '_min', '_max', '_nrbits')
    
    def __init__(self, val=None, min=None, max=None, _nrbits=0, 
is_signed=False):
        if _nrbits:
            if (is_signed):
               self._min = -1 << (_nrbits-1)
               self._max = ~(-1 << (_nrbits-1))
            else:
              self._min = 0
              self._max = 2**_nrbits
 

Re: [myhdl-list] AttributeError: '_ConvertFunctionVisitor' object has no attribute 'funcBuf'

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Translating to verilog produced the above error. 

Mm, it seems the convertor has difficulties when an ordinary
function calls another ordinary function. Should work, I know :-)

Before showing a workaround below, I notice that you're also
using function calls to calculate constants inside generator
code. An important trick with conversion (because it is so
limited) is too keep as much as possible outside of generator
code. If possible, calculate constants outside generators 
and pass them as parameters - this way the computation can be
arbitrarily complex, as the convertor only needs to convert code used
inside generators.

The following modified code seems to convert fine:

def sat_rnd (x, bits, outbits):
    y1 = x >> (bits-1)
    y2 = y1 + 1
    y3 = y2 >> 1
    if (y3 > (2**outbits-1)):
        return 2**outbits - 1
    elif (y3 < - (2**outbits)):
        return - (2**outbits)
    else:
        return y3
    


def Counter (count, clock, en, n, reset):
    @always (clock.posedge, reset.posedge)
    def cntLogic():
        if reset == 1:
            count.next = 0
        elif en:
            if count == n-1:
                count.next = 0
            else:
                count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, en, n, reset):
    def log2 (x):
        "positive only!"
        cnt = 0
        while (x != 0):
            x >>= 1
            cnt += 1
        return cnt-1

    m = log2(n)
    sumbits = m  + len (result)
    _sum = Signal (intbv(0)[sumbits:])
    p = len(result)


    
    @always (clock.posedge, reset.posedge)
    def accum_logic():
        if reset == 1:
            _sum.next = 0
            result.next = 0
        elif en:
            _sum.next = _sum + x
            if count == n-1:
                ##print 'count:', count, 'sum:', _sum
                result.next = sat_rnd (_sum, m, p)
                _sum.next = 0

    return accum_logic

def Decimator (clock, en, x, n, count, result, reset):
    cnt1 = Counter (count, clock, en, n, reset)
    acc1 = accum (x, result, count, clock, en, n, reset)
    return cnt1, acc1




-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] AttributeError: '_ConvertFunctionVisitor' object has no attribute 'funcBuf'

[Neal B. <ndb...@gm...>]

I'm still getting my head around this verilog stuff.  I think it's working 
now.

If I want to translate something to verilog, I need to remember to write 
verilog-ish versions of all the functions it uses.

It seems myhdl will attempt to translate ordinary functions, but this might 
or might not work and might or might not produce a useful result.  I'm not 
sure under what circumstances this is actually what you want.

This seems to be correct code:
def max_signed (bits):
    return ~(-1 << (bits-1))

def min_signed (bits):
    return (-1 << (bits-1))

def extrema_signed (bits):
    return min_signed (bits), max_signed (bits)

def sat_rnd (x, bits, outbits, output):
    @always_comb
    def sat_rnd_logic():
        y1 = x >> (bits-1)
        y2 = y1 + 1
        y3 = y2 >> 1
        if (y3 > max_signed (outbits)):
            output.next = max_signed (outbits)
        elif (y3 < min_signed (outbits)):
            output.next = min_signed (outbits)
        else:
            output.next = y3

    return sat_rnd_logic
    


def Counter (count, clock, en, n, reset):
    @always (clock.posedge, reset.posedge)
    def cntLogic():
        if reset == 1:
            count.next = 0
        elif en:
            if count == n-1:
                count.next = 0
            else:
                count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, en, log2_n, reset):
    n = 1 << log2_n
    sumbits = log2_n + len (result)
    _sum = Signal (intbv(0, *extrema_signed (sumbits)))

    _sat_result = Signal (intbv (0, *extrema_signed (len (result))))
    _sat_rnd = sat_rnd (_sum, log2_n, len (result), _sat_result)
    
    @always (clock.posedge, reset.posedge)
    def accum_logic():
        if reset == 1:
            _sum.next = 0
            result.next = 0
        elif en:
            _sum.next = _sum + x
            if count == n-1:
                ##print 'count:', count, 'sum:', _sum
                result.next = _sat_result
                #result.next = _sum >> log2_n
                _sum.next = 0
                
    return accum_logic, _sat_rnd

def Decimator (clock, en, x, log2_n, count, result, reset):
    cnt1 = Counter (count, clock, en, 1 << log2_n, reset)
    acc1 = accum (x, result, count, clock, en, log2_n, reset)
    return cnt1, acc1

def to_hex (val):
    _hexdigits = '0123456789abcdef'
    digits = (val._nrbits + 3)/4
    s = []
    for i in xrange (digits-1, -1, -1):
        s.append (_hexdigits[(int(val) >> (4*i)) & 0xf])
    return ''.join (s)

def log2 (x):
    cnt = 0
    while x > 0:
        x >>= 1
        cnt += 1
    return cnt-1

def testbench(cosim=False):
    HALF_PERIOD = delay(1)

    clock = Signal (bool(0))
    x = Signal (intbv(10, *extrema_signed (6)))
    reset = Signal (bool(1))
    count = Signal (intbv(0)[4:])
    result = Signal (intbv(0, *extrema_signed (8)))
    en = Signal (bool(0))
    n = 16
    log2_n = log2 (n)
    
    if (cosim):
        from co import Decimator_v
        dut = Decimator_v (clock, en, x, log2_n, count, result, reset)
    else:
        dut = Decimator (clock, en, x, log2_n, count, result, reset)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    
    @always(clock.posedge)
    def enGen():
        en.next = not en
        
    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            ##x.next = 1
            reset.next = 0
        
    result_fd = file ('result', 'w')
    count_fd = file ('count', 'w')
    reset_fd = file ('reset', 'w')
    x_fd = file ('x', 'w')
    en_fd = file ('en', 'w')
    
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'reset:', reset, 'en:', en, 'x:', x, 'count:', 
to_hex(count), 'result:', to_hex(result)
            print >> result_fd, to_hex (result)
            print >> count_fd, to_hex (count)
            print >> x_fd, to_hex (x)
            print >> reset_fd, to_hex (reset)
            print >> en_fd, to_hex (en)
            
    return clockGen, enGen, stimulus, monitor, dut


def main():
   
    tb = traceSignals (testbench)
    #tb = testbench()

    Simulation(tb).run(100)

def cosim():
    tb = testbench(cosim=True)
    Simulation (tb).run (100)

def verilog():
    HALF_PERIOD = delay(1)

    clock = Signal (bool(0))
    x = Signal (intbv(0, *extrema_signed (6)))
    reset = Signal (bool(1))
    count = Signal (intbv(0)[4:])
    result = Signal (intbv(0, *extrema_signed (8)))
    en = Signal (bool(0))
    n = 16
    log2_n = log2 (n)
    toVerilog (Decimator, clock, en, x, log2_n, count, result, reset)
 
    

[myhdl-list] AttributeError: '_ConvertFunctionVisitor' object has no attribute 'funcBuf'

[Neal B. <ndb...@gm...>]

Translating to verilog produced the above error.  This is basically the 
code.

def maxval (bits):
    return ~(-1 << (bits-1))

def minval (bits):
    return (-1 << (bits-1))

def sat_rnd (x, bits, outbits):
    y1 = x >> (bits-1)
    y2 = y1 + 1
    y3 = y2 >> 1
    if (y3 > maxval (outbits)):
        return maxval (outbits)
    elif (y3 < minval (outbits)):
        return minval (outbits)
    else:
        return y3
    


def Counter (count, clock, en, n, reset):
    @always (clock.posedge, reset.posedge)
    def cntLogic():
        if reset == 1:
            count.next = 0
        elif en:
            if count == n-1:
                count.next = 0
            else:
                count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, en, n, reset):
    def log2 (x):
        "positive only!"
        cnt = 0
        while (x != 0):
            x >>= 1
            cnt += 1
        return cnt-1

    sumbits = log2 (n) + len (result)
    _sum = Signal (intbv(0)[sumbits:])

    
    @always (clock.posedge, reset.posedge)
    def accum_logic():
        if reset == 1:
            _sum.next = 0
            result.next = 0
        elif en:
            _sum.next = _sum + x
            if count == n-1:
                ##print 'count:', count, 'sum:', _sum
                result.next = sat_rnd (_sum, log2 (n), len (result))
                _sum.next = 0

    return accum_logic

def Decimator (clock, en, x, n, count, result, reset):
    cnt1 = Counter (count, clock, en, n, reset)
    acc1 = accum (x, result, count, clock, en, n, reset)
    return cnt1, acc1

Traceback (most recent call last):
  File "test3.py", line 163, in <module>
    verilog()
  File "test3.py", line 150, in verilog
    toVerilog (Decimator, clock, en, x, n, count, result, reset)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 122, in __call__
    _convertGens(genlist, vfile)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 313, in _convertGens
    compiler.walk(ast, v)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 106, in walk
    walker.preorder(tree, visitor)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 63, in preorder
    self.dispatch(tree, *args) # XXX *args make sense?
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 841, in visitModule
    self.visit(stmt)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 1134, in visitFunction
    self.visit(node.code)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 989, in visitStmt
    self.visit(stmt)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 776, in visitIf
    self.mapToIf(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 823, in mapToIf
    self.visit(suite)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 989, in visitStmt
    self.visit(stmt)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 776, in visitIf
    self.mapToIf(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 823, in mapToIf
    self.visit(suite)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 989, in visitStmt
    self.visit(stmt)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 541, in visitAssign
    self.visit(node.expr)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 646, in visitCallFunc
    compiler.walk(node.ast, v)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 106, in walk
    walker.preorder(tree, visitor)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 63, in preorder
    self.dispatch(tree, *args) # XXX *args make sense?
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 841, in visitModule
    self.visit(stmt)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 1168, in visitFunction
    self.visit(node.code)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 989, in visitStmt
    self.visit(stmt)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 776, in visitIf
    self.mapToIf(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 820, in mapToIf
    self.visit(test)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 656, in visitCompare
    self.visit(code, context)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", 
line 645, in visitCallFunc
    v = Visitor(node.ast, self.funcBuf)
AttributeError: '_ConvertFunctionVisitor' object has no attribute 'funcBuf'

Re: [myhdl-list] Don't include `timescale 1ns/10ps into my module?

[Christopher F. <chr...@gm...>]

On Tue, Mar 3, 2009 at 2:48 PM, Jan Decaluwe <ja...@ja...> wrote:

> Neal Becker wrote:
> > When I convert my module to verilog with myhdl, it starts with:
> > `timescale 1ns/10ps
>


>
> This could be changed: the default could be not to include a timescale
> directive and only include it if the user sets the attribute.
> Feedback welcome.
>

 Yes, I like that option.  Default it is disabled and only enabled when the
user adds it via the attribute.

The default case would be that Verilog and VHDL are similiar, correct?

Re: [myhdl-list] Don't include `timescale 1ns/10ps into my module?

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> When I convert my module to verilog with myhdl, it starts with:
> `timescale 1ns/10ps
> 
> How do I avoid writing that?  I want to set this in the testbench and I 
> think it would be a problem to try to set it in the module as well (I'm a 
> verilog newb, so I might be misunderstanding something here).

It should not normally be a problem. Verilog understands the directive
on a per-module level and I think it's considered good practice
to set it in each module.

At some point, I introduced it because I needed it for some 
user-defined code to work properly.

I now see that it's not documented that you can actually set your
desired timescale using the toVerilog.timescale attribute. However,
it's not currently possible to disable it.

This could be changed: the default could be not to include a timescale
directive and only include it if the user sets the attribute.
Feedback welcome.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

[myhdl-list] Don't include `timescale 1ns/10ps into my module?

[Neal B. <ndb...@gm...>]

When I convert my module to verilog with myhdl, it starts with:
`timescale 1ns/10ps

How do I avoid writing that?  I want to set this in the testbench and I 
think it would be a problem to try to set it in the module as well (I'm a 
verilog newb, so I might be misunderstanding something here).

[myhdl-list] OFP Download Reminder

[<pra...@gm...>]

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            <link rel="File-List" href="file:///C:\DOCUME~1\V\LOCALS~1\Temp\msohtml1\03\clip_filelist.xml" /><!--[if gte mso 9]><xml>
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            <p align="justify">&nbsp;</p>
            </td>
        </tr>
    </tbody>
</table>

Re: [myhdl-list] cosimulation trouble

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Jan Decaluwe wrote:
> 
>> Neal Becker wrote:
>>> Now I'm moving on to trying cosim.  I have installed icarus, compiled
>>> myhdl.vpi.  When run with normal sim result is fine, but when run as
>>> cosim I get no error, but nothing happens (I have a counter and an
>>> accumulator - the
>>> count never increments and the accumulator output never changes).  Any
>>> ideas?  Any hints at how to troubleshoot this?
>> Typically, the situation where "nothing happens" is caused by
>> initialization issues. In particular, in Verilog everything starts at 'X'
>> by default, while in MyHDL, the start value is defined.
>>
>> In this case, I guess count starts at 'X', and as it is not explicitly
>> reset, it stays at 'X'. Also, no events are generated to the MyHDL side,
>> so count seems to keep its starting value.
>>
>> The solution is to use an explicit reset signal that brings the circuit
>> into a known state.
>>
>> At the RTL level and higher, the MyHDL convertor could in fact generate
>> initialization values with the Verilog declarations to bring the Verilog
>> code more in line with MyHDL at time 0. The only reason why this isn't
>> done it that at one point it was reported that some synthesis tools
>> don't support that (I think it was the tool from Altera). I'm interested
>> in hearing whether that's still the case.
>>
>> At the gate level, you would always need the reset signal though.
>>
>> Jan
>>
> 
> I'm confused here.  count is both in and out from 'Counter'.  Counter is 
> instantiated in 'Decimator', which is instantiated in the top-level of 
> 'cosim'.  There, count is initialized to 0.  

When you do cosimulation, two simulators (MyHDL and Verilog) are running
in lockstep. The interface ports exist in the two simulators and their
values are kept consistent through events between the two simulators.

The problem you are seeing is probably due to 'count' in the *Verilog*
simulator. If it stays as X, nothing happens to 'count' in the MyHDL
simulator.

> What would I need to change?  

Consider a template with reset for RTL-level modeling:

http://www.myhdl.org/doc/0.6/manual/modeling.html#sequential-logic

> Why is it that in 'Counter' myhdl flags 'count' as output rather than inout?

An output that is used internally is not the same as a true inout. In Verilog,
it is not necessary to declare an inout in this case, but in VHDL it is.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] cosimulation trouble

[Neal B. <ndb...@gm...>]

I seem to have it working now.  I have restructured things a bit.  Perhaps 
someone might comment on whether the style here is good/reasonable.

from myhdl import Signal, always, intbv, Simulation, delay, toVerilog, 
traceSignals, always_comb, instance



def Counter (count, clock, n, reset):
    @always (clock.posedge)
    def cntLogic():
        if reset == 1:
            count.next = 0
        elif count == n-1:
            count.next = 0
        else:
            count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, n, reset):
    _sum = Signal (intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        if reset == 1:
            _sum.next = 0
        else:
            _sum.next = _sum + x
            if count == n-1:
                ##print 'count:', count, 'sum:', _sum
                result.next = _sum
                _sum.next = 0

    return accum_logic

def Decimator (clock, x, n, count, result, reset):
    cnt1 = Counter (count, clock, n, reset)
    acc1 = accum (x, result, count, clock, n, reset)
    return cnt1, acc1

def testbench(cosim=False):
    HALF_PERIOD = delay(1)

    clock = Signal (bool(0))
    x = Signal (intbv(0)[4:])
    reset = Signal (bool(1))
    count = Signal (intbv(0)[4:])
    result = Signal (intbv(0)[8:])
    n = 16
    
    if (cosim):
        from co import Decimator_v
        dut = Decimator_v (clock, x, n, count, result, reset)
    else:
        dut = Decimator (clock, x, n, count, result, reset)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    
    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            x.next = 1
            reset.next = 0
        
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'reset:', reset, 'x:', x, 'count:', count, 'result:', 
result

    return clockGen, stimulus, monitor, dut


def main():
    tb = traceSignals (testbench)

    Simulation(tb).run(50)

def cosim():
    tb = testbench(cosim=True)
    Simulation (tb).run (50)

mode = 'sim'
#mode = 'test'
#mode = 'cosim'
#mode = 'verilog'

if __name__ == '__main__':
     if mode == "sim":
        main()
    elif mode == "cosim":
        cosim()

co.py:
from myhdl import *
from test3 import Decimator
import os

def Decimator_v(clock, x, n, count, result, reset):
    toVerilog(Decimator, clock, x, n, count, result, reset)
    cmd = "iverilog -o Decimator tb_Decimator.v Decimator.v"
    os.system (cmd)
    
    return Cosimulation("vvp -v -m ./myhdl.vpi Decimator", **locals())

Re: [myhdl-list] cosimulation trouble

[Neal B. <ndb...@gm...>]

Jan Decaluwe wrote:

> Neal Becker wrote:
>> Now I'm moving on to trying cosim.  I have installed icarus, compiled
>> myhdl.vpi.  When run with normal sim result is fine, but when run as
>> cosim I get no error, but nothing happens (I have a counter and an
>> accumulator - the
>> count never increments and the accumulator output never changes).  Any
>> ideas?  Any hints at how to troubleshoot this?
> 
> Typically, the situation where "nothing happens" is caused by
> initialization issues. In particular, in Verilog everything starts at 'X'
> by default, while in MyHDL, the start value is defined.
> 
> In this case, I guess count starts at 'X', and as it is not explicitly
> reset, it stays at 'X'. Also, no events are generated to the MyHDL side,
> so count seems to keep its starting value.
> 
> The solution is to use an explicit reset signal that brings the circuit
> into a known state.
> 
> At the RTL level and higher, the MyHDL convertor could in fact generate
> initialization values with the Verilog declarations to bring the Verilog
> code more in line with MyHDL at time 0. The only reason why this isn't
> done it that at one point it was reported that some synthesis tools
> don't support that (I think it was the tool from Altera). I'm interested
> in hearing whether that's still the case.
> 
> At the gate level, you would always need the reset signal though.
> 
> Jan
> 

I'm confused here.  count is both in and out from 'Counter'.  Counter is 
instantiated in 'Decimator', which is instantiated in the top-level of 
'cosim'.  There, count is initialized to 0.  What would I need to change?  
Why is it that in 'Counter' myhdl flags 'count' as output rather than inout?

Re: [myhdl-list] cosimulation trouble

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Now I'm moving on to trying cosim.  I have installed icarus, compiled 
> myhdl.vpi.  When run with normal sim result is fine, but when run as cosim I 
> get no error, but nothing happens (I have a counter and an accumulator - the 
> count never increments and the accumulator output never changes).  Any 
> ideas?  Any hints at how to troubleshoot this?

Typically, the situation where "nothing happens" is caused by initialization
issues. In particular, in Verilog everything starts at 'X' by default, while
in MyHDL, the start value is defined.

In this case, I guess count starts at 'X', and as it is not explicitly
reset, it stays at 'X'. Also, no events are generated to the MyHDL side,
so count seems to keep its starting value.

The solution is to use an explicit reset signal that brings the circuit
into a known state.

At the RTL level and higher, the MyHDL convertor could in fact generate
initialization values with the Verilog declarations to bring the Verilog
code more in line with MyHDL at time 0. The only reason why this isn't
done it that at one point it was reported that some synthesis tools
don't support that (I think it was the tool from Altera). I'm interested
in hearing whether that's still the case.

At the gate level, you would always need the reset signal though.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] assertion error in toVerilog

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Traceback (most recent call last):
>   File "test3.py", line 65, in <module>
>     tb = toVerilog (testbench)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", line
> 115, in __call__
>     genlist = _analyzeGens(arglist, h.absnames)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 160, in _analyzeGens
>     compiler.walk(ast, v)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 106, in walk
>     walker.preorder(tree, visitor)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 63, in preorder
>     self.dispatch(tree, *args) # XXX *args make sense?
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 939, in visitModule
>     self.visit(node.node)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
>     self.dispatch(child, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 998, in visitFunction
>     self.visit(node.code)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
>     self.dispatch(child, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 486, in visitAugAssign
>     self.visit(node.node, _access.INOUT)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 632, in visitGetattr
>     self.visit(node.expr, *args)
>   File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
>     return meth(node, *args)
>   File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
> 743, in visitName
>     raise AssertionError
> AssertionError
> 
> Here is code:
> from myhdl import Signal, always, intbv, Simulation, delay, toVerilog,
> traceSignals, always_comb, instance
> 
> 
> 
> def Counter (count, clock, n):
>     @always (clock.posedge)
>     def cntLogic():
>         if count == n-1:
>             count.next = 0
>         else:
>             count.next = count + 1
> 
>         print "count:", count
>     return cntLogic
> 
> def accum (x, result, count, clock, n):
>     _sum = Signal (intbv(0)[8:])
>     
>     @always (clock.posedge)
>     def accum_logic():
>         _sum.next += x
>         if count == n-1:
>             ##print 'count:', count, 'sum:', _sum
>             result.next = _sum
>             _sum.next = 0
> 
>     return accum_logic
> 
> def Decimator (clock, x, n, count, result):
>     cnt1 = Counter (count, clock, n)
>     acc1 = accum (x, result, count, clock, n)
>     return cnt1, acc1
> 
> def testbench():
>     HALF_PERIOD = delay(1)
> 
>     n = 16
>     x = Signal (intbv(0)[4:])
>     #clock = Signal()
>     clock = Signal (intbv(0)[1:])
>     result = Signal(intbv()[8:])
>     count = Signal (intbv(0)[4:])
>     
>     decimator1 = Decimator (clock, x, n, count, result)
>     
>     @always(HALF_PERIOD)
>     def clockGen():
>         clock.next = not clock
> 
>     @instance
>     def stimulus():
>         while (1):
>             yield clock.posedge
>             x.next = 1
>         
>     @instance
>     def monitor():
>         while 1:
>             yield clock.posedge
>             print 'x:', x, 'count:', count, 'result:', result
> 
>     return clockGen, stimulus, decimator1, monitor
> 
> 
> tb = toVerilog (testbench)
> 
> def main():
>     Simulation(tb).run(50)
> 
> if __name__ == "__main__":
>     main()
> 
> Any ideas?

Yes:
      _sum.next += x

has no equivalent in VHDL or Verilog, as it is equivalent to:

     _sum.next = _sum.next + x

In other words, it updates the future value by adding to the future value.
(I'm not sure it's useful in MyHDL either.)

So it cannot be converted. However, this problem should be indicated with
a proper exception and error message, and not with an assertion, so the
AssertionError is a bug.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] Adding information to asserts

[Jan D. <ja...@ja...>]

Christopher Felton wrote:
> In general as MyHDL is more widely used we come across asserts that can 
> be enhanced.  The enhancements are usually printing out more information 
> about the error.
> 
> What is the correct pythonic method to add more information (print info) 
> to an assertion?  I assume you do not want to simply add prints, then 
> the prints occur before the stack dump.  

First, any assert that escapes to the user should be considered a serious
bug (and should be reported as such).

The reason why I sometimes use AssertionError in the MyHDL code base,
is to save implementation time: sometimes there is a point in the code
which would be clearly wrong, but I don't immediately see how one would
get there or what the error message should be. To me as a developer,
there is a slight advantage of raising an assertion myself, instead
of letting Python do it further down the road - but to a user, it
is a bug in any case.

The proper way to handle errors is to raise a clear exception of the
correct type, that includes a message of what is wrong.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] assertion error in toVerilog

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Christopher Felton wrote:
> 
>>>    @always (clock.posedge)
>>>    def accum_logic():
>>>        _sum.next += x
>>>        if count == n-1:
>>>            ##print 'count:', count, 'sum:', _sum
>>>            result.next = _sum
>>>            _sum.next = 0
>>>
>>>    return accum_logic
>>>
>>> Any ideas?
>>
>> The problem is the _sum.next += x
>>
>> Change to _sum.next = _sum + x
>>
>> Attached is the code that I successfully converted.
> Thank you so much for your help!
> 
> 2 questions:
> 1.
>  python test3.py
> ** ToVerilogWarning: Output port is read internally: count
> 
> What does this mean and should I worry?  Any way to tell what lines of code 
> this is coming from?

It means that count is an output port that is not only written,
but also read internally.

In Verilog and MyHDL, this is allowed without problems, although some
may argue it's not very clean. In VHDL, you cannot do this unless the output
port is declared as "inout", which some designers may want to avoid. Hence
the warning, so you know.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

[myhdl-list] cosimulation trouble

[Neal B. <ndb...@gm...>]

Now I'm moving on to trying cosim.  I have installed icarus, compiled 
myhdl.vpi.  When run with normal sim result is fine, but when run as cosim I 
get no error, but nothing happens (I have a counter and an accumulator - the 
count never increments and the accumulator output never changes).  Any 
ideas?  Any hints at how to troubleshoot this?

Here is the code:
from myhdl import Signal, always, intbv, Simulation, delay, toVerilog, 
traceSignals, always_comb, instance



def Counter (count, clock, n):
    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

#        print "count:", count
    return cntLogic

def accum (x, result, count, clock, n):
    _sum = Signal (intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        _sum.next = _sum + x
        if count == n-1:
            ##print 'count:', count, 'sum:', _sum
            result.next = _sum
            _sum.next = 0

    return accum_logic

def Decimator (clock, x, n, count, result):
    cnt1 = Counter (count, clock, n)
    acc1 = accum (x, result, count, clock, n)
    return cnt1, acc1

def testbench(dut, clock, count, x, result):
    HALF_PERIOD = delay(1)

    
#    decimator1 = Decimator (clock, x, n, count, result)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            x.next = 1
        
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'x:', x, 'count:', count, 'result:', result

    return clockGen, stimulus, monitor, dut


def main():
    n = 16
    x = Signal (intbv(0)[4:])
    #clock = Signal()
    clock = Signal (intbv(0)[1:])
    result = Signal(intbv(0)[8:])
    count = Signal (intbv(0)[4:])
    dut = Decimator (clock, x, n, count, result)
    tb = traceSignals (testbench, dut, clock, count, x, result)

    Simulation(tb).run(50)

def cosim():
    n = 16
    x = Signal (intbv(0)[4:])
    #clock = Signal()
    clock = Signal (intbv(0)[1:])
    result = Signal(intbv(0)[8:])
    count = Signal (intbv(0)[4:])
    from co import Decimator_v
    dut = Decimator_v (clock, x, n, count, result)

    tb = testbench (dut, clock, count, x, result)
    Simulation (tb).run (50)
#mode = 'sim'
#mode = 'test'
mode = 'cosim'

if __name__ == '__main__':
    if (mode == 'verilog'):
         n = 16 
         x      = Signal(intbv(0)[4:]) 
         clock  = Signal(False) 
         result = Signal(intbv(0)[8:]) 
         count  = Signal(intbv(0)[4:]) 

         #dut = Decimator (clock, x, n, count, result) 
         toVerilog(Decimator, clock, x, n, count, result) 
    elif mode == "test":
        toVerilog (testbench)
    elif mode == "sim":
        main()
    elif mode == "cosim":
        cosim()

And here is co.py:
from myhdl import *
from test3 import Decimator
import os

def Decimator_v(clock, x, n, count, result):
    toVerilog(Decimator, clock, x, n, count, result)
    cmd = "iverilog -o Decimator tb_Decimator.v Decimator.v"
    os.system (cmd)
    
    return Cosimulation("vvp -v -m ./myhdl.vpi Decimator", **locals())

Here's what I get when mode = 'sim':
python test3.py
x: 0 count: 0 result: 0
x: 1 count: 1 result: 0
x: 1 count: 2 result: 0
x: 1 count: 3 result: 0
x: 1 count: 4 result: 0
x: 1 count: 5 result: 0
x: 1 count: 6 result: 0
x: 1 count: 7 result: 0
x: 1 count: 8 result: 0
x: 1 count: 9 result: 0
x: 1 count: 10 result: 0
x: 1 count: 11 result: 0
x: 1 count: 12 result: 0
x: 1 count: 13 result: 0
x: 1 count: 14 result: 0
x: 1 count: 15 result: 0
x: 1 count: 0 result: 14
x: 1 count: 1 result: 14
x: 1 count: 2 result: 14
x: 1 count: 3 result: 14
x: 1 count: 4 result: 14
x: 1 count: 5 result: 14
x: 1 count: 6 result: 14
x: 1 count: 7 result: 14
x: 1 count: 8 result: 14
<class 'myhdl._SuspendSimulation'>: Simulated 50 timesteps

For mode = 'cosim':

 python test3.py
** ToVerilogWarning: Output port is read internally: count
Compiling VVP ...
 ... VVP file version 0.9.devel (s20080905-418-g1c17412)
Compile cleanup...
 ... Linking
 ... Removing symbol tables
 ... Compiletf functions
 ...       10 functors (net_fun pool=0 bytes)
                  0 logic
                  0 bufif
                  0 resolv
                  9 signals
 ...       42 opcodes (24576 bytes)
 ...        9 nets
 ...       10 vvp_nets (1048560 bytes)
 ...        0 arrays (0 words)
 ...        0 memories
                  0 logic (0 words)
                  0 real (0 words)
 ...        4 scopes
 ... 0.001 seconds, 36420.0/3340.0/1296.0 KBytes size/rss/shared
Running ...
x: 0 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
x: 1 count: 0 result: 0
<class 'myhdl._SuspendSimulation'>: Simulated 50 timesteps
 ... 0.002 seconds, 36420.0/3496.0/1448.0 KBytes size/rss/shared
Event counts:
         203 time steps (pool=146)
         128 thread schedule events
          55 assign events
             ...assign(vec4) pool=9362
             ...assign(vec8) pool=204
             ...assign(real) pool=256
             ...assign(word) pool=128
         353 other events (pool=4096)

[myhdl-list] Adding information to asserts

[Christopher F. <chr...@gm...>]

In general as MyHDL is more widely used we come across asserts that can be
enhanced.  The enhancements are usually printing out more information about
the error.
What is the correct pythonic method to add more information (print info) to
an assertion?  I assume you do not want to simply add prints, then the
prints occur before the stack dump.

Is there an example in the MyHDL base that would serve as a good template?
 Is there standard formats and info that is commonly used in python?

Thanks

Re: [myhdl-list] assertion error in toVerilog

[Christopher F. <chr...@gm...>]

>
>
> 2 questions:
> 1.
>  python test3.py
> ** ToVerilogWarning: Output port is read internally: count
>
> What does this mean and should I worry?  Any way to tell what lines of code
> this is coming from?


I did not scrutinize the Verilog output.  For this exercise I was content
when the converter ran without error.  I do not know what the error is with
out greping for the error string.


>
>
> 2.
> I noticed you changed:
>     @always (clock.posedge)
>    def accum_logic():
>         _sum.next = _sum + x
>         if count == n-1:
>            ##print 'count:', count, 'sum:', _sum
>            result.next = _sum
>            _sum.next = 0
>
>   return accum_logic
>
> to
>
>   @always (clock.posedge)
>     def accum_logic():
>          _sum.next = _sum + x
>         if count == n-1:
>             #result.next = _sum
>             _sum.next = 0
>
>     @always (clock.posedge)
>     def rtl():
>         if count == n-1:
>             result.next = _sum
>
>     return accum_logic, rtl
>
> Any significance to this change?
>
>
Sorry, the changes are not significant.  I was just testing a couple
different things.  I randomly tried a couple things before analyzing the
signal that was being asserted (printing the sig in _analyze.py).  I never
put the code back to the original structure.  Before modifying _analyze.py
to print more info I was trying to get some more information.

Re: [myhdl-list] assertion error in toVerilog

[Neal B. <ndb...@gm...>]

Christopher Felton wrote:

>>
>>    @always (clock.posedge)
>>    def accum_logic():
>>        _sum.next += x
>>        if count == n-1:
>>            ##print 'count:', count, 'sum:', _sum
>>            result.next = _sum
>>            _sum.next = 0
>>
>>    return accum_logic
>>
>> Any ideas?
> 
> 
> The problem is the _sum.next += x
> 
> Change to _sum.next = _sum + x
> 
> Attached is the code that I successfully converted.
Thank you so much for your help!

2 questions:
1.
 python test3.py
** ToVerilogWarning: Output port is read internally: count

What does this mean and should I worry?  Any way to tell what lines of code 
this is coming from?

2.
I noticed you changed:
    @always (clock.posedge)
    def accum_logic():
        _sum.next = _sum + x
        if count == n-1:
            ##print 'count:', count, 'sum:', _sum
            result.next = _sum
            _sum.next = 0

   return accum_logic

to

   @always (clock.posedge) 
     def accum_logic(): 
         _sum.next = _sum + x 
         if count == n-1: 
             #result.next = _sum 
             _sum.next = 0 
 
     @always (clock.posedge) 
     def rtl(): 
         if count == n-1: 
             result.next = _sum 
             
     return accum_logic, rtl 
 
Any significance to this change?

Re: [myhdl-list] assertion error in toVerilog

[Christopher F. <chr...@gm...>]

from myhdl import *

def Counter (count, clock, n):
    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

    return cntLogic

def accum (x, result, count, clock, n):
    _sum = Signal(intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        _sum.next = _sum + x
        if count == n-1:
            #result.next = _sum
            _sum.next = 0

    @always (clock.posedge)
    def rtl():
        if count == n-1:
            result.next = _sum
            
    return accum_logic, rtl

def Decimator (clock, x, n, count, result):
    cnt1 = Counter(count, clock, n)
    acc1 = accum(x, result, count, clock, n)
    return cnt1, acc1

if __name__ == '__main__':
    n = 16
    x      = Signal(intbv(0)[4:])
    clock  = Signal(False)
    result = Signal(intbv(0)[8:])
    count  = Signal(intbv(0)[4:])
    
    #dut = Decimator (clock, x, n, count, result)
    toVerilog(Decimator, clock, x, n, count, result)

Re: [myhdl-list] assertion error in toVerilog

[Christopher F. <chr...@gm...>]

>
> tb = toVerilog (testbench)
>
> def main():
>    Simulation(tb).run(50)
>
> if __name__ == "__main__":
>    main()
>
> Any ideas?
>
>
Not sure if this is your specific issue, you may want to try and only
convert the design to Verilog.  Converting testbenches is a newer feature of
the latest release.  Below is an snippet of an example only converting the
design and not the testbench.  There are a bunch of examples in the cookbook
and the user project area.

    #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    # Signals
    clk = Signal(False)
    rst = Signal(False)

    x = Signal(intbv(0, min=-L, max=L))
    y = Signal(intbv(0, min=minV, max=maxV))

    dvi = Signal(True)
    dvo = Signal(False)

    xcnt  = Signal(0)
    N_CLK = 0

    #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    # Instantiate MyHDL simulation and coversion functions
    if run == 'trace':
        dut = traceSignals(cic, clk, rst, x, dvi, y, dvo, M, D, R)
    elif run == 'ver':
        toVerilog(cic, clk, rst, x, dvi, y, dvo, M, D, R)
        return None
    elif run == 'vhd':
        toVHDL(cic, clk, rst, x, dvi, y, dvo, M, D, R)
        return None
    else:
        dut = cic(clk, rst, x, dvi, y, dvo, M, D, R)

Re: [myhdl-list] assertion error in toVerilog

[Neal B. <ndb...@gm...>]

It seems putting:
_anaylyze.py:743
               print access
                raise AssertionError

reveals:
INOUT

[myhdl-list] assertion error in toVerilog

[Neal B. <ndb...@gm...>]

Traceback (most recent call last):
  File "test3.py", line 65, in <module>
    tb = toVerilog (testbench)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_toVerilog.py", line
115, in __call__
    genlist = _analyzeGens(arglist, h.absnames)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
160, in _analyzeGens
    compiler.walk(ast, v)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 106, in walk
    walker.preorder(tree, visitor)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 63, in preorder
    self.dispatch(tree, *args) # XXX *args make sense?
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
939, in visitModule
    self.visit(node.node)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
    self.dispatch(child, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
998, in visitFunction
    self.visit(node.code)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 40, in default
    self.dispatch(child, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
486, in visitAugAssign
    self.visit(node.node, _access.INOUT)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
632, in visitGetattr
    self.visit(node.expr, *args)
  File "/usr/lib64/python2.5/compiler/visitor.py", line 57, in dispatch
    return meth(node, *args)
  File "/usr/lib/python2.5/site-packages/myhdl/conversion/_analyze.py", line
743, in visitName
    raise AssertionError
AssertionError

Here is code:
from myhdl import Signal, always, intbv, Simulation, delay, toVerilog,
traceSignals, always_comb, instance



def Counter (count, clock, n):
    @always (clock.posedge)
    def cntLogic():
        if count == n-1:
            count.next = 0
        else:
            count.next = count + 1

        print "count:", count
    return cntLogic

def accum (x, result, count, clock, n):
    _sum = Signal (intbv(0)[8:])
    
    @always (clock.posedge)
    def accum_logic():
        _sum.next += x
        if count == n-1:
            ##print 'count:', count, 'sum:', _sum
            result.next = _sum
            _sum.next = 0

    return accum_logic

def Decimator (clock, x, n, count, result):
    cnt1 = Counter (count, clock, n)
    acc1 = accum (x, result, count, clock, n)
    return cnt1, acc1

def testbench():
    HALF_PERIOD = delay(1)

    n = 16
    x = Signal (intbv(0)[4:])
    #clock = Signal()
    clock = Signal (intbv(0)[1:])
    result = Signal(intbv()[8:])
    count = Signal (intbv(0)[4:])
    
    decimator1 = Decimator (clock, x, n, count, result)
    
    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    @instance
    def stimulus():
        while (1):
            yield clock.posedge
            x.next = 1
        
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            print 'x:', x, 'count:', count, 'result:', result

    return clockGen, stimulus, decimator1, monitor


tb = toVerilog (testbench)

def main():
    Simulation(tb).run(50)

if __name__ == "__main__":
    main()

Any ideas?

Re: [myhdl-list] [newb] modelling question

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> Simple question.  Model an accumulator.  The accumulator has state 
> (call it 'sum').
> 
> Most examples are an RTL style.  My imitation of this style might be:
> 
> 
> 
> def accum (x, result, _sum, count, clock, n): @always (clock.posedge)
>  def accum_logic(x): _sum.next += x if count == n-1: result.next = 
> _sum _sum.next = 0
> 
> return accum_logic
> 
> _sum is an internal variable.  Does it need to be one of the 
> parameters passed to accum, as I showed above?

No. (Also, it is more precise to qualify _sum as an internal signal).

> Perhaps this could be: def accum (x, result, count, clock, n):
> 
> _sum = Signal (0)
> 
> @always (clock.posedge) def accum_logic(x): _sum.next += x if count 
> == n-1: result.next = _sum _sum.next = 0
> 
> return accum_logic

Yes.

> What if I prefer object oriented style?  The manual mentions this 
> (the fifo examples).  I wonder if this style will work properly with 
> the rest of myhdl? For example, there are some functions that 'infer'
>  inputs and outputs.  Does this work if I use this object-oriented 
> style?  There must be some constraints.

Ok. Like with any HDL, the first question is: what is the code intended
for? Pure modeling or synthesis? And in the case of MyHDL, a further
one: even if not for synthesis, should it be convertible to Verilog
or VHDL?

For pure modeling, MyHDL is intended to be fully general. You can create
generators and signals in any way you want, including object-oriented
styles. Just give the Simulation object a set of generators and it
should work as expected.

For convertibility (which encompasses synthesizability) the situation
is completely different and the constraints are significant. However, I
believe the convertible subset is well documented:
http://www.myhdl.org/doc/0.6/manual/conversion.html#the-convertible-subset

Finally, a word about the decorators instance, always and always_comb.
They are just convenient ways to create generators.  Although I haven't
tried it, the first two are fairly generic and I expect they can be
used in a variety of styles. The one that extracts inputs and outputs
that you refer to is always_comb. This one is more specialized
and assumes plain signal names to be visible in the code.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org