myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] MyHDL logic synthesis

[Jan D. <ja...@ja...>]

Newell Jensen wrote:

> So in the end....if I am going to make optimisations and go through the 
> trouble of fine tunning things hopefully there is a direct mapping in 
> the conversion.

There is, for working code.

> Just to see if this was so I went and tried to code up 
> the second example here in MyHDL.  I got it to convert fine, but what I 
> got fails during synthesis for Xilinx ISE 10.1 (service pack is the 
> latest as well).  This is my myhdl module and following it is the 
> conversion:

Newell, here's a golden advice for using conversion.

    http://www.myhdl.org/doc/0.6/manual/conversion.html#simulate-first

Until you are very experienced with MyHDL and conversion, please
simulate first. I agree that the conversion could do a better job of
catching common errors, but due to the nature of Python, it will
never do as good a job as a simulation. Unless simulation works,
all bets are off for the meaningfulness of conversion.

Below you are doing signal assignment on variables. You would get
a run-time error in simulation immediately.

Unlike Verilog, MyHDL makes a distinction between signals and variables.

Signals are used for communication between generators:
    http://www.myhdl.org/doc/0.6/manual/intro.html#signals-ports-and-concurrency

However, you can also use them in a single generator just to get their
parallel semantics, as your example suggests. But you still have to define
them outside the generator as usual. Alternatively, you can use variables
but then you have to control the order carefully.

For example, using your original example:

>     @always(clk.posedge)
>     def logic():
>         XPower1 = intbv(min=0, max=256)
>         XPower2 = intbv(min=0, max=256)
>         X1 = intbv(min=0, max=256)
>         X2 = intbv(min=0, max=256)
>         # Pipeline stage one
>         X1.next = X
>         XPower1.next = X
>         # Pipeline stage two
>         X2.next = X1
>         XPower2.next = XPower1 * X1
>         # Pipeline stage three
>         XPower.next = XPower2 * X2
>            
>     return logic
>    

With signal semantics:

    XPower1 = Signal(intbv(min=0, max=256))
    XPower2 = Signal(intbv(min=0, max=256))
    X1 = Signal(intbv(min=0, max=256))
    X2 = Signal(intbv(min=0, max=256))
 
    @always(clk.posedge)
    def logic():
        # Pipeline stage one
        X1.next = X
        XPower1.next = X        
        # Pipeline stage two
        X2.next = X1
        XPower2.next = XPower1 * X1
        # Pipeline stage three
        XPower.next = XPower2 * X2

With variable semantics:

    @always(clk.posedge)
    def logic():
        XPower1 = intbv(min=0, max=256)
        XPower2 = intbv(min=0, max=256)
        X1 = intbv(min=0, max=256)
        X2 = intbv(min=0, max=256)
        # Pipeline stage three
        XPower[:] = XPower2 * X2
        # Pipeline stage two
        X2[:] = X1
        XPower2[:]= XPower1 * X1
         # Pipeline stage one
        X1[:] = X
        XPower1[:] = X        
    

Both case should simulate, convert, and sythesize similarly.
(Interesting test!)

Jan
      

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as an HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDL logic synthesis

[Newell J. <pil...@gm...>]

On Mon, Mar 23, 2009 at 4:58 AM, Jan Decaluwe <ja...@ja...> wrote:

> Newell Jensen wrote:
> > Jan,
> >
> > Have you ever thought of giving MyHDL synthesis capabilities?
>
> No.
>
> Synthesis, the way I define it, would be a formidable task, certainly
> beyond my capabilities as an open-source developer.
>
> In addition to powerful HDL inference capabilites and logic minimization,
> my definition of synthesis includes timing-driven optimization with an
> integrated timing analyzer and powerful technology mapping, ideally
> including placement info from an integrated P&R tool.
>
> Morever, what would be the value proposition? Today I get these tools
> basically for free from Xilinx and Altera for their architecture.
>
>  > Icarus Verilog can synthesis designs and personally, I would find it a
> huge
> > advantage to not have to go the MyHDL --> Verilog route as there are
> > many things that are not convertable such as delays etc.
>
> I respect Stephen Williams very much and the value of Icarus the simulator
> if very clear to me, including its tremendous value to the MyHDL project.
> However, I don't see this for Icarus the synthesis tool.
> I don't believe it matches my definition of a synthesis tool. It's kind of
> hard to judge, as there is virtually no documentation that I can find,
> but I'm pretty sure we would have heard about it otherwise.
>
> So I suspect that after Icarus "synthesis" some other tool still has
> to perform some tasks (e.g. timing optimization) that I consider part
> of synthesis. In other words, it probably gives you an entry point
> at a somewhat lower level than Verilog RTL, in a tool flow that you
> have to run anyway, and which is basically free anyway.
> Again, what's the point?


There are a couple of points.

                                   As an example, consider the following
piece of
code that would most likely be used in a software implementation for finding
the
third power of X. Note that the term “software” here refers to code that is
targeted
at a set of procedural instructions that will be executed on a
microprocessor.
     XPower = 1;
     for (i=0;i < 3; i++)
        XPower = X * XPower;
Note that the above code is an iterative algorithm. The same variables and
addresses are accessed until the computation is complete. There is no use
for par-
allelism because a microprocessor only executes one instruction at a time
(for the
purpose of argument, just consider a single core processor). A similar
implemen-
tation can be created in hardware. Consider the following Verilog
implementation
of the same algorithm (output scaling not considered):
     module power3(
        output [7:0]      XPower,
        output            finished,
        input [7:0]       X,
        input             clk, start); // the duration of start is a
                                                single clock
        reg      [7:0] ncount;
        reg      [7:0] XPower;
        assign finished = (ncount == 0);
        always@(posedge clk)
           if(start) begin
              XPower <= X;
              ncount <= 2;
           end

           else if(!finished) begin
              ncount <= ncount - 1;
              XPower <= XPower * X;
           end
     endmodule
In the above example, the same register and computational resources are
reused
until the computation is finished as shown in Figure 1.1.
     With this type of iterative implementation, no new computations can
begin
until the previous computation has completed. This iterative scheme is very
similar to a software implementation. Also note that certain handshaking
signals
are required to indicate the beginning and completion of a computation. An
external module must also use the handshaking to pass new data to the module
and receive a completed calculation. The performance of this implementation
is
     Throughput 1⁄4 8/3, or 2.7 bits/clock
     Latency 1⁄4 3 clocks
     Timing 1⁄4 One multiplier delay in the critical path
Contrast this with a pipelined version of the same algorithm:
     module power3(
        output reg [7:0] XPower,
        input                  clk,
        input         [7:0] X
        );
        reg           [7:0] XPower1, XPower2;
        reg           [7:0] X1, X2;
        always @(posedge clk) begin
           // Pipeline stage 1
           X1        <= X;
           XPower1 <= X;
           // Pipeline stage 2
           X2        <= X1;
           XPower2 <= XPower1 * X1;
           // Pipeline stage 3
           XPower <= XPower2 * X2;
        end
     endmodule

In the above implementation, the value of X is passed to both pipeline
stages
where independent resources compute the corresponding multiply operation.
Note
that while X is being used to calculate the final power of 3 in the second
pipeline
stage, the next value of X can be sent to the first pipeline stage as shown
in
Figure 1.2.
     Both the final calculation of X3 (XPower3 resources) and the first
calculation
of the next value of X (XPower2 resources) occur simultaneously. The
perform-
ance of this design is
     Throughput 1⁄4 8/1, or 8 bits/clock
     Latency 1⁄4 3 clocks
     Timing 1⁄4 One multiplier delay in the critical path
The throughput performance increased by a factor of 3 over the iterative
implementation. In general, if an algorithm requiring n iterative loops is
“unrolled,” the pipelined implementation will exhibit a throughput
performance
increase of a factor of n. There was no penalty in terms of latency as the
pipelined
implementation still required 3 clocks to propagate the final computation.
Like-
wise, there was no timing penalty as the critical path still contained only
one
multiplier.

So in the end....if I am going to make optimisations and go through the
trouble of fine tunning things hopefully there is a direct mapping in the
conversion.  Just to see if this was so I went and tried to code up the
second example here in MyHDL.  I got it to convert fine, but what I got
fails during synthesis for Xilinx ISE 10.1 (service pack is the latest as
well).  This is my myhdl module and following it is the conversion:

from myhdl import *

def power3(
    XPower,
    X,
    clk):


    @always(clk.posedge)
    def logic():
        XPower1 = intbv(min=0, max=256)
        XPower2 = intbv(min=0, max=256)
        X1 = intbv(min=0, max=256)
        X2 = intbv(min=0, max=256)
        # Pipeline stage one
        X1.next = X
        XPower1.next = X
        # Pipeline stage two
        X2.next = X1
        XPower2.next = XPower1 * X1
        # Pipeline stage three
        XPower.next = XPower2 * X2

    return logic


def convert():

    XPower, X = [Signal(intbv(0)[8:]) for i in range(2)]
    clk = Signal(bool(0))

    toVerilog(power3, XPower, X, clk)

convert()

#############################################
// File: power3.v
// Generated by MyHDL 0.6
// Date: Mon Mar 23 20:15:45 2009

`timescale 1ns/10ps

module power3 (
    XPower,
    X,
    clk
);

output [7:0] XPower;
reg [7:0] XPower;
input [7:0] X;
input clk;




always @(posedge clk) begin: POWER3_LOGIC
    reg [8-1:0] X2;
    reg [8-1:0] X1;
    reg [8-1:0] XPower2;
    reg [8-1:0] XPower1;
    XPower1 = 0;
    XPower2 = 0;
    X1 = 0;
    X2 = 0;
    X1 <= X;
    XPower1 <= X;
    X2 <= X1;
    XPower2 <= (XPower1 * X1);
    XPower <= (XPower2 * X2);
end

endmodule


The Error that I am getting is --> Cannot mix blocking and non blocking
assignments on signal

So, maybe there is a way to define intermediate registers within the file
outside of the blocks?? I tried using an @instance block as well but got the
same results.

Any ideas??

This is one of the headaches of switching between one HDL and another....




>
>
> If I'm wrong, we can always wrap a synthesize() function around
> the Icarus engine :-)
>
>  From your question I infer that you assume that a direct synthesis
> flow from MyHDL would somehow remove some synthesis-related restrictions
> But that is not true. The restrictions would be just the same as
> today. They are there for Icarus synthesis also, believe me.
>
> However, those "synthesis restrictions" are in fact badly explained in
> text books. So what could be meaningful is to write a guide for
> "Efficient synthesis with MyHDL". (If I would do that, it would be
> totally different from what you read today. I would basically start
> with synchronous processes and flip-flop inferencing from variables.)
>
> > I haven't looked into what would need to happen to make this happen but
> > I wanted to ask you to see what you thought about this.
> >
> > Personaly, writing everything in Python would be a dream come true.
>
> For all practical purposes, for me this dream is true today. After a
> project
> is properly setup, conversion is hidden somewhere in a Makefile right
> before
> synthesis. Verilog is just one of the many back-end formats used by the
> back-end tools needed to go from MyHDL to an implementation. That's how
> I see it, and it works fine.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>     From Python to silicon:
>     http://www.myhdl.org
>
>
>
> ------------------------------------------------------------------------------
> Apps built with the Adobe(R) Flex(R) framework and Flex Builder(TM) are
> powering Web 2.0 with engaging, cross-platform capabilities. Quickly and
> easily build your RIAs with Flex Builder, the Eclipse(TM)based development
> software that enables intelligent coding and step-through debugging.
> Download the free 60 day trial. http://p.sf.net/sfu/www-adobe-com
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits

Re: [myhdl-list] MyHDL logic synthesis

[Jan D. <ja...@ja...>]

Newell Jensen wrote:
> Jan,
> 
> Have you ever thought of giving MyHDL synthesis capabilities?

No.

Synthesis, the way I define it, would be a formidable task, certainly
beyond my capabilities as an open-source developer.

In addition to powerful HDL inference capabilites and logic minimization,
my definition of synthesis includes timing-driven optimization with an
integrated timing analyzer and powerful technology mapping, ideally
including placement info from an integrated P&R tool.

Morever, what would be the value proposition? Today I get these tools
basically for free from Xilinx and Altera for their architecture.

 > Icarus Verilog can synthesis designs and personally, I would find it a huge
> advantage to not have to go the MyHDL --> Verilog route as there are 
> many things that are not convertable such as delays etc.

I respect Stephen Williams very much and the value of Icarus the simulator
if very clear to me, including its tremendous value to the MyHDL project.
However, I don't see this for Icarus the synthesis tool.
I don't believe it matches my definition of a synthesis tool. It's kind of
hard to judge, as there is virtually no documentation that I can find,
but I'm pretty sure we would have heard about it otherwise.

So I suspect that after Icarus "synthesis" some other tool still has
to perform some tasks (e.g. timing optimization) that I consider part
of synthesis. In other words, it probably gives you an entry point
at a somewhat lower level than Verilog RTL, in a tool flow that you
have to run anyway, and which is basically free anyway.
Again, what's the point?

If I'm wrong, we can always wrap a synthesize() function around
the Icarus engine :-)

 From your question I infer that you assume that a direct synthesis
flow from MyHDL would somehow remove some synthesis-related restrictions
But that is not true. The restrictions would be just the same as
today. They are there for Icarus synthesis also, believe me.

However, those "synthesis restrictions" are in fact badly explained in
text books. So what could be meaningful is to write a guide for
"Efficient synthesis with MyHDL". (If I would do that, it would be
totally different from what you read today. I would basically start
with synchronous processes and flip-flop inferencing from variables.)

> I haven't looked into what would need to happen to make this happen but 
> I wanted to ask you to see what you thought about this.
> 
> Personaly, writing everything in Python would be a dream come true.

For all practical purposes, for me this dream is true today. After a project
is properly setup, conversion is hidden somewhere in a Makefile right before
synthesis. Verilog is just one of the many back-end formats used by the
back-end tools needed to go from MyHDL to an implementation. That's how
I see it, and it works fine.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org

Re: [myhdl-list] MyHDL logic synthesis

[David B. <dav...@ya...>]

Yes,
 
I agree with Newell Jensen.  I believe a synthesis capability built within MyHDL would also be a dream come true.  
 
David Blubaugh

--- On Sat, 3/21/09, Newell Jensen <pil...@gm...> wrote:


From: Newell Jensen <pil...@gm...>
Subject: Re: [myhdl-list] MyHDL logic synthesis
To: "General discussions on MyHDL" <myh...@li...>
Date: Saturday, March 21, 2009, 10:16 PM





On Sat, Mar 21, 2009 at 6:37 PM, Newell Jensen <pil...@gm...> wrote:

Jan,

Have you ever thought of giving MyHDL synthesis capabilities?  Icarus Verilog can synthesis designs and personally, I would find it a huge advantage to not have to go the MyHDL --> Verilog route as there are many things that are not convertable such as delays etc.

After re-reading this I realize that using a delays wasn't a good example.
 



I haven't looked into what would need to happen to make this happen but I wanted to ask you to see what you thought about this.

Personaly, writing everything in Python would be a dream come true.

-- 
Newell



-- 
Newell


-----Inline Attachment Follows-----


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software that enables intelligent coding and step-through debugging.
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Re: [myhdl-list] MyHDL logic synthesis

[Newell J. <pil...@gm...>]

On Sat, Mar 21, 2009 at 6:37 PM, Newell Jensen <pil...@gm...> wrote:

> Jan,
>
> Have you ever thought of giving MyHDL synthesis capabilities?  Icarus
> Verilog can synthesis designs and personally, I would find it a huge
> advantage to not have to go the MyHDL --> Verilog route as there are many
> things that are not convertable such as delays etc.


After re-reading this I realize that using a delays wasn't a good example.


>
>
> I haven't looked into what would need to happen to make this happen but I
> wanted to ask you to see what you thought about this.
>
> Personaly, writing everything in Python would be a dream come true.
>
> --
> Newell
>



-- 
Newell

[myhdl-list] MyHDL logic synthesis

[Newell J. <pil...@gm...>]

Jan,

Have you ever thought of giving MyHDL synthesis capabilities?  Icarus
Verilog can synthesis designs and personally, I would find it a huge
advantage to not have to go the MyHDL --> Verilog route as there are many
things that are not convertable such as delays etc.

I haven't looked into what would need to happen to make this happen but I
wanted to ask you to see what you thought about this.

Personaly, writing everything in Python would be a dream come true.

-- 
Newell

Re: [myhdl-list] Good news: real silicon!

[Christopher F. <chr...@gm...>]

> Early 2008 I designed the digital controller in a mixed-signal
> ASIC design with MyHDL.
>
> Overall, the project has been a big success and soon the chip
> will go into high-volume production (millions).
>
> I have now received permission to write a paper about the
> role that MyHDL played in the project. Needless to say, I'm
> very proud on this accomplishment. In a project like this,
> reliability and cost are crucial. Therefore, this will also
> be my answer to those who question the reliability and
> efficiency of MyHDL-based design - an answer in silicon!
>
> I'm aware of several FPGA projects that have been completed
> successfully with MyHDL, but no ASIC projects so far. So
> I'm going to claim this is the first ASIC tape-out, unless
> someone tells me otherwise! (This can be in private email.)
>
> Best regards,
>
> Jan
>


Congratulations!!!!  That is a very big milestone for MyHDL and very
exciting.  Good job with all the hard work!

Kudos again.
Chris

[myhdl-list] Good news: real silicon!

[Jan D. <ja...@ja...>]

Early 2008 I designed the digital controller in a mixed-signal
ASIC design with MyHDL. 

Overall, the project has been a big success and soon the chip
will go into high-volume production (millions).

I have now received permission to write a paper about the
role that MyHDL played in the project. Needless to say, I'm
very proud on this accomplishment. In a project like this,
reliability and cost are crucial. Therefore, this will also
be my answer to those who question the reliability and
efficiency of MyHDL-based design - an answer in silicon!

I'm aware of several FPGA projects that have been completed
successfully with MyHDL, but no ASIC projects so far. So
I'm going to claim this is the first ASIC tape-out, unless
someone tells me otherwise! (This can be in private email.)

Best regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as an HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] StopIteration caught?

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> My stimulus will read from the input vectors using .next().  Eventually 
> raising StopIteration.  It appears this is being caught?  And, does not stop 
> the simulation.  Is this the expected behavior?

Yes.

A MyHDL simulation consists of a number of "simultaneously" running
generators. If StopIteration weren't caught, the simulation would stop
as soon as one of them runs out of steam. Instead, a simulation has
to run as long as some generator remains active.

Of course, the problem then is that you can easily create simulations
that run forever. Not unlike VHDL and Verilog, you have to make sure
that the simulation stops when you know you're done. For this reason,
StopSimulation is explicitly exported by myhdl and it is the intention
that users raise it.

> I guess I need to catch StopIteration myself, and raise StopSimulation if I 
> want to stop?

Yes. Note that you would probably have to raise StopSimulation also in other
cases, for example when using a for-loop instead of a generator.
Otherwise the simulation runs as long as there are events e.g.
from a clock generator.

Alternatively you can give a time duration to Simulation.run().

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
   Python as a HDL: http://www.myhdl.org
   VHDL development, the modern way: http://www.sigasi.com
   Analog design automation: http://www.mephisto-da.com
   World-class digital design: http://www.easics.com

[myhdl-list] polytopes within MYHDL

[David B. <dav...@ya...>]

Has anyone ever developed a polytopes arithmetic operation in MYHDL, which was also successfully synthesize such a design to VHDL or Verilog?  Polytopes are a sort of enumerated integer type operation.   Thanks, David Blubaugh


      

Re: [myhdl-list] StopIteration caught?

[Christopher F. <chr...@gm...>]

On Tue, Mar 17, 2009 at 12:57 PM, Neal Becker <ndb...@gm...> wrote:

> My stimulus will read from the input vectors using .next().  Eventually
> raising StopIteration.  It appears this is being caught?  And, does not
> stop
> the simulation.  Is this the expected behavior?
>
> I guess I need to catch StopIteration myself, and raise StopSimulation if I
> want to stop?
>
>
That would be my guess as well since I have only ever used raise
StopSimulation.

[myhdl-list] StopIteration caught?

[Neal B. <ndb...@gm...>]

My stimulus will read from the input vectors using .next().  Eventually 
raising StopIteration.  It appears this is being caught?  And, does not stop 
the simulation.  Is this the expected behavior?

I guess I need to catch StopIteration myself, and raise StopSimulation if I 
want to stop?

Re: [myhdl-list] strange problem

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> I'm still trying to wrap my head around myhdl.  This one is weird.

It is purely a Python scope issue. Consider:

def f():
    n = 0
    def g():
            n += 1
            print n
    g()

f()

Running this gives:

> python tmp.py
Traceback (most recent call last):
  File "tmp.py", line 8, in <module>
    f()
  File "tmp.py", line 6, in f
    g()
  File "tmp.py", line 4, in g
    n += 1
UnboundLocalError: local variable 'n' referenced before assignment


To understand what happens, consider that 'n += 1' is equivalent to:
  n = n + 1

When you *assign* to n somewhere locally, Python considers it a
local variable. As the n in the rhs as not been locally assigned yet,
you get the error.
Note that as long you don't assign to n, you would have read
access to the n in the enclosing scope.

For your case, put the initialization in the generator before
the while loop.

Jan

> 
> In my testbench/monitor, which was working, I just added a variable 
> 'input_sample_cnt':
> 
>     input_sample_cnt = 0
>     
>     @instance
>     def stimulus():
>         while (1):
>             yield clock.negedge
>             if (en):
>                 in_i.next = in_i_iter.next()
>                 in_q.next = in_q_iter.next()
>                 input_sample_cnt += 1
>                 
>             reset.next = 0
> 
> I get:
>     input_sample_cnt += 1
> UnboundLocalError: local variable 'input_sample_cnt' referenced before 
> assignment
> 
> But I've had this all along:
>     result_fd = file ('result', 'w')
>     count_fd = file ('count', 'w')
>     reset_fd = file ('reset', 'w')
>     x_fd = file ('x', 'w')
>     en_fd = file ('en', 'w')
>     oe_fd = file ('oe', 'w')
>     
>     @instance
>     def monitor():
>         while 1:
>             yield clock.posedge
>             ##print 'reset:', reset, 'en:', en, 'x:', x, 'count:', 
> to_hex(count), 'result:', to_hex(result)
>             if (oe):
>                 print >> result_fd, to_hex (result_i), to_hex (result_q)
>             print >> count_fd, to_hex (count)
>             print >> x_fd, to_hex (in_i), to_hex (in_q)
>             print >> reset_fd, to_hex (reset)
>             print >> en_fd, to_hex (en)
>             print >> oe_fd, to_hex (oe)
> 
> This seems functionally the same thing (other than using +=).  Why does this 
> latter work, but the former not?  What should I be doing instead?
> 
> 
> 
> ------------------------------------------------------------------------------
> Apps built with the Adobe(R) Flex(R) framework and Flex Builder(TM) are
> powering Web 2.0 with engaging, cross-platform capabilities. Quickly and
> easily build your RIAs with Flex Builder, the Eclipse(TM)based development
> software that enables intelligent coding and step-through debugging.
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] strange problem

[Christopher F. <chr...@gm...>]

On Tue, Mar 17, 2009 at 9:59 AM, Neal Becker <ndb...@gm...> wrote:

> I'm still trying to wrap my head around myhdl.  This one is weird.
>
> In my testbench/monitor, which was working, I just added a variable
> 'input_sample_cnt':
>
>    input_sample_cnt = 0
>
>    @instance
>    def stimulus():
>        while (1):
>            yield clock.negedge
>            if (en):
>                in_i.next = in_i_iter.next()
>                in_q.next = in_q_iter.next()
>                input_sample_cnt += 1
>
>            reset.next = 0
>
> I get:
>    input_sample_cnt += 1
> UnboundLocalError: local variable 'input_sample_cnt' referenced before
> assignment
>
> But I've had this all along:
>    result_fd = file ('result', 'w')
>    count_fd = file ('count', 'w')
>    reset_fd = file ('reset', 'w')
>    x_fd = file ('x', 'w')
>    en_fd = file ('en', 'w')
>    oe_fd = file ('oe', 'w')
>
>    @instance
>    def monitor():
>        while 1:
>            yield clock.posedge
>            ##print 'reset:', reset, 'en:', en, 'x:', x, 'count:',
> to_hex(count), 'result:', to_hex(result)
>            if (oe):
>                print >> result_fd, to_hex (result_i), to_hex (result_q)
>            print >> count_fd, to_hex (count)
>            print >> x_fd, to_hex (in_i), to_hex (in_q)
>            print >> reset_fd, to_hex (reset)
>            print >> en_fd, to_hex (en)
>            print >> oe_fd, to_hex (oe)
>
> This seems functionally the same thing (other than using +=).  Why does
> this
> latter work, but the former not?  What should I be doing instead?
>
>
I am not the most knowledgeable with this issue.  But I think it is an issue
of scope.  In your example the "input_sample_cnt" is part of the testbench
and not part of the stimulus generator.  I forgot the relationship that the
"Signal" introduces.  There should be a way to use simple variables as you
outline (need to check the cookbooks and examples to refresh my memory).
If you make your variable a "Signal+, and use input_sample_cnt.next = ... it
will work.  As mentioned above  I believe there is a method to use variable
but I don't know off the top of my head.

[myhdl-list] strange problem

[Neal B. <ndb...@gm...>]

I'm still trying to wrap my head around myhdl.  This one is weird.

In my testbench/monitor, which was working, I just added a variable 
'input_sample_cnt':

    input_sample_cnt = 0
    
    @instance
    def stimulus():
        while (1):
            yield clock.negedge
            if (en):
                in_i.next = in_i_iter.next()
                in_q.next = in_q_iter.next()
                input_sample_cnt += 1
                
            reset.next = 0

I get:
    input_sample_cnt += 1
UnboundLocalError: local variable 'input_sample_cnt' referenced before 
assignment

But I've had this all along:
    result_fd = file ('result', 'w')
    count_fd = file ('count', 'w')
    reset_fd = file ('reset', 'w')
    x_fd = file ('x', 'w')
    en_fd = file ('en', 'w')
    oe_fd = file ('oe', 'w')
    
    @instance
    def monitor():
        while 1:
            yield clock.posedge
            ##print 'reset:', reset, 'en:', en, 'x:', x, 'count:', 
to_hex(count), 'result:', to_hex(result)
            if (oe):
                print >> result_fd, to_hex (result_i), to_hex (result_q)
            print >> count_fd, to_hex (count)
            print >> x_fd, to_hex (in_i), to_hex (in_q)
            print >> reset_fd, to_hex (reset)
            print >> en_fd, to_hex (en)
            print >> oe_fd, to_hex (oe)

This seems functionally the same thing (other than using +=).  Why does this 
latter work, but the former not?  What should I be doing instead?

Re: [myhdl-list] generate verilog with parameter statement

[Christopher F. <chr...@gm...>]

>
> How do I convert to verilog so that it will contain a 'parameter'
> statement?
>
> I want to specify a value via a verilog 'parameter'.  For example, I have a
> 'frame length' that will be passed to all modules via a verilog parameter.
> What would the corresponding myhdl source look like?
>
>
This isn't part of the standard conversion.  The philosophy is that your
complete design (for the most part) is implemented in MyHDL and that the
Verilog/VHDL is the output, similar to how netlists are generated by
synthesis tools but not, necessarily, directly used in the design.  There is
no conversion of the parameters since the generated code isn't intended to
be modular.  Other words the generated code is a direct representation of
the MyHDL after elaboration (after the parameters have been applied in
python etc).  See the conversion page for a better explanation than mine.

But it may not be practical to re-implement your design in MyHDL.  You may
want to start implementing some of the modules in MyHDL and incorporate it
to your design.  In that case, BOMK, you will have to use the "User-defined
code" (http://www.myhdl.org/doc/0.6/manual/conversion.html)<http://www.myhdl.org/doc/0.6/manual/conversion.html>,
__verilog__, to add the parameters you want.

Hope that helps, Good luck

[myhdl-list] generate verilog with parameter statement

[Neal B. <ndb...@gm...>]

How do I convert to verilog so that it will contain a 'parameter' statement?

I want to specify a value via a verilog 'parameter'.  For example, I have a 
'frame length' that will be passed to all modules via a verilog parameter.  
What would the corresponding myhdl source look like?

Re: [myhdl-list] essay about integer arithmetic

[Christopher F. <chr...@gm...>]

>
> However, if we're talking about abstract behavior of numbers, how about
> some fixed-point support?  One of the nice things about VHDL is the
> ability to specify negative indicies that align with negative powers of
> 2.  Verilog doesn't (or at least didn't) provide even this level of support.
>
>
>  +1
>
> I would love to have a fixed-point type with arthimetic support.  It is a
> lot of book keeping and quite messy syntactically to add /subtract/multiply
> two fixed point numbers, especially when they have different fractional
> widths.  When adding/subtracting, for example, you have to zero pad the LSBs
> until the decimal points line up prior to adding.  Something like (in
> verilog):
>
> wire [DATA_WIDTH-1:0] result = data1 + { data2, {FRAC_WIDTH1 - FRAC_WIDTH2
> {1'b0}};
>
> Furthermore, you have to know up front which one is going to have more
> fractional bits so that you can pad the appropriate one.
>
>
I think this is one of the strong benefits of MyHDL / Python.  MyHDL
provides the basics building blocks for simulation and conversion.  You can
add your packages / modules that do all the book keeping for things like
fixed-point.  This probably isn't something that should be built into the
language but additional modules and packages that can be created.

Re: [myhdl-list] essay about integer arithmetic

[Lane B. <la...@ub...>]

Andrew Lentvorski wrote:
> Jan Decaluwe wrote:
>   
>> This is an essay that I wanted to write for a long time.
>> It describes what I think is wrong with integer arithmetic
>> in VHDL and Verilog, and why MyHDL provides a solution.
>>
>> Before releasing it to the general public, I'm interested
>> to hear what you think about it.
>>
>>     http://www.jandecaluwe.com/hdldesign/counting.html
>>     
>
> The essay sums up some of my gripes about the mishmash that is the whole 
> abstract behavior of numbers problem.  Nicely done.  I know that I'll 
> point more than a few newbies at it.
>
>
> I do have a bit of a gripe about statements like:
> "This situation would not persist without the widespread support of the 
> designer community."
>
> Ummmmm, no.  Most of the designers I know of hate the way a *lot* of 
> things are done in Verilog and VHDL.  Would we be using MyHDL if that 
> were not the case?  ;)  However, an individual designer has very limited 
> options to push back into these standards.  See SystemVerilog, for 
> example.  EDA vendors have a high incentive and large resources to 
> push/implement what is *profitable* to them--usefulness to the the user 
> is an orthogonal consideration.
>
>
> However, if we're talking about abstract behavior of numbers, how about 
> some fixed-point support?  One of the nice things about VHDL is the 
> ability to specify negative indicies that align with negative powers of 
> 2.  Verilog doesn't (or at least didn't) provide even this level of support.
>   
+1

I would love to have a fixed-point type with arthimetic support.  It is 
a lot of book keeping and quite messy syntactically to add 
/subtract/multiply two fixed point numbers, especially when they have 
different fractional widths.  When adding/subtracting, for example, you 
have to zero pad the LSBs until the decimal points line up prior to 
adding.  Something like (in verilog):

wire [DATA_WIDTH-1:0] result = data1 + { data2, {FRAC_WIDTH1 - 
FRAC_WIDTH2 {1'b0}};

Furthermore, you have to know up front which one is going to have more 
fractional bits so that you can pad the appropriate one.


Lane

Re: [myhdl-list] essay about integer arithmetic

[Neal B. <ndb...@gm...>]

Jan Decaluwe wrote:

> Andrew Lentvorski wrote:
> 
>> However, if we're talking about abstract behavior of numbers, how about
>> some fixed-point support?  One of the nice things about VHDL is the
>> ability to specify negative indicies that align with negative powers of
>> 2.  Verilog doesn't (or at least didn't) provide even this level of
>> support.
>> 
>> Writing, say, a delta-sigma modulator in any HDL language is kind of a
>> pain because we don't have an abstract "fixed point number" that you can
>> assert against.  Adding extra bits at either end to cover different
>> issues (Did it overflow?  I need more integer bits.  Is the error too
>> large?  I need more fractional bits.) is a pain when it interacts with
>> sign bits.
> 

I have written fixed-pt code using c++ boost::python, if anyone's interested.

Re: [myhdl-list] essay about integer arithmetic

[David B. <da...@we...>]

Jan Decaluwe wrote:
> Andrew Lentvorski wrote:
> 
>> However, if we're talking about abstract behavior of numbers, how about 
>> some fixed-point support?  One of the nice things about VHDL is the 
>> ability to specify negative indicies that align with negative powers of 
>> 2.  Verilog doesn't (or at least didn't) provide even this level of support.
>>
>> Writing, say, a delta-sigma modulator in any HDL language is kind of a 
>> pain because we don't have an abstract "fixed point number" that you can 
>> assert against.  Adding extra bits at either end to cover different 
>> issues (Did it overflow?  I need more integer bits.  Is the error too 
>> large?  I need more fractional bits.) is a pain when it interacts with 
>> sign bits.
> 
> I have no experience with this. Is there synthesis support for it?
> 

I haven't used that feature myself, but I believe it is synthesisable in 
VHDL.  It just allows indexes that don't start at 0.  However, I expect 
it would be a little awkward to use the same idea with intbv since 
negative indexes have a different meaning for slicing in Python.

>> Unrelated note: I *STILL* hate c.next = <some expression>
>>
>> The fact that c = <some expression> often silently does the wrong thing 
>> when you really meant c.next = <some expression> is very un-Pythonic.
>>
>> Did Python 3K enable some form of introspection that could do something 
>> about this?
> 
> Some MyHDL decorators (always_comb) use introspection already.
> So we could use them to do checks like the one you propose.
> Of course, this would only work when decorators are used to
> create generators.
> 
> Jan
> 
> 

Re: [myhdl-list] essay about integer arithmetic

[Jan D. <ja...@ja...>]

Andrew Lentvorski wrote:

> However, if we're talking about abstract behavior of numbers, how about 
> some fixed-point support?  One of the nice things about VHDL is the 
> ability to specify negative indicies that align with negative powers of 
> 2.  Verilog doesn't (or at least didn't) provide even this level of support.
> 
> Writing, say, a delta-sigma modulator in any HDL language is kind of a 
> pain because we don't have an abstract "fixed point number" that you can 
> assert against.  Adding extra bits at either end to cover different 
> issues (Did it overflow?  I need more integer bits.  Is the error too 
> large?  I need more fractional bits.) is a pain when it interacts with 
> sign bits.

I have no experience with this. Is there synthesis support for it?

> Unrelated note: I *STILL* hate c.next = <some expression>
> 
> The fact that c = <some expression> often silently does the wrong thing 
> when you really meant c.next = <some expression> is very un-Pythonic.
> 
> Did Python 3K enable some form of introspection that could do something 
> about this?

Some MyHDL decorators (always_comb) use introspection already.
So we could use them to do checks like the one you propose.
Of course, this would only work when decorators are used to
create generators.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] essay about integer arithmetic

[Jan D. <ja...@ja...>]

Andrew Lentvorski wrote:
> Jan Decaluwe wrote:
>> This is an essay that I wanted to write for a long time.
>> It describes what I think is wrong with integer arithmetic
>> in VHDL and Verilog, and why MyHDL provides a solution.
>>
>> Before releasing it to the general public, I'm interested
>> to hear what you think about it.
>>
>>     http://www.jandecaluwe.com/hdldesign/counting.html
> 
> The essay sums up some of my gripes about the mishmash that is the whole 
> abstract behavior of numbers problem.  Nicely done.  I know that I'll 
> point more than a few newbies at it.
> 
> 
> I do have a bit of a gripe about statements like:
> "This situation would not persist without the widespread support of the 
> designer community."
> 
> Ummmmm, no.  Most of the designers I know of hate the way a *lot* of 
> things are done in Verilog and VHDL.  Would we be using MyHDL if that 
> were not the case?  ;)  However, an individual designer has very limited 
> options to push back into these standards.  See SystemVerilog, for 
> example.

I agree that "widespread support" sounds a bit harsh and perhaps too
"active". Perhaps "compliancy" is a better description?

On the other hand, most designers I know *personally* also favor
a more abstract approach, but overall I have every indication
that this is a currently a minority view. Otherwise, wouldn't
VHDL integer subtypes be used more than they are? Wouldn't
people complain more about Verilog's bizarre integer
interpretation, instead of silently obeying the rules?

And even in the MyHDL community, I don't expect everyone to
agree. Look at some responses in this thread.

There's a reason I put this essay on my personal website
instead of myhdl.org. I expect controversy (and I'm just
starting :-)). It's not necessary to agree with my
viewpoints to be able use MyHDL successfully, so I shouldn't
alienate people unnecessarily.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a hardware description language:
    http://www.myhdl.org

Re: [myhdl-list] essay about integer arithmetic

[Andrew L. <bs...@al...>]

Jan Decaluwe wrote:
> This is an essay that I wanted to write for a long time.
> It describes what I think is wrong with integer arithmetic
> in VHDL and Verilog, and why MyHDL provides a solution.
> 
> Before releasing it to the general public, I'm interested
> to hear what you think about it.
> 
>     http://www.jandecaluwe.com/hdldesign/counting.html

The essay sums up some of my gripes about the mishmash that is the whole 
abstract behavior of numbers problem.  Nicely done.  I know that I'll 
point more than a few newbies at it.


I do have a bit of a gripe about statements like:
"This situation would not persist without the widespread support of the 
designer community."

Ummmmm, no.  Most of the designers I know of hate the way a *lot* of 
things are done in Verilog and VHDL.  Would we be using MyHDL if that 
were not the case?  ;)  However, an individual designer has very limited 
options to push back into these standards.  See SystemVerilog, for 
example.  EDA vendors have a high incentive and large resources to 
push/implement what is *profitable* to them--usefulness to the the user 
is an orthogonal consideration.


However, if we're talking about abstract behavior of numbers, how about 
some fixed-point support?  One of the nice things about VHDL is the 
ability to specify negative indicies that align with negative powers of 
2.  Verilog doesn't (or at least didn't) provide even this level of support.

Writing, say, a delta-sigma modulator in any HDL language is kind of a 
pain because we don't have an abstract "fixed point number" that you can 
assert against.  Adding extra bits at either end to cover different 
issues (Did it overflow?  I need more integer bits.  Is the error too 
large?  I need more fractional bits.) is a pain when it interacts with 
sign bits.


Unrelated note: I *STILL* hate c.next = <some expression>

The fact that c = <some expression> often silently does the wrong thing 
when you really meant c.next = <some expression> is very un-Pythonic.

Did Python 3K enable some form of introspection that could do something 
about this?

-a

Re: [myhdl-list] essay about integer arithmetic

[Thomas H. <th...@ct...>]

Jan Decaluwe schrieb:
> This is an essay that I wanted to write for a long time.
> It describes what I think is wrong with integer arithmetic
> in VHDL and Verilog, and why MyHDL provides a solution.
> 
> Before releasing it to the general public, I'm interested
> to hear what you think about it.
> 
>     http://www.jandecaluwe.com/hdldesign/counting.html
> 
> 
> 
Jan,

let me say that I enjoyed your essay very much. I have done some designs
in VHDL but did not have to use arithmetic in the past, other than the
usual '+1' for counters.

MyHDL to the rescue when I had to implement a serial pipelined divider:
your article explains very well the issues that I could avoid with it.

-- 
Thanks,
Thomas