linux-mips-commits — CVS Commit Patches

[Linux-mips-commits]CVS: linux/include/asm-mips/ddb5xxx ddb5476.h,NONE,1.1 ddb5477.h,1.2,1.3 ddb5xxx.h,1.1.1.1,1.2

[Jun S. <ju...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/ddb5xxx
In directory usw-pr-cvs1:/tmp/cvs-serv16561/include/asm-mips/ddb5xxx

Modified Files:
	ddb5477.h ddb5xxx.h 
Added Files:
	ddb5476.h 
Log Message:
Update DDB5476 and sync up with oss tree.


--- NEW FILE: ddb5476.h ---
/*
 * header file specific for ddb5476
 *
 * Copyright (C) 2001 MontaVista Software Inc.
 * Author: Jun Sun, js...@mv... or js...@ju...
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

/*
 *  Memory map (physical address)
 *
 *  Note most of the following address must be properly aligned by the
 *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
 *  PCI_IO_BASE must be aligned along 16MB boundary.
 */
#define DDB_SDRAM_BASE		0x00000000
#define DDB_SDRAM_SIZE		0x04000000      /* 64MB */

#define	DDB_DCS3_BASE		0x04000000	/* flash 1 */
#define	DDB_DCS3_SIZE		0x01000000	/* 16MB */

#define	DDB_DCS2_BASE		0x05000000	/* flash 2 */
#define	DDB_DCS2_SIZE		0x01000000	/* 16MB */

#define DDB_PCI_IO_BASE		0x06000000      
#define DDB_PCI_IO_SIZE		0x02000000      /* 32 MB */

#define	DDB_PCI_MEM_BASE	0x08000000
#define	DDB_PCI_MEM_SIZE	0x08000000	/* 128 MB */

#define	DDB_DCS5_BASE		0x13000000	/* DDB status regs */
#define	DDB_DCS5_SIZE		0x00200000	/* 2MB, 8-bit */

#define	DDB_DCS4_BASE		0x14000000	/* DDB control regs */
#define	DDB_DCS4_SIZE		0x00200000	/* 2MB, 8-bit */

#define DDB_INTCS_BASE		0x1fa00000      /* VRC5476 control regs */
#define DDB_INTCS_SIZE		0x00200000      /* 2MB */

#define DDB_BOOTCS_BASE         0x1fc00000      /* Boot ROM / EPROM /Flash */
#define DDB_BOOTCS_SIZE         0x00200000      /* 2 MB - doc says 4MB */


/* aliases */
#define	DDB_PCI_CONFIG_BASE	DDB_PCI_MEM_BASE
#define	DDB_PCI_CONFIG_SIZE	DDB_PCI_MEM_SIZE

/* PCI intr ack share PCIW0 with PCI IO */
#define	DDB_PCI_IACK_BASE	DDB_PCI_IO_BASE

/*
 * Interrupt mapping
 *
 * We have three interrupt controllers:
 *
 *   . CPU itself - 8 sources
 *   . i8259 - 16 sources
 *   . vrc5476 - 16 sources
 *
 *  They connected as follows:
 *    all vrc5476 interrupts are routed to cpu IP2 (by software setting)
 *    all i2869 are routed to INTC in vrc5476 (by hardware connection)
 *
 *  All VRC5476 PCI interrupts are level-triggered (no ack needed).
 *  All PCI irq but INTC are active low.
 */

/* 
 * irq number block assignment
 */

#define	NUM_CPU_IRQ		8
#define	NUM_I8259_IRQ		16
#define	NUM_VRC5476_IRQ		16

#define	DDB_IRQ_BASE		0

#define	I8259_IRQ_BASE		DDB_IRQ_BASE
#define	VRC5476_IRQ_BASE	(I8259_IRQ_BASE + NUM_I8259_IRQ)
#define	CPU_IRQ_BASE		(VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)

/*
 * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
 */

#define VRC5476_IRQ_CPCE	0	/* cpu parity error */
#define VRC5476_IRQ_CNTD	1	/* cpu no target */
#define VRC5476_IRQ_MCE		2	/* memory check error */
#define VRC5476_IRQ_DMA		3	/* DMA */
#define VRC5476_IRQ_UART	4	/* vrc5476 builtin UART, not used */
#define VRC5476_IRQ_WDOG	5	/* watchdog timer */
#define VRC5476_IRQ_GPT		6	/* general purpose timer */
#define VRC5476_IRQ_LBRT	7	/* local bus read timeout */
#define VRC5476_IRQ_INTA	8	/* PCI INT #A */
#define VRC5476_IRQ_INTB	9	/* PCI INT #B */
#define VRC5476_IRQ_INTC	10	/* PCI INT #C */
#define VRC5476_IRQ_INTD	11	/* PCI INT #D */
#define VRC5476_IRQ_INTE	12	/* PCI INT #E */
#define VRC5476_IRQ_RESERVED_13	13	/* reserved  */
#define VRC5476_IRQ_PCIS	14	/* PCI SERR #  */
#define VRC5476_IRQ_PCI		15	/* PCI internal error */

/*
 * i2859 irq assignment
 */
#define I8259_IRQ_RESERVED_0	0	
#define I8259_IRQ_KEYBOARD	1	/* M1543 default */
#define I8259_IRQ_CASCADE	2
#define I8259_IRQ_UART_B	3	/* M1543 default, may conflict with RTC according to schematic diagram  */
#define I8259_IRQ_UART_A	4	/* M1543 default */
#define I8259_IRQ_PARALLEL	5	/* M1543 default */
#define I8259_IRQ_RESERVED_6	6
#define I8259_IRQ_RESERVED_7	7
#define I8259_IRQ_RTC		8	/* who set this? */
#define I8259_IRQ_USB		9	/* ddb_setup */
#define I8259_IRQ_PMU		10	/* ddb_setup */
#define I8259_IRQ_RESERVED_11	11
#define I8259_IRQ_RESERVED_12	12	/* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13	13
#define I8259_IRQ_HDC1		14	/* default and ddb_setup */
#define I8259_IRQ_HDC2		15	/* default */


/*
 * misc
 */
#define	VRC5476_I8259_CASCADE	VRC5476_IRQ_INTC
#define	CPU_VRC5476_CASCADE	2

#define is_i8259_irq(irq)       ((irq) < NUM_I8259_IRQ)
#define nile4_to_irq(n)         ((n)+NUM_I8259_IRQ)
#define irq_to_nile4(n)         ((n)-NUM_I8259_IRQ)

/*
 * low-level irq functions
 */
#ifndef _LANGUAGE_ASSEMBLY
extern void nile4_map_irq(int nile4_irq, int cpu_irq);
extern void nile4_map_irq_all(int cpu_irq);
extern void nile4_enable_irq(int nile4_irq);
extern void nile4_disable_irq(int nile4_irq);
extern void nile4_disable_irq_all(void);
extern u16 nile4_get_irq_stat(int cpu_irq);
extern void nile4_enable_irq_output(int cpu_irq);
extern void nile4_disable_irq_output(int cpu_irq);
extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
extern void nile4_clear_irq(int nile4_irq);
extern void nile4_clear_irq_mask(u32 mask);
extern u8 nile4_i8259_iack(void);
extern void nile4_dump_irq_status(void);        /* Debug */
#endif

Index: ddb5477.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/ddb5xxx/ddb5477.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- ddb5477.h	2001/08/22 14:42:24	1.2
+++ ddb5477.h	2001/10/07 05:40:22	1.3
@@ -18,7 +18,6 @@
 #define __ASM_DDB5XXX_DDB5477_H
 
 #include <linux/config.h>
-#include <asm/ddb5xxx/ddb5xxx.h>
 
 /*
  * This contains macros that are specific to DDB5477 or renamed from
@@ -28,9 +27,9 @@
 /*
  * renamed PADRs
  */
-#define	DDB_LCS0	DDB_LDCS0
-#define	DDB_LCS1	DDB_LDCS1
-#define	DDB_LCS2	DDB_LDCS2
+#define	DDB_LCS0	DDB_DCS2
+#define	DDB_LCS1	DDB_DCS3
+#define	DDB_LCS2	DDB_DCS4
 #define	DDB_VRC5477	DDB_INTCS
 
 /*

Index: ddb5xxx.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/ddb5xxx/ddb5xxx.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- ddb5xxx.h	2001/06/22 02:29:33	1.1.1.1
+++ ddb5xxx.h	2001/10/07 05:40:22	1.2
@@ -1,5 +1,4 @@
-/***********************************************************************
- *
+/*
  * Copyright 2001 MontaVista Software Inc.
  * Author: js...@mv... or js...@ju...
  *
@@ -14,7 +13,6 @@
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
- ***********************************************************************
  */
 
 #ifndef __ASM_DDB5XXX_DDB5XXX_H
@@ -49,12 +47,13 @@
 
 #define DDB_SDRAM0	0x0000	/* SDRAM Bank 0 [R/W] */
 #define DDB_SDRAM1	0x0008	/* SDRAM Bank 1 [R/W] */
-#define DDB_LDCS0	0x0010	/* Device Chip-Select 0 [R/W] */
-#define DDB_LDCS1	0x0018	/* Device Chip-Select 1 [R/W] */
-#define DDB_LDCS2	0x0020	/* Device Chip-Select 2 [R/W] */
-#define DDB_LDCS3	0x0028	/* Device Chip-Select 3 [R/W] */
-#define DDB_LDCS4	0x0030	/* Device Chip-Select 4 [R/W] */
-#define DDB_LDCS5	0x0038	/* Device Chip-Select 5 [R/W] */
+#define DDB_DCS2	0x0010	/* Device Chip-Select 2 [R/W] */
+#define DDB_DCS3	0x0018	/* Device Chip-Select 3 [R/W] */
+#define DDB_DCS4	0x0020	/* Device Chip-Select 4 [R/W] */
+#define DDB_DCS5	0x0028	/* Device Chip-Select 5 [R/W] */
+#define DDB_DCS6	0x0030	/* Device Chip-Select 6 [R/W] */
+#define DDB_DCS7	0x0038	/* Device Chip-Select 7 [R/W] */
+#define DDB_DCS8	0x0040	/* Device Chip-Select 8 [R/W] */
 #define DDB_PCIW0	0x0060	/* PCI Address Window 0 [R/W] */
 #define DDB_PCIW1	0x0068	/* PCI Address Window 1 [R/W] */
 #define DDB_INTCS	0x0070	/* Controller Internal Registers and Devices */

[Linux-mips-commits]CVS: linux/drivers/pci Makefile,1.4,1.5

[Jun S. <ju...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/pci
In directory usw-pr-cvs1:/tmp/cvs-serv16561/drivers/pci

Modified Files:
	Makefile 
Log Message:
Update DDB5476 and sync up with oss tree.


Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/pci/Makefile,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- Makefile	2001/08/25 02:19:28	1.4
+++ Makefile	2001/10/07 05:40:22	1.5
@@ -27,7 +27,6 @@
 obj-$(CONFIG_ARM) += setup-bus.o setup-irq.o
 obj-$(CONFIG_SUPERH) += setup-bus.o setup-irq.o
 obj-$(CONFIG_ALL_PPC) += setup-bus.o
-obj-$(CONFIG_DDB5476) += setup-bus.o
 obj-$(CONFIG_SGI_IP27) += setup-irq.o
 
 ifndef CONFIG_X86

[Linux-mips-commits]CVS: linux/arch/mips/ddb5xxx/ddb5476 Makefile,NONE,1.1 dbg_io.c,NONE,1.1 int-handler.S,NONE,1.1 irq.c,NONE,1.1 nile4_pic.c,NONE,1.1 pci.c,NONE,1.1 pci_ops.c,NONE,1.1 setup.c,NONE,1.1 vrc5476_irq.c,NONE,1.1

[Jun S. <ju...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476
In directory usw-pr-cvs1:/tmp/cvs-serv16561/arch/mips/ddb5xxx/ddb5476

Added Files:
	Makefile dbg_io.c int-handler.S irq.c nile4_pic.c pci.c 
	pci_ops.c setup.c vrc5476_irq.c 
Log Message:
Update DDB5476 and sync up with oss tree.


--- NEW FILE: Makefile ---
#
# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines
# under Linux.
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
# Note 2! The CFLAGS definitions are now in the main makefile...
#

.S.s:
	$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
	$(CC) $(CFLAGS) -c $< -o $*.o

O_TARGET = ddb5476.o

obj-y				+= setup.o irq.o int-handler.o pci.o pci_ops.o \
				   nile4_pic.o vrc5476_irq.o
obj-$(CONFIG_REMOTE_DEBUG)	+= dbg_io.o

include $(TOPDIR)/Rules.make

--- NEW FILE: dbg_io.c ---
/*
 * kgdb io functions for DDB5476.  We use the second serial port.
 *
 * Copyright (C) 2001 MontaVista Software Inc.
 * Author: js...@mv... or js...@ju...
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

/* ======================= CONFIG ======================== */

/* [jsun] we use the second serial port for kdb */
#define         BASE                    0xa60002f8
#define         MAX_BAUD                115200

/* distance in bytes between two serial registers */
#define         REG_OFFSET              1

/*
 * 0 - kgdb does serial init
 * 1 - kgdb skip serial init
 */
static int remoteDebugInitialized = 0;

/*
 * the default baud rate *if* kgdb does serial init
 */
#define		BAUD_DEFAULT		UART16550_BAUD_38400

/* ======================= END OF CONFIG ======================== */

typedef unsigned char uint8;
typedef unsigned int uint32;

#define         UART16550_BAUD_2400             2400
#define         UART16550_BAUD_4800             4800
#define         UART16550_BAUD_9600             9600
#define         UART16550_BAUD_19200            19200
#define         UART16550_BAUD_38400            38400
#define         UART16550_BAUD_57600            57600
#define         UART16550_BAUD_115200           115200

#define         UART16550_PARITY_NONE           0
#define         UART16550_PARITY_ODD            0x08
#define         UART16550_PARITY_EVEN           0x18
#define         UART16550_PARITY_MARK           0x28
#define         UART16550_PARITY_SPACE          0x38

#define         UART16550_DATA_5BIT             0x0
#define         UART16550_DATA_6BIT             0x1
#define         UART16550_DATA_7BIT             0x2
#define         UART16550_DATA_8BIT             0x3

#define         UART16550_STOP_1BIT             0x0
#define         UART16550_STOP_2BIT             0x4

/* register offset */
#define         OFS_RCV_BUFFER          0
#define         OFS_TRANS_HOLD          0
#define         OFS_SEND_BUFFER         0
#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
#define         OFS_INTR_ID             (2*REG_OFFSET)
#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
#define         OFS_LINE_STATUS         (5*REG_OFFSET)
#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
#define         OFS_RS232_INPUT         (6*REG_OFFSET)
#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)

#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)


/* memory-mapped read/write of the port */
#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)

void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
        /* disable interrupts */
        UART16550_WRITE(OFS_INTR_ENABLE, 0);

        /* set up buad rate */
        {
                uint32 divisor;

                /* set DIAB bit */
                UART16550_WRITE(OFS_LINE_CONTROL, 0x80);

                /* set divisor */
                divisor = MAX_BAUD / baud;
                UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
                UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);

                /* clear DIAB bit */
                UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
        }

        /* set data format */
        UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}


uint8 getDebugChar(void)
{
        if (!remoteDebugInitialized) {
                remoteDebugInitialized = 1;
                debugInit(BAUD_DEFAULT,
                          UART16550_DATA_8BIT,
                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
        }

        while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
        return UART16550_READ(OFS_RCV_BUFFER);
}


int putDebugChar(uint8 byte)
{
        if (!remoteDebugInitialized) {
                remoteDebugInitialized = 1;
                debugInit(BAUD_DEFAULT,
                          UART16550_DATA_8BIT,
                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
        }

        while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
        UART16550_WRITE(OFS_SEND_BUFFER, byte);
        return 1;
}

--- NEW FILE: int-handler.S ---
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: js...@mv... or js...@ju...
 *
 * First-level interrupt dispatcher for ddb5476
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/config.h>

#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>

#include <asm/ddb5xxx/ddb5476.h>

/*
 * first level interrupt dispatcher for ocelot board -
 * We check for the timer first, then check PCI ints A and D.
 * Then check for serial IRQ and fall through.
 */
	.align	5
	NESTED(ddb5476_handle_int, PT_SIZE, sp)
	SAVE_ALL
	CLI
	.set	at
	.set	noreorder
	mfc0	t0, CP0_CAUSE  
	mfc0	t2, CP0_STATUS

	and	t0, t2

        andi    t1, t0, STATUSF_IP7     /* cpu timer */
        bnez    t1, ll_cpu_ip7
        andi    t1, t0, STATUSF_IP2	/* vrc5476 & i8259 */
        bnez    t1, ll_cpu_ip2
        andi    t1, t0, STATUSF_IP3
        bnez    t1, ll_cpu_ip3
        andi    t1, t0, STATUSF_IP4
        bnez    t1, ll_cpu_ip4
        andi    t1, t0, STATUSF_IP5
        bnez    t1, ll_cpu_ip5
        andi    t1, t0, STATUSF_IP6
        bnez    t1, ll_cpu_ip6
        andi    t1, t0, STATUSF_IP0     /* software int 0 */
        bnez    t1, ll_cpu_ip0
        andi    t1, t0, STATUSF_IP1     /* software int 1 */
        bnez    t1, ll_cpu_ip1
        nop

	.set	reorder

	/* wrong alarm or masked ... */
	// j	spurious_interrupt
	move 	a0, sp
	jal	vrc5476_irq_dispatch
	j	ret_from_irq
	nop

	.align	5

ll_cpu_ip0:	
	li	a0, CPU_IRQ_BASE + 0
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip1:	
	li	a0, CPU_IRQ_BASE + 1
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip2:		/* jump to second-level dispatching */
	move	a0, sp
	jal	vrc5476_irq_dispatch
	j	ret_from_irq

ll_cpu_ip3:	
	li	a0, CPU_IRQ_BASE + 3
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip4:	
	li	a0, CPU_IRQ_BASE + 4
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip5:	
	li	a0, CPU_IRQ_BASE + 5
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip6:	
	li	a0, CPU_IRQ_BASE + 6
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip7:
	li	a0, CPU_IRQ_BASE + 7
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

	END(ddb5476_handle_int)

--- NEW FILE: irq.c ---
/*
 *  arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
 *
 *  Copyright (C) 2000 Geert Uytterhoeven <ge...@so...>
 *                     Sony Software Development Center Europe (SDCE), Brussels
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <asm/io.h>
#include <asm/ptrace.h>

#include <asm/ddb5xxx/ddb5xxx.h>

#define M1543_PNP_CONFIG	0x03f0	/* PnP Config Port */
#define M1543_PNP_INDEX		0x03f0	/* PnP Index Port */
#define M1543_PNP_DATA		0x03f1	/* PnP Data Port */

#define M1543_PNP_ALT_CONFIG	0x0370	/* Alternative PnP Config Port */
#define M1543_PNP_ALT_INDEX	0x0370	/* Alternative PnP Index Port */
#define M1543_PNP_ALT_DATA	0x0371	/* Alternative PnP Data Port */

#define M1543_INT1_MASTER_CTRL	0x0020	/* INT_1 (master) Control Register */
#define M1543_INT1_MASTER_MASK	0x0021	/* INT_1 (master) Mask Register */

#define M1543_INT1_SLAVE_CTRL	0x00a0	/* INT_1 (slave) Control Register */
#define M1543_INT1_SLAVE_MASK	0x00a1	/* INT_1 (slave) Mask Register */

#define M1543_INT1_MASTER_ELCR	0x04d0	/* INT_1 (master) Edge/Level Control */
#define M1543_INT1_SLAVE_ELCR	0x04d1	/* INT_1 (slave) Edge/Level Control */

static void m1543_irq_setup(void)
{
	/*
	 *  The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13.  Not all
	 *  the possible IO sources in the M1543 are in use by us.  We will
	 *  use the following mapping:
	 *
	 *      IRQ1  - keyboard (default set by M1543)
	 *      IRQ3  - reserved for UART B (default set by M1543) (note that
	 *              the schematics for the DDB Vrc-5476 board seem to 
	 *              indicate that IRQ3 is connected to the DS1386 
	 *              watchdog timer interrupt output so we might have 
	 *              a conflict)
	 *      IRQ4  - reserved for UART A (default set by M1543)
	 *      IRQ5  - parallel (default set by M1543)
	 *      IRQ8  - DS1386 time of day (RTC) interrupt
	 *      IRQ9  - USB (hardwired in ddb_setup)
	 *      IRQ10 - PMU (hardwired in ddb_setup)
	 *      IRQ12 - mouse
	 *      IRQ14,15 - IDE controller (need to be confirmed, jsun)
	 */

	/*
	 *  Assing mouse interrupt to IRQ12 
	 */

	/* Enter configuration mode */
	outb(0x51, M1543_PNP_CONFIG);
	outb(0x23, M1543_PNP_CONFIG);

	/* Select logical device 7 (Keyboard) */
	outb(0x07, M1543_PNP_INDEX);
	outb(0x07, M1543_PNP_DATA);

	/* Select IRQ12 */
	outb(0x72, M1543_PNP_INDEX);
	outb(0x0c, M1543_PNP_DATA);

	/* Leave configration mode */
	outb(0xbb, M1543_PNP_CONFIG);
}

static void nile4_irq_setup(void)
{
	int i;

	/* Map all interrupts to CPU int #0 (IP2) */
	nile4_map_irq_all(0);

	/* PCI INTA#-E# must be level triggered */
	nile4_set_pci_irq_level_or_edge(0, 1);
	nile4_set_pci_irq_level_or_edge(1, 1);
	nile4_set_pci_irq_level_or_edge(2, 1);
	nile4_set_pci_irq_level_or_edge(3, 1);

	/* PCI INTA#, B#, D# must be active low, INTC# must be active high */
	nile4_set_pci_irq_polarity(0, 0);
	nile4_set_pci_irq_polarity(1, 0);
	nile4_set_pci_irq_polarity(2, 1);
	nile4_set_pci_irq_polarity(3, 0);

	for (i = 0; i < 16; i++)
		nile4_clear_irq(i);

	/* Enable CPU int #0 */
	nile4_enable_irq_output(0);

	/* memory resource acquire in ddb_setup */
}

static void error_action(int irq, void *dev_id, struct pt_regs *regs)
{
	printk(KERN_ERR "Error interrupt happend: %d\n", irq);
}

static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
static struct irqaction irq_error = { no_action, 0, 0, "error", NULL, NULL };

extern asmlinkage void ddb5476_handle_int(void);
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
extern void mips_cpu_irq_init(u32 irq_base);
extern void vrc5476_irq_init(u32 irq_base);

void __init ddb5476_irq_setup(void)
{
	/* hardware initialization */
	nile4_irq_setup();
	m1543_irq_setup();

	/* controller setup */
	init_i8259_irqs();
	vrc5476_irq_init(VRC5476_IRQ_BASE);
	mips_cpu_irq_init(CPU_IRQ_BASE);

	/* setup cascade interrupts */
	setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
	setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);

	/* setup error interrupts for debugging */
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);

	/* setup the grandpa intr vector */
	set_except_vector(0, ddb5476_handle_int);
}

--- NEW FILE: nile4_pic.c ---
/*
 *  arch/mips/ddb5476/nile4.c -- 
 *  	low-level PIC code for NEC Vrc-5476 (Nile 4)
 *
 *  Copyright (C) 2000 Geert Uytterhoeven <ge...@so...>
 *                     Sony Software Development Center Europe (SDCE), Brussels
 *
 *  Copyright 2001 MontaVista Software Inc.
 *  Author: js...@mv... or js...@ju...
 *
 */
#include <linux/kernel.h>
#include <linux/types.h>

#include <asm/addrspace.h>

#include <asm/ddb5xxx/ddb5xxx.h>


/*
 *  Interrupt Programming
 */
void nile4_map_irq(int nile4_irq, int cpu_irq)
{
	u32 offset, t;

	offset = DDB_INTCTRL;
	if (nile4_irq >= 8) {
		offset += 4;
		nile4_irq -= 8;
	}
	t = ddb_in32(offset);
	t &= ~(7 << (nile4_irq * 4));
	t |= cpu_irq << (nile4_irq * 4);
	ddb_out32(offset, t);
}

void nile4_map_irq_all(int cpu_irq)
{
	u32 all, t;

	all = cpu_irq;
	all |= all << 4;
	all |= all << 8;
	all |= all << 16;
	t = ddb_in32(DDB_INTCTRL);
	t &= 0x88888888;
	t |= all;
	ddb_out32(DDB_INTCTRL, t);
	t = ddb_in32(DDB_INTCTRL + 4);
	t &= 0x88888888;
	t |= all;
	ddb_out32(DDB_INTCTRL + 4, t);
}

void nile4_enable_irq(int nile4_irq)
{
	u32 offset, t;

	offset = DDB_INTCTRL;
	if (nile4_irq >= 8) {
		offset += 4;
		nile4_irq -= 8;
	}
	t = ddb_in32(offset);
	t |= 8 << (nile4_irq * 4);
	ddb_out32(offset, t);
}

void nile4_disable_irq(int nile4_irq)
{
	u32 offset, t;

	offset = DDB_INTCTRL;
	if (nile4_irq >= 8) {
		offset += 4;
		nile4_irq -= 8;
	}
	t = ddb_in32(offset);
	t &= ~(8 << (nile4_irq * 4));
	ddb_out32(offset, t);
}

void nile4_disable_irq_all(void)
{
	ddb_out32(DDB_INTCTRL, 0);
	ddb_out32(DDB_INTCTRL + 4, 0);
}

u16 nile4_get_irq_stat(int cpu_irq)
{
	return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
}

void nile4_enable_irq_output(int cpu_irq)
{
	u32 t;

	t = ddb_in32(DDB_INTSTAT1 + 4);
	t |= 1 << (16 + cpu_irq);
	ddb_out32(DDB_INTSTAT1, t);
}

void nile4_disable_irq_output(int cpu_irq)
{
	u32 t;

	t = ddb_in32(DDB_INTSTAT1 + 4);
	t &= ~(1 << (16 + cpu_irq));
	ddb_out32(DDB_INTSTAT1, t);
}

void nile4_set_pci_irq_polarity(int pci_irq, int high)
{
	u32 t;

	t = ddb_in32(DDB_INTPPES);
	if (high)
		t &= ~(1 << (pci_irq * 2));
	else
		t |= 1 << (pci_irq * 2);
	ddb_out32(DDB_INTPPES, t);
}

void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
{
	u32 t;

	t = ddb_in32(DDB_INTPPES);
	if (level)
		t |= 2 << (pci_irq * 2);
	else
		t &= ~(2 << (pci_irq * 2));
	ddb_out32(DDB_INTPPES, t);
}

void nile4_clear_irq(int nile4_irq)
{
	ddb_out32(DDB_INTCLR, 1 << nile4_irq);
}

void nile4_clear_irq_mask(u32 mask)
{
	ddb_out32(DDB_INTCLR, mask);
}

u8 nile4_i8259_iack(void)
{
	u8 irq;
	u32 reg;

	/* Set window 0 for interrupt acknowledge */
	reg = ddb_in32(DDB_PCIINIT0);

	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
	irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
	/* restore window 0 for PCI I/O space */
	// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
	ddb_out32(DDB_PCIINIT0, reg);

	/* i8269.c set the base vector to be 0x20, as it does for i386 */
	return irq - 0x20;
}

#if defined(CONFIG_LL_DEBUG)
void nile4_dump_irq_status(void)
{
	printk(KERN_DEBUG "
	       CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
	       (void *) ddb_in32(DDB_CPUSTAT));
	printk(KERN_DEBUG "
	       INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
	       (void *) ddb_in32(DDB_INTCTRL));
	printk(KERN_DEBUG
	       "INTSTAT0 = %p:%p\n",
	       (void *) ddb_in32(DDB_INTSTAT0 + 4),
	       (void *) ddb_in32(DDB_INTSTAT0));
	printk(KERN_DEBUG
	       "INTSTAT1 = %p:%p\n",
	       (void *) ddb_in32(DDB_INTSTAT1 + 4),
	       (void *) ddb_in32(DDB_INTSTAT1));
	printk(KERN_DEBUG
	       "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
	       (void *) ddb_in32(DDB_INTCLR));
	printk(KERN_DEBUG
	       "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
	       (void *) ddb_in32(DDB_INTPPES));
}
#endif

--- NEW FILE: pci.c ---
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>

#include <asm/pci_channel.h>

#include <asm/ddb5xxx/ddb5xxx.h>
#include <asm/ddb5xxx/debug.h>

static struct resource extpci_io_resource = {
	"pci IO space", 
	0x1000,				/* leave some room for ISA bus */
	DDB_PCI_IO_SIZE -1,
	IORESOURCE_IO};

static struct resource extpci_mem_resource = {
	"pci memory space", 
	DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
	DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE -1,
	IORESOURCE_MEM};

extern struct pci_ops ddb5476_ext_pci_ops;

struct pci_channel mips_pci_channels[] = {
	{ &ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource },
	{ NULL, NULL, NULL}
};


/*
 * we fix up irqs based on the slot number.
 * The first entry is at AD:11.
 * 
 * This does not work for devices on sub-buses yet.
 */

/*
 * temporary
 */

#define		PCI_EXT_INTA		8
#define		PCI_EXT_INTB		9
#define		PCI_EXT_INTC		10
#define		PCI_EXT_INTD		11
#define		PCI_EXT_INTE		12

/*
 * based on ddb5477 manual page 11
 */
#define		MAX_SLOT_NUM		21
static unsigned char irq_map[MAX_SLOT_NUM] = {
	/* SLOT:  0, AD:11 */ 0xff,
	/* SLOT:  1, AD:12 */ 0xff,
	/* SLOT:  2, AD:13 */ 9,
	/* SLOT:  3, AD:14 */ 10,
	/* SLOT:  4, AD:15 */ 0xff,
	/* SLOT:  5, AD:16 */ 0xff,
	/* SLOT:  6, AD:17 */ nile4_to_irq(PCI_EXT_INTB),
	/* SLOT:  7, AD:18 */ nile4_to_irq(PCI_EXT_INTC),
	/* SLOT:  8, AD:19 */ nile4_to_irq(PCI_EXT_INTD),
	/* SLOT:  9, AD:20 */ nile4_to_irq(PCI_EXT_INTA),
	/* SLOT: 10, AD:21 */ 0xff,
	/* SLOT: 11, AD:22 */ 0xff,
	/* SLOT: 12, AD:23 */ 0xff,
	/* SLOT: 13, AD:24 */ 14,		/* HD controller, M5229 */
	/* SLOT: 14, AD:25 */ 0xff,
	/* SLOT: 15, AD:26 */ 0xff,
	/* SLOT: 16, AD:27 */ 0xff,
	/* SLOT: 17, AD:28 */ 0xff,
	/* SLOT: 18, AD:29 */ 0xff,
	/* SLOT: 19, AD:30 */ 0xff,
	/* SLOT: 20, AD:31 */ 0xff
};

extern int vrc5477_irq_to_irq(int irq);
void __init pcibios_fixup_irqs(void)
{
        struct pci_dev *dev;
        int slot_num;

	pci_for_each_dev(dev) {
		slot_num = PCI_SLOT(dev->devfn);
		MIPS_ASSERT(slot_num < MAX_SLOT_NUM);
		MIPS_ASSERT(irq_map[slot_num] != 0xff);

		pci_write_config_byte(dev, 
				      PCI_INTERRUPT_LINE,
				      irq_map[slot_num]);
		dev->irq = irq_map[slot_num];
	}
}

#if defined(CONFIG_LL_DEBUG)
extern void jsun_scan_pci_bus(void);
#endif

void __init ddb_pci_reset_bus(void)
{	
	u32 temp;

	/*
	 * I am not sure about the "official" procedure, the following
	 * steps work as far as I know:
	 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
	 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
	 * The same is true for both PCI channels.
	 */
	temp = ddb_in32(DDB_PCICTRL+4);
	temp |= 0x80000000;
	ddb_out32(DDB_PCICTRL+4, temp);
	temp &= ~0xc0000000;
	ddb_out32(DDB_PCICTRL+4, temp);

}

unsigned __init int pcibios_assign_all_busses(void)
{
	/* we hope pci_auto has assigned the bus numbers to all buses */
	return 1;
}

void __init pcibios_fixup_resources(struct pci_dev *dev)
{
}

void __init pcibios_fixup(void)
{
}


--- NEW FILE: pci_ops.c ---
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: Jun Sun, js...@mv... or js...@ju...
 *
 * arch/mips/ddb5xxx/ddb5477/pci_ops.c
 *     Define the pci_ops for DB5477.
 *
 * Much of the code is derived from the original DDB5074 port by 
 * Geert Uytterhoeven <ge...@so...>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#include <linux/config.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/types.h>

#include <asm/addrspace.h>

#include <asm/ddb5xxx/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>

/*
 * config_swap structure records what set of pdar/pmr are used
 * to access pci config space.  It also provides a place hold the
 * original values for future restoring.
 */
struct pci_config_swap {
	u32 	pdar;
	u32	pmr;
	u32	config_base;
	u32	config_size;
	u32	pdar_backup;
	u32	pmr_backup;
};

/*
 * On DDB5476, we have one set of swap registers
 */
struct pci_config_swap ext_pci_swap = {
	DDB_PCIW0,  
	DDB_PCIINIT0,
	DDB_PCI_CONFIG_BASE,
	DDB_PCI_CONFIG_SIZE
};

static int pci_config_workaround=1;

/*
 * access config space
 */	
static inline u32 ddb_access_config_base(struct pci_config_swap *swap,
					 u32 bus,/* 0 means top level bus */
					 u32 slot_num)
{
	u32 pci_addr = 0;
	u32 pciinit_offset = 0;
        u32 virt_addr = swap->config_base;
	u32 option;

	if (pci_config_workaround) {
	/* [jsun] work around Vrc5476 controller itself */
	if (slot_num == 12) slot_num = 0;

	/* BUG : skip P2P bridge for now */
	if (slot_num == 5) slot_num = 0;
	} else {
		if (slot_num == 12) return DDB_BASE + DDB_PCI_BASE;
	}

	/* minimum pdar (window) size is 2MB */
	MIPS_ASSERT(swap->config_size >= (2 << 20));

	MIPS_ASSERT(slot_num < (1 << 5));
	MIPS_ASSERT(bus < (1 << 8));

	/* backup registers */
	swap->pdar_backup = ddb_in32(swap->pdar);
	swap->pmr_backup = ddb_in32(swap->pmr);

	/* set the pdar (pci window) register */
	ddb_set_pdar(swap->pdar,
		     swap->config_base,
		     swap->config_size,
		     32,	/* 32 bit wide */
		     0,		/* not on local memory bus */
		     0);	/* not visible from PCI bus (N/A) */

	/* 
	 * calcuate the absolute pci config addr; 
	 * according to the spec, we start scanning from adr:11 (0x800)
	 */ 
	if (bus == 0) {
		/* type 0 config */
		pci_addr = 0x800 << slot_num;
	} else {
		/* type 1 config */
		pci_addr = (bus << 16) | (slot_num << 11);
		panic("ddb_access_config_base: we don't support type 1 config Yet");
	}

	/*
	 * if pci_addr is less than pci config window size,  we set
	 * pciinit_offset to 0 and adjust the virt_address.
	 * Otherwise we will try to adjust pciinit_offset.
	 */
	if (pci_addr < swap->config_size) {
		virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
		pciinit_offset = 0;
	} else {
		MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0);
		virt_addr = KSEG1ADDR(swap->config_base);
		pciinit_offset = pci_addr;
	}

	/* set the pmr register */
	option = DDB_PCI_ACCESS_32;
	if (bus != 0) option |= DDB_PCI_CFGTYPE1;
	ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);

	return virt_addr;
}

static inline void ddb_close_config_base(struct pci_config_swap *swap)
{
	ddb_out32(swap->pdar, swap->pdar_backup);
	ddb_out32(swap->pmr, swap->pmr_backup);
}

static int read_config_dword(struct pci_config_swap *swap,
			     struct pci_dev *dev,
			     u32 where,
			     u32 *val)
{
	u32 bus, slot_num, func_num;
	u32 base;

	MIPS_ASSERT((where & 3) == 0);
	MIPS_ASSERT(where < (1 << 8));

	/* check if the bus is top-level */
	if (dev->bus->parent != NULL) {
		bus = dev->bus->number;
		MIPS_ASSERT(bus != 0);
	} else {
		bus = 0;
	}

	slot_num = PCI_SLOT(dev->devfn);
	func_num = PCI_FUNC(dev->devfn);
	base = ddb_access_config_base(swap, bus, slot_num);
	*val = *(volatile u32*) (base + (func_num << 8) + where);
	ddb_close_config_base(swap);
	return PCIBIOS_SUCCESSFUL;
}

static int read_config_word(struct pci_config_swap *swap,
			    struct pci_dev *dev,
			    u32 where,
			    u16 *val)
{
        int status;
        u32 result;

	MIPS_ASSERT((where & 1) == 0);

        status = read_config_dword(swap, dev, where & ~3, &result);
        if (where & 2) result >>= 16;
        *val = result & 0xffff;
        return status;
}

static int read_config_byte(struct pci_config_swap *swap,
			    struct pci_dev *dev,
			    u32 where,
			    u8 *val)
{
        int status;
        u32 result;

        status = read_config_dword(swap, dev, where & ~3, &result);
        if (where & 1) result >>= 8;
        if (where & 2) result >>= 16;
        *val = result & 0xff;
        return status;
}

static int write_config_dword(struct pci_config_swap *swap,
			      struct pci_dev *dev,
			      u32 where,
			      u32 val)
{
	u32 bus, slot_num, func_num;
	u32 base;

	MIPS_ASSERT((where & 3) == 0);
	MIPS_ASSERT(where < (1 << 8));

	/* check if the bus is top-level */
	if (dev->bus->parent != NULL) {
		bus = dev->bus->number;
		MIPS_ASSERT(bus != 0);
	} else {
		bus = 0;
	}

	slot_num = PCI_SLOT(dev->devfn);
	func_num = PCI_FUNC(dev->devfn);
	base = ddb_access_config_base(swap, bus, slot_num);
	*(volatile u32*) (base + (func_num << 8) + where) = val; 
	ddb_close_config_base(swap);
	return PCIBIOS_SUCCESSFUL;
}

static int write_config_word(struct pci_config_swap *swap,
			     struct pci_dev *dev,
			     u32 where,
			     u16 val)
{
	int status, shift=0;
	u32 result;

	MIPS_ASSERT((where & 1) == 0);

	status = read_config_dword(swap, dev, where & ~3, &result);
	if (status != PCIBIOS_SUCCESSFUL) return status;

        if (where & 2)
                shift += 16;
        result &= ~(0xffff << shift);
        result |= val << shift;
        return write_config_dword(swap, dev, where & ~3, result);
}

static int write_config_byte(struct pci_config_swap *swap,
			     struct pci_dev *dev,
			     u32 where,
			     u8 val)
{
	int status, shift=0;
	u32 result;

	status = read_config_dword(swap, dev, where & ~3, &result);
	if (status != PCIBIOS_SUCCESSFUL) return status;

        if (where & 2)
                shift += 16;
        if (where & 1)
                shift += 8;
        result &= ~(0xff << shift);
        result |= val << shift;
        return write_config_dword(swap, dev, where & ~3, result);
}

#define	MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
{ \
     return rw##_config_##unitname(pciswap, \
                                   dev, \
                                   where, \
                                   val); \
}

MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)

MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)

struct pci_ops ddb5476_ext_pci_ops ={
	extpci_read_config_byte,
	extpci_read_config_word,
	extpci_read_config_dword,
	extpci_write_config_byte,
	extpci_write_config_word,
	extpci_write_config_dword
};


#if defined(CONFIG_LL_DEBUG)
void jsun_scan_pci_bus(void)
{
	struct pci_bus bus;
	struct pci_dev dev;
	unsigned int devfn;
	int j;

	pci_config_workaround = 0;

	bus.parent = NULL;	/* we scan the top level only */
	dev.bus = &bus;
	dev.sysdata = NULL;

	/* scan ext pci bus and io pci bus*/
	for (j=0; j< 1; j++) {
		printk(KERN_INFO "scan ddb5476 external PCI bus:\n");
		bus.ops = &ddb5476_ext_pci_ops;
	
		for (devfn = 0; devfn < 0x100; devfn += 8) {
			u32 temp;
			u16 temp16;
			u8 temp8;
			int i;

			dev.devfn = devfn;
			MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp),
				    == PCIBIOS_SUCCESSFUL);
			if (temp == 0xffffffff) continue;

			printk(KERN_INFO "slot %d: (addr %d) \n", devfn/8,
			       11+devfn/8);

			/* verify read word and byte */
			MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16),
				    == PCIBIOS_SUCCESSFUL);
			MIPS_ASSERT(temp16 == (temp >> 16));
			MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8),
				    == PCIBIOS_SUCCESSFUL);
			MIPS_ASSERT(temp8 == (temp >> 24));
			MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8),
				    == PCIBIOS_SUCCESSFUL);
			MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff));

			for (i=0; i < 16; i++) {
				if ((i%4) == 0)
					printk(KERN_INFO);
				MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp),
					    == PCIBIOS_SUCCESSFUL);
				printk("\t%08X", temp);
				if ((i%4) == 3)
					printk("\n");
			}
		}
	}

	pci_config_workaround = 1;
}
#endif

--- NEW FILE: setup.c ---
/*
 *  arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
 *
 *  Copyright (C) 2000 Geert Uytterhoeven <ge...@so...>
 *                     Sony Software Development Center Europe (SDCE), Brussels
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kbd_ll.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/console.h>
#include <linux/sched.h>
#include <linux/mc146818rtc.h>
#include <linux/pc_keyb.h>
#include <linux/pci.h>
#include <linux/ide.h>

#include <asm/addrspace.h>
#include <asm/bcache.h>
#include <asm/keyboard.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/time.h>

#include <asm/ddb5xxx/ddb5xxx.h>

#ifdef CONFIG_REMOTE_DEBUG
extern void rs_kgdb_hook(int);
extern void breakpoint(void);
#endif

#if defined(CONFIG_SERIAL_CONSOLE)
extern void console_setup(char *);
#endif

extern struct ide_ops std_ide_ops;
extern struct kbd_ops std_kbd_ops;

static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;

static void ddb_machine_restart(char *command)
{
	u32 t;

	/* PCI cold reset */
	t = ddb_in32(DDB_PCICTRL + 4);
	t |= 0x40000000;
	ddb_out32(DDB_PCICTRL + 4, t);
	/* CPU cold reset */
	t = ddb_in32(DDB_CPUSTAT);
	t |= 1;
	ddb_out32(DDB_CPUSTAT, t);
	/* Call the PROM */
	back_to_prom();
}

static void ddb_machine_halt(void)
{
	printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
	while (1);
}

static void ddb_machine_power_off(void)
{
	printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
	while (1);
}

extern void ddb_irq_setup(void);
extern void rtc_ds1386_init(unsigned long base);

static void __init ddb_time_init(void)
{
	mips_counter_frequency = 83000000;

	/* we have ds1396 RTC chip */
	rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));

	/* optional: we don't have a good way to set RTC time,
	 * so we will hack here to set a time.  In normal running.
	 * it should *not* be called becaues RTC will keep the correct time.
	 */
	/* rtc_set_time(mktime(2001, 10, 05, 17, 20, 0)); */
}


extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void __init ddb_timer_setup(struct irqaction *irq)
{
	unsigned int count;

	/* we are using the cpu counter for timer interrupts */
	setup_irq(CPU_IRQ_BASE + 7, irq);

	/* to generate the first timer interrupt */
	count = read_32bit_cp0_register(CP0_COUNT);
	write_32bit_cp0_register(CP0_COMPARE, count + 1000);
}

static struct {
	struct resource dma1;
	struct resource pic1;
	struct resource timer;
	struct resource rtc;
	struct resource dma_page_reg;
	struct resource pic2;
	struct resource dma2;
} ddb5476_ioport = {
	{
	"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
	"pic1", 0x20, 0x3f, IORESOURCE_BUSY}, {
	"timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
	"rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
	"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
	"pic2", 0xa0, 0xbf, IORESOURCE_BUSY}, {
	"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
};

static struct {
	struct resource nile4;
} ddb5476_iomem = {
	{ "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
};

static void ddb5476_board_init(void);
extern void ddb5476_irq_setup(void);
extern void (*irq_setup)(void);

void __init 
ddb_setup(void)
{
	extern int panic_timeout;

	irq_setup = ddb5476_irq_setup;
	mips_io_port_base = KSEG1ADDR(DDB_PCI_IO_BASE);

	board_time_init = ddb_time_init;
	board_timer_setup = ddb_timer_setup;

	_machine_restart = ddb_machine_restart;
	_machine_halt = ddb_machine_halt;
	_machine_power_off = ddb_machine_power_off;

	/* request io port/mem resources  */
	if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
	    request_resource(&ioport_resource, &ddb5476_ioport.pic1) ||
	    request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
	    request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
	    request_resource(&ioport_resource,
			     &ddb5476_ioport.dma_page_reg)
	    || request_resource(&ioport_resource, &ddb5476_ioport.pic2)
	    || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
	    || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
		printk
		    ("ddb_setup - requesting oo port resources failed.\n");
		for (;;);
	}
#ifdef CONFIG_BLK_DEV_IDE
	ide_ops = &std_ide_ops;
#endif

#ifdef CONFIG_PC_KEYB
	kbd_ops = &std_kbd_ops;
#endif

	/* Reboot on panic */
	panic_timeout = 180;

	/* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
	/* *(long*)0xbfa00218 = 0x8; */

#ifdef CONFIG_FB
	conswitchp = &dummy_con;
#endif

	/* board initialization stuff */
	ddb5476_board_init();
}

/*
 * We don't trust bios.  We essentially does hardware re-initialization
 * as complete as possible, as far as we know we can safely do.
 */
static void 
ddb5476_board_init(void)
{
	/* ----------- setup PDARs ------------ */
	/* check SDRAM0, whether we are on MEM bus does not matter */
	MIPS_ASSERT((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
		    ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));

	/* SDRAM1 should be turned off.  What is this for anyway ? */
	MIPS_ASSERT( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);

	/* flash 1&2, DDB status, DDB control */
	ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
	ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
	ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
	ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);

	/* shut off other pdar so they don't accidentally get into the way */
	ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
	ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
	ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);

	/* verify VRC5477 base addr */
	/* don't care about some details */
	MIPS_ASSERT((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
		    ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));

	/* verify BOOT ROM addr */
	/* don't care about some details */
	MIPS_ASSERT((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
		    ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));

	/* setup PCI windows - window1 for MEM/config, window0 for IO */
	ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);

	ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);

	/* ----------- setup PDARs ------------ */
	/* this is problematic - it will reset Aladin which cause we loose
	 * serial port, and we don't know how to set up Aladin chip again.
	 */
	// ddb_pci_reset_bus(); 

	ddb_out32(DDB_BAR0, 0x00000008);

	ddb_out32(DDB_BARC, 0xffffffff);
	ddb_out32(DDB_BARB, 0xffffffff);
	ddb_out32(DDB_BAR1, 0xffffffff);
	ddb_out32(DDB_BAR2, 0xffffffff);
	ddb_out32(DDB_BAR3, 0xffffffff);
	ddb_out32(DDB_BAR4, 0xffffffff);
	ddb_out32(DDB_BAR5, 0xffffffff);
	ddb_out32(DDB_BAR6, 0xffffffff);
	ddb_out32(DDB_BAR7, 0xffffffff);
	ddb_out32(DDB_BAR8, 0xffffffff);

	/* ----------- switch PCI1 to PCI CONFIG space  ------------ */
	ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);

	/* ----- M1543 PCI setup ------ */

	/* we know M1543 PCI-ISA controller is at addr:18 */
	/* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
	*(volatile unsigned char *) 0xa8040072 &= 0xf0;
	*(volatile unsigned char *) 0xa8040072 |= 0xa;

	/* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
	 * no IOCHRDY signal, (bit 7 - 1)
	 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
	 * Bypass USB Master INTAJ level to edge conversion (bit 4 - 0)
	 */
	*(unsigned char *) 0xa8040074 = 0xc1;

	/* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
	 * SCI routing to IRQ 13 disabled (bit 7 - 1)
	 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
	 */
	*(unsigned char *) 0xa8040076 = 0x83;

	/* setup IDE controller
	 * enable IDE controller (bit 6 - 1)
	 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
	 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
	 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
	 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
	 */
	// *(unsigned char*)0xa8040058 = 0x71;
	// *(unsigned char*)0xa8040058 = 0x79;
	// *(unsigned char*)0xa8040058 = 0x74;              // use SIRQ, primary tri-state
	*(unsigned char *) 0xa8040058 = 0x75;	// primary tri-state

#if 0
	/* this is not necessary if M5229 does not use SIRQ */
	*(unsigned char *) 0xa8040044 = 0x0d;	// primary to IRQ 14
	*(unsigned char *) 0xa8040075 = 0x0d;	// secondary to IRQ 14
#endif

	/* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
	/* M5229 IDSEL is addr:24; see above setting */
	*(unsigned char *) 0xa9000050 |= 0x1;

	/* enable bus master (bit 2)  and IO decoding  (bit 0) */
	*(unsigned char *) 0xa9000004 |= 0x5;

	/* enable native, copied from arch/ppc/k2boot/head.S */
	/* TODO - need volatile, need to be portable */
	*(unsigned char *) 0xa9000009 = 0xff;

	/* ----- end of M1543 PCI setup ------ */

	/* ----- reset on-board ether chip  ------ */
	*((volatile u32 *) 0xa8020004) |= 1;	/* decode I/O */
	*((volatile u32 *) 0xa8020010) = 0;	/* set BAR address */

	/* send reset command */
	*((volatile u32 *) 0xa6000000) = 1;	/* do a soft reset */

	/* disable ether chip */
	*((volatile u32 *) 0xa8020004) = 0;	/* disable any decoding */

	/* put it into sleep */
	*((volatile u32 *) 0xa8020040) = 0x80000000;

	/* ----- end of reset on-board ether chip  ------ */

	/* ----------- switch PCI1 back to PCI MEM space  ------------ */
	ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
}

--- NEW FILE: vrc5476_irq.c ---
/*
 * The irq controller for vrc5476.
 *
 * Copyright (C) 2001 MontaVista Software Inc.
 * Author: js...@mv... or js...@ju...
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/ptrace.h>

#include <asm/system.h>

#include <asm/ddb5xxx/ddb5xxx.h>
#include <asm/ddb5xxx/debug.h>

static int irq_base;

static void vrc5476_irq_enable(uint irq)
{
	nile4_enable_irq(irq - irq_base);
}

static void vrc5476_irq_disable(uint irq)
{
	nile4_disable_irq(irq - irq_base);
}

static unsigned int vrc5476_irq_startup(uint irq)
{
	nile4_enable_irq(irq - irq_base);
	return 0;
}

#define vrc5476_irq_shutdown	vrc5476_irq_disable

static void vrc5476_irq_ack(uint irq)
{
	nile4_clear_irq(irq - irq_base);
	nile4_disable_irq(irq - irq_base);
}

#define	vrc5476_irq_end		vrc5476_irq_enable

static hw_irq_controller vrc5476_irq_controller = {
	"vrc5476",
	vrc5476_irq_startup,
	vrc5476_irq_shutdown,
	vrc5476_irq_enable,
	vrc5476_irq_disable,
	vrc5476_irq_ack,
	vrc5476_irq_end,
	NULL				/* no affinity stuff for UP */
};

void __init 
vrc5476_irq_init(u32 base)
{
	extern irq_desc_t irq_desc[];
	u32 i;

	irq_base = base;
	for (i= base; i< base + NUM_VRC5476_IRQ; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		 irq_desc[i].depth = 1;
		 irq_desc[i].handler = &vrc5476_irq_controller;
	}
}


asmlinkage void 
vrc5476_irq_dispatch(struct pt_regs *regs)
{
	extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
	extern void spurious_interrupt(void);

	u32 mask;
	int nile4_irq;

	mask = nile4_get_irq_stat(0);

	/* quick check for possible time interrupt */
	if (mask & (1 << VRC5476_IRQ_GPT)) {
		do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs);
		return;
	}

	/* check for i8259 interrupts */
	if (mask & (1 << VRC5476_I8259_CASCADE)) {
		int i8259_irq = nile4_i8259_iack();
		do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
		return;
	}

	/* regular nile4 interrupts (we should not really have any */
	for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) {
		if (mask & 1) {
			do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs);
			return;
		}
	}
	spurious_interrupt();
}

[Linux-mips-commits]CVS: linux/arch/mips/ddb5476 int-handler.S,1.1.1.1,NONE pci.c,1.1,NONE setup.c,1.1.1.1,NONE

[Jun S. <ju...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ddb5476
In directory usw-pr-cvs1:/tmp/cvs-serv16561/arch/mips/ddb5476

Removed Files:
	int-handler.S pci.c setup.c 
Log Message:
Update DDB5476 and sync up with oss tree.


--- int-handler.S DELETED ---

--- pci.c DELETED ---

--- setup.c DELETED ---

[Linux-mips-commits]CVS: linux/arch/mips/configs defconfig-ddb5476,1.8,1.9

[Jun S. <ju...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/configs
In directory usw-pr-cvs1:/tmp/cvs-serv16561/arch/mips/configs

Modified Files:
	defconfig-ddb5476 
Log Message:
Update DDB5476 and sync up with oss tree.


Index: defconfig-ddb5476
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-ddb5476,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- defconfig-ddb5476	2001/10/02 18:35:48	1.8
+++ defconfig-ddb5476	2001/10/07 05:40:22	1.9
@@ -18,6 +18,7 @@
 # CONFIG_COBALT_MICRO_SERVER is not set
 # CONFIG_DECSTATION is not set
 # CONFIG_DDB5074 is not set
+# CONFIG_NEC_OSPREY is not set
 # CONFIG_NEC_EAGLE is not set
 # CONFIG_NEC_KORVA is not set
 # CONFIG_MIPS_EV96100 is not set
@@ -44,11 +45,14 @@
 CONFIG_ISA=y
 CONFIG_PCI=y
 CONFIG_PC_KEYB=y
-CONFIG_ROTTEN_IRQ=y
+CONFIG_NEW_IRQ=y
+CONFIG_IRQ_CPU=y
+CONFIG_I8259=y
 CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+CONFIG_NEW_PCI=y
+CONFIG_PCI_AUTO=y
 CONFIG_NEW_TIME_C=y
 CONFIG_EISA=y
-# CONFIG_I8259 is not set
 
 #
 # Loadable module support
@@ -253,7 +257,6 @@
 # CONFIG_PDC202XX_BURST is not set
 # CONFIG_PDC202XX_FORCE is not set
 # CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_OSB4 is not set
 # CONFIG_BLK_DEV_SIS5513 is not set
 # CONFIG_BLK_DEV_SLC90E66 is not set
 # CONFIG_BLK_DEV_TRM290 is not set
@@ -547,16 +550,16 @@
 # CONFIG_FB_CLGEN is not set
 # CONFIG_FB_PM2 is not set
 # CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_E1355 is not set
 # CONFIG_FB_PVR2 is not set
 # CONFIG_FB_PVR2_DEBUG is not set
-# CONFIG_FB_E1355 is not set
-# CONFIG_FB_E1356 is not set
 # CONFIG_FB_MQ200 is not set
 # CONFIG_FB_MATROX is not set
 # CONFIG_FB_ATY is not set
 # CONFIG_FB_ATY128 is not set
 CONFIG_FB_3DFX=y
 # CONFIG_FB_SIS is not set
+# CONFIG_FB_E1356 is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FBCON_ADVANCED is not set
 CONFIG_FBCON_CFB8=y
@@ -588,6 +591,6 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_GDB_CONSOLE is not set
-# CONFIG_LL_DEBUG is not set
+CONFIG_LL_DEBUG=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_MIPS_UNCACHED is not set

[Linux-mips-commits]CVS: linux/arch/mips Makefile,1.19,1.20 config.in,1.29,1.30

[Jun S. <ju...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv16561/arch/mips

Modified Files:
	Makefile config.in 
Log Message:
Update DDB5476 and sync up with oss tree.


Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -d -r1.19 -r1.20
--- Makefile	2001/10/05 21:04:45	1.19
+++ Makefile	2001/10/07 05:40:22	1.20
@@ -201,8 +201,9 @@
 # NEC DDB Vrc-5476
 #
 ifdef CONFIG_DDB5476
-SUBDIRS       += arch/mips/ddb5476
-LIBS          += arch/mips/ddb5476/ddb5476.a
+SUBDIRS       += arch/mips/ddb5xxx/common arch/mips/ddb5xxx/ddb5476
+LIBS          += arch/mips/ddb5xxx/common/ddb5xxx.o \
+		 arch/mips/ddb5xxx/ddb5476/ddb5476.o
 LOADADDR      += 0x80080000
 endif
 

Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.29
retrieving revision 1.30
diff -u -d -r1.29 -r1.30
--- config.in	2001/10/02 17:18:31	1.29
+++ config.in	2001/10/07 05:40:22	1.30
@@ -169,8 +169,12 @@
    define_bool CONFIG_ISA y
    define_bool CONFIG_PCI y
    define_bool CONFIG_PC_KEYB y
-   define_bool CONFIG_ROTTEN_IRQ y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_IRQ_CPU y
+   define_bool CONFIG_I8259 y
    define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_PCI_AUTO y
    define_bool CONFIG_NEW_TIME_C y
 fi
 if [ "$CONFIG_DDB5477" = "y" ]; then

[Linux-mips-commits]CVS: linux/arch/mips/ddb5xxx/ddb5476 - New directory

[Jun S. <ju...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476
In directory usw-pr-cvs1:/tmp/cvs-serv13381/ddb5476

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476 added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/philips/nino Makefile,1.1.1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino
In directory usw-pr-cvs1:/tmp/cvs-serv18373

Modified Files:
	Makefile 
Log Message:
Now use the generic ramdisk support.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/Makefile,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- Makefile	2001/06/22 02:29:32	1.1.1.1
+++ Makefile	2001/10/05 21:29:43	1.2
@@ -21,12 +21,6 @@
 
 obj-$(CONFIG_REMOTE_DEBUG)	+= kgdb.o
 
-obj-$(CONFIG_BLK_DEV_INITRD)	+= ramdisk.o
-
-ramdisk.o:
-		$(MAKE) -C ramdisk
-		mv ramdisk/ramdisk.o ramdisk.o
-
 clean:
 		rm -f *.o
 

[Linux-mips-commits]CVS: linux/arch/mips/philips/nino/ramdisk Makefile,1.1.1.1,NONE ld.script,1.1.1.1,NONE

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino/ramdisk
In directory usw-pr-cvs1:/tmp/cvs-serv17843

Removed Files:
	Makefile ld.script 
Log Message:
Now use the generic ramdisk support.

--- Makefile DELETED ---

--- ld.script DELETED ---

[Linux-mips-commits]CVS: linux/arch/mips/korva Makefile,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/korva
In directory usw-pr-cvs1:/tmp/cvs-serv17029

Modified Files:
	Makefile 
Log Message:
Now use the generic ramdisk support.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile	2001/09/17 17:02:29	1.2
+++ Makefile	2001/10/05 21:26:19	1.3
@@ -16,7 +16,6 @@
 obj-y    := setup.o prom.o reset.o int_handler.o irq.o irq_cpu.o irq_korva.o \
 		candy_setup.o
 
-obj-$(CONFIG_BLK_DEV_INITRD)    += ramdisk.o
 obj-$(CONFIG_REMOTE_DEBUG)      += dbg_io.o
 
 include $(TOPDIR)/Rules.make

[Linux-mips-commits]CVS: linux/arch/mips/ite-boards/qed-4n-s01b Makefile,1.1.1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ite-boards/qed-4n-s01b
In directory usw-pr-cvs1:/tmp/cvs-serv16685

Modified Files:
	Makefile 
Log Message:
Now use the generic ramdisk support.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ite-boards/qed-4n-s01b/Makefile,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- Makefile	2001/06/22 02:29:31	1.1.1.1
+++ Makefile	2001/10/05 21:25:32	1.2
@@ -26,11 +26,6 @@
 obj-y += pci_fixup.o
 endif
 
-ifdef CONFIG_BLK_DEV_INITRD
-obj-y += le_ramdisk.o
-endif
-
-
 dep:
 	$(CPP) -M *.c > .depend
 

[Linux-mips-commits]CVS: linux/arch/mips/ddb5xxx/ddb5477 Makefile,1.1.1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477
In directory usw-pr-cvs1:/tmp/cvs-serv16171

Modified Files:
	Makefile 
Log Message:
Now use the generic ramdisk support.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/Makefile,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- Makefile	2001/06/22 02:29:31	1.1.1.1
+++ Makefile	2001/10/05 21:24:19	1.2
@@ -17,6 +17,5 @@
 
 obj-$(CONFIG_LL_DEBUG) 		+= debug.o
 obj-$(CONFIG_REMOTE_DEBUG)	+= kgdb_io.o
-obj-$(CONFIG_BLK_DEV_INITRD)	+= ramdisk.o
 
 include $(TOPDIR)/Rules.make

[Linux-mips-commits]CVS: linux/arch/mips Makefile,1.18,1.19

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv7029

Modified Files:
	Makefile 
Log Message:
Added generic ramdisk support based on Pete's work.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -d -r1.18 -r1.19
--- Makefile	2001/09/29 00:42:25	1.18
+++ Makefile	2001/10/05 21:04:45	1.19
@@ -103,6 +103,16 @@
 SUBDIRS		+=arch/mips/math-emu
 
 #
+# ramdisk/initrd support
+# You need a compressed ramdisk image, named ramdisk.gz in
+# arch/mips/ramdisk
+#
+ifdef CONFIG_BLK_DEV_INITRD
+CORE_FILES	+= arch/mips/ramdisk/ramdisk.o
+SUBDIRS		+= arch/mips/ramdisk
+endif
+
+#
 # Board-dependent options and extra files
 #
 ifdef CONFIG_ALGOR_P4032

[Linux-mips-commits]CVS: linux/arch/mips/ramdisk Makefile,NONE,1.1 ld.script.in,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ramdisk
In directory usw-pr-cvs1:/tmp/cvs-serv7029/ramdisk

Added Files:
	Makefile ld.script.in 
Log Message:
Added generic ramdisk support based on Pete's work.

--- NEW FILE: Makefile ---
#
# Makefile for a ramdisk image
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

ramdisk.o: ramdisk.gz ld.script
	$(LD) -T ld.script -b binary -o $@ ramdisk.gz

include $(TOPDIR)/Rules.make


--- NEW FILE: ld.script.in ---
OUTPUT_ARCH(mips)
SECTIONS
{
  .initrd :
  {
       *(.data)
  }
}

[Linux-mips-commits]CVS: linux/arch/mips/ramdisk - New directory

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ramdisk
In directory usw-pr-cvs1:/tmp/cvs-serv1739/ramdisk

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/ramdisk added to the repository

[Linux-mips-commits]CVS: linux/arch/mips64/sgi-ip27 ip27-irq.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27
In directory usw-pr-cvs1:/tmp/cvs-serv1183

Modified Files:
	ip27-irq.c 
Log Message:
Move generic SMP code to where it should be.

Index: ip27-irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27/ip27-irq.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- ip27-irq.c	2001/08/24 18:59:54	1.3
+++ ip27-irq.c	2001/10/05 17:17:08	1.4
@@ -440,189 +440,6 @@
 	set_except_vector(0, ip27_irq);
 }
 
-#ifdef CONFIG_SMP
-
-/*
- * This following are the global intr on off routines, copied almost
- * entirely from i386 code.
- */
-
-int global_irq_holder = NO_PROC_ID;
-spinlock_t global_irq_lock = SPIN_LOCK_UNLOCKED;
-
-extern void show_stack(unsigned long* esp);
-
-static void show(char * str)
-{
-	int i;
-	int cpu = smp_processor_id();
-
-	printk("\n%s, CPU %d:\n", str, cpu);
-	printk("irq:  %d [",irqs_running());
-	for(i=0;i < smp_num_cpus;i++)
-		printk(" %d",local_irq_count(i));
-	printk(" ]\nbh:   %d [",spin_is_locked(&global_bh_lock) ? 1 : 0);
-	for(i=0;i < smp_num_cpus;i++)
-		printk(" %d",local_bh_count(i));
-
-	printk(" ]\nStack dumps:");
-	for(i = 0; i < smp_num_cpus; i++) {
-		if (i == cpu)
-			continue;
-		printk("\nCPU %d:",i);
-		printk("Code not developed yet\n");
-		/* show_stack(0); */
-	}
-	printk("\nCPU %d:",cpu);
-	printk("Code not developed yet\n");
-	/* show_stack(NULL); */
-	printk("\n");
-}
-
-#define MAXCOUNT 		100000000
-#define SYNC_OTHER_CORES(x)	udelay(x+1)
-
-static inline void wait_on_irq(int cpu)
-{
-	int count = MAXCOUNT;
-
-	for (;;) {
-
-		/*
-		 * Wait until all interrupts are gone. Wait
-		 * for bottom half handlers unless we're
-		 * already executing in one..
-		 */
-		if (!irqs_running())
-			if (local_bh_count(cpu) || !spin_is_locked(&global_bh_lock))
-				break;
-
-		/* Duh, we have to loop. Release the lock to avoid deadlocks */
-		spin_unlock(&global_irq_lock);
-
-		for (;;) {
-			if (!--count) {
-				show("wait_on_irq");
-				count = ~0;
-			}
-			__sti();
-			SYNC_OTHER_CORES(cpu);
-			__cli();
-			if (irqs_running())
-				continue;
-			if (spin_is_locked(&global_irq_lock))
-				continue;
-			if (!local_bh_count(cpu) && spin_is_locked(&global_bh_lock))
-				continue;
-			if (spin_trylock(&global_irq_lock))
-				break;
-		}
-	}
-}
-
-void synchronize_irq(void)
-{
-	if (irqs_running()) {
-		/* Stupid approach */
-		cli();
-		sti();
-	}
-}
-
-static inline void get_irqlock(int cpu)
-{
-	if (!spin_trylock(&global_irq_lock)) {
-		/* do we already hold the lock? */
-		if ((unsigned char) cpu == global_irq_holder)
-			return;
-		/* Uhhuh.. Somebody else got it. Wait.. */
-		spin_lock(&global_irq_lock);
-	}
-	/*
-	 * We also to make sure that nobody else is running
-	 * in an interrupt context.
-	 */
-	wait_on_irq(cpu);
-
-	/*
-	 * Ok, finally..
-	 */
-	global_irq_holder = cpu;
-}
-
-void __global_cli(void)
-{
-	unsigned int flags;
-
-	__save_flags(flags);
-	if (flags & ST0_IE) {
-		int cpu = smp_processor_id();
-		__cli();
-		if (!local_irq_count(cpu))
-			get_irqlock(cpu);
-	}
-}
-
-void __global_sti(void)
-{
-	int cpu = smp_processor_id();
-
-	if (!local_irq_count(cpu))
-		release_irqlock(cpu);
-	__sti();
-}
-
-/*
- * SMP flags value to restore to:
- * 0 - global cli
- * 1 - global sti
- * 2 - local cli
- * 3 - local sti
- */
-unsigned long __global_save_flags(void)
-{
-	int retval;
-	int local_enabled;
-	unsigned long flags;
-	int cpu = smp_processor_id();
-
-	__save_flags(flags);
-	local_enabled = (flags & ST0_IE);
-	/* default to local */
-	retval = 2 + local_enabled;
-
-	/* check for global flags if we're not in an interrupt */
-	if (!local_irq_count(cpu)) {
-		if (local_enabled)
-			retval = 1;
-		if (global_irq_holder == cpu)
-			retval = 0;
-	}
-	return retval;
-}
-
-void __global_restore_flags(unsigned long flags)
-{
-	switch (flags) {
-		case 0:
-			__global_cli();
-			break;
-		case 1:
-			__global_sti();
-			break;
-		case 2:
-			__cli();
-			break;
-		case 3:
-			__sti();
-			break;
-		default:
-			printk("global_restore_flags: %08lx\n", flags);
-	}
-}
-
-#endif /* CONFIG_SMP */
-
 /*
  * Get values that vary depending on which CPU and bit we're operating on.
  */

[Linux-mips-commits]CVS: linux/arch/mips64/kernel smp.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv32358

Modified Files:
	smp.c 
Log Message:
Move generic SMP code to where it should be.

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/smp.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- smp.c	2001/10/04 15:49:40	1.3
+++ smp.c	2001/10/05 17:15:12	1.4
@@ -8,7 +8,9 @@
  * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
  */
 #include <linux/config.h>
+#include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/spinlock.h>
 #include <linux/threads.h>
 #include <linux/time.h>
@@ -122,6 +124,184 @@
 }
 
 /*
+ * This following are the global intr on off routines, copied almost
+ * entirely from i386 code.
+ */
+
+int global_irq_holder = NO_PROC_ID;
+spinlock_t global_irq_lock = SPIN_LOCK_UNLOCKED;
+
+extern void show_stack(unsigned long* esp);
+
+static void show(char * str)
+{
+	int i;
+	int cpu = smp_processor_id();
+
+	printk("\n%s, CPU %d:\n", str, cpu);
+	printk("irq:  %d [",irqs_running());
+	for(i=0;i < smp_num_cpus;i++)
+		printk(" %d",local_irq_count(i));
+	printk(" ]\nbh:   %d [",spin_is_locked(&global_bh_lock) ? 1 : 0);
+	for(i=0;i < smp_num_cpus;i++)
+		printk(" %d",local_bh_count(i));
+
+	printk(" ]\nStack dumps:");
+	for(i = 0; i < smp_num_cpus; i++) {
+		if (i == cpu)
+			continue;
+		printk("\nCPU %d:",i);
+		printk("Code not developed yet\n");
+		/* show_stack(0); */
+	}
+	printk("\nCPU %d:",cpu);
+	printk("Code not developed yet\n");
+	/* show_stack(NULL); */
+	printk("\n");
+}
+
+#define MAXCOUNT 		100000000
+#define SYNC_OTHER_CORES(x)	udelay(x+1)
+
+static inline void wait_on_irq(int cpu)
+{
+	int count = MAXCOUNT;
+
+	for (;;) {
+
+		/*
+		 * Wait until all interrupts are gone. Wait
+		 * for bottom half handlers unless we're
+		 * already executing in one..
+		 */
+		if (!irqs_running())
+			if (local_bh_count(cpu) || !spin_is_locked(&global_bh_lock))
+				break;
+
+		/* Duh, we have to loop. Release the lock to avoid deadlocks */
+		spin_unlock(&global_irq_lock);
+
+		for (;;) {
+			if (!--count) {
+				show("wait_on_irq");
+				count = ~0;
+			}
+			__sti();
+			SYNC_OTHER_CORES(cpu);
+			__cli();
+			if (irqs_running())
+				continue;
+			if (spin_is_locked(&global_irq_lock))
+				continue;
+			if (!local_bh_count(cpu) && spin_is_locked(&global_bh_lock))
+				continue;
+			if (spin_trylock(&global_irq_lock))
+				break;
+		}
+	}
+}
+
+void synchronize_irq(void)
+{
+	if (irqs_running()) {
+		/* Stupid approach */
+		cli();
+		sti();
+	}
+}
+
+static inline void get_irqlock(int cpu)
+{
+	if (!spin_trylock(&global_irq_lock)) {
+		/* do we already hold the lock? */
+		if ((unsigned char) cpu == global_irq_holder)
+			return;
+		/* Uhhuh.. Somebody else got it. Wait.. */
+		spin_lock(&global_irq_lock);
+	}
+	/*
+	 * We also to make sure that nobody else is running
+	 * in an interrupt context.
+	 */
+	wait_on_irq(cpu);
+
+	/*
+	 * Ok, finally..
+	 */
+	global_irq_holder = cpu;
+}
+
+void __global_cli(void)
+{
+	unsigned int flags;
+
+	__save_flags(flags);
+	if (flags & ST0_IE) {
+		int cpu = smp_processor_id();
+		__cli();
+		if (!local_irq_count(cpu))
+			get_irqlock(cpu);
+	}
+}
+
+void __global_sti(void)
+{
+	int cpu = smp_processor_id();
+
+	if (!local_irq_count(cpu))
+		release_irqlock(cpu);
+	__sti();
+}
+
+/*
+ * SMP flags value to restore to:
+ * 0 - global cli
+ * 1 - global sti
+ * 2 - local cli
+ * 3 - local sti
+ */
+unsigned long __global_save_flags(void)
+{
+	int retval;
+	int local_enabled;
+	unsigned long flags;
+	int cpu = smp_processor_id();
+
+	__save_flags(flags);
+	local_enabled = (flags & ST0_IE);
+	/* default to local */
+	retval = 2 + local_enabled;
+
+	/* check for global flags if we're not in an interrupt */
+	if (!local_irq_count(cpu)) {
+		if (local_enabled)
+			retval = 1;
+		if (global_irq_holder == cpu)
+			retval = 0;
+	}
+	return retval;
+}
+
+void __global_restore_flags(unsigned long flags)
+{
+	switch (flags) {
+		case 0:
+			__global_cli();
+			break;
+		case 1:
+			__global_sti();
+			break;
+		case 2:
+			__cli();
+			break;
+		case 3:
+			__sti();
+			break;
+		default:
+			printk("global_restore_flags: %08lx\n", flags);
+	}
+}
+/*
  * Run a function on all other CPUs.
  *  <func>      The function to run. This must be fast and non-blocking.
  *  <info>      An arbitrary pointer to pass to the function.
@@ -294,4 +474,3 @@
 	}
 	_flush_tlb_page(vma, page);
 }
-

[Linux-mips-commits]CVS: linux/arch/mips/kernel process.c,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv30327/kernel

Modified Files:
	process.c 
Log Message:
Remove remaining  clobbers.

Index: process.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/process.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- process.c	2001/07/12 18:55:01	1.2
+++ process.c	2001/10/05 17:10:56	1.3
@@ -174,16 +174,15 @@
 		"1:  addiu   $sp,32           \n"
 		"    move    %0,$2            \n"
 		".set reorder"
-		:"=r" (retval)
-		:"i" (__NR_clone), "i" (__NR_exit),
-		 "r" (arg), "r" (fn),
-		 "r" (flags | CLONE_VM)
+		: "=r" (retval)
+		: "i" (__NR_clone), "i" (__NR_exit), "r" (arg), "r" (fn),
+		  "r" (flags | CLONE_VM)
 		 /*
 		  * The called subroutine might have destroyed any of the
 		  * at, result, argument or temporary registers ...
 		  */
-		:"$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
-		 "$9","$10","$11","$12","$13","$14","$15","$24","$25");
+		: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		  "$9","$10","$11","$12","$13","$14","$15","$24","$25");
 
 	return retval;
 }

[Linux-mips-commits]CVS: linux/arch/mips/mm pg-andes.c,NONE,1.1 pg-mips32.c,NONE,1.1 pg-r2300.c,NONE,1.1 pg-r5432.c,NONE,1.1 pg-rm7k.c,NONE,1.1 sb1.c,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv30327/mm

Added Files:
	pg-andes.c pg-mips32.c pg-r2300.c pg-r5432.c pg-rm7k.c sb1.c 
Log Message:
Remove remaining  clobbers.

--- NEW FILE: pg-andes.c ---
/*
 * andes.c: MMU and cache operations for the R10000 (ANDES).
 *
 * Copyright (C) 1996 David S. Miller (dm...@en...)
 */
#include <asm/page.h>

/* page functions */
void andes_clear_page(void * page)
{
	__asm__ __volatile__(
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		"addiu\t$1,%0,%2\n"
		"1:\tsw\t$0,(%0)\n\t"
		"sw\t$0,4(%0)\n\t"
		"sw\t$0,8(%0)\n\t"
		"sw\t$0,12(%0)\n\t"
		"addiu\t%0,32\n\t"
		"sw\t$0,-16(%0)\n\t"
		"sw\t$0,-12(%0)\n\t"
		"sw\t$0,-8(%0)\n\t"
		"bne\t$1,%0,1b\n\t"
		"sw\t$0,-4(%0)\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (page)
		: "0" (page), "I" (PAGE_SIZE)
		: "memory");
}

void andes_copy_page(void * to, void * from)
{
	unsigned long dummy1, dummy2;
	unsigned long reg1, reg2, reg3, reg4;

	__asm__ __volatile__(
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		"addiu\t$1,%0,%8\n"
		"1:\tlw\t%2,(%1)\n\t"
		"lw\t%3,4(%1)\n\t"
		"lw\t%4,8(%1)\n\t"
		"lw\t%5,12(%1)\n\t"
		"sw\t%2,(%0)\n\t"
		"sw\t%3,4(%0)\n\t"
		"sw\t%4,8(%0)\n\t"
		"sw\t%5,12(%0)\n\t"
		"lw\t%2,16(%1)\n\t"
		"lw\t%3,20(%1)\n\t"
		"lw\t%4,24(%1)\n\t"
		"lw\t%5,28(%1)\n\t"
		"sw\t%2,16(%0)\n\t"
		"sw\t%3,20(%0)\n\t"
		"sw\t%4,24(%0)\n\t"
		"sw\t%5,28(%0)\n\t"
		"addiu\t%0,64\n\t"
		"addiu\t%1,64\n\t"
		"lw\t%2,-32(%1)\n\t"
		"lw\t%3,-28(%1)\n\t"
		"lw\t%4,-24(%1)\n\t"
		"lw\t%5,-20(%1)\n\t"
		"sw\t%2,-32(%0)\n\t"
		"sw\t%3,-28(%0)\n\t"
		"sw\t%4,-24(%0)\n\t"
		"sw\t%5,-20(%0)\n\t"
		"lw\t%2,-16(%1)\n\t"
		"lw\t%3,-12(%1)\n\t"
		"lw\t%4,-8(%1)\n\t"
		"lw\t%5,-4(%1)\n\t"
		"sw\t%2,-16(%0)\n\t"
		"sw\t%3,-12(%0)\n\t"
		"sw\t%4,-8(%0)\n\t"
		"bne\t$1,%0,1b\n\t"
		"sw\t%5,-4(%0)\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (dummy1), "=r" (dummy2),
		  "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
		: "0" (to), "1" (from), "I" (PAGE_SIZE));
}

--- NEW FILE: pg-mips32.c ---
/*
 * Kevin D. Kissell, ke...@mi... and Carsten Langgaard, car...@mi...
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 *
 * This program is free software; you can distribute it and/or modify it
 * under the terms of the GNU General Public License (Version 2) as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * MIPS32 CPU variant specific MMU/Cache routines.
 */
#include <asm/bootinfo.h>
#include <asm/cacheops.h>
#include <asm/cpu.h>
#include <asm/page.h>

extern int dc_lsize, ic_lsize, sc_lsize;

/*
 * Zero an entire page.
 */

void mips32_clear_page_dc(unsigned long page)
{
	unsigned long i;

        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
	        for (i=page; i<page+PAGE_SIZE; i+=dc_lsize) {
		        __asm__ __volatile__(
			        ".set\tnoreorder\n\t"
				".set\tnoat\n\t"
				".set\tmips3\n\t"
				"cache\t%2,(%0)\n\t"
				".set\tmips0\n\t"
				".set\tat\n\t"
				".set\treorder"
				:"=r" (i)
				:"0" (i),
				"I" (Create_Dirty_Excl_D));
		}
	}
	for (i=page; i<page+PAGE_SIZE; i+=4)
	        *(unsigned long *)(i) = 0;
}

void mips32_clear_page_sc(unsigned long page)
{
	unsigned long i;

        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
	        for (i=page; i<page+PAGE_SIZE; i+=sc_lsize) {
		        __asm__ __volatile__(
				".set\tnoreorder\n\t"
				".set\tnoat\n\t"
				".set\tmips3\n\t"
				"cache\t%2,(%0)\n\t"
				".set\tmips0\n\t"
				".set\tat\n\t"
				".set\treorder"
				:"=r" (i)
				:"0" (i),
				"I" (Create_Dirty_Excl_SD));
		}
	}
	for (i=page; i<page+PAGE_SIZE; i+=4)
	        *(unsigned long *)(i) = 0;
}

void mips32_copy_page_dc(unsigned long to, unsigned long from)
{
	unsigned long i;

        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
	        for (i=to; i<to+PAGE_SIZE; i+=dc_lsize) {
		        __asm__ __volatile__(
			        ".set\tnoreorder\n\t"
				".set\tnoat\n\t"
				".set\tmips3\n\t"
				"cache\t%2,(%0)\n\t"
				".set\tmips0\n\t"
				".set\tat\n\t"
				".set\treorder"
				:"=r" (i)
				:"0" (i),
				"I" (Create_Dirty_Excl_D));
		}
	}
	for (i=0; i<PAGE_SIZE; i+=4)
	        *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
}

void mips32_copy_page_sc(unsigned long to, unsigned long from)
{
	unsigned long i;

        if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
	        for (i=to; i<to+PAGE_SIZE; i+=sc_lsize) {
		        __asm__ __volatile__(
				".set\tnoreorder\n\t"
				".set\tnoat\n\t"
				".set\tmips3\n\t"
				"cache\t%2,(%0)\n\t"
				".set\tmips0\n\t"
				".set\tat\n\t"
				".set\treorder"
				:"=r" (i)
				:"0" (i),
				"I" (Create_Dirty_Excl_SD));
		}
	}
	for (i=0; i<PAGE_SIZE; i+=4)
	        *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
}

--- NEW FILE: pg-r2300.c ---
/*
 * Copyright (C) 2001 Ralf Baechle (ra...@gn...)
 */
#include <asm/page.h>

/* page functions */
void r3k_clear_page(void * page)
{
	__asm__ __volatile__(
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		"addiu\t$1,%0,%2\n"
		"1:\tsw\t$0,(%0)\n\t"
		"sw\t$0,4(%0)\n\t"
		"sw\t$0,8(%0)\n\t"
		"sw\t$0,12(%0)\n\t"
		"addiu\t%0,32\n\t"
		"sw\t$0,-16(%0)\n\t"
		"sw\t$0,-12(%0)\n\t"
		"sw\t$0,-8(%0)\n\t"
		"bne\t$1,%0,1b\n\t"
		"sw\t$0,-4(%0)\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (page)
		: "0" (page), "I" (PAGE_SIZE)
		: "memory");
}

void r3k_copy_page(void * to, void * from)
{
	unsigned long dummy1, dummy2;
	unsigned long reg1, reg2, reg3, reg4;

	__asm__ __volatile__(
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		"addiu\t$1,%0,%8\n"
		"1:\tlw\t%2,(%1)\n\t"
		"lw\t%3,4(%1)\n\t"
		"lw\t%4,8(%1)\n\t"
		"lw\t%5,12(%1)\n\t"
		"sw\t%2,(%0)\n\t"
		"sw\t%3,4(%0)\n\t"
		"sw\t%4,8(%0)\n\t"
		"sw\t%5,12(%0)\n\t"
		"lw\t%2,16(%1)\n\t"
		"lw\t%3,20(%1)\n\t"
		"lw\t%4,24(%1)\n\t"
		"lw\t%5,28(%1)\n\t"
		"sw\t%2,16(%0)\n\t"
		"sw\t%3,20(%0)\n\t"
		"sw\t%4,24(%0)\n\t"
		"sw\t%5,28(%0)\n\t"
		"addiu\t%0,64\n\t"
		"addiu\t%1,64\n\t"
		"lw\t%2,-32(%1)\n\t"
		"lw\t%3,-28(%1)\n\t"
		"lw\t%4,-24(%1)\n\t"
		"lw\t%5,-20(%1)\n\t"
		"sw\t%2,-32(%0)\n\t"
		"sw\t%3,-28(%0)\n\t"
		"sw\t%4,-24(%0)\n\t"
		"sw\t%5,-20(%0)\n\t"
		"lw\t%2,-16(%1)\n\t"
		"lw\t%3,-12(%1)\n\t"
		"lw\t%4,-8(%1)\n\t"
		"lw\t%5,-4(%1)\n\t"
		"sw\t%2,-16(%0)\n\t"
		"sw\t%3,-12(%0)\n\t"
		"sw\t%4,-8(%0)\n\t"
		"bne\t$1,%0,1b\n\t"
		"sw\t%5,-4(%0)\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (dummy1), "=r" (dummy2),
		  "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
		: "0" (to), "1" (from),
		  "I" (PAGE_SIZE));
}

--- NEW FILE: pg-r5432.c ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * r5432.c: NEC Vr5432 processor.  We cannot use r4xx0.c because of
 *      its unique way-selection method for indexed operations.
 *
 * Copyright (C) 1996 David S. Miller (dm...@en...)
 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle (ra...@gn...)
 * Copyright (C) 2000 Jun Sun (js...@mv...)
 *
 */
#include <asm/cacheops.h>
#include <asm/page.h>

void r5432_clear_page_d32(void * page)
{
	__asm__ __volatile__(
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		".set\tmips3\n\t"
		"daddiu\t$1,%0,%2\n"
		"1:\tcache\t%3,(%0)\n\t"
		"sd\t$0,(%0)\n\t"
		"sd\t$0,8(%0)\n\t"
		"sd\t$0,16(%0)\n\t"
		"sd\t$0,24(%0)\n\t"
		"daddiu\t%0,64\n\t"
		"cache\t%3,-32(%0)\n\t"
		"sd\t$0,-32(%0)\n\t"
		"sd\t$0,-24(%0)\n\t"
		"sd\t$0,-16(%0)\n\t"
		"bne\t$1,%0,1b\n\t"
		"sd\t$0,-8(%0)\n\t"
		".set\tmips0\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (page)
		: "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_D)
		: "memory");
}



/*
 * This is still inefficient.  We only can do better if we know the
 * virtual address where the copy will be accessed.
 */

void r5432_copy_page_d32(void * to, void * from)
{
	unsigned long dummy1, dummy2;
	unsigned long reg1, reg2, reg3, reg4;

	__asm__ __volatile__(
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		".set\tmips3\n\t"
		"daddiu\t$1,%0,%8\n"
		"1:\tcache\t%9,(%0)\n\t"
		"lw\t%2,(%1)\n\t"
		"lw\t%3,4(%1)\n\t"
		"lw\t%4,8(%1)\n\t"
		"lw\t%5,12(%1)\n\t"
		"sw\t%2,(%0)\n\t"
		"sw\t%3,4(%0)\n\t"
		"sw\t%4,8(%0)\n\t"
		"sw\t%5,12(%0)\n\t"
		"lw\t%2,16(%1)\n\t"
		"lw\t%3,20(%1)\n\t"
		"lw\t%4,24(%1)\n\t"
		"lw\t%5,28(%1)\n\t"
		"sw\t%2,16(%0)\n\t"
		"sw\t%3,20(%0)\n\t"
		"sw\t%4,24(%0)\n\t"
		"sw\t%5,28(%0)\n\t"
		"cache\t%9,32(%0)\n\t"
		"daddiu\t%0,64\n\t"
		"daddiu\t%1,64\n\t"
		"lw\t%2,-32(%1)\n\t"
		"lw\t%3,-28(%1)\n\t"
		"lw\t%4,-24(%1)\n\t"
		"lw\t%5,-20(%1)\n\t"
		"sw\t%2,-32(%0)\n\t"
		"sw\t%3,-28(%0)\n\t"
		"sw\t%4,-24(%0)\n\t"
		"sw\t%5,-20(%0)\n\t"
		"lw\t%2,-16(%1)\n\t"
		"lw\t%3,-12(%1)\n\t"
		"lw\t%4,-8(%1)\n\t"
		"lw\t%5,-4(%1)\n\t"
		"sw\t%2,-16(%0)\n\t"
		"sw\t%3,-12(%0)\n\t"
		"sw\t%4,-8(%0)\n\t"
		"bne\t$1,%0,1b\n\t"
		"sw\t%5,-4(%0)\n\t"
		".set\tmips0\n\t"
		".set\tat\n\t"
		".set\treorder"
		:"=r" (dummy1), "=r" (dummy2),
		 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
		:"0" (to), "1" (from),
		 "I" (PAGE_SIZE),
		 "i" (Create_Dirty_Excl_D));
}

--- NEW FILE: pg-rm7k.c ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996 David S. Miller (dm...@en...)
 * Copyright (C) 1997, 1998 Ralf Baechle ra...@gn...
 */
#include <asm/addrspace.h>
#include <asm/cacheops.h>
#include <asm/page.h>
#include <asm/system.h>

/*
 * Zero an entire page.  Note that while the RM7000 has a second level cache
 * it doesn't have a Create_Dirty_Excl_SD operation.
 */
void rm7k_clear_page(void * page)
{
	__asm__ __volatile__(
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		".set\tmips3\n\t"
		"daddiu\t$1,%0,%2\n"
		"1:\tcache\t%3,(%0)\n\t"
		"sd\t$0,(%0)\n\t"
		"sd\t$0,8(%0)\n\t"
		"sd\t$0,16(%0)\n\t"
		"sd\t$0,24(%0)\n\t"
		"daddiu\t%0,64\n\t"
		"cache\t%3,-32(%0)\n\t"
		"sd\t$0,-32(%0)\n\t"
		"sd\t$0,-24(%0)\n\t"
		"sd\t$0,-16(%0)\n\t"
		"bne\t$1,%0,1b\n\t"
		"sd\t$0,-8(%0)\n\t"
		".set\tmips0\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (page)
		: "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_D)
		: "memory");
}

/*
 * Copy an entire page.  Note that while the RM7000 has a second level cache
 * it doesn't have a Create_Dirty_Excl_SD operation.
 */
void rm7k_copy_page(void * to, void * from)
{
	unsigned long dummy1, dummy2;
	unsigned long reg1, reg2, reg3, reg4;

	__asm__ __volatile__(
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		".set\tmips3\n\t"
		"daddiu\t$1,%0,%8\n"
		"1:\tcache\t%9,(%0)\n\t"
		"lw\t%2,(%1)\n\t"
		"lw\t%3,4(%1)\n\t"
		"lw\t%4,8(%1)\n\t"
		"lw\t%5,12(%1)\n\t"
		"sw\t%2,(%0)\n\t"
		"sw\t%3,4(%0)\n\t"
		"sw\t%4,8(%0)\n\t"
		"sw\t%5,12(%0)\n\t"
		"lw\t%2,16(%1)\n\t"
		"lw\t%3,20(%1)\n\t"
		"lw\t%4,24(%1)\n\t"
		"lw\t%5,28(%1)\n\t"
		"sw\t%2,16(%0)\n\t"
		"sw\t%3,20(%0)\n\t"
		"sw\t%4,24(%0)\n\t"
		"sw\t%5,28(%0)\n\t"
		"cache\t%9,32(%0)\n\t"
		"daddiu\t%0,64\n\t"
		"daddiu\t%1,64\n\t"
		"lw\t%2,-32(%1)\n\t"
		"lw\t%3,-28(%1)\n\t"
		"lw\t%4,-24(%1)\n\t"
		"lw\t%5,-20(%1)\n\t"
		"sw\t%2,-32(%0)\n\t"
		"sw\t%3,-28(%0)\n\t"
		"sw\t%4,-24(%0)\n\t"
		"sw\t%5,-20(%0)\n\t"
		"lw\t%2,-16(%1)\n\t"
		"lw\t%3,-12(%1)\n\t"
		"lw\t%4,-8(%1)\n\t"
		"lw\t%5,-4(%1)\n\t"
		"sw\t%2,-16(%0)\n\t"
		"sw\t%3,-12(%0)\n\t"
		"sw\t%4,-8(%0)\n\t"
		"bne\t$1,%0,1b\n\t"
		"sw\t%5,-4(%0)\n\t"
		".set\tmips0\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (dummy1), "=r" (dummy2),
		  "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
		: "0" (to), "1" (from), "I" (PAGE_SIZE),
		 "i" (Create_Dirty_Excl_D));
}

[Linux-mips-commits]CVS: linux/arch/mips64/sgi-ip22 ip22-sc.c,1.1.1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip22
In directory usw-pr-cvs1:/tmp/cvs-serv28836/mips64/sgi-ip22

Modified Files:
	ip22-sc.c 
Log Message:
Nuke more  clobbers.

Index: ip22-sc.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip22/ip22-sc.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- ip22-sc.c	2001/06/22 02:29:32	1.1.1.1
+++ ip22-sc.c	2001/10/05 17:07:14	1.2
@@ -38,8 +38,7 @@
 	"daddu\t%0, 32\n\t"
 	".set reorder"
 	: "=r" (first), "=r" (last)
-	: "0" (first), "1" (last), "r" (0x9000000080000000)
-	: "$1");
+	: "0" (first), "1" (last), "r" (0x9000000080000000));
 }
 
 static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size)

[Linux-mips-commits]CVS: linux/arch/mips64/kernel process.c,NONE,1.1 unaligned.c,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv28836/mips64/kernel

Modified Files:
	unaligned.c 
Added Files:
	process.c 
Log Message:
Nuke more  clobbers.

--- NEW FILE: process.c ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others.
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 */
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/mman.h>
#include <linux/sys.h>
#include <linux/user.h>
#include <linux/a.out.h>

#include <asm/bootinfo.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/mipsregs.h>
#include <asm/processor.h>
#include <asm/stackframe.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/elf.h>

asmlinkage int cpu_idle(void)
{
	/* endless idle loop with no priority at all */
	init_idle();
	current->nice = 20;
	current->counter = -100;
	while (1) {
		while (!current->need_resched)
			if (wait_available)
				__asm__("wait");
		schedule();
		check_pgt_cache();
	}
}

struct task_struct *last_task_used_math = NULL;

asmlinkage void ret_from_fork(void);

void exit_thread(void)
{
	/* Forget lazy fpu state */
	if (IS_FPU_OWNER()) {
		set_cp0_status(ST0_CU1, ST0_CU1);
		__asm__ __volatile__("cfc1\t$0,$31");
		CLEAR_FPU_OWNER();
	}
}

void flush_thread(void)
{
	/* Forget lazy fpu state */
	if (IS_FPU_OWNER()) {
		set_cp0_status(ST0_CU1, ST0_CU1);
		__asm__ __volatile__("cfc1\t$0,$31");
		CLEAR_FPU_OWNER();
	}
}

int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
		 unsigned long unused,
                 struct task_struct * p, struct pt_regs * regs)
{
	struct pt_regs * childregs;
	long childksp;

	childksp = (unsigned long)p + KERNEL_STACK_SIZE - 32;

	if (IS_FPU_OWNER()) {
		save_fp(p);
	}
	/* set up new TSS. */
	childregs = (struct pt_regs *) childksp - 1;
	*childregs = *regs;
	childregs->regs[7] = 0;	/* Clear error flag */
	if (current->personality == PER_LINUX) {
		childregs->regs[2] = 0;	/* Child gets zero as return value */
		regs->regs[2] = p->pid;
	} else {
		/* Under IRIX things are a little different. */
		childregs->regs[2] = 0;
		childregs->regs[3] = 1;
		regs->regs[2] = p->pid;
		regs->regs[3] = 0;
	}
	if (childregs->cp0_status & ST0_CU0) {
		childregs->regs[28] = (unsigned long) p;
		childregs->regs[29] = childksp;
		p->thread.current_ds = KERNEL_DS;
	} else {
		childregs->regs[29] = usp;
		p->thread.current_ds = USER_DS;
	}
	p->thread.reg29 = (unsigned long) childregs;
	p->thread.reg31 = (unsigned long) ret_from_fork;

	/*
	 * New tasks loose permission to use the fpu. This accelerates context
	 * switching for most programs since they don't use the fpu.
	 */
	p->thread.cp0_status = read_32bit_cp0_register(CP0_STATUS) &
                            ~(ST0_CU3|ST0_CU2|ST0_CU1|ST0_KSU);
	childregs->cp0_status &= ~(ST0_CU3|ST0_CU2|ST0_CU1);

	return 0;
}

/* Fill in the fpu structure for a core dump.. */
int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r)
{
	/* We actually store the FPU info in the task->thread
	 * area.
	 */
	if(regs->cp0_status & ST0_CU1) {
		memcpy(r, &current->thread.fpu, sizeof(current->thread.fpu));
		return 1;
	}
	return 0; /* Task didn't use the fpu at all. */
}

/* Fill in the user structure for a core dump.. */
void dump_thread(struct pt_regs *regs, struct user *dump)
{
	dump->magic = CMAGIC;
	dump->start_code  = current->mm->start_code;
	dump->start_data  = current->mm->start_data;
	dump->start_stack = regs->regs[29] & ~(PAGE_SIZE - 1);
	dump->u_tsize = (current->mm->end_code - dump->start_code)
	                >> PAGE_SHIFT;
	dump->u_dsize = (current->mm->brk + (PAGE_SIZE - 1) - dump->start_data)
	                >> PAGE_SHIFT;
	dump->u_ssize = (current->mm->start_stack - dump->start_stack +
	                 PAGE_SIZE - 1) >> PAGE_SHIFT;
	memcpy(&dump->regs[0], regs, sizeof(struct pt_regs));
	memcpy(&dump->regs[EF_SIZE/4], &current->thread.fpu,
	       sizeof(current->thread.fpu));
}

/*
 * Create a kernel thread
 */
int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
{
	int retval;

	__asm__ __volatile__(
		"move\t$6, $sp\n\t"
		"move\t$4, %5\n\t"
		"li\t$2, %1\n\t"
		"syscall\n\t"
		"beq\t$6, $sp, 1f\n\t"
		"move\t$4, %3\n\t"
		"jalr\t%4\n\t"
		"move\t$4, $2\n\t"
		"li\t$2, %2\n\t"
		"syscall\n"
		"1:\tmove\t%0, $2"
		:"=r" (retval)
		:"i" (__NR_clone), "i" (__NR_exit), "r" (arg), "r" (fn),
		 "r" (flags | CLONE_VM)

		 /* The called subroutine might have destroyed any of the
		  * at, result, argument or temporary registers ...  */
		: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
		  "$9","$10","$11","$12","$13","$14","$15","$24","$25");

	return retval;
}

/*
 * These bracket the sleeping functions..
 */
extern void scheduling_functions_start_here(void);
extern void scheduling_functions_end_here(void);
#define first_sched	((unsigned long) scheduling_functions_start_here)
#define last_sched	((unsigned long) scheduling_functions_end_here)

/* get_wchan - a maintenance nightmare ...  */
unsigned long get_wchan(struct task_struct *p)
{
	unsigned long frame, pc;

	if (!p || p == current || p->state == TASK_RUNNING)
		return 0;

	pc = thread_saved_pc(&p->thread);
	if (pc < first_sched || pc >= last_sched)
		goto out;

	if (pc >= (unsigned long) sleep_on_timeout)
		goto schedule_timeout_caller;
	if (pc >= (unsigned long) sleep_on)
		goto schedule_caller;
	if (pc >= (unsigned long) interruptible_sleep_on_timeout)
		goto schedule_timeout_caller;
	if (pc >= (unsigned long)interruptible_sleep_on)
		goto schedule_caller;
	goto schedule_timeout_caller;

schedule_caller:
	frame = ((unsigned long *)p->thread.reg30)[10];
	pc    = ((unsigned long *)frame)[7];
	goto out;

schedule_timeout_caller:
	/* Must be schedule_timeout ...  */
	pc    = ((unsigned long *)p->thread.reg30)[11];
	frame = ((unsigned long *)p->thread.reg30)[10];

	/* The schedule_timeout frame ...  */
	pc    = ((unsigned long *)frame)[9];
	frame = ((unsigned long *)frame)[8];

	if (pc >= first_sched && pc < last_sched) {
		/* schedule_timeout called by interruptible_sleep_on_timeout */
		pc    = ((unsigned long *)frame)[7];
		frame = ((unsigned long *)frame)[6];
	}

out:
	if (current->thread.mflags & MF_32BIT)	/* Kludge for 32-bit ps  */
		pc &= 0xffffffff;

	return pc;
}

Index: unaligned.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/unaligned.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- unaligned.c	2001/08/24 18:59:54	1.2
+++ unaligned.c	2001/10/05 17:07:14	1.3
@@ -163,8 +163,7 @@
 			STR(PTR)"\t2b,%2\n\t"
 			".previous"
 			:"=&r" (value)
-			:"r" (addr), "i" (&&fault)
-			:"$1");
+			:"r" (addr), "i" (&&fault));
 		regs->regs[insn.i_format.rt] = value;
 		return;
 
@@ -208,8 +207,7 @@
 			STR(PTR)"\t2b,%2\n\t"
 			".previous"
 			:"=&r" (value)
-			:"r" (addr), "i" (&&fault)
-			:"$1");
+			:"r" (addr), "i" (&&fault));
 		regs->regs[insn.i_format.rt] = value;
 		return;
 
@@ -279,8 +277,7 @@
 			STR(PTR)"\t2b,%2\n\t"
 			".previous"
 			: /* no outputs */
-			:"r" (value), "r" (addr), "i" (&&fault)
-			:"$1");
+			:"r" (value), "r" (addr), "i" (&&fault));
 		return;
 
 	case sw_op:

[Linux-mips-commits]CVS: linux/arch/mips64/mips-boards/generic time.c,1.1.1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/mips-boards/generic
In directory usw-pr-cvs1:/tmp/cvs-serv28836/mips64/mips-boards/generic

Modified Files:
	time.c 
Log Message:
Nuke more  clobbers.

Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mips-boards/generic/time.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- time.c	2001/06/22 02:29:32	1.1.1.1
+++ time.c	2001/10/05 17:07:14	1.2
@@ -323,8 +323,7 @@
 			:"r" (timerhi),
 			 "m" (timerlo),
 			 "r" (tmp),
-			 "r" (USECS_PER_JIFFY)
-			:"$1");
+			 "r" (USECS_PER_JIFFY));
 		cached_quotient = quotient;
 	}
 

[Linux-mips-commits]CVS: linux/arch/mips/mips-boards/generic time.c,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mips-boards/generic
In directory usw-pr-cvs1:/tmp/cvs-serv28836/mips/mips-boards/generic

Modified Files:
	time.c 
Log Message:
Nuke more  clobbers.

Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mips-boards/generic/time.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- time.c	2001/07/10 16:30:10	1.1
+++ time.c	2001/10/05 17:07:14	1.2
@@ -333,8 +333,7 @@
 			:"r" (timerhi),
 			 "m" (timerlo),
 			 "r" (tmp),
-			 "r" (USECS_PER_JIFFY)
-			:"$1");
+			 "r" (USECS_PER_JIFFY));
 		cached_quotient = quotient;
 #endif
 	}

[Linux-mips-commits]CVS: linux/arch/mips/kernel old-time.c,1.4,1.5 time.c,1.8,1.9

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv28836/mips/kernel

Modified Files:
	old-time.c time.c 
Log Message:
Nuke more  clobbers.

Index: old-time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/old-time.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- old-time.c	2001/08/22 18:19:17	1.4
+++ old-time.c	2001/10/05 17:07:14	1.5
@@ -89,8 +89,7 @@
 			:"r" (timerhi),
 			 "m" (timerlo),
 			 "r" (tmp),
-			 "r" (USECS_PER_JIFFY)
-			:"$1");
+			 "r" (USECS_PER_JIFFY));
 		cached_quotient = quotient;
 	}
 

Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/time.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- time.c	2001/09/07 18:21:54	1.8
+++ time.c	2001/10/05 17:07:14	1.9
@@ -255,8 +255,7 @@
 	        :"r" (timerhi),
 	         "m" (timerlo),
 	         "r" (tmp),
-	         "r" (USECS_PER_JIFFY)
-	        :"$1");
+	         "r" (USECS_PER_JIFFY));
 	        cached_quotient = quotient;
 	}
 

[Linux-mips-commits]CVS: linux/arch/mips/ite-boards/generic time.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ite-boards/generic
In directory usw-pr-cvs1:/tmp/cvs-serv28836/mips/ite-boards/generic

Modified Files:
	time.c 
Log Message:
Nuke more  clobbers.

Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ite-boards/generic/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- time.c	2001/08/25 02:19:27	1.3
+++ time.c	2001/10/05 17:07:14	1.4
@@ -303,8 +303,7 @@
 			:"r" (timerhi),
 			 "m" (timerlo),
 			 "r" (tmp),
-			 "r" (USECS_PER_JIFFY)
-			:"$1");
+			 "r" (USECS_PER_JIFFY));
 		cached_quotient = quotient;
 	}