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From: James S. <jsi...@us...> - 2001-10-08 18:06:10
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/common
In directory usw-pr-cvs1:/tmp/cvs-serv30706/vr4122/common
Modified Files:
reset.c
Log Message:
Osprey fixs that where posted. Thank you.
Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/common/reset.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- reset.c 2001/09/22 04:27:15 1.1
+++ reset.c 2001/10/08 18:06:07 1.2
@@ -18,8 +18,8 @@
void vr4122_restart(char *command)
{
- set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
- set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+ change_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
|
|
From: James S. <jsi...@us...> - 2001-10-08 18:06:10
|
Update of /cvsroot/linux-mips/linux/arch/mips In directory usw-pr-cvs1:/tmp/cvs-serv30706 Modified Files: Makefile Log Message: Osprey fixs that where posted. Thank you. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v retrieving revision 1.20 retrieving revision 1.21 diff -u -d -r1.20 -r1.21 --- Makefile 2001/10/07 05:40:22 1.20 +++ Makefile 2001/10/08 18:06:07 1.21 @@ -232,9 +232,9 @@ # NEC Eagle (vr4122) board # ifdef CONFIG_NEC_EAGLE -SUBDIRS += arch/mips/vr41xx arch/mips/vr41xx/vr4121 -LIBS += arch/mips/vr41xx/vr41xx.o \ - arch/mips/vr41xx/vr4121/vr4121.o +SUBDIRS += arch/mips/vr4122/common arch/mips/vr4122/eagle +LIBS += arch/mips/vr4122/common/vr4122.o \ + arch/mips/vr4122/eagle/eagle.o LOADADDR += 0x80004000 endif |
|
From: James S. <jsi...@us...> - 2001-10-08 16:52:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/common In directory usw-pr-cvs1:/tmp/cvs-serv5816 Removed Files: kbd.c Log Message: Use dummy_keyb.c instead. --- kbd.c DELETED --- |
|
From: James S. <jsi...@us...> - 2001-10-08 16:51:31
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/common In directory usw-pr-cvs1:/tmp/cvs-serv5581 Modified Files: Makefile Log Message: Fix for eagle. It has a framebuffer but no real keyboard. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/common/Makefile,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- Makefile 2001/09/22 04:27:15 1.1 +++ Makefile 2001/10/08 16:51:28 1.2 @@ -20,7 +20,7 @@ O_TARGET := vr4122.o export-objs := serial.o -obj-y := cmu.o icu.o int-handler.o kbd.o reset.o time.o +obj-y := cmu.o icu.o int-handler.o reset.o time.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o |
|
From: James S. <jsi...@us...> - 2001-10-08 16:50:45
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv5329
Modified Files:
config.in
Log Message:
Fix for eagle. It has a framebuffer but no real keyboard.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.31
retrieving revision 1.32
diff -u -d -r1.31 -r1.32
--- config.in 2001/10/07 16:57:19 1.31
+++ config.in 2001/10/08 16:50:42 1.32
@@ -202,6 +202,7 @@
define_bool CONFIG_VRC4173 y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_PCI y
fi
if [ "$CONFIG_NEC_KORVA" = "y" ]; then
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:39:43
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv2351 Modified Files: defconfig-osprey Log Message: defconfig-osprey Index: defconfig-osprey =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-osprey,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- defconfig-osprey 2001/10/02 18:40:35 1.4 +++ defconfig-osprey 2001/10/08 16:39:41 1.5 @@ -1,5 +1,5 @@ # -# Automatically generated by make menuconfig: don't edit +# Automatically generated make config: don't edit # CONFIG_MIPS=y # CONFIG_SMP is not set @@ -158,6 +158,10 @@ # CONFIG_IPV6 is not set # CONFIG_KHTTPD is not set # CONFIG_ATM is not set + +# +# +# # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_DECNET is not set @@ -317,6 +321,10 @@ # Joysticks # # CONFIG_JOYSTICK is not set + +# +# Input core support is needed for joysticks +# # CONFIG_QIC02_TAPE is not set # |
|
From: James S. <jsi...@us...> - 2001-10-08 16:35:02
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64/sgi In directory usw-pr-cvs1:/tmp/cvs-serv1087 Modified Files: sgint23.h Log Message: Definitions for VINO interrupt. Index: sgint23.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/sgi/sgint23.h,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- sgint23.h 2001/07/24 17:00:17 1.2 +++ sgint23.h 2001/10/08 16:35:00 1.3 @@ -28,15 +28,16 @@ /* * Individual interrupt definitions for the INDY and Indigo2 */ -#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ -#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ -#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ +#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ +#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ +#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ -#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ +#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ +#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */ -#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ +#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ #define SGI_KEYBOARD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ -#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ +#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ /* INT2 occupies HPC PBUS slot 4, INT3 uses slot 6. */ #define SGI_INT2_BASE 0x1fbd9000 /* physical */ |
|
From: James S. <jsi...@us...> - 2001-10-08 16:33:09
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/sgi In directory usw-pr-cvs1:/tmp/cvs-serv535 Added Files: sgint23.h Log Message: Definitions for VINO interrupt. |
|
From: James S. <jsi...@us...> - 2001-10-08 16:31:54
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv32445
Modified Files:
sgiseeq.c
Log Message:
Improve error handling.
Index: sgiseeq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/sgiseeq.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- sgiseeq.c 2001/07/09 19:28:47 1.2
+++ sgiseeq.c 2001/10/08 16:31:35 1.3
@@ -450,19 +450,22 @@
unsigned long flags;
int err;
- save_and_cli(flags);
- if (request_irq(dev->irq, sgiseeq_interrupt, 0, sgiseeqstr, (void *) dev)) {
+ __save_and_cli(flags);
+
+ err = -EAGAIN;
+ if (request_irq(dev->irq, sgiseeq_interrupt, 0, sgiseeqstr, dev)) {
printk("Seeq8003: Can't get irq %d\n", dev->irq);
- restore_flags(flags);
- return -EAGAIN;
+ goto out;
}
err = init_seeq(dev, sp, sregs);
if (err)
- return err;
+ goto out;
netif_start_queue(dev);
- restore_flags(flags);
- return 0;
+
+out:
+ __restore_flags(flags);
+ return err;
}
static int sgiseeq_close(struct net_device *dev)
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:30:45
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv32084
Added Files:
page.h
Log Message:
Move all clear_page / copy_page variations in separate files. Rewrite all R4xx0 variants to assembler code.
--- NEW FILE: page.h ---
/*
* Definitions for page handling
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 - 1999 by Ralf Baechle
*/
#ifndef __ASM_PAGE_H
#define __ASM_PAGE_H
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
#ifdef __KERNEL__
#ifndef _LANGUAGE_ASSEMBLY
#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); *(int *)0=0; } while (0)
#define PAGE_BUG(page) do { BUG(); } while (0)
/*
* Prototypes for clear_page / copy_page variants with processor dependant
* optimizations.
*/
void andes_clear_page(void * page);
void mips32_clear_page_dc(unsigned long page);
void mips32_clear_page_sc(unsigned long page);
void r3k_clear_page(void * page);
void r4k_clear_page_d16(void * page);
void r4k_clear_page_d32(void * page);
void r4k_clear_page_r4600_v1(void * page);
void r4k_clear_page_r4600_v2(void * page);
void r4k_clear_page_s16(void * page);
void r4k_clear_page_s32(void * page);
void r4k_clear_page_s64(void * page);
void r4k_clear_page_s128(void * page);
void r5432_clear_page_d32(void * page);
void rm7k_clear_page(void * page);
void andes_copy_page(void * to, void * from);
void mips32_copy_page_dc(unsigned long to, unsigned long from);
void mips32_copy_page_sc(unsigned long to, unsigned long from);
void r3k_copy_page(void * to, void * from);
void r4k_copy_page_d16(void * to, void * from);
void r4k_copy_page_d32(void * to, void * from);
void r4k_copy_page_r4600_v1(void * to, void * from);
void r4k_copy_page_r4600_v2(void * to, void * from);
void r4k_copy_page_s16(void * to, void * from);
void r4k_copy_page_s32(void * to, void * from);
void r4k_copy_page_s64(void * to, void * from);
void r4k_copy_page_s128(void * to, void * from);
void r5432_copy_page_d32(void * to, void * from);
void rm7k_copy_page(void * to, void * from);
extern void (*_clear_page)(void * page);
extern void (*_copy_page)(void * to, void * from);
#define clear_page(page) _clear_page(page)
#define copy_page(to, from) _copy_page(to, from)
#define clear_user_page(page, vaddr) clear_page(page)
#define copy_user_page(to, from, vaddr) copy_page(to, from)
/*
* These are used to make use of C type-checking..
*/
typedef struct { unsigned long pte; } pte_t;
typedef struct { unsigned long pmd; } pmd_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
#define pte_val(x) ((x).pte)
#define pmd_val(x) ((x).pmd)
#define pgd_val(x) ((x).pgd)
#define pgprot_val(x) ((x).pgprot)
#define __pte(x) ((pte_t) { (x) } )
#define __pme(x) ((pme_t) { (x) } )
#define __pgd(x) ((pgd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
/* Pure 2^n version of get_order */
extern __inline__ int get_order(unsigned long size)
{
int order;
size = (size-1) >> (PAGE_SHIFT-1);
order = -1;
do {
size >>= 1;
order++;
} while (size);
return order;
}
#endif /* _LANGUAGE_ASSEMBLY */
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
/*
* This handles the memory map.
* We handle pages at KSEG0 for kernels with 32 bit address space.
*/
#define PAGE_OFFSET 0x80000000UL
#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
#define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
#endif /* defined (__KERNEL__) */
#endif /* __ASM_PAGE_H */
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:29:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv31620
Modified Files:
Makefile andes.c mips32.c r2300.c r4xx0.c r5432.c
Added Files:
pg-r4xx0.S
Log Message:
Move all clear_page / copy_page variations in separate files. Rewrite all R4xx0 variants to assembler code.
--- NEW FILE: pg-r4xx0.S ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* r4xx0.c: R4000 processor variant specific MMU/Cache routines.
*
* Copyright (C) 1996 David S. Miller (dm...@en...)
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ra...@gn...
*/
#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
#define PAGE_SIZE 0x1000
.text
.set mips3
.set noreorder
.set nomacro
.set noat
/*
* Zero an entire page. Basically a simple unrolled loop should do the
* job but we want more performance by saving memory bus bandwidth. We
* have five flavours of the routine available for:
*
* - 16byte cachelines and no second level cache
* - 32byte cachelines second level cache
* - a version which handles the buggy R4600 v1.x
* - a version which handles the buggy R4600 v2.0
* - Finally a last version without fancy cache games for the SC and MC
* versions of R4000 and R4400.
*/
LEAF(r4k_clear_page_d16)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
sd zero, (a0)
sd zero, 8(a0)
cache Create_Dirty_Excl_D, 16(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_D, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
cache Create_Dirty_Excl_D, -16(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_d16)
LEAF(r4k_clear_page_d32)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_D, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_d32)
/*
* This flavour of r4k_clear_page is for the R4600 V1.x. Cite from the
* IDT R4600 V1.7 errata:
*
* 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
* Hit_Invalidate_D and Create_Dirty_Excl_D should only be
* executed if there is no other dcache activity. If the dcache is
* accessed for another instruction immeidately preceding when these
* cache instructions are executing, it is possible that the dcache
* tag match outputs used by these cache instructions will be
* incorrect. These cache instructions should be preceded by at least
* four instructions that are not any kind of load or store
* instruction.
*
* This is not allowed: lw
* nop
* nop
* nop
* cache Hit_Writeback_Invalidate_D
*
* This is allowed: lw
* nop
* nop
* nop
* nop
* cache Hit_Writeback_Invalidate_D
*/
LEAF(r4k_clear_page_r4600_v1)
addiu AT, a0, PAGE_SIZE
1: nop
nop
nop
nop
cache Create_Dirty_Excl_D, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
nop
nop
nop
cache Create_Dirty_Excl_D, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_r4600_v1)
LEAF(r4k_clear_page_r4600_v2)
mfc0 a1, CP0_STATUS
ori AT, a1, 1
xori AT, 1
mtc0 AT, CP0_STATUS
nop
nop
nop
.set volatile
la AT, KSEG1
lw zero, (AT)
.set novolatile
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_D, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
mfc0 AT, CP0_STATUS # __restore_flags
andi a1, 1
ori AT, 1
xori AT, 1
or a1, AT
mtc0 a1, CP0_STATUS
nop
nop
nop
jr ra
END(r4k_clear_page_r4600_v2)
/*
* The next 4 versions are optimized for all possible scache configurations
* of the SC / MC versions of R4000 and R4400 ...
*
* Todo: For even better performance we should have a routine optimized for
* every legal combination of dcache / scache linesize. When I (Ralf) tried
* this the kernel crashed shortly after mounting the root filesystem. CPU
* bug? Weirdo cache instruction semantics?
*/
LEAF(r4k_clear_page_s16)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
sd zero, (a0)
sd zero, 8(a0)
cache Create_Dirty_Excl_SD, 16(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_SD, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
cache Create_Dirty_Excl_SD, -16(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_s16)
LEAF(r4k_clear_page_s32)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
cache Create_Dirty_Excl_SD, -32(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_s32)
LEAF(r4k_clear_page_s64)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
addiu a0, 64
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_s64)
LEAF(r4k_clear_page_s128)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
sd zero, (a0)
sd zero, 8(a0)
sd zero, 16(a0)
sd zero, 24(a0)
sd zero, 32(a0)
sd zero, 40(a0)
sd zero, 48(a0)
sd zero, 56(a0)
addiu a0, 128
sd zero, -64(a0)
sd zero, -56(a0)
sd zero, -48(a0)
sd zero, -40(a0)
sd zero, -32(a0)
sd zero, -24(a0)
sd zero, -16(a0)
bne AT, a0, 1b
sd zero, -8(a0)
jr ra
END(r4k_clear_page_s128)
/*
* This is still inefficient. We only can do better if we know the
* virtual address where the copy will be accessed.
*/
LEAF(r4k_copy_page_d16)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
cache Create_Dirty_Excl_D, 16(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
cache Create_Dirty_Excl_D, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
cache Create_Dirty_Excl_D, -16(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_d16)
LEAF(r4k_copy_page_d32)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_D, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
cache Create_Dirty_Excl_D, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_d32)
/*
* Again a special version for the R4600 V1.x
*/
LEAF(r4k_copy_page_r4600_v1)
addiu AT, a0, PAGE_SIZE
1: nop
nop
nop
nop
cache Create_Dirty_Excl_D, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
nop
nop
nop
nop
cache Create_Dirty_Excl_D, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_r4600_v1)
LEAF(r4k_copy_page_r4600_v2)
mfc0 v1, CP0_STATUS
ori AT, v1, 1
xori AT, 1
mtc0 AT, CP0_STATUS
nop
nop
nop
addiu AT, a0, PAGE_SIZE
1: nop
nop
nop
nop
cache Create_Dirty_Excl_D, (a0)
lw t1, (a1)
lw t0, 4(a1)
lw a3, 8(a1)
lw a2, 12(a1)
sw t1, (a0)
sw t0, 4(a0)
sw a3, 8(a0)
sw a2, 12(a0)
lw t1, 16(a1)
lw t0, 20(a1)
lw a3, 24(a1)
lw a2, 28(a1)
sw t1, 16(a0)
sw t0, 20(a0)
sw a3, 24(a0)
sw a2, 28(a0)
nop
nop
nop
nop
cache Create_Dirty_Excl_D, 32(a0)
addiu a0, 64
addiu a1, 64
lw t1, -32(a1)
lw t0, -28(a1)
lw a3, -24(a1)
lw a2, -20(a1)
sw t1, -32(a0)
sw t0, -28(a0)
sw a3, -24(a0)
sw a2, -20(a0)
lw t1, -16(a1)
lw t0, -12(a1)
lw a3, -8(a1)
lw a2, -4(a1)
sw t1, -16(a0)
sw t0, -12(a0)
sw a3, -8(a0)
bne AT, a0, 1b
sw a2, -4(a0)
mfc0 AT, CP0_STATUS # __restore_flags
andi v1, 1
ori AT, 1
xori AT, 1
or v1, AT
mtc0 v1, CP0_STATUS
nop
nop
nop
jr ra
END(r4k_copy_page_r4600_v2)
/*
* These are for R4000SC / R4400MC
*/
LEAF(r4k_copy_page_s16)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
cache Create_Dirty_Excl_SD, 16(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
cache Create_Dirty_Excl_SD, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
cache Create_Dirty_Excl_SD, -16(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_s16)
LEAF(r4k_copy_page_s32)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
cache Create_Dirty_Excl_SD, 32(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_s32)
LEAF(r4k_copy_page_s64)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
addiu a0, 64
addiu a1, 64
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_s64)
LEAF(r4k_copy_page_s128)
addiu AT, a0, PAGE_SIZE
1: cache Create_Dirty_Excl_SD, (a0)
lw a3, (a1)
lw a2, 4(a1)
lw v1, 8(a1)
lw v0, 12(a1)
sw a3, (a0)
sw a2, 4(a0)
sw v1, 8(a0)
sw v0, 12(a0)
lw a3, 16(a1)
lw a2, 20(a1)
lw v1, 24(a1)
lw v0, 28(a1)
sw a3, 16(a0)
sw a2, 20(a0)
sw v1, 24(a0)
sw v0, 28(a0)
lw a3, 32(a1)
lw a2, 36(a1)
lw v1, 40(a1)
lw v0, 44(a1)
sw a3, 32(a0)
sw a2, 36(a0)
sw v1, 40(a0)
sw v0, 44(a0)
lw a3, 48(a1)
lw a2, 52(a1)
lw v1, 56(a1)
lw v0, 60(a1)
sw a3, 48(a0)
sw a2, 52(a0)
sw v1, 56(a0)
sw v0, 60(a0)
addiu a0, 128
addiu a1, 128
lw a3, -64(a1)
lw a2, -60(a1)
lw v1, -56(a1)
lw v0, -52(a1)
sw a3, -64(a0)
sw a2, -60(a0)
sw v1, -56(a0)
sw v0, -52(a0)
lw a3, -48(a1)
lw a2, -44(a1)
lw v1, -40(a1)
lw v0, -36(a1)
sw a3, -48(a0)
sw a2, -44(a0)
sw v1, -40(a0)
sw v0, -36(a0)
lw a3, -32(a1)
lw a2, -28(a1)
lw v1, -24(a1)
lw v0, -20(a1)
sw a3, -32(a0)
sw a2, -28(a0)
sw v1, -24(a0)
sw v0, -20(a0)
lw a3, -16(a1)
lw a2, -12(a1)
lw v1, -8(a1)
lw v0, -4(a1)
sw a3, -16(a0)
sw a2, -12(a0)
sw v1, -8(a0)
bne AT, a0, 1b
sw v0, -4(a0)
jr ra
END(r4k_copy_page_s128)
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/Makefile,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- Makefile 2001/08/16 17:10:03 1.3
+++ Makefile 2001/10/08 16:29:33 1.4
@@ -12,16 +12,17 @@
export-objs += ioremap.o umap.o
obj-y += extable.o init.o ioremap.o fault.o loadmmu.o
-obj-$(CONFIG_CPU_R3000) += r2300.o
-obj-$(CONFIG_CPU_R4300) += r4xx0.o
-obj-$(CONFIG_CPU_R4X00) += r4xx0.o
-obj-$(CONFIG_CPU_VR41XX) += r4xx0.o
-obj-$(CONFIG_CPU_R5000) += r4xx0.o
-obj-$(CONFIG_CPU_NEVADA) += r4xx0.o
-obj-$(CONFIG_CPU_R5432) += r5432.o
-obj-$(CONFIG_CPU_RM7000) += rm7k.o
-obj-$(CONFIG_CPU_MIPS32) += mips32.o
-obj-$(CONFIG_CPU_MIPS64) += mips32.o
+obj-$(CONFIG_CPU_R3000) += pg-r2300.o r2300.o
+obj-$(CONFIG_CPU_R4300) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_R4X00) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_VR41XX) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_R5000) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_NEVADA) += pg-r4xx0.o r4xx0.o
+obj-$(CONFIG_CPU_R5432) += pg-r5432.o r5432.o
+obj-$(CONFIG_CPU_RM7000) += pg-rm7k.o rm7k.o
+obj-$(CONFIG_CPU_MIPS32) += pg-mips32.o mips32.o
+obj-$(CONFIG_CPU_MIPS64) += pg-mips32.o mips32.o
+
obj-$(CONFIG_SGI_IP22) += umap.o
obj-$(CONFIG_BAGET_MIPS) += umap.o
Index: andes.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/andes.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- andes.c 2001/07/23 23:53:57 1.3
+++ andes.c 2001/10/08 16:29:33 1.4
@@ -13,83 +13,6 @@
#include <asm/sgialib.h>
#include <asm/mmu_context.h>
-/* page functions */
-void andes_clear_page(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "addiu\t$1,%0,%2\n"
- "1:\tsw\t$0,(%0)\n\t"
- "sw\t$0,4(%0)\n\t"
- "sw\t$0,8(%0)\n\t"
- "sw\t$0,12(%0)\n\t"
- "addiu\t%0,32\n\t"
- "sw\t$0,-16(%0)\n\t"
- "sw\t$0,-12(%0)\n\t"
- "sw\t$0,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t$0,-4(%0)\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE)
- :"$1","memory");
-}
-
-static void andes_copy_page(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "addiu\t$1,%0,%8\n"
- "1:\tlw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "addiu\t%0,64\n\t"
- "addiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE));
-}
-
/* Cache operations. XXX Write these dave... */
static inline void andes_flush_cache_all(void)
{
Index: mips32.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/mips32.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- mips32.c 2001/07/23 23:53:57 1.3
+++ mips32.c 2001/10/08 16:29:33 1.4
@@ -37,11 +37,11 @@
".set reorder\n\t")
/* Primary cache parameters. */
-static int icache_size, dcache_size; /* Size in bytes */
-static int ic_lsize, dc_lsize; /* LineSize in bytes */
+int icache_size, dcache_size; /* Size in bytes */
+int ic_lsize, dc_lsize; /* LineSize in bytes */
/* Secondary cache (if present) parameters. */
-static unsigned int scache_size, sc_lsize; /* Again, in bytes */
+unsigned int scache_size, sc_lsize; /* Again, in bytes */
#include <asm/cacheops.h>
#include <asm/mips32_cache.h>
@@ -59,103 +59,6 @@
};
struct bcache_ops *bcops = &no_sc_ops;
-
-
-/*
- * Zero an entire page.
- */
-
-static void mips32_clear_page_dc(unsigned long page)
-{
- unsigned long i;
-
- if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
- for (i=page; i<page+PAGE_SIZE; i+=dc_lsize) {
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "cache\t%2,(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (i)
- :"0" (i),
- "I" (Create_Dirty_Excl_D));
- }
- }
- for (i=page; i<page+PAGE_SIZE; i+=4)
- *(unsigned long *)(i) = 0;
-}
-
-static void mips32_clear_page_sc(unsigned long page)
-{
- unsigned long i;
-
- if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
- for (i=page; i<page+PAGE_SIZE; i+=sc_lsize) {
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "cache\t%2,(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (i)
- :"0" (i),
- "I" (Create_Dirty_Excl_SD));
- }
- }
- for (i=page; i<page+PAGE_SIZE; i+=4)
- *(unsigned long *)(i) = 0;
-}
-
-static void mips32_copy_page_dc(unsigned long to, unsigned long from)
-{
- unsigned long i;
-
- if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
- for (i=to; i<to+PAGE_SIZE; i+=dc_lsize) {
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "cache\t%2,(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (i)
- :"0" (i),
- "I" (Create_Dirty_Excl_D));
- }
- }
- for (i=0; i<PAGE_SIZE; i+=4)
- *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
-}
-
-static void mips32_copy_page_sc(unsigned long to, unsigned long from)
-{
- unsigned long i;
-
- if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) {
- for (i=to; i<to+PAGE_SIZE; i+=sc_lsize) {
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "cache\t%2,(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (i)
- :"0" (i),
- "I" (Create_Dirty_Excl_SD));
- }
- }
- for (i=0; i<PAGE_SIZE; i+=4)
- *(unsigned long *)(to+i) = *(unsigned long *)(from+i);
-}
static inline void mips32_flush_cache_all_sc(void)
{
Index: r2300.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/r2300.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- r2300.c 2001/07/17 17:27:36 1.3
+++ r2300.c 2001/10/08 16:29:33 1.4
@@ -41,83 +41,6 @@
#undef DEBUG_TLB
#undef DEBUG_CACHE
-/* page functions */
-void r3k_clear_page(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "addiu\t$1,%0,%2\n"
- "1:\tsw\t$0,(%0)\n\t"
- "sw\t$0,4(%0)\n\t"
- "sw\t$0,8(%0)\n\t"
- "sw\t$0,12(%0)\n\t"
- "addiu\t%0,32\n\t"
- "sw\t$0,-16(%0)\n\t"
- "sw\t$0,-12(%0)\n\t"
- "sw\t$0,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t$0,-4(%0)\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE)
- :"$1","memory");
-}
-
-static void r3k_copy_page(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "addiu\t$1,%0,%8\n"
- "1:\tlw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "addiu\t%0,64\n\t"
- "addiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE));
-}
-
unsigned long __init r3k_cache_size(unsigned long ca_flags)
{
unsigned long flags, status, dummy, size;
Index: r4xx0.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/r4xx0.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- r4xx0.c 2001/08/16 17:13:31 1.6
+++ r4xx0.c 2001/10/08 16:29:33 1.7
@@ -66,835 +66,6 @@
#define dcache_waybit (dcache_size >> 1)
/*
- * Zero an entire page. Basically a simple unrolled loop should do the
- * job but we want more performance by saving memory bus bandwidth. We
- * have five flavours of the routine available for:
- *
- * - 16byte cachelines and no second level cache
- * - 32byte cachelines second level cache
- * - a version which handles the buggy R4600 v1.x
- * - a version which handles the buggy R4600 v2.0
- * - Finally a last version without fancy cache games for the SC and MC
- * versions of R4000 and R4400.
- */
-
-static void r4k_clear_page_d16(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "cache\t%3,16(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "cache\t%3,-16(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
-}
-
-static void r4k_clear_page_d32(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
-}
-
-
-/*
- * This flavour of r4k_clear_page is for the R4600 V1.x. Cite from the
- * IDT R4600 V1.7 errata:
- *
- * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
- * Hit_Invalidate_D and Create_Dirty_Excl_D should only be
- * executed if there is no other dcache activity. If the dcache is
- * accessed for another instruction immeidately preceding when these
- * cache instructions are executing, it is possible that the dcache
- * tag match outputs used by these cache instructions will be
- * incorrect. These cache instructions should be preceded by at least
- * four instructions that are not any kind of load or store
- * instruction.
- *
- * This is not allowed: lw
- * nop
- * nop
- * nop
- * cache Hit_Writeback_Invalidate_D
- *
- * This is allowed: lw
- * nop
- * nop
- * nop
- * nop
- * cache Hit_Writeback_Invalidate_D
- */
-static void r4k_clear_page_r4600_v1(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tnop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "cache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
-}
-
-/*
- * And this one is for the R4600 V2.0
- */
-static void r4k_clear_page_r4600_v2(void * page)
-{
- unsigned int flags;
-
- __save_and_cli(flags);
- *(volatile unsigned int *)KSEG1;
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
- __restore_flags(flags);
-}
-
-/*
- * The next 4 versions are optimized for all possible scache configurations
- * of the SC / MC versions of R4000 and R4400 ...
- *
- * Todo: For even better performance we should have a routine optimized for
- * every legal combination of dcache / scache linesize. When I (Ralf) tried
- * this the kernel crashed shortly after mounting the root filesystem. CPU
- * bug? Weirdo cache instruction semantics?
- */
-static void r4k_clear_page_s16(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "cache\t%3,16(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "cache\t%3,-16(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD)
- :"$1","memory");
-}
-
-static void r4k_clear_page_s32(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD)
- :"$1","memory");
-}
-
-static void r4k_clear_page_s64(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD)
- :"$1","memory");
-}
-
-static void r4k_clear_page_s128(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "sd\t$0,32(%0)\n\t"
- "sd\t$0,40(%0)\n\t"
- "sd\t$0,48(%0)\n\t"
- "sd\t$0,56(%0)\n\t"
- "daddiu\t%0,128\n\t"
- "sd\t$0,-64(%0)\n\t"
- "sd\t$0,-56(%0)\n\t"
- "sd\t$0,-48(%0)\n\t"
- "sd\t$0,-40(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD)
- :"$1","memory");
-}
-
-
-/*
- * This is still inefficient. We only can do better if we know the
- * virtual address where the copy will be accessed.
- */
-
-static void r4k_copy_page_d16(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "cache\t%9,16(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "cache\t%9,-16(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
-}
-
-static void r4k_copy_page_d32(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
-}
-
-/*
- * Again a special version for the R4600 V1.x
- */
-static void r4k_copy_page_r4600_v1(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tnop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
-}
-
-static void r4k_copy_page_r4600_v2(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
- unsigned int flags;
-
- __save_and_cli(flags);
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tnop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
- __restore_flags(flags);
-}
-
-/*
- * These are for R4000SC / R4400MC
- */
-static void r4k_copy_page_s16(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "cache\t%9,16(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "cache\t%9,-16(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD));
-}
-
-static void r4k_copy_page_s32(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD));
-}
-
-static void r4k_copy_page_s64(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD));
-}
-
-static void r4k_copy_page_s128(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "lw\t%2,32(%1)\n\t"
- "lw\t%3,36(%1)\n\t"
- "lw\t%4,40(%1)\n\t"
- "lw\t%5,44(%1)\n\t"
- "sw\t%2,32(%0)\n\t"
- "sw\t%3,36(%0)\n\t"
- "sw\t%4,40(%0)\n\t"
- "sw\t%5,44(%0)\n\t"
- "lw\t%2,48(%1)\n\t"
- "lw\t%3,52(%1)\n\t"
- "lw\t%4,56(%1)\n\t"
- "lw\t%5,60(%1)\n\t"
- "sw\t%2,48(%0)\n\t"
- "sw\t%3,52(%0)\n\t"
- "sw\t%4,56(%0)\n\t"
- "sw\t%5,60(%0)\n\t"
- "daddiu\t%0,128\n\t"
- "daddiu\t%1,128\n\t"
- "lw\t%2,-64(%1)\n\t"
- "lw\t%3,-60(%1)\n\t"
- "lw\t%4,-56(%1)\n\t"
- "lw\t%5,-52(%1)\n\t"
- "sw\t%2,-64(%0)\n\t"
- "sw\t%3,-60(%0)\n\t"
- "sw\t%4,-56(%0)\n\t"
- "sw\t%5,-52(%0)\n\t"
- "lw\t%2,-48(%1)\n\t"
- "lw\t%3,-44(%1)\n\t"
- "lw\t%4,-40(%1)\n\t"
- "lw\t%5,-36(%1)\n\t"
- "sw\t%2,-48(%0)\n\t"
- "sw\t%3,-44(%0)\n\t"
- "sw\t%4,-40(%0)\n\t"
- "sw\t%5,-36(%0)\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_SD));
-}
-
-
-/*
* If you think for one second that this stuff coming up is a lot
* of bulky code eating too many kernel cache lines. Think _again_.
*
Index: r5432.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/r5432.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- r5432.c 2001/07/23 23:53:57 1.2
+++ r5432.c 2001/10/08 16:29:33 1.3
@@ -254,100 +254,6 @@
/* -------------------------------------------------------------------- */
-static void r5432_clear_page_d32(void * page)
-{
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%2\n"
- "1:\tcache\t%3,(%0)\n\t"
- "sd\t$0,(%0)\n\t"
- "sd\t$0,8(%0)\n\t"
- "sd\t$0,16(%0)\n\t"
- "sd\t$0,24(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "cache\t%3,-32(%0)\n\t"
- "sd\t$0,-32(%0)\n\t"
- "sd\t$0,-24(%0)\n\t"
- "sd\t$0,-16(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sd\t$0,-8(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (page)
- :"0" (page),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D)
- :"$1","memory");
-}
-
-
-
-/*
- * This is still inefficient. We only can do better if we know the
- * virtual address where the copy will be accessed.
- */
-
-static void r5432_copy_page_d32(void * to, void * from)
-{
- unsigned long dummy1, dummy2;
- unsigned long reg1, reg2, reg3, reg4;
-
- __asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips3\n\t"
- "daddiu\t$1,%0,%8\n"
- "1:\tcache\t%9,(%0)\n\t"
- "lw\t%2,(%1)\n\t"
- "lw\t%3,4(%1)\n\t"
- "lw\t%4,8(%1)\n\t"
- "lw\t%5,12(%1)\n\t"
- "sw\t%2,(%0)\n\t"
- "sw\t%3,4(%0)\n\t"
- "sw\t%4,8(%0)\n\t"
- "sw\t%5,12(%0)\n\t"
- "lw\t%2,16(%1)\n\t"
- "lw\t%3,20(%1)\n\t"
- "lw\t%4,24(%1)\n\t"
- "lw\t%5,28(%1)\n\t"
- "sw\t%2,16(%0)\n\t"
- "sw\t%3,20(%0)\n\t"
- "sw\t%4,24(%0)\n\t"
- "sw\t%5,28(%0)\n\t"
- "cache\t%9,32(%0)\n\t"
- "daddiu\t%0,64\n\t"
- "daddiu\t%1,64\n\t"
- "lw\t%2,-32(%1)\n\t"
- "lw\t%3,-28(%1)\n\t"
- "lw\t%4,-24(%1)\n\t"
- "lw\t%5,-20(%1)\n\t"
- "sw\t%2,-32(%0)\n\t"
- "sw\t%3,-28(%0)\n\t"
- "sw\t%4,-24(%0)\n\t"
- "sw\t%5,-20(%0)\n\t"
- "lw\t%2,-16(%1)\n\t"
- "lw\t%3,-12(%1)\n\t"
- "lw\t%4,-8(%1)\n\t"
- "lw\t%5,-4(%1)\n\t"
- "sw\t%2,-16(%0)\n\t"
- "sw\t%3,-12(%0)\n\t"
- "sw\t%4,-8(%0)\n\t"
- "bne\t$1,%0,1b\n\t"
- "sw\t%5,-4(%0)\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- :"=r" (dummy1), "=r" (dummy2),
- "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
- :"0" (to), "1" (from),
- "I" (PAGE_SIZE),
- "i" (Create_Dirty_Excl_D));
-}
-
-
/*
* If you think for one second that this stuff coming up is a lot
* of bulky code eating too many kernel cache lines. Think _again_.
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:25:28
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv30438
Modified Files:
system.h
Log Message:
Rewrite __sti, __cli, __save_flags, __restore_flags and save_and_cli in a way that makes debugging gcc output quite a bit easier.
Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/system.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- system.h 2001/10/04 16:26:39 1.3
+++ system.h 2001/10/08 16:25:25 1.4
@@ -17,17 +17,23 @@
#include <linux/kernel.h>
-static inline void __sti(void)
+__asm__ (
+ ".macro\t__sti\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1,$12\n\t"
+ "ori\t$1,0x1f\n\t"
+ "xori\t$1,0x1e\n\t"
+ "mtc0\t$1,$12\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+
+extern __inline__ void
+__sti(void)
{
__asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "mfc0\t$1,$12\n\t"
- "ori\t$1,0x1f\n\t"
- "xori\t$1,0x1e\n\t"
- "mtc0\t$1,$12\n\t"
- ".set\tat\n\t"
- ".set\treorder"
+ "__sti"
: /* no outputs */
: /* no inputs */
: "memory");
@@ -40,67 +46,90 @@
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
* no nops at all.
*/
-static inline void __cli(void)
+__asm__ (
+ ".macro\t__cli\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1,$12\n\t"
+ "ori\t$1,1\n\t"
+ "xori\t$1,1\n\t"
+ ".set\tnoreorder\n\t"
+ "mtc0\t$1,$12\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+
+extern __inline__ void
+__cli(void)
{
__asm__ __volatile__(
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- "mfc0\t$1,$12\n\t"
- "ori\t$1,1\n\t"
- "xori\t$1,1\n\t"
- "mtc0\t$1,$12\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- ".set\tat\n\t"
- ".set\treorder"
+ "__cli"
: /* no outputs */
: /* no inputs */
: "memory");
}
+__asm__ (
+ ".macro\t__save_flags flags\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ "mfc0\t\\flags, $12\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+
#define __save_flags(x) \
__asm__ __volatile__( \
- ".set\tnoreorder\n\t" \
- "mfc0\t%0,$12\n\t" \
- ".set\treorder" \
+ "__save_flags %0" \
: "=r" (x))
+__asm__ (
+ ".macro\t__save_and_cli result\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t\\result, $12\n\t"
+ "ori\t$1, \\result, 1\n\t"
+ "xori\t$1, 1\n\t"
+ ".set\tnoreorder\n\t"
+ "mtc0\t$1, $12\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+
#define __save_and_cli(x) \
__asm__ __volatile__( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n\t" \
- "mfc0\t%0,$12\n\t" \
- "ori\t$1,%0,1\n\t" \
- "xori\t$1,1\n\t" \
- "mtc0\t$1,$12\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- ".set\tat\n\t" \
- ".set\treorder" \
+ "__save_and_cli\t%0" \
: "=r" (x) \
: /* no inputs */ \
: "memory")
+__asm__(".macro\t__restore_flags flags\n\t"
+ ".set\tnoreorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1, $12\n\t"
+ "andi\t\\flags, 1\n\t"
+ "ori\t$1, 1\n\t"
+ "xori\t$1, 1\n\t"
+ "or\t\\flags, $1\n\t"
+ "mtc0\t\\flags, $12\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ ".set\tat\n\t"
+ ".set\treorder\n\t"
+ ".endm");
+
#define __restore_flags(flags) \
do { \
unsigned long __tmp1; \
\
__asm__ __volatile__( \
- ".set\tnoreorder\t\t\t# __restore_flags\n\t" \
- ".set\tnoat\n\t" \
- "mfc0\t$1, $12\n\t" \
- "andi\t%0, 1\n\t" \
- "ori\t$1, 1\n\t" \
- "xori\t$1, 1\n\t" \
- "or\t%0, $1\n\t" \
- "mtc0\t%0, $12\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- ".set\tat\n\t" \
- ".set\treorder" \
+ "__restore_flags\t%0" \
: "=r" (__tmp1) \
: "0" (flags) \
: "memory"); \
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:23:57
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv29848/include/asm-mips
Modified Files:
system.h
Log Message:
Typo fixes.
Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/system.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- system.h 2001/08/22 18:18:14 1.3
+++ system.h 2001/10/08 16:23:52 1.4
@@ -21,98 +21,122 @@
#include <asm/ptrace.h>
#include <linux/kernel.h>
+__asm__ (
+ ".macro\t__sti\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1,$12\n\t"
+ "ori\t$1,0x1f\n\t"
+ "xori\t$1,0x1e\n\t"
+ "mtc0\t$1,$12\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+
extern __inline__ void
__sti(void)
{
__asm__ __volatile__(
- ".set\tpush\n\t"
- ".set\treorder\n\t"
- ".set\tnoat\n\t"
- "mfc0\t$1,$12\n\t"
- "ori\t$1,0x1f\n\t"
- "xori\t$1,0x1e\n\t"
- "mtc0\t$1,$12\n\t"
- ".set\tpop\n\t"
+ "__sti"
: /* no outputs */
: /* no inputs */
- : "$1", "memory");
+ : "memory");
}
/*
- * For cli() we have to insert nops to make shure that the new value
+ * For cli() we have to insert nops to make sure that the new value
* has actually arrived in the status register before the end of this
* macro.
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
* no nops at all.
*/
+__asm__ (
+ ".macro\t__cli\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1,$12\n\t"
+ "ori\t$1,1\n\t"
+ "xori\t$1,1\n\t"
+ ".set\tnoreorder\n\t"
+ "mtc0\t$1,$12\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+
extern __inline__ void
__cli(void)
{
__asm__ __volatile__(
- ".set\tpush\n\t"
- ".set\treorder\n\t"
- ".set\tnoat\n\t"
- "mfc0\t$1,$12\n\t"
- "ori\t$1,1\n\t"
- "xori\t$1,1\n\t"
- ".set\tnoreorder\n\t"
- "mtc0\t$1,$12\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
- ".set\tpop\n\t"
+ "__cli"
: /* no outputs */
: /* no inputs */
- : "$1", "memory");
+ : "memory");
}
+__asm__ (
+ ".macro\t__save_flags flags\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ "mfc0\t\\flags, $12\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+
#define __save_flags(x) \
__asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "mfc0\t%0,$12\n\t" \
- ".set\tpop\n\t" \
+ "__save_flags %0" \
: "=r" (x))
+__asm__ (
+ ".macro\t__save_and_cli result\n\t"
+ ".set\tpush\n\t"
+ ".set\treorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t\\result, $12\n\t"
+ "ori\t$1, \\result, 1\n\t"
+ "xori\t$1, 1\n\t"
+ ".set\tnoreorder\n\t"
+ "mtc0\t$1, $12\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ ".set\tpop\n\t"
+ ".endm");
+
#define __save_and_cli(x) \
__asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- ".set\tnoat\n\t" \
- "mfc0\t%0,$12\n\t" \
- "ori\t$1,%0,1\n\t" \
- "xori\t$1,1\n\t" \
- ".set\tnoreorder\n\t" \
- "mtc0\t$1,$12\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- ".set\tpop\n\t" \
+ "__save_and_cli\t%0" \
: "=r" (x) \
: /* no inputs */ \
- : "$1", "memory")
+ : "memory")
+
+__asm__(".macro\t__restore_flags flags\n\t"
+ ".set\tnoreorder\n\t"
+ ".set\tnoat\n\t"
+ "mfc0\t$1, $12\n\t"
+ "andi\t\\flags, 1\n\t"
+ "ori\t$1, 1\n\t"
+ "xori\t$1, 1\n\t"
+ "or\t\\flags, $1\n\t"
+ "mtc0\t\\flags, $12\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ ".set\tat\n\t"
+ ".set\treorder\n\t"
+ ".endm");
#define __restore_flags(flags) \
do { \
unsigned long __tmp1; \
\
__asm__ __volatile__( \
- ".set\tnoreorder\t\t\t# __restore_flags\n\t" \
- ".set\tnoat\n\t" \
- "mfc0\t$1, $12\n\t" \
- "andi\t%0, 1\n\t" \
- "ori\t$1, 1\n\t" \
- "xori\t$1, 1\n\t" \
- "or\t%0, $1\n\t" \
- "mtc0\t%0, $12\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- ".set\tat\n\t" \
- ".set\treorder" \
+ "__restore_flags\t%0" \
: "=r" (__tmp1) \
: "0" (flags) \
- : "$1", "memory"); \
+ : "memory"); \
} while(0)
#ifdef CONFIG_SMP
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:23:57
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip22 In directory usw-pr-cvs1:/tmp/cvs-serv29848/arch/mips64/sgi-ip22 Modified Files: ip22-reset.c Log Message: Typo fixes. Index: ip22-reset.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip22/ip22-reset.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- ip22-reset.c 2001/06/22 02:29:32 1.1.1.1 +++ ip22-reset.c 2001/10/08 16:23:52 1.2 @@ -20,7 +20,7 @@ /* * Just powerdown if init hasn't done after POWERDOWN_TIMEOUT seconds. - * I'm not shure if this feature is a good idea, for now it's here just to + * I'm not sure if this feature is a good idea, for now it's here just to * make the power button make behave just like under IRIX. */ #define POWERDOWN_TIMEOUT 120 |
|
From: James S. <jsi...@us...> - 2001-10-08 16:23:57
|
Update of /cvsroot/linux-mips/linux/arch/mips/sgi/kernel In directory usw-pr-cvs1:/tmp/cvs-serv29848/arch/mips/sgi/kernel Modified Files: reset.c Log Message: Typo fixes. Index: reset.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/sgi/kernel/reset.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- reset.c 2001/06/22 02:29:31 1.1.1.1 +++ reset.c 2001/10/08 16:23:52 1.2 @@ -19,7 +19,7 @@ /* * Just powerdown if init hasn't done after POWERDOWN_TIMEOUT seconds. - * I'm not shure if this feature is a good idea, for now it's here just to + * I'm not sure if this feature is a good idea, for now it's here just to * make the power button make behave just like under IRIX. */ #define POWERDOWN_TIMEOUT 120 |
|
From: James S. <jsi...@us...> - 2001-10-08 16:19:45
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64 In directory usw-pr-cvs1:/tmp/cvs-serv28595 Added Files: hw_irq.h Log Message: Interrupt numbers used with IP27 SMP. --- NEW FILE: hw_irq.h --- /* * This exists merely to satisfy <linux/irq.h>. There is * nothing that would go here of general interest. * * Everything of consequence is in arch/alpha/kernel/irq_impl.h, * to be used only in arch/alpha/kernel/. */ /* * Special interrupt numbers for SMP * * XXX ATM this is IP27 specific. */ #define DORESCHED 0xab #define DOCALL 0xbc |
|
From: James S. <jsi...@us...> - 2001-10-08 16:18:42
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv28376
Modified Files:
bitops.h string.h
Added Files:
checksum.h
Log Message:
Remove a bunch more clobbers.
Index: bitops.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bitops.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- bitops.h 2001/07/16 18:30:08 1.3
+++ bitops.h 2001/10/08 16:18:38 1.4
@@ -621,8 +621,7 @@
"2:"
: "=r" (res), "=r" (dummy), "=r" (addr)
: "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff),
- "2" (addr), "r" (size)
- : "$1");
+ "2" (addr), "r" (size));
return res;
}
@@ -657,8 +656,7 @@
".set\treorder\n"
"1:"
: "=r" (set), "=r" (dummy)
- : "0" (0), "1" (1 << bit), "r" (*p)
- : "$1");
+ : "0" (0), "1" (1 << bit), "r" (*p));
if (set < (32 - bit))
return set + offset;
set = 32 - bit;
@@ -697,8 +695,7 @@
".set\treorder\n"
"2:\n\t"
: "=&r" (__res), "=r" (mask)
- : "r" (word), "1" (mask)
- : "$1");
+ : "r" (word), "1" (mask));
return __res;
}
Index: string.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/string.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- string.h 2001/07/24 16:42:46 1.1
+++ string.h 2001/10/08 16:18:38 1.2
@@ -28,7 +28,7 @@
".set\treorder"
: "=r" (__dest), "=r" (__src)
: "0" (__dest), "1" (__src)
- : "$1","memory");
+ : "memory");
return __xdest;
}
@@ -56,7 +56,7 @@
".set\treorder"
: "=r" (__dest), "=r" (__src), "=r" (__n)
: "0" (__dest), "1" (__src), "2" (__n)
- : "$1","memory");
+ : "memory");
return __dest;
}
@@ -84,8 +84,7 @@
"3:\t.set\tat\n\t"
".set\treorder"
: "=r" (__cs), "=r" (__ct), "=r" (__res)
- : "0" (__cs), "1" (__ct)
- : "$1");
+ : "0" (__cs), "1" (__ct));
return __res;
}
@@ -116,8 +115,7 @@
".set\tat\n\t"
".set\treorder"
: "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
- : "0" (__cs), "1" (__ct), "2" (__count)
- : "$1");
+ : "0" (__cs), "1" (__ct), "2" (__count));
return __res;
}
@@ -148,8 +146,7 @@
"bne\t$1,%z4,1b\n"
"2:\t.set\tpop"
: "=r" (__addr), "=r" (__end)
- : "0" (__addr), "1" (__end), "Jr" (__c)
- : "$1");
+ : "0" (__addr), "1" (__end), "Jr" (__c));
return __addr;
}
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:17:00
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27
In directory usw-pr-cvs1:/tmp/cvs-serv27765
Modified Files:
ip27-irq.c
Log Message:
Move sendintr to IP27 code. This is SMP specific, so not yet the optimal place.
Index: ip27-irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27/ip27-irq.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- ip27-irq.c 2001/10/05 17:17:08 1.4
+++ ip27-irq.c 2001/10/08 16:16:58 1.5
@@ -33,10 +33,13 @@
#include <asm/pci/bridge.h>
#include <asm/sn/sn0/hub.h>
#include <asm/sn/sn0/ip27.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/agent.h>
#include <asm/sn/arch.h>
#include <asm/sn/intr.h>
#include <asm/sn/intr_public.h>
+
#undef DEBUG_IRQ
#ifdef DEBUG_IRQ
#define DBG(x...) printk(x)
@@ -513,6 +516,34 @@
{
/* Nothing, the return from intr will work for us */
}
+
+#ifdef CONFIG_SMP
+
+void sendintr(int destid, unsigned char status)
+{
+ int irq;
+
+#if (CPUS_PER_NODE == 2)
+ switch (status) {
+ case DORESCHED: irq = CPU_RESCHED_A_IRQ; break;
+ case DOCALL: irq = CPU_CALL_A_IRQ; break;
+ default: panic("sendintr");
+ }
+ irq += cputoslice(destid);
+
+ /*
+ * Convert the compact hub number to the NASID to get the correct
+ * part of the address space. Then set the interrupt bit associated
+ * with the CPU we want to send the interrupt to.
+ */
+ REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cputocnode(destid)),
+ FAST_IRQ_TO_LEVEL(irq));
+#else
+ << Bomb! Must redefine this for more than 2 CPUS. >>
+#endif
+}
+
+#endif
extern void smp_call_function_interrupt(void);
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:15:00
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv27015
Modified Files:
smp.c
Log Message:
Remove code that was move to IP27 specific code a few days ago.
Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/smp.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- smp.c 2001/10/05 17:15:12 1.4
+++ smp.c 2001/10/08 16:14:57 1.5
@@ -7,7 +7,6 @@
* Copyright (C) 2000, 2001 Ralf Baechle
* Copyright (C) 2000, 2001 Silicon Graphics, Inc.
*/
-#include <linux/config.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
@@ -24,43 +23,6 @@
#include <asm/softirq.h>
#include <asm/mmu_context.h>
#include <asm/irq.h>
-
-#ifdef CONFIG_SGI_IP27
-
-#include <asm/sn/arch.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/agent.h>
-#include <asm/sn/sn0/ip27.h>
-
-#define DORESCHED 0xab
-#define DOCALL 0xbc
-
-static void sendintr(int destid, unsigned char status)
-{
- int irq;
-
-#if (CPUS_PER_NODE == 2)
- switch (status) {
- case DORESCHED: irq = CPU_RESCHED_A_IRQ; break;
- case DOCALL: irq = CPU_CALL_A_IRQ; break;
- default: panic("sendintr");
- }
- irq += cputoslice(destid);
-
- /*
- * Convert the compact hub number to the NASID to get the correct
- * part of the address space. Then set the interrupt bit associated
- * with the CPU we want to send the interrupt to.
- */
- REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cputocnode(destid)),
- FAST_IRQ_TO_LEVEL(irq));
-#else
- << Bomb! Must redefine this for more than 2 CPUS. >>
-#endif
-}
-
-#endif /* CONFIG_SGI_IP27 */
/* The 'big kernel lock' */
spinlock_t kernel_flag = SPIN_LOCK_UNLOCKED;
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:13:50
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv26613
Added Files:
unistd.h
Log Message:
Rewrite _syscallX macros to make them safe against gcc miss optimization.
--- NEW FILE: unistd.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*
* Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
* the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
*/
#ifndef _ASM_UNISTD_H
#define _ASM_UNISTD_H
/*
* Linux o32 style syscalls are in the range from 4000 to 4999.
*/
#define __NR_Linux32 4000
#define __NR_Linux32_syscall (__NR_Linux32 + 0)
#define __NR_Linux32_exit (__NR_Linux32 + 1)
#define __NR_Linux32_fork (__NR_Linux32 + 2)
#define __NR_Linux32_read (__NR_Linux32 + 3)
#define __NR_Linux32_write (__NR_Linux32 + 4)
#define __NR_Linux32_open (__NR_Linux32 + 5)
#define __NR_Linux32_close (__NR_Linux32 + 6)
#define __NR_Linux32_waitpid (__NR_Linux32 + 7)
#define __NR_Linux32_creat (__NR_Linux32 + 8)
#define __NR_Linux32_link (__NR_Linux32 + 9)
#define __NR_Linux32_unlink (__NR_Linux32 + 10)
#define __NR_Linux32_execve (__NR_Linux32 + 11)
#define __NR_Linux32_chdir (__NR_Linux32 + 12)
#define __NR_Linux32_time (__NR_Linux32 + 13)
#define __NR_Linux32_mknod (__NR_Linux32 + 14)
#define __NR_Linux32_chmod (__NR_Linux32 + 15)
#define __NR_Linux32_lchown (__NR_Linux32 + 16)
#define __NR_Linux32_break (__NR_Linux32 + 17)
#define __NR_Linux32_oldstat (__NR_Linux32 + 18)
#define __NR_Linux32_lseek (__NR_Linux32 + 19)
#define __NR_Linux32_getpid (__NR_Linux32 + 20)
#define __NR_Linux32_mount (__NR_Linux32 + 21)
#define __NR_Linux32_umount (__NR_Linux32 + 22)
#define __NR_Linux32_setuid (__NR_Linux32 + 23)
#define __NR_Linux32_getuid (__NR_Linux32 + 24)
#define __NR_Linux32_stime (__NR_Linux32 + 25)
#define __NR_Linux32_ptrace (__NR_Linux32 + 26)
#define __NR_Linux32_alarm (__NR_Linux32 + 27)
#define __NR_Linux32_oldfstat (__NR_Linux32 + 28)
#define __NR_Linux32_pause (__NR_Linux32 + 29)
#define __NR_Linux32_utime (__NR_Linux32 + 30)
#define __NR_Linux32_stty (__NR_Linux32 + 31)
#define __NR_Linux32_gtty (__NR_Linux32 + 32)
#define __NR_Linux32_access (__NR_Linux32 + 33)
#define __NR_Linux32_nice (__NR_Linux32 + 34)
#define __NR_Linux32_ftime (__NR_Linux32 + 35)
#define __NR_Linux32_sync (__NR_Linux32 + 36)
#define __NR_Linux32_kill (__NR_Linux32 + 37)
#define __NR_Linux32_rename (__NR_Linux32 + 38)
#define __NR_Linux32_mkdir (__NR_Linux32 + 39)
#define __NR_Linux32_rmdir (__NR_Linux32 + 40)
#define __NR_Linux32_dup (__NR_Linux32 + 41)
#define __NR_Linux32_pipe (__NR_Linux32 + 42)
#define __NR_Linux32_times (__NR_Linux32 + 43)
#define __NR_Linux32_prof (__NR_Linux32 + 44)
#define __NR_Linux32_brk (__NR_Linux32 + 45)
#define __NR_Linux32_setgid (__NR_Linux32 + 46)
#define __NR_Linux32_getgid (__NR_Linux32 + 47)
#define __NR_Linux32_signal (__NR_Linux32 + 48)
#define __NR_Linux32_geteuid (__NR_Linux32 + 49)
#define __NR_Linux32_getegid (__NR_Linux32 + 50)
#define __NR_Linux32_acct (__NR_Linux32 + 51)
#define __NR_Linux32_umount2 (__NR_Linux32 + 52)
#define __NR_Linux32_lock (__NR_Linux32 + 53)
#define __NR_Linux32_ioctl (__NR_Linux32 + 54)
#define __NR_Linux32_fcntl (__NR_Linux32 + 55)
#define __NR_Linux32_mpx (__NR_Linux32 + 56)
#define __NR_Linux32_setpgid (__NR_Linux32 + 57)
#define __NR_Linux32_ulimit (__NR_Linux32 + 58)
#define __NR_Linux32_unused59 (__NR_Linux32 + 59)
#define __NR_Linux32_umask (__NR_Linux32 + 60)
#define __NR_Linux32_chroot (__NR_Linux32 + 61)
#define __NR_Linux32_ustat (__NR_Linux32 + 62)
#define __NR_Linux32_dup2 (__NR_Linux32 + 63)
#define __NR_Linux32_getppid (__NR_Linux32 + 64)
#define __NR_Linux32_getpgrp (__NR_Linux32 + 65)
#define __NR_Linux32_setsid (__NR_Linux32 + 66)
#define __NR_Linux32_sigaction (__NR_Linux32 + 67)
#define __NR_Linux32_sgetmask (__NR_Linux32 + 68)
#define __NR_Linux32_ssetmask (__NR_Linux32 + 69)
#define __NR_Linux32_setreuid (__NR_Linux32 + 70)
#define __NR_Linux32_setregid (__NR_Linux32 + 71)
#define __NR_Linux32_sigsuspend (__NR_Linux32 + 72)
#define __NR_Linux32_sigpending (__NR_Linux32 + 73)
#define __NR_Linux32_sethostname (__NR_Linux32 + 74)
#define __NR_Linux32_setrlimit (__NR_Linux32 + 75)
#define __NR_Linux32_getrlimit (__NR_Linux32 + 76)
#define __NR_Linux32_getrusage (__NR_Linux32 + 77)
#define __NR_Linux32_gettimeofday (__NR_Linux32 + 78)
#define __NR_Linux32_settimeofday (__NR_Linux32 + 79)
#define __NR_Linux32_getgroups (__NR_Linux32 + 80)
#define __NR_Linux32_setgroups (__NR_Linux32 + 81)
#define __NR_Linux32_reserved82 (__NR_Linux32 + 82)
#define __NR_Linux32_symlink (__NR_Linux32 + 83)
#define __NR_Linux32_oldlstat (__NR_Linux32 + 84)
#define __NR_Linux32_readlink (__NR_Linux32 + 85)
#define __NR_Linux32_uselib (__NR_Linux32 + 86)
#define __NR_Linux32_swapon (__NR_Linux32 + 87)
#define __NR_Linux32_reboot (__NR_Linux32 + 88)
#define __NR_Linux32_readdir (__NR_Linux32 + 89)
#define __NR_Linux32_mmap (__NR_Linux32 + 90)
#define __NR_Linux32_munmap (__NR_Linux32 + 91)
#define __NR_Linux32_truncate (__NR_Linux32 + 92)
#define __NR_Linux32_ftruncate (__NR_Linux32 + 93)
#define __NR_Linux32_fchmod (__NR_Linux32 + 94)
#define __NR_Linux32_fchown (__NR_Linux32 + 95)
#define __NR_Linux32_getpriority (__NR_Linux32 + 96)
#define __NR_Linux32_setpriority (__NR_Linux32 + 97)
#define __NR_Linux32_profil (__NR_Linux32 + 98)
#define __NR_Linux32_statfs (__NR_Linux32 + 99)
#define __NR_Linux32_fstatfs (__NR_Linux32 + 100)
#define __NR_Linux32_ioperm (__NR_Linux32 + 101)
#define __NR_Linux32_socketcall (__NR_Linux32 + 102)
#define __NR_Linux32_syslog (__NR_Linux32 + 103)
#define __NR_Linux32_setitimer (__NR_Linux32 + 104)
#define __NR_Linux32_getitimer (__NR_Linux32 + 105)
#define __NR_Linux32_stat (__NR_Linux32 + 106)
#define __NR_Linux32_lstat (__NR_Linux32 + 107)
#define __NR_Linux32_fstat (__NR_Linux32 + 108)
#define __NR_Linux32_unused109 (__NR_Linux32 + 109)
#define __NR_Linux32_iopl (__NR_Linux32 + 110)
#define __NR_Linux32_vhangup (__NR_Linux32 + 111)
#define __NR_Linux32_idle (__NR_Linux32 + 112)
#define __NR_Linux32_vm86 (__NR_Linux32 + 113)
#define __NR_Linux32_wait4 (__NR_Linux32 + 114)
#define __NR_Linux32_swapoff (__NR_Linux32 + 115)
#define __NR_Linux32_sysinfo (__NR_Linux32 + 116)
#define __NR_Linux32_ipc (__NR_Linux32 + 117)
#define __NR_Linux32_fsync (__NR_Linux32 + 118)
#define __NR_Linux32_sigreturn (__NR_Linux32 + 119)
#define __NR_Linux32_clone (__NR_Linux32 + 120)
#define __NR_Linux32_setdomainname (__NR_Linux32 + 121)
#define __NR_Linux32_uname (__NR_Linux32 + 122)
#define __NR_Linux32_modify_ldt (__NR_Linux32 + 123)
#define __NR_Linux32_adjtimex (__NR_Linux32 + 124)
#define __NR_Linux32_mprotect (__NR_Linux32 + 125)
#define __NR_Linux32_sigprocmask (__NR_Linux32 + 126)
#define __NR_Linux32_create_module (__NR_Linux32 + 127)
#define __NR_Linux32_init_module (__NR_Linux32 + 128)
#define __NR_Linux32_delete_module (__NR_Linux32 + 129)
#define __NR_Linux32_get_kernel_syms (__NR_Linux32 + 130)
#define __NR_Linux32_quotactl (__NR_Linux32 + 131)
#define __NR_Linux32_getpgid (__NR_Linux32 + 132)
#define __NR_Linux32_fchdir (__NR_Linux32 + 133)
#define __NR_Linux32_bdflush (__NR_Linux32 + 134)
#define __NR_Linux32_sysfs (__NR_Linux32 + 135)
#define __NR_Linux32_personality (__NR_Linux32 + 136)
#define __NR_Linux32_afs_syscall (__NR_Linux32 + 137) /* Syscall for Andrew File System */
#define __NR_Linux32_setfsuid (__NR_Linux32 + 138)
#define __NR_Linux32_setfsgid (__NR_Linux32 + 139)
#define __NR_Linux32__llseek (__NR_Linux32 + 140)
#define __NR_Linux32_getdents (__NR_Linux32 + 141)
#define __NR_Linux32__newselect (__NR_Linux32 + 142)
#define __NR_Linux32_flock (__NR_Linux32 + 143)
#define __NR_Linux32_msync (__NR_Linux32 + 144)
#define __NR_Linux32_readv (__NR_Linux32 + 145)
#define __NR_Linux32_writev (__NR_Linux32 + 146)
#define __NR_Linux32_cacheflush (__NR_Linux32 + 147)
#define __NR_Linux32_cachectl (__NR_Linux32 + 148)
#define __NR_Linux32_sysmips (__NR_Linux32 + 149)
#define __NR_Linux32_unused150 (__NR_Linux32 + 150)
#define __NR_Linux32_getsid (__NR_Linux32 + 151)
#define __NR_Linux32_fdatasync (__NR_Linux32 + 152)
#define __NR_Linux32__sysctl (__NR_Linux32 + 153)
#define __NR_Linux32_mlock (__NR_Linux32 + 154)
#define __NR_Linux32_munlock (__NR_Linux32 + 155)
#define __NR_Linux32_mlockall (__NR_Linux32 + 156)
#define __NR_Linux32_munlockall (__NR_Linux32 + 157)
#define __NR_Linux32_sched_setparam (__NR_Linux32 + 158)
#define __NR_Linux32_sched_getparam (__NR_Linux32 + 159)
#define __NR_Linux32_sched_setscheduler (__NR_Linux32 + 160)
#define __NR_Linux32_sched_getscheduler (__NR_Linux32 + 161)
#define __NR_Linux32_sched_yield (__NR_Linux32 + 162)
#define __NR_Linux32_sched_get_priority_max (__NR_Linux32 + 163)
#define __NR_Linux32_sched_get_priority_min (__NR_Linux32 + 164)
#define __NR_Linux32_sched_rr_get_interval (__NR_Linux32 + 165)
#define __NR_Linux32_nanosleep (__NR_Linux32 + 166)
#define __NR_Linux32_mremap (__NR_Linux32 + 167)
#define __NR_Linux32_accept (__NR_Linux32 + 168)
#define __NR_Linux32_bind (__NR_Linux32 + 169)
#define __NR_Linux32_connect (__NR_Linux32 + 170)
#define __NR_Linux32_getpeername (__NR_Linux32 + 171)
#define __NR_Linux32_getsockname (__NR_Linux32 + 172)
#define __NR_Linux32_getsockopt (__NR_Linux32 + 173)
#define __NR_Linux32_listen (__NR_Linux32 + 174)
#define __NR_Linux32_recv (__NR_Linux32 + 175)
#define __NR_Linux32_recvfrom (__NR_Linux32 + 176)
#define __NR_Linux32_recvmsg (__NR_Linux32 + 177)
#define __NR_Linux32_send (__NR_Linux32 + 178)
#define __NR_Linux32_sendmsg (__NR_Linux32 + 179)
#define __NR_Linux32_sendto (__NR_Linux32 + 180)
#define __NR_Linux32_setsockopt (__NR_Linux32 + 181)
#define __NR_Linux32_shutdown (__NR_Linux32 + 182)
#define __NR_Linux32_socket (__NR_Linux32 + 183)
#define __NR_Linux32_socketpair (__NR_Linux32 + 184)
#define __NR_Linux32_setresuid (__NR_Linux32 + 185)
#define __NR_Linux32_getresuid (__NR_Linux32 + 186)
#define __NR_Linux32_query_module (__NR_Linux32 + 187)
#define __NR_Linux32_poll (__NR_Linux32 + 188)
#define __NR_Linux32_nfsservctl (__NR_Linux32 + 189)
#define __NR_Linux32_setresgid (__NR_Linux32 + 190)
#define __NR_Linux32_getresgid (__NR_Linux32 + 191)
#define __NR_Linux32_prctl (__NR_Linux32 + 192)
#define __NR_Linux32_rt_sigreturn (__NR_Linux32 + 193)
#define __NR_Linux32_rt_sigaction (__NR_Linux32 + 194)
#define __NR_Linux32_rt_sigprocmask (__NR_Linux32 + 195)
#define __NR_Linux32_rt_sigpending (__NR_Linux32 + 196)
#define __NR_Linux32_rt_sigtimedwait (__NR_Linux32 + 197)
#define __NR_Linux32_rt_sigqueueinfo (__NR_Linux32 + 198)
#define __NR_Linux32_rt_sigsuspend (__NR_Linux32 + 199)
#define __NR_Linux32_pread (__NR_Linux32 + 200)
#define __NR_Linux32_pwrite (__NR_Linux32 + 201)
#define __NR_Linux32_chown (__NR_Linux32 + 202)
#define __NR_Linux32_getcwd (__NR_Linux32 + 203)
#define __NR_Linux32_capget (__NR_Linux32 + 204)
#define __NR_Linux32_capset (__NR_Linux32 + 205)
#define __NR_Linux32_sigaltstack (__NR_Linux32 + 206)
#define __NR_Linux32_sendfile (__NR_Linux32 + 207)
#define __NR_Linux32_getpmsg (__NR_Linux32 + 208)
#define __NR_Linux32_putpmsg (__NR_Linux32 + 209)
#define __NR_Linux32_mmap2 (__NR_Linux32 + 210)
#define __NR_Linux32_truncate64 (__NR_Linux32 + 211)
#define __NR_Linux32_ftruncate64 (__NR_Linux32 + 212)
#define __NR_Linux32_stat64 (__NR_Linux32 + 213)
#define __NR_Linux32_lstat64 (__NR_Linux32 + 214)
#define __NR_Linux32_fstat64 (__NR_Linux32 + 215)
#define __NR_Linux32_root_pivot (__NR_Linux32 + 216)
#define __NR_Linux32_mincore (__NR_Linux32 + 217)
#define __NR_Linux32_madvise (__NR_Linux32 + 218)
#define __NR_Linux32_getdents64 (__NR_Linux32 + 219)
#define __NR_Linux32_fcntl64 (__NR_Linux32 + 220)
/*
* Offset of the last Linux o32 flavoured syscall
*/
#define __NR_Linux32_syscalls 220
/*
* Linux 64-bit syscalls are in the range from 5000 to 5999.
*/
#define __NR_Linux 5000
#define __NR_syscall (__NR_Linux + 0)
#define __NR_exit (__NR_Linux + 1)
#define __NR_fork (__NR_Linux + 2)
#define __NR_read (__NR_Linux + 3)
#define __NR_write (__NR_Linux + 4)
#define __NR_open (__NR_Linux + 5)
#define __NR_close (__NR_Linux + 6)
#define __NR_waitpid (__NR_Linux + 7)
#define __NR_creat (__NR_Linux + 8)
#define __NR_link (__NR_Linux + 9)
#define __NR_unlink (__NR_Linux + 10)
#define __NR_execve (__NR_Linux + 11)
#define __NR_chdir (__NR_Linux + 12)
#define __NR_time (__NR_Linux + 13)
#define __NR_mknod (__NR_Linux + 14)
#define __NR_chmod (__NR_Linux + 15)
#define __NR_lchown (__NR_Linux + 16)
#define __NR_break (__NR_Linux + 17)
#define __NR_oldstat (__NR_Linux + 18)
#define __NR_lseek (__NR_Linux + 19)
#define __NR_getpid (__NR_Linux + 20)
#define __NR_mount (__NR_Linux + 21)
#define __NR_umount (__NR_Linux + 22)
#define __NR_setuid (__NR_Linux + 23)
#define __NR_getuid (__NR_Linux + 24)
#define __NR_stime (__NR_Linux + 25)
#define __NR_ptrace (__NR_Linux + 26)
#define __NR_alarm (__NR_Linux + 27)
#define __NR_oldfstat (__NR_Linux + 28)
#define __NR_pause (__NR_Linux + 29)
#define __NR_utime (__NR_Linux + 30)
#define __NR_stty (__NR_Linux + 31)
#define __NR_gtty (__NR_Linux + 32)
#define __NR_access (__NR_Linux + 33)
#define __NR_nice (__NR_Linux + 34)
#define __NR_ftime (__NR_Linux + 35)
#define __NR_sync (__NR_Linux + 36)
#define __NR_kill (__NR_Linux + 37)
#define __NR_rename (__NR_Linux + 38)
#define __NR_mkdir (__NR_Linux + 39)
#define __NR_rmdir (__NR_Linux + 40)
#define __NR_dup (__NR_Linux + 41)
#define __NR_pipe (__NR_Linux + 42)
#define __NR_times (__NR_Linux + 43)
#define __NR_prof (__NR_Linux + 44)
#define __NR_brk (__NR_Linux + 45)
#define __NR_setgid (__NR_Linux + 46)
#define __NR_getgid (__NR_Linux + 47)
#define __NR_signal (__NR_Linux + 48)
#define __NR_geteuid (__NR_Linux + 49)
#define __NR_getegid (__NR_Linux + 50)
#define __NR_acct (__NR_Linux + 51)
#define __NR_umount2 (__NR_Linux + 52)
#define __NR_lock (__NR_Linux + 53)
#define __NR_ioctl (__NR_Linux + 54)
#define __NR_fcntl (__NR_Linux + 55)
#define __NR_mpx (__NR_Linux + 56)
#define __NR_setpgid (__NR_Linux + 57)
#define __NR_ulimit (__NR_Linux + 58)
#define __NR_unused59 (__NR_Linux + 59)
#define __NR_umask (__NR_Linux + 60)
#define __NR_chroot (__NR_Linux + 61)
#define __NR_ustat (__NR_Linux + 62)
#define __NR_dup2 (__NR_Linux + 63)
#define __NR_getppid (__NR_Linux + 64)
#define __NR_getpgrp (__NR_Linux + 65)
#define __NR_setsid (__NR_Linux + 66)
#define __NR_sigaction (__NR_Linux + 67)
#define __NR_sgetmask (__NR_Linux + 68)
#define __NR_ssetmask (__NR_Linux + 69)
#define __NR_setreuid (__NR_Linux + 70)
#define __NR_setregid (__NR_Linux + 71)
#define __NR_sigsuspend (__NR_Linux + 72)
#define __NR_sigpending (__NR_Linux + 73)
#define __NR_sethostname (__NR_Linux + 74)
#define __NR_setrlimit (__NR_Linux + 75)
#define __NR_getrlimit (__NR_Linux + 76)
#define __NR_getrusage (__NR_Linux + 77)
#define __NR_gettimeofday (__NR_Linux + 78)
#define __NR_settimeofday (__NR_Linux + 79)
#define __NR_getgroups (__NR_Linux + 80)
#define __NR_setgroups (__NR_Linux + 81)
#define __NR_reserved82 (__NR_Linux + 82)
#define __NR_symlink (__NR_Linux + 83)
#define __NR_oldlstat (__NR_Linux + 84)
#define __NR_readlink (__NR_Linux + 85)
#define __NR_uselib (__NR_Linux + 86)
#define __NR_swapon (__NR_Linux + 87)
#define __NR_reboot (__NR_Linux + 88)
#define __NR_readdir (__NR_Linux + 89)
#define __NR_mmap (__NR_Linux + 90)
#define __NR_munmap (__NR_Linux + 91)
#define __NR_truncate (__NR_Linux + 92)
#define __NR_ftruncate (__NR_Linux + 93)
#define __NR_fchmod (__NR_Linux + 94)
#define __NR_fchown (__NR_Linux + 95)
#define __NR_getpriority (__NR_Linux + 96)
#define __NR_setpriority (__NR_Linux + 97)
#define __NR_profil (__NR_Linux + 98)
#define __NR_statfs (__NR_Linux + 99)
#define __NR_fstatfs (__NR_Linux + 100)
#define __NR_ioperm (__NR_Linux + 101)
#define __NR_socketcall (__NR_Linux + 102)
#define __NR_syslog (__NR_Linux + 103)
#define __NR_setitimer (__NR_Linux + 104)
#define __NR_getitimer (__NR_Linux + 105)
#define __NR_stat (__NR_Linux + 106)
#define __NR_lstat (__NR_Linux + 107)
#define __NR_fstat (__NR_Linux + 108)
#define __NR_unused109 (__NR_Linux + 109)
#define __NR_iopl (__NR_Linux + 110)
#define __NR_vhangup (__NR_Linux + 111)
#define __NR_idle (__NR_Linux + 112)
#define __NR_vm86 (__NR_Linux + 113)
#define __NR_wait4 (__NR_Linux + 114)
#define __NR_swapoff (__NR_Linux + 115)
#define __NR_sysinfo (__NR_Linux + 116)
#define __NR_ipc (__NR_Linux + 117)
#define __NR_fsync (__NR_Linux + 118)
#define __NR_sigreturn (__NR_Linux + 119)
#define __NR_clone (__NR_Linux + 120)
#define __NR_setdomainname (__NR_Linux + 121)
#define __NR_uname (__NR_Linux + 122)
#define __NR_modify_ldt (__NR_Linux + 123)
#define __NR_adjtimex (__NR_Linux + 124)
#define __NR_mprotect (__NR_Linux + 125)
#define __NR_sigprocmask (__NR_Linux + 126)
#define __NR_create_module (__NR_Linux + 127)
#define __NR_init_module (__NR_Linux + 128)
#define __NR_delete_module (__NR_Linux + 129)
#define __NR_get_kernel_syms (__NR_Linux + 130)
#define __NR_quotactl (__NR_Linux + 131)
#define __NR_getpgid (__NR_Linux + 132)
#define __NR_fchdir (__NR_Linux + 133)
#define __NR_bdflush (__NR_Linux + 134)
#define __NR_sysfs (__NR_Linux + 135)
#define __NR_personality (__NR_Linux + 136)
#define __NR_afs_syscall (__NR_Linux + 137) /* Syscall for Andrew File System */
#define __NR_setfsuid (__NR_Linux + 138)
#define __NR_setfsgid (__NR_Linux + 139)
#define __NR__llseek (__NR_Linux + 140)
#define __NR_getdents (__NR_Linux + 141)
#define __NR__newselect (__NR_Linux + 142)
#define __NR_flock (__NR_Linux + 143)
#define __NR_msync (__NR_Linux + 144)
#define __NR_readv (__NR_Linux + 145)
#define __NR_writev (__NR_Linux + 146)
#define __NR_cacheflush (__NR_Linux + 147)
#define __NR_cachectl (__NR_Linux + 148)
#define __NR_sysmips (__NR_Linux + 149)
#define __NR_unused150 (__NR_Linux + 150)
#define __NR_getsid (__NR_Linux + 151)
#define __NR_fdatasync (__NR_Linux + 152)
#define __NR__sysctl (__NR_Linux + 153)
#define __NR_mlock (__NR_Linux + 154)
#define __NR_munlock (__NR_Linux + 155)
#define __NR_mlockall (__NR_Linux + 156)
#define __NR_munlockall (__NR_Linux + 157)
#define __NR_sched_setparam (__NR_Linux + 158)
#define __NR_sched_getparam (__NR_Linux + 159)
#define __NR_sched_setscheduler (__NR_Linux + 160)
#define __NR_sched_getscheduler (__NR_Linux + 161)
#define __NR_sched_yield (__NR_Linux + 162)
#define __NR_sched_get_priority_max (__NR_Linux + 163)
#define __NR_sched_get_priority_min (__NR_Linux + 164)
#define __NR_sched_rr_get_interval (__NR_Linux + 165)
#define __NR_nanosleep (__NR_Linux + 166)
#define __NR_mremap (__NR_Linux + 167)
#define __NR_accept (__NR_Linux + 168)
#define __NR_bind (__NR_Linux + 169)
#define __NR_connect (__NR_Linux + 170)
#define __NR_getpeername (__NR_Linux + 171)
#define __NR_getsockname (__NR_Linux + 172)
#define __NR_getsockopt (__NR_Linux + 173)
#define __NR_listen (__NR_Linux + 174)
#define __NR_recv (__NR_Linux + 175)
#define __NR_recvfrom (__NR_Linux + 176)
#define __NR_recvmsg (__NR_Linux + 177)
#define __NR_send (__NR_Linux + 178)
#define __NR_sendmsg (__NR_Linux + 179)
#define __NR_sendto (__NR_Linux + 180)
#define __NR_setsockopt (__NR_Linux + 181)
#define __NR_shutdown (__NR_Linux + 182)
#define __NR_socket (__NR_Linux + 183)
#define __NR_socketpair (__NR_Linux + 184)
#define __NR_setresuid (__NR_Linux + 185)
#define __NR_getresuid (__NR_Linux + 186)
#define __NR_query_module (__NR_Linux + 187)
#define __NR_poll (__NR_Linux + 188)
#define __NR_nfsservctl (__NR_Linux + 189)
#define __NR_setresgid (__NR_Linux + 190)
#define __NR_getresgid (__NR_Linux + 191)
#define __NR_prctl (__NR_Linux + 192)
#define __NR_rt_sigreturn (__NR_Linux + 193)
#define __NR_rt_sigaction (__NR_Linux + 194)
#define __NR_rt_sigprocmask (__NR_Linux + 195)
#define __NR_rt_sigpending (__NR_Linux + 196)
#define __NR_rt_sigtimedwait (__NR_Linux + 197)
#define __NR_rt_sigqueueinfo (__NR_Linux + 198)
#define __NR_rt_sigsuspend (__NR_Linux + 199)
#define __NR_pread (__NR_Linux + 200)
#define __NR_pwrite (__NR_Linux + 201)
#define __NR_chown (__NR_Linux + 202)
#define __NR_getcwd (__NR_Linux + 203)
#define __NR_capget (__NR_Linux + 204)
#define __NR_capset (__NR_Linux + 205)
#define __NR_sigaltstack (__NR_Linux + 206)
#define __NR_sendfile (__NR_Linux + 207)
#define __NR_getpmsg (__NR_Linux + 208)
#define __NR_putpmsg (__NR_Linux + 209)
#define __NR_root_pivot (__NR_Linux + 210)
#define __NR_mincore (__NR_Linux + 211)
#define __NR_madvise (__NR_Linux + 212)
#define __NR_getdents64 (__NR_Linux + 213)
/*
* Offset of the last Linux flavoured syscall
*/
#define __NR_Linux_syscalls 213
#ifndef _LANGUAGE_ASSEMBLY
/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
#define _syscall0(type,name) \
type name(void) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a3 asm("$7"); \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"li\t$2, %2\t\t\t# " #name "\n\t" \
"syscall\n\t" \
".set\treorder" \
: "=&r" (__v0), "=r" (__a3) \
: "i" (__NR_##name) \
: "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
/*
* DANGER: This macro isn't usable for the pipe(2) call
* which has a unusual return convention.
*/
#define _syscall1(type,name,atype,a) \
type name(atype a) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a3 asm("$7"); \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"li\t$2, %3\t\t\t# " #name "\n\t" \
"syscall\n\t" \
".set\treorder" \
: "=&r" (__v0), "=r" (__a3) \
: "r" (__a0), "i" (__NR_##name) \
: "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#define _syscall2(type,name,atype,a,btype,b) \
type name(atype a, btype b) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a1 asm("$5") = (unsigned long) b; \
register unsigned long __a3 asm("$7"); \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"li\t$2, %4\t\t\t# " #name "\n\t" \
"syscall\n\t" \
".set\treorder" \
: "=&r" (__v0), "=r" (__a3) \
: "r" (__a0), "r" (__a1), "i" (__NR_##name) \
: "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#define _syscall3(type,name,atype,a,btype,b,ctype,c) \
type name(atype a, btype b, ctype c) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a1 asm("$5") = (unsigned long) b; \
register unsigned long __a2 asm("$6") = (unsigned long) c; \
register unsigned long __a3 asm("$7"); \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"li\t$2, %5\t\t\t# " #name "\n\t" \
"syscall\n\t" \
".set\treorder" \
: "=&r" (__v0), "=r" (__a3) \
: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
: "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#define _syscall4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
type name(atype a, btype b, ctype c, dtype d) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a1 asm("$5") = (unsigned long) b; \
register unsigned long __a2 asm("$6") = (unsigned long) c; \
register unsigned long __a3 asm("$7") = (unsigned long) d; \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"li\t$2, %5\t\t\t# " #name "\n\t" \
"syscall\n\t" \
".set\treorder" \
: "=&r" (__v0), "+r" (__a3) \
: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
: "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#if (_MIPS_SIM == _ABIN32) || (_MIPS_SIM == _ABI64)
#define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
type name (atype a,btype b,ctype c,dtype d,etype e) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a1 asm("$5") = (unsigned long) b; \
register unsigned long __a2 asm("$6") = (unsigned long) c; \
register unsigned long __a3 asm("$7") = (unsigned long) d; \
register unsigned long __a4 asm("$8") = (unsigned long) e; \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"li\t$2, %6\t\t\t# " #name "\n\t" \
"syscall\n\t" \
".set\treorder" \
: "=&r" (__v0), "+r" (__a3), "+r" (__a4) \
: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
: "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \
type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a1 asm("$5") = (unsigned long) b; \
register unsigned long __a2 asm("$6") = (unsigned long) c; \
register unsigned long __a3 asm("$7") = (unsigned long) d; \
register unsigned long __a4 asm("$8") = (unsigned long) e; \
register unsigned long __a5 asm("$9") = (unsigned long) f; \
\
__asm__ volatile ( "" \
: "+r" (__a5) \
: \
: "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"li\t$2, %6\t\t\t# " #name "\n\t" \
"syscall\n\t" \
".set\treorder" \
: "=&r" (__v0), "+r" (__a3), "+r" (__a4) \
: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
: "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#define _syscall7(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f,gtype,g) \
type name (atype a,btype b,ctype c,dtype d,etype e,ftype f,gtype g) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a1 asm("$5") = (unsigned long) b; \
register unsigned long __a2 asm("$6") = (unsigned long) c; \
register unsigned long __a3 asm("$7") = (unsigned long) d; \
register unsigned long __a4 asm("$8") = (unsigned long) e; \
register unsigned long __a5 asm("$9") = (unsigned long) f; \
register unsigned long __a6 asm("$10") = (unsigned long) g; \
\
__asm__ volatile ( "" \
: "+r" (__a5), "+r" (__a6) \
: \
: "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"li\t$2, %6\t\t\t# " #name "\n\t" \
"syscall\n\t" \
".set\treorder" \
: "=&r" (__v0), "+r" (__a3), "+r" (__a4) \
: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
: "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#else /* not N32 or 64 ABI */
/*
* Using those means your brain needs more than an oil change ;-)
*/
#define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
type name(atype a, btype b, ctype c, dtype d, etype e) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a1 asm("$5") = (unsigned long) b; \
register unsigned long __a2 asm("$6") = (unsigned long) c; \
register unsigned long __a3 asm("$7") = (unsigned long) d; \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"lw\t$2, %6\n\t" \
"subu\t$29, 32\n\t" \
"sw\t$2, 16($29)\n\t" \
"li\t$2, %5\t\t\t# " #name "\n\t" \
"syscall\n\t" \
"addiu\t$29, 32\n\t" \
".set\treorder" \
: "=&r" (__v0), "+r" (__a3) \
: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
"m" ((unsigned long)e) \
: "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \
type name(atype a, btype b, ctype c, dtype d, etype e, ftype f) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a1 asm("$5") = (unsigned long) b; \
register unsigned long __a2 asm("$6") = (unsigned long) c; \
register unsigned long __a3 asm("$7") = (unsigned long) d; \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"lw\t$2, %6\n\t" \
"lw\t$8, %7\n\t" \
"subu\t$29, 32\n\t" \
"sw\t$2, 16($29)\n\t" \
"sw\t$8, 20($29)\n\t" \
"li\t$2, %5\t\t\t# " #name "\n\t" \
"syscall\n\t" \
"addiu\t$29, 32\n\t" \
".set\treorder" \
: "=&r" (__v0), "+r" (__a3) \
: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
"m" ((unsigned long)e), "m" ((unsigned long)f) \
: "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#define _syscall7(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f,gtype,g) \
type name(atype a, btype b, ctype c, dtype d, etype e, ftype f, gtype g) \
{ \
register unsigned long __v0 asm("$2") = __NR_##name; \
register unsigned long __a0 asm("$4") = (unsigned long) a; \
register unsigned long __a1 asm("$5") = (unsigned long) b; \
register unsigned long __a2 asm("$6") = (unsigned long) c; \
register unsigned long __a3 asm("$7") = (unsigned long) d; \
\
__asm__ volatile ( \
".set\tnoreorder\n\t" \
"lw\t$2, %6\n\t" \
"lw\t$8, %7\n\t" \
"lw\t$9, %8\n\t" \
"subu\t$29, 32\n\t" \
"sw\t$2, 16($29)\n\t" \
"sw\t$8, 20($29)\n\t" \
"sw\t$9, 24($29)\n\t" \
"li\t$2, %5\t\t\t# " #name "\n\t" \
"syscall\n\t" \
"addiu\t$29, 32\n\t" \
".set\treorder" \
: "=&r" (__v0), "+r" (__a3) \
: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
"m" ((unsigned long)e), "m" ((unsigned long)f), \
"m" ((unsigned long)g), \
: "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
\
if (__a3 == 0) \
return (type) __v0; \
errno = __v0; \
return -1; \
}
#endif
#ifdef __KERNEL_SYSCALLS__
/*
* we need this inline - forking from kernel space will result
* in NO COPY ON WRITE (!!!), until an execve is executed. This
* is no problem, but for the stack. This is handled by not letting
* main() use the stack at all after fork(). Thus, no function
* calls - which means inline code for fork too, as otherwise we
* would use the stack upon exit from 'fork()'.
*
* Actually only pause and fork are needed inline, so that there
* won't be any messing with the stack from main(), but we define
* some others too.
*/
#define __NR__exit __NR_exit
static inline _syscall0(int,sync)
static inline _syscall0(pid_t,setsid)
static inline _syscall3(int,write,int,fd,const char *,buf,off_t,count)
static inline _syscall3(int,read,int,fd,char *,buf,off_t,count)
static inline _syscall3(off_t,lseek,int,fd,off_t,offset,int,count)
static inline _syscall1(int,dup,int,fd)
static inline _syscall3(int,execve,const char *,file,char **,argv,char **,envp)
static inline _syscall3(int,open,const char *,file,int,flag,int,mode)
static inline _syscall1(int,close,int,fd)
static inline _syscall1(int,_exit,int,exitcode)
static inline _syscall3(pid_t,waitpid,pid_t,pid,int *,wait_stat,int,options)
static inline _syscall1(int,delete_module,const char *,name)
static inline pid_t wait(int * wait_stat)
{
return waitpid(-1,wait_stat,0);
}
#endif /* !defined (__KERNEL_SYSCALLS__) */
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#endif /* _ASM_UNISTD_H */
|
|
From: James S. <jsi...@us...> - 2001-10-08 16:12:30
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv26016 Added Files: unistd.h Log Message: Rewrite _syscallX macros to make them safe against gcc miss optimization. |
|
From: Jun S. <ju...@us...> - 2001-10-07 16:57:23
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv4535/arch/mips/vr4181/osprey
Modified Files:
Makefile dbg_io.c prom.c reset.c setup.c
Log Message:
Update Osprey code. Sync up with OSS CVS tree.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile 2001/09/27 23:59:15 1.2
+++ Makefile 2001/10/07 16:57:20 1.3
@@ -11,7 +11,7 @@
.S.o:
$(CC) $(CFLAGS) -c $< -o $*.o
-O_TARGET:= osprey.o
+O_TARGET := osprey.o
obj-y := setup.o prom.o reset.o dbg_io.o
Index: dbg_io.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/dbg_io.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- dbg_io.c 2001/09/22 04:27:15 1.1
+++ dbg_io.c 2001/10/07 16:57:20 1.2
@@ -9,37 +9,37 @@
/* --- END OF CONFIG --- */
-#define UART16550_BAUD_2400 2400
-#define UART16550_BAUD_4800 4800
-#define UART16550_BAUD_9600 9600
-#define UART16550_BAUD_19200 19200
-#define UART16550_BAUD_38400 38400
-#define UART16550_BAUD_57600 57600
-#define UART16550_BAUD_115200 115200
+#define UART16550_BAUD_2400 2400
+#define UART16550_BAUD_4800 4800
+#define UART16550_BAUD_9600 9600
+#define UART16550_BAUD_19200 19200
+#define UART16550_BAUD_38400 38400
+#define UART16550_BAUD_57600 57600
+#define UART16550_BAUD_115200 115200
-#define UART16550_PARITY_NONE 0
-#define UART16550_PARITY_ODD 0x08
-#define UART16550_PARITY_EVEN 0x18
-#define UART16550_PARITY_MARK 0x28
-#define UART16550_PARITY_SPACE 0x38
+#define UART16550_PARITY_NONE 0
+#define UART16550_PARITY_ODD 0x08
+#define UART16550_PARITY_EVEN 0x18
+#define UART16550_PARITY_MARK 0x28
+#define UART16550_PARITY_SPACE 0x38
-#define UART16550_DATA_5BIT 0x0
-#define UART16550_DATA_6BIT 0x1
-#define UART16550_DATA_7BIT 0x2
-#define UART16550_DATA_8BIT 0x3
+#define UART16550_DATA_5BIT 0x0
+#define UART16550_DATA_6BIT 0x1
+#define UART16550_DATA_7BIT 0x2
+#define UART16550_DATA_8BIT 0x3
-#define UART16550_STOP_1BIT 0x0
-#define UART16550_STOP_2BIT 0x4
+#define UART16550_STOP_1BIT 0x0
+#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the debug board serial port for kdb */
-#define BASE 0xb7fffff0
-#define MAX_BAUD 115200
+#define BASE 0xb7fffff0
+#define MAX_BAUD 115200
-#define REG_OFFSET 1
+#define REG_OFFSET 1
static int remoteDebugInitialized = 1;
@@ -47,27 +47,27 @@
/* register offset */
-#define OFS_RCV_BUFFER 0
-#define OFS_TRANS_HOLD 0
-#define OFS_SEND_BUFFER 0
-#define OFS_INTR_ENABLE (1*REG_OFFSET)
-#define OFS_INTR_ID (2*REG_OFFSET)
-#define OFS_DATA_FORMAT (3*REG_OFFSET)
-#define OFS_LINE_CONTROL (3*REG_OFFSET)
-#define OFS_MODEM_CONTROL (4*REG_OFFSET)
-#define OFS_RS232_OUTPUT (4*REG_OFFSET)
-#define OFS_LINE_STATUS (5*REG_OFFSET)
-#define OFS_MODEM_STATUS (6*REG_OFFSET)
-#define OFS_RS232_INPUT (6*REG_OFFSET)
-#define OFS_SCRATCH_PAD (7*REG_OFFSET)
+#define OFS_RCV_BUFFER 0
+#define OFS_TRANS_HOLD 0
+#define OFS_SEND_BUFFER 0
+#define OFS_INTR_ENABLE (1*REG_OFFSET)
+#define OFS_INTR_ID (2*REG_OFFSET)
+#define OFS_DATA_FORMAT (3*REG_OFFSET)
+#define OFS_LINE_CONTROL (3*REG_OFFSET)
+#define OFS_MODEM_CONTROL (4*REG_OFFSET)
+#define OFS_RS232_OUTPUT (4*REG_OFFSET)
+#define OFS_LINE_STATUS (5*REG_OFFSET)
+#define OFS_MODEM_STATUS (6*REG_OFFSET)
+#define OFS_RS232_INPUT (6*REG_OFFSET)
+#define OFS_SCRATCH_PAD (7*REG_OFFSET)
-#define OFS_DIVISOR_LSB (0*REG_OFFSET)
-#define OFS_DIVISOR_MSB (1*REG_OFFSET)
+#define OFS_DIVISOR_LSB (0*REG_OFFSET)
+#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
-#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
-#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
+#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
+#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/prom.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- prom.c 2001/09/27 23:59:15 1.3
+++ prom.c 2001/10/07 16:57:20 1.4
@@ -1,17 +1,15 @@
-/***********************************************************************
- *
+/*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* arch/mips/vr4181/osprey/prom.c
* prom code for osprey.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
- ***********************************************************************
*/
#include <linux/init.h>
@@ -32,15 +30,15 @@
void __init prom_init()
{
strcpy(arcs_cmdline, "ip=bootp ");
- strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
- // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
+ strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
+ // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
// strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 ");
- mips_machgroup = MACH_GROUP_NEC_VR41XX;
- mips_machtype = MACH_NEC_OSPREY;
+ mips_machgroup = MACH_GROUP_NEC_VR41XX;
+ mips_machtype = MACH_NEC_OSPREY;
- /* 16MB fixed */
- add_memory_region(0, 16 << 20, BOOT_MEM_RAM);
+ /* 16MB fixed */
+ add_memory_region(0, 16 << 20, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/reset.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- reset.c 2001/09/22 16:35:15 1.2
+++ reset.c 2001/10/07 16:57:20 1.3
@@ -1,6 +1,6 @@
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
@@ -30,7 +30,7 @@
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t"
- "wait\n\t"
+ "wait\n\t"
".set\tmips0");
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c 2001/10/01 19:33:00 1.3
+++ setup.c 2001/10/07 16:57:20 1.4
@@ -6,6 +6,9 @@
* Copyright (C) 1999 Bradley D. LaRonde
* Copyright (C) 1999, 2000 Michael Klar
*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: js...@mv... or js...@ju...
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
@@ -21,63 +24,11 @@
#include <asm/vr4181/vr4181.h>
#include <asm/io.h>
-#include <linux/pc_keyb.h>
-extern struct kbd_ope no_kbd_ops;
-struct semaphore vr4181_dma_sem;
-
-// This enables the CF hacks below, to be replaced with real CF driver eventually
-#if defined(CONFIG_EVEREX_FREESTYLE)
-#define CF_HACK
-#else
-// If CF doesn't work on your device, try changing this to #define:
-#undef CF_HACK
-#endif
-
-#ifdef CONFIG_TCIC
-#define TCIC_BASE 0x240
-
-#define TCIC_MODE 0x08
-#define TCIC_AUX 0x0E
-
-#define TCIC_MODE_PGMMASK 0x1f
-#define TCIC_AUX_ILOCK (6<<5)
-#define TCIC_ILOCK_CRESET 0x04
-#endif
-
extern void nec_osprey_restart(char* c);
extern void nec_osprey_halt(void);
extern void nec_osprey_power_off(void);
-#if defined(CF_HACK) || defined(CONFIG_I82365)
-void __init put_cf_reg(unsigned char reg, unsigned char val)
-{
-#ifdef CONFIG_CPU_VR4181
- *VR4181_PCCARDINDEX = reg;
- barrier();
- *VR4181_PCCARDDATA = val;
-#else
- outb(reg, 0x3e0);
- outb(val, 0x3e1);
-#endif
-}
-#endif
-
-#if defined(CONFIG_NEC_OSPREY) || defined(CONFIG_IBM_WORKPAD) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R300) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R310) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R430) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R530) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R700) || \
- defined(CONFIG_NEC_MOBILEGEAR2_R730) || \
- defined(CONFIG_DOCOMO_SIGMARION) || \
- defined(CONFIG_AGENDA_VR3)
-// extern void platdep_setup(void);
-void platdep_setup(void) {}
-#else
-void platdep_setup(void) {}
-#endif
-
extern void vr4181_init_serial(void);
extern void vr4181_init_time(void);
@@ -89,91 +40,17 @@
vr4181_init_serial();
vr4181_init_time();
-#ifdef CONFIG_BLK_DEV_IDE
- ide_ops = &vr4181_ide_ops;
-#endif
-
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
- // reset the PC card, and power off
-#ifdef CONFIG_I82365
- put_cf_reg(0x03, 0x20); // socket 0
- put_cf_reg(0x43, 0x20); // socket 1
- put_cf_reg(0x02, 0x00); // socket 0
- put_cf_reg(0x42, 0x00); // socket 1
-#endif
-#ifdef CONFIG_TCIC
-{
- u_char mode;
- mode = (inb(TCIC_BASE+TCIC_MODE) & TCIC_MODE_PGMMASK) | TCIC_AUX_ILOCK;
- outb(mode, TCIC_BASE+TCIC_MODE);
- outb(TCIC_ILOCK_CRESET, TCIC_BASE+TCIC_AUX);
-}
-#endif
-
-#ifdef CF_HACK
- // this is a nasty hack to initialize the CF registers, eventually this
- // is to be replaced with a real CF controller driver
- {
- unsigned char i;
- unsigned char cfinitdata[] = { 0x90, 0x63, 0x00, 0x35, 0x00, 0x55,
- 0x76, 0x03, 0x77, 0x03, 0x70, 0x01, 0x78, 0x01, 0x10, 0x00,
- 0x1f, 0x00, 0xf0, 0x7f, 0x00, 0x00, 0x20, 0x00, 0xe4, 0x00,
- 0xe0, 0x3f, 0x00, 0x02, 0xe5, 0x00, 0xed, 0x00, 0x1b, 0x3f,
- 0x00, 0x00, 0xee, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x01,
- 0xf7, 0x00, 0xff, 0x00, 0x00, 0x00 };
-
-#ifdef CONFIG_CPU_VR4181
- // Enable CF, not key scan.
- *VR4181_KEYEN = 0;
-
- // Unmask all CF IRQs for now except for IRQ 3 (which makes it fail)
- // I think the bit sense in reversed from what User Manual states
- *VR4181_INTMSKREG = 0xdeb0;
-
- // Set CF wait states.
- *VR4181_CFG_REG_1 = 1;
-#else
-#warning "Generic CF hack in use, assuming non-i82365 registers set up prior to boot"
-#endif
-
- put_cf_reg(0x02, 0x10);
- udelay(1);
-
- for (i = 0x02; i < 0x36; i++)
- put_cf_reg(i, cfinitdata[i-2]);
-
- // enable the IO and mem windows, now that start and stop values set up
- put_cf_reg(0x06, 0xdf);
-
- // reset the card
- put_cf_reg(0x03, 0x23);
- udelay(1);
- put_cf_reg(0x03, 0x63);
- mdelay(30);
-
- // now set up CF config register (this assumes it is a CF card...)
- writeb(0x43, ioremap(0x10200, 1));
- }
-#endif
-
_machine_restart = nec_osprey_restart;
_machine_halt = nec_osprey_halt;
_machine_power_off = nec_osprey_power_off;
/* setup resource limit */
ioport_resource.end = 0xffffffff;
- iomem_resource.end = 0xffffffff;
-
- // Insure that vr4181_dma_sem is initialized as unlocked, even
- // in the case of a failed hibernate/wakeup:
- init_MUTEX(&vr4181_dma_sem);
-
- // Do platform-dependent setup.
- // This is mostly stuff that doesn't fit well anywhere else.
- platdep_setup();
+ iomem_resource.end = 0xffffffff;
/* [jsun] hack */
/*
|
|
From: Jun S. <ju...@us...> - 2001-10-07 16:57:23
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4181
In directory usw-pr-cvs1:/tmp/cvs-serv4535/include/asm-mips/vr4181
Modified Files:
irq.h vr4181.h
Log Message:
Update Osprey code. Sync up with OSS CVS tree.
Index: irq.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4181/irq.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- irq.h 2001/09/27 23:59:15 1.1
+++ irq.h 2001/10/07 16:57:20 1.2
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 1999 by Michael Klar
+ * Macros for vr4181 IRQ numbers.
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
@@ -120,4 +120,3 @@
#define VR4181_IRQ_MAX (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \
VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ)
-
Index: vr4181.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4181/vr4181.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- vr4181.h 2001/09/27 23:59:15 1.2
+++ vr4181.h 2001/10/07 16:57:20 1.3
@@ -1,14 +1,16 @@
-/* $Id$
- *
+/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Michael Klar
- * Copyright (C) 2001 Monta Vista Software, js...@mv...
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: js...@mv... or js...@ju...
+ *
*/
-#ifndef __ASM_MIPS_VR4181_H
-#define __ASM_MIPS_VR4181_H
+#ifndef __ASM_VR4181_VR4181_H
+#define __ASM_VR4181_VR4181_H
#include <asm/addrspace.h>
@@ -408,4 +410,4 @@
#define VR4181_PORT_BASE (KSEG1 + VR4181_ISA_IO)
#define VR4181_ISAMEM_BASE (KSEG1 + VR4181_ISA_MEM)
-#endif /* __ASM_MIPS_VR4181_H */
+#endif /* __ASM_VR4181_VR4181_H */
|
|
From: Jun S. <ju...@us...> - 2001-10-07 16:57:23
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv4535/arch/mips/vr4181/common
Modified Files:
int_handler.S irq.c serial.c time.c
Log Message:
Update Osprey code. Sync up with OSS CVS tree.
Index: int_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/int_handler.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- int_handler.S 2001/09/29 00:42:25 1.2
+++ int_handler.S 2001/10/07 16:57:19 1.3
@@ -1,13 +1,5 @@
/*
- * linux/arch/mips/vr4181/common/int_handler.S
- *
- * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
- *
- * Written by Ralf Baechle and Andreas Busse, modified for DECStation
- * support by Paul Antoine and Harald Koerfgen.
- *
- * completly rewritten:
- * Copyright (C) 1998 Harald Koerfgen
+ * arch/mips/vr4181/common/int_handler.S
*
* Adapted to the VR4181 and almost entirely rewritten:
* Copyright (C) 1999 Bradley D. LaRonde and Michael Klar
@@ -47,86 +39,86 @@
.set at
.set noreorder
- mfc0 t0, CP0_CAUSE
- mfc0 t2, CP0_STATUS
+ mfc0 t0, CP0_CAUSE
+ mfc0 t2, CP0_STATUS
- and t0, t2
+ and t0, t2
/* we check IP3 first; it happens most frequently */
- andi t1, t0, STATUSF_IP3
- bnez t1, ll_cpu_ip3
- andi t1, t0, STATUSF_IP2
- bnez t1, ll_cpu_ip2
- andi t1, t0, STATUSF_IP7 /* cpu timer */
- bnez t1, ll_cputimer_irq
- andi t1, t0, STATUSF_IP4
- bnez t1, ll_cpu_ip4
- andi t1, t0, STATUSF_IP5
- bnez t1, ll_cpu_ip5
- andi t1, t0, STATUSF_IP6
- bnez t1, ll_cpu_ip6
- andi t1, t0, STATUSF_IP0 /* software int 0 */
- bnez t1, ll_cpu_ip0
- andi t1, t0, STATUSF_IP1 /* software int 1 */
- bnez t1, ll_cpu_ip1
- nop
+ andi t1, t0, STATUSF_IP3
+ bnez t1, ll_cpu_ip3
+ andi t1, t0, STATUSF_IP2
+ bnez t1, ll_cpu_ip2
+ andi t1, t0, STATUSF_IP7 /* cpu timer */
+ bnez t1, ll_cputimer_irq
+ andi t1, t0, STATUSF_IP4
+ bnez t1, ll_cpu_ip4
+ andi t1, t0, STATUSF_IP5
+ bnez t1, ll_cpu_ip5
+ andi t1, t0, STATUSF_IP6
+ bnez t1, ll_cpu_ip6
+ andi t1, t0, STATUSF_IP0 /* software int 0 */
+ bnez t1, ll_cpu_ip0
+ andi t1, t0, STATUSF_IP1 /* software int 1 */
+ bnez t1, ll_cpu_ip1
+ nop
.set reorder
do_spurious:
- j spurious_interrupt
+ j spurious_interrupt
/*
* regular CPU irqs
*/
ll_cputimer_irq:
- li a0, VR4181_IRQ_TIMER
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_TIMER
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip0:
- li a0, VR4181_IRQ_SW1
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_SW1
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip1:
- li a0, VR4181_IRQ_SW2
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_SW2
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip3:
- li a0, VR4181_IRQ_INT1
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_INT1
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip4:
- li a0, VR4181_IRQ_INT2
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_INT2
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip5:
- li a0, VR4181_IRQ_INT3
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_INT3
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
ll_cpu_ip6:
- li a0, VR4181_IRQ_INT4
- move a1, sp
- jal do_IRQ
- j ret_from_irq
+ li a0, VR4181_IRQ_INT4
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
/*
* One of the sys irq has happend.
*
* In the interest of speed, we first determine in the following order
* which 16-irq block have pending interrupts:
- * sysint1 (16 sources, including cascading intrs from GPIO)
+ * sysint1 (16 sources, including cascading intrs from GPIO)
* sysint2
* gpio (16 intr sources)
*
@@ -135,8 +127,8 @@
ll_cpu_ip2:
lui t3,%hi(VR4181_SYSINT1REG)
- lhu t0,%lo(VR4181_SYSINT1REG)(t3)
- lhu t2,%lo(VR4181_MSYSINT1REG)(t3)
+ lhu t0,%lo(VR4181_SYSINT1REG)(t3)
+ lhu t2,%lo(VR4181_MSYSINT1REG)(t3)
and t0, 0xfffb /* hack - remove RTC Long 1 intr */
and t0, t2
beqz t0, check_sysint2
@@ -151,24 +143,22 @@
check_sysint2:
- lhu t0,%lo(VR4181_SYSINT2REG)(t3)
- lhu t2,%lo(VR4181_MSYSINT2REG)(t3)
+ lhu t0,%lo(VR4181_SYSINT2REG)(t3)
+ lhu t2,%lo(VR4181_MSYSINT2REG)(t3)
and t0, 0xfffe /* hack - remove RTC Long 2 intr */
and t0, t2
li a0, VR4181_SYS_IRQ_BASE + 16 - 1
j check_16
check_gpio_int:
- lui t3,%hi(VR4181_GPINTMSK)
- lhu t0,%lo(VR4181_GPINTMSK)(t3)
- lhu t2,%lo(VR4181_GPINTSTAT)(t3)
+ lui t3,%hi(VR4181_GPINTMSK)
+ lhu t0,%lo(VR4181_GPINTMSK)(t3)
+ lhu t2,%lo(VR4181_GPINTSTAT)(t3)
xori t0, 0xffff /* why? reverse logic? */
and t0, t2
li a0, VR4181_GPIO_IRQ_BASE - 1
j check_16
-
-
/*
* When we reach check_16, we have 16-bit status in t0 and base irq number
* in a0.
@@ -181,7 +171,6 @@
addi a0, 8
j check_8
-
/*
* When we reach check_8, we have 8-bit status in t0 and base irq number
* in a0.
@@ -213,5 +202,5 @@
jal do_IRQ
j ret_from_irq
-
+
END(vr4181_handle_irq)
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/irq.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- irq.c 2001/09/29 00:42:25 1.5
+++ irq.c 2001/10/07 16:57:19 1.6
@@ -7,13 +7,12 @@
*
* Credits to Bradley D. LaRonde and Michael Klar for writing the original
* irq.c file which was derived from the common irq.c file.
- *
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
-
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
@@ -76,19 +75,19 @@
return 0;
}
-#define sys_irq_shutdown sys_irq_disable
-#define sys_irq_ack sys_irq_disable
-#define sys_irq_end sys_irq_enable
+#define sys_irq_shutdown sys_irq_disable
+#define sys_irq_ack sys_irq_disable
+#define sys_irq_end sys_irq_enable
static hw_irq_controller sys_irq_controller = {
- "vr4181_sys_irq",
- sys_irq_startup,
- sys_irq_shutdown,
- sys_irq_enable,
- sys_irq_disable,
- sys_irq_ack,
- sys_irq_end,
- NULL /* no affinity stuff for UP */
+ "vr4181_sys_irq",
+ sys_irq_startup,
+ sys_irq_shutdown,
+ sys_irq_enable,
+ sys_irq_disable,
+ sys_irq_ack,
+ sys_irq_end,
+ NULL /* no affinity stuff for UP */
};
/* ---------------------- gpio irq ------------------------ */
@@ -149,17 +148,17 @@
}
}
-#define gpio_irq_end gpio_irq_enable
+#define gpio_irq_end gpio_irq_enable
static hw_irq_controller gpio_irq_controller = {
- "vr4181_gpio_irq",
- gpio_irq_startup,
- gpio_irq_shutdown,
- gpio_irq_enable,
- gpio_irq_disable,
- gpio_irq_ack,
- gpio_irq_end,
- NULL /* no affinity stuff for UP */
+ "vr4181_gpio_irq",
+ gpio_irq_startup,
+ gpio_irq_shutdown,
+ gpio_irq_enable,
+ gpio_irq_disable,
+ gpio_irq_ack,
+ gpio_irq_end,
+ NULL /* no affinity stuff for UP */
};
/* --------------------- IRQ init stuff ---------------------- */
@@ -187,36 +186,36 @@
/* init sys irqs */
sys_irq_base = VR4181_SYS_IRQ_BASE;
for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].action = NULL;
- irq_desc[i].depth = 1;
- irq_desc[i].handler = &sys_irq_controller;
- }
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &sys_irq_controller;
+ }
/* init gpio irqs */
gpio_irq_base = VR4181_GPIO_IRQ_BASE;
for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].action = NULL;
- irq_desc[i].depth = 1;
- irq_desc[i].handler = &gpio_irq_controller;
- }
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &gpio_irq_controller;
+ }
- /* Default all ICU IRQs to off ... */
- *VR4181_MSYSINT1REG = 0;
- *VR4181_MSYSINT2REG = 0;
+ /* Default all ICU IRQs to off ... */
+ *VR4181_MSYSINT1REG = 0;
+ *VR4181_MSYSINT2REG = 0;
- /* We initialize the level 2 ICU registers to all bits disabled. */
- *VR4181_MPIUINTREG = 0;
- *VR4181_MAIUINTREG = 0;
- *VR4181_MKIUINTREG = 0;
+ /* We initialize the level 2 ICU registers to all bits disabled. */
+ *VR4181_MPIUINTREG = 0;
+ *VR4181_MAIUINTREG = 0;
+ *VR4181_MKIUINTREG = 0;
/* disable all GPIO intrs */
- *VR4181_GPINTMSK = 0xffff;
+ *VR4181_GPINTMSK = 0xffff;
- /* vector handler. What these do is register the IRQ as non-sharable */
- setup_irq(VR4181_IRQ_INT0, &cascade);
- setup_irq(VR4181_IRQ_GIU, &cascade);
+ /* vector handler. What these do is register the IRQ as non-sharable */
+ setup_irq(VR4181_IRQ_INT0, &cascade);
+ setup_irq(VR4181_IRQ_GIU, &cascade);
/*
* RTC interrupts are interesting. They have two destinations.
@@ -225,11 +224,11 @@
* We enable them here, but timer routine will register later
* with CPU IP3/IP4.
*/
- setup_irq(VR4181_IRQ_RTCL1, &reserved);
- setup_irq(VR4181_IRQ_RTCL2, &reserved);
+ setup_irq(VR4181_IRQ_RTCL1, &reserved);
+ setup_irq(VR4181_IRQ_RTCL2, &reserved);
#ifdef CONFIG_REMOTE_DEBUG
- printk("Setting debug traps - please connect the remote debugger.\n");
+ printk("Setting debug traps - please connect the remote debugger.\n");
set_debug_traps();
@@ -237,4 +236,3 @@
breakpoint();
#endif
}
-
Index: serial.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/serial.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- serial.c 2001/09/25 19:57:07 1.2
+++ serial.c 2001/10/07 16:57:19 1.3
@@ -5,8 +5,8 @@
* arch/mips/vr4181/common/serial.c
* initialize serial port on vr4181.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
@@ -15,8 +15,8 @@
/*
* [jsun, 010925]
* You need to make sure rs_table has at least one element in
- * drivers/char/serial.c file. There is no good way to do it right
- * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your
+ * drivers/char/serial.c file. There is no good way to do it right
+ * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your
* configure file, which would gives you 64 ports and wastes 11K ram.
*/
@@ -29,21 +29,21 @@
void __init vr4181_init_serial(void)
{
- struct serial_struct s;
+ struct serial_struct s;
/* turn on UART clock */
*VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU;
- /* clear memory */
- memset(&s, 0, sizeof(s));
+ /* clear memory */
+ memset(&s, 0, sizeof(s));
- s.line = 0; /* we set the first one */
- s.baud_base = 1152000;
- s.irq = VR4181_IRQ_SIU;
- s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */
- s.iomem_base = (u8*)VR4181_SIURB;
- s.iomem_reg_shift = 0;
- s.io_type = SERIAL_IO_MEM;
+ s.line = 0; /* we set the first one */
+ s.baud_base = 1152000;
+ s.irq = VR4181_IRQ_SIU;
+ s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */
+ s.iomem_base = (u8*)VR4181_SIURB;
+ s.iomem_reg_shift = 0;
+ s.io_type = SERIAL_IO_MEM;
if (early_serial_setup(&s) != 0) {
panic("vr4181_init_serial() failed!\n");
}
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- time.c 2001/10/01 19:32:59 1.3
+++ time.c 2001/10/07 16:57:19 1.4
@@ -2,11 +2,11 @@
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
- * rtc and time ops for vr4181. Part of code is drived from
- * linux-vr, originally written by Bradley D. LaRonde & Michael Klar.
+ * rtc and time ops for vr4181. Part of code is drived from
+ * linux-vr, originally written by Bradley D. LaRonde & Michael Klar.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
@@ -35,48 +35,48 @@
static inline unsigned short
read_time_reg(volatile unsigned short *reg)
{
- unsigned short value;
- do {
- value = *reg;
- barrier();
- } while (value != *reg);
- return value;
+ unsigned short value;
+ do {
+ value = *reg;
+ barrier();
+ } while (value != *reg);
+ return value;
}
static unsigned long
vr4181_rtc_get_time(void)
{
- unsigned short regh, regm, regl;
+ unsigned short regh, regm, regl;
- // why this crazy order, you ask? to guarantee that neither m
- // nor l wrap before all 3 read
- do {
- regm = read_time_reg(VR4181_ETIMEMREG);
- barrier();
- regh = read_time_reg(VR4181_ETIMEHREG);
- barrier();
- regl = read_time_reg(VR4181_ETIMELREG);
- } while (regm != read_time_reg(VR4181_ETIMEMREG));
- return ((regh << 17) | (regm << 1) | (regl >> 15));
+ // why this crazy order, you ask? to guarantee that neither m
+ // nor l wrap before all 3 read
+ do {
+ regm = read_time_reg(VR4181_ETIMEMREG);
+ barrier();
+ regh = read_time_reg(VR4181_ETIMEHREG);
+ barrier();
+ regl = read_time_reg(VR4181_ETIMELREG);
+ } while (regm != read_time_reg(VR4181_ETIMEMREG));
+ return ((regh << 17) | (regm << 1) | (regl >> 15));
}
static int
vr4181_rtc_set_time(unsigned long timeval)
{
- unsigned short intreg;
- unsigned long flags;
+ unsigned short intreg;
+ unsigned long flags;
- spin_lock_irqsave(&rtc_lock, flags);
- intreg = *VR4181_RTCINTREG & 0x05;
- barrier();
- *VR4181_ETIMELREG = timeval << 15;
- *VR4181_ETIMEMREG = timeval >> 1;
- *VR4181_ETIMEHREG = timeval >> 17;
- barrier();
- // assume that any ints that just triggered are invalid, since the
- // time value is written non-atomically in 3 separate regs
- *VR4181_RTCINTREG = 0x05 ^ intreg;
- spin_unlock_irqrestore(&rtc_lock, flags);
+ spin_lock_irqsave(&rtc_lock, flags);
+ intreg = *VR4181_RTCINTREG & 0x05;
+ barrier();
+ *VR4181_ETIMELREG = timeval << 15;
+ *VR4181_ETIMEMREG = timeval >> 1;
+ *VR4181_ETIMEHREG = timeval >> 17;
+ barrier();
+ // assume that any ints that just triggered are invalid, since the
+ // time value is written non-atomically in 3 separate regs
+ *VR4181_RTCINTREG = 0x05 ^ intreg;
+ spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
@@ -91,7 +91,7 @@
static void
vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
- /* Clear the interrupt. */
+ /* Clear the interrupt. */
*VR4181_RTCINTREG = 0x2;
/* call the generic one */
@@ -103,7 +103,7 @@
* vr4181_time_init:
*
* We pick the following choices:
- * . we use elapsed timer as the RTC. We set some reasonable init data since
+ * . we use elapsed timer as the RTC. We set some reasonable init data since
* it does not persist across reset
* . we use RTC1 as the system timer interrupt source.
* . we use CPU counter for fast_gettimeoffset and we calivrate the cpu
|
|
From: Jun S. <ju...@us...> - 2001-10-07 16:57:23
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv4535/arch/mips
Modified Files:
config.in
Log Message:
Update Osprey code. Sync up with OSS CVS tree.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.30
retrieving revision 1.31
diff -u -d -r1.30 -r1.31
--- config.in 2001/10/07 05:40:22 1.30
+++ config.in 2001/10/07 16:57:19 1.31
@@ -21,7 +21,6 @@
bool 'Support for Cobalt Server (EXPERIMENTAL)' CONFIG_COBALT_MICRO_SERVER
bool 'Support for DECstations (EXPERIMENTAL)' CONFIG_DECSTATION
bool 'Support for NEC DDB Vrc-5074 (EXPERIMENTAL)' CONFIG_DDB5074
- bool 'Support for NEC Osprey board (EXPERIMENTAL)' CONFIG_NEC_OSPREY
bool 'Support for NEC Eagle board (EXPERIMENTAL)' CONFIG_NEC_EAGLE
if [ "$CONFIG_NEC_EAGLE" = "y" ]; then
int ' Memory size' CONFIG_NEC_EAGLE_MEM_SIZE 32
@@ -197,17 +196,6 @@
define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_SCSI n
fi
-if [ "$CONFIG_NEC_OSPREY" = "y" ]; then
- define_bool CONFIG_CPU_VR41XX y
- define_bool CONFIG_VR4181 y
- define_bool CONFIG_SERIAL y
- define_bool CONFIG_SERIAL_MANY_PORTS y
- define_bool CONFIG_NEW_IRQ y
- define_bool CONFIG_IRQ_CPU y
- define_bool CONFIG_NEW_TIME_C y
- define_bool CONFIG_DUMMY_KEYB y
- define_bool CONFIG_SCSI n
-fi
if [ "$CONFIG_NEC_EAGLE" = "y" ]; then
define_bool CONFIG_CPU_VR41XX y
define_bool CONFIG_VR4122 y
@@ -344,7 +332,6 @@
if [ "$CONFIG_DECSTATION" = "y" -o \
"$CONFIG_DDB5074" = "y" -o \
"$CONFIG_NINO" = "y" -o \
- "$CONFIG_NEC_OSPREY" = "y" -o \
"$CONFIG_NEC_KORVA" = "y" ]; then
define_bool CONFIG_CPU_LITTLE_ENDIAN y
else
|
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