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From: James S. <jsi...@us...> - 2001-10-02 18:35:51
|
Update of /cvsroot/linux-mips/linux/arch/mips In directory usw-pr-cvs1:/tmp/cvs-serv22595/arch/mips Modified Files: defconfig Log Message: Synced to Ralph's tree for Osprey support. Index: defconfig =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/defconfig,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- defconfig 2001/09/10 16:27:08 1.8 +++ defconfig 2001/10/02 18:35:47 1.9 @@ -26,6 +26,7 @@ # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set # CONFIG_OLIVETTI_M700 is not set CONFIG_SGI_IP22=y # CONFIG_SNI_RM200_PCI is not set |
|
From: James S. <jsi...@us...> - 2001-10-02 17:18:35
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv6109/kernel Modified Files: entry.S Log Message: Make RM200C compile again. Index: entry.S =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/entry.S,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- entry.S 2001/08/22 18:18:13 1.5 +++ entry.S 2001/10/02 17:18:31 1.6 @@ -66,6 +66,7 @@ lw v1, TASK_SIGPENDING($28) bnez v0, reschedule bnez v1, signal_return + FEXPORT(restore_all) restore_all: .set noat RESTORE_ALL_AND_RET .set at |
|
From: James S. <jsi...@us...> - 2001-10-02 17:18:35
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv6109/configs Modified Files: defconfig-rm200 Log Message: Make RM200C compile again. Index: defconfig-rm200 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-rm200,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- defconfig-rm200 2001/09/15 17:06:10 1.5 +++ defconfig-rm200 2001/10/02 17:18:31 1.6 @@ -31,6 +31,7 @@ # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set CONFIG_SNI_RM200_PCI=y @@ -44,9 +45,9 @@ CONFIG_ARC32=y CONFIG_I8259=y CONFIG_ISA=y +CONFIG_NEW_IRQ=y CONFIG_PC_KEYB=y CONFIG_PCI=y -CONFIG_ROTTEN_IRQ=y CONFIG_OLD_TIME_C=y CONFIG_EISA=y @@ -64,8 +65,8 @@ # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -CONFIG_CPU_R5000=y +CONFIG_CPU_R4X00=y +# CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set # CONFIG_CPU_RM7000 is not set |
|
From: James S. <jsi...@us...> - 2001-10-02 17:18:35
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv6109
Modified Files:
config.in
Log Message:
Make RM200C compile again.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.28
retrieving revision 1.29
diff -u -d -r1.28 -r1.29
--- config.in 2001/10/01 19:33:00 1.28
+++ config.in 2001/10/02 17:18:31 1.29
@@ -51,6 +51,7 @@
bool 'Support for Momentum Ocelot board' CONFIG_MOMENCO_OCELOT
bool 'Support for NEC DDB Vrc-5476' CONFIG_DDB5476
bool 'Support for NEC DDB Vrc-5477' CONFIG_DDB5477
+bool 'Support for NEC Osprey board' CONFIG_NEC_OSPREY
bool 'Support for Olivetti M700-10' CONFIG_OLIVETTI_M700
bool 'Support for SGI IP22' CONFIG_SGI_IP22
bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
@@ -150,9 +151,9 @@
define_bool CONFIG_ARC32 y
define_bool CONFIG_I8259 y
define_bool CONFIG_ISA y
+ define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_PCI y
- define_bool CONFIG_ROTTEN_IRQ y
define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_DDB5074" = "y" ]; then
@@ -180,6 +181,17 @@
define_bool CONFIG_NEW_PCI y
define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_DUMMY_KEYB y
+fi
+if [ "$CONFIG_NEC_OSPREY" = "y" ]; then
+ define_bool CONFIG_CPU_VR41XX y
+ define_bool CONFIG_VR4181 y
+ define_bool CONFIG_SERIAL y
+ define_bool CONFIG_SERIAL_MANY_PORTS y
+ define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_IRQ_CPU y
+ define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_DUMMY_KEYB y
+ define_bool CONFIG_SCSI n
fi
if [ "$CONFIG_NEC_OSPREY" = "y" ]; then
define_bool CONFIG_CPU_VR41XX y
|
|
From: James S. <jsi...@us...> - 2001-10-02 17:18:34
|
Update of /cvsroot/linux-mips/linux/arch/mips/sni
In directory usw-pr-cvs1:/tmp/cvs-serv6109/sni
Modified Files:
int-handler.S irq.c setup.c
Log Message:
Make RM200C compile again.
Index: int-handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sni/int-handler.S,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- int-handler.S 2001/06/22 02:29:31 1.1.1.1
+++ int-handler.S 2001/10/02 17:18:31 1.2
@@ -1,7 +1,7 @@
/*
* SNI RM200 PCI specific interrupt handler code.
*
- * Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000 by Ralf Baechle
+ * Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000, 01 by Ralf Baechle
*/
#include <asm/asm.h>
#include <asm/mipsregs.h>
@@ -9,12 +9,13 @@
#include <asm/sni.h>
#include <asm/stackframe.h>
-/* The PCI ASIC has the nasty property that it may delay writes if it is busy.
- As a consequence from writes that have not graduated when we exit from the
- interrupt handler we might catch a spurious interrupt. To avoid this we
- force the PCI ASIC to graduate all writes by executing a read from the
- PCI bus. */
-
+/*
+ * The PCI ASIC has the nasty property that it may delay writes if it is busy.
+ * As a consequence from writes that have not graduated when we exit from the
+ * interrupt handler we might catch a spurious interrupt. To avoid this we
+ * force the PCI ASIC to graduate all writes by executing a read from the
+ * PCI bus.
+ */
.set noreorder
.set noat
.align 5
@@ -46,7 +47,7 @@
bnez t1, _hwint0
nop
- j return # spurious interrupt
+ j restore_all # spurious interrupt
nop
##############################################################################
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sni/irq.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- irq.c 2001/06/22 02:29:31 1.1.1.1
+++ irq.c 2001/10/02 17:18:31 1.2
@@ -126,7 +126,7 @@
void __init init_pciasic(void)
{
- unsigned int flags;
+ unsigned long flags;
spin_lock_irqsave(&pciasic_lock, flags);
* (volatile u8 *) PCIMT_IRQSEL =
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sni/setup.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- setup.c 2001/06/22 02:29:31 1.1.1.1
+++ setup.c 2001/10/02 17:18:31 1.2
@@ -30,6 +30,7 @@
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/sni.h>
+#include <asm/time.h>
extern void sni_machine_restart(char *command);
extern void sni_machine_halt(void);
@@ -39,8 +40,6 @@
extern struct rtc_ops std_rtc_ops;
extern struct kbd_ops std_kbd_ops;
-void (*board_time_init)(struct irqaction *irq);
-
static void __init sni_rm200_pci_time_init(struct irqaction *irq)
{
/* set the clock to 100 Hz */
@@ -50,7 +49,6 @@
setup_irq(0, irq);
}
-unsigned char aux_device_present;
extern unsigned char sni_map_isa_cache;
/*
|
|
From: Jun S. <ju...@us...> - 2001-10-01 19:34:17
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181 In directory usw-pr-cvs1:/tmp/cvs-serv20282/arch/mips/vr4181 Removed Files: TODO Log Message: Aha, we have nothing to do, at least at this point. --- TODO DELETED --- |
|
From: Jun S. <ju...@us...> - 2001-10-01 19:33:05
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv19857/arch/mips
Modified Files:
config.in
Log Message:
Move Osprey/vr4181 to use the new time.c file. Now the code is really
getting pretty ...
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.27
retrieving revision 1.28
diff -u -d -r1.27 -r1.28
--- config.in 2001/09/29 00:42:25 1.27
+++ config.in 2001/10/01 19:33:00 1.28
@@ -188,6 +188,7 @@
define_bool CONFIG_SERIAL_MANY_PORTS y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_IRQ_CPU y
+ define_bool CONFIG_NEW_TIME_C y
define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_SCSI n
fi
|
|
From: Jun S. <ju...@us...> - 2001-10-01 19:33:05
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv19857/arch/mips/vr4181/common
Modified Files:
time.c
Log Message:
Move Osprey/vr4181 to use the new time.c file. Now the code is really
getting pretty ...
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/time.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- time.c 2001/09/29 00:42:25 1.2
+++ time.c 2001/10/01 19:32:59 1.3
@@ -1,228 +1,148 @@
/*
- * linux/arch/mips/vr41xx/time.c
- *
- * VR4181 timer interrupt using real-time clock.
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: js...@mv... or js...@ju...
*
- * Copyright (C) 1991, 1992, 1995 Linus Torvalds
- * Copyright (C) 1999 Bradley D. LaRonde
- * Copyright (C) 2000 Michael Klar
+ * rtc and time ops for vr4181. Part of code is drived from
+ * linux-vr, originally written by Bradley D. LaRonde & Michael Klar.
*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
*
*/
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/param.h> /* for HZ */
+#include <linux/time.h>
#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/pm.h>
-#include <asm/vr4181/vr4181.h>
-extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
-extern volatile unsigned long wall_jiffies;
-extern rwlock_t xtime_lock;
+#include <asm/system.h>
+#include <asm/time.h>
-#define USECS_PER_JIFFY (1000000/HZ)
+#include <asm/vr4181/vr4181.h>
+
#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ)
-spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED;
+/*
+ * RTC ops
+ */
-#ifdef CONFIG_RTC
-unsigned long epoch_adj;
-#else
-#define epoch_adj 0
-#endif
+spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED;
-// per VR41xx docs, bad data can be read if between 2 counts
-static inline unsigned short read_time_reg(volatile unsigned short *reg)
+/* per VR41xx docs, bad data can be read if between 2 counts */
+static inline unsigned short
+read_time_reg(volatile unsigned short *reg)
{
- unsigned short value;
- do {
- value = *reg;
- barrier();
- } while (value != *reg);
- return value;
+ unsigned short value;
+ do {
+ value = *reg;
+ barrier();
+ } while (value != *reg);
+ return value;
}
-unsigned long get_rtc_time(volatile unsigned short *reg)
+static unsigned long
+vr4181_rtc_get_time(void)
{
- unsigned short regh, regm, regl;
+ unsigned short regh, regm, regl;
- // why this crazy order, you ask? to guarantee that neither m
- // nor l wrap before all 3 read
- do {
- regm = read_time_reg(reg + 1);
- barrier();
- regh = read_time_reg(reg + 2);
- barrier();
- regl = read_time_reg(reg);
- } while (regm != read_time_reg(reg + 1));
- return ((regh << 17) | (regm << 1) | (regl >> 15)) + epoch_adj;
+ // why this crazy order, you ask? to guarantee that neither m
+ // nor l wrap before all 3 read
+ do {
+ regm = read_time_reg(VR4181_ETIMEMREG);
+ barrier();
+ regh = read_time_reg(VR4181_ETIMEHREG);
+ barrier();
+ regl = read_time_reg(VR4181_ETIMELREG);
+ } while (regm != read_time_reg(VR4181_ETIMEMREG));
+ return ((regh << 17) | (regm << 1) | (regl >> 15));
}
-void set_rtc_time(unsigned long settime, volatile unsigned short *reg)
+static int
+vr4181_rtc_set_time(unsigned long timeval)
{
- unsigned short intreg;
- unsigned long flags, timeval = settime - epoch_adj;
-
- spin_lock_irqsave(&rtc_lock, flags);
- intreg = *VR4181_RTCINTREG & 0x05;
- barrier();
- *reg = timeval << 15;
- *(reg + 1) = timeval >> 1;
- *(reg + 2) = timeval >> 17;
- barrier();
- // assume that any ints that just triggered are invalid, since the
- // time value is written non-atomically in 3 separate regs
- *VR4181_RTCINTREG = 0x05 ^ intreg;
- spin_unlock_irqrestore(&rtc_lock, flags);
-}
+ unsigned short intreg;
+ unsigned long flags;
-// must be called with ints disabled:
-//
-static unsigned long do_gettimeoffset(void)
-{
- unsigned short count;
- unsigned long offset;
+ spin_lock_irqsave(&rtc_lock, flags);
+ intreg = *VR4181_RTCINTREG & 0x05;
+ barrier();
+ *VR4181_ETIMELREG = timeval << 15;
+ *VR4181_ETIMEMREG = timeval >> 1;
+ *VR4181_ETIMEHREG = timeval >> 17;
+ barrier();
+ // assume that any ints that just triggered are invalid, since the
+ // time value is written non-atomically in 3 separate regs
+ *VR4181_RTCINTREG = 0x05 ^ intreg;
+ spin_unlock_irqrestore(&rtc_lock, flags);
- count = read_time_reg(VR4181_RTCL1CNTLREG);
- if (count == 1)
- offset = 0;
- else
- offset = (COUNTS_PER_JIFFY - count + 1) * 1000000 / 32768;
- // detect if the counter wrapped, but int not serviced yet, being
- // careful not to adjust if int happen after count was read just now
- if (*VR4181_RTCINTREG & 0x0002 && (jiffies == wall_jiffies) && count != 2)
- offset += USECS_PER_JIFFY;
- return offset;
+ return 0;
}
-// This version of gettimeofday has about 30us resolution
-void do_gettimeofday(struct timeval *tv)
-{
- unsigned long flags, lost;
-
- read_lock_irqsave(&xtime_lock, flags);
- *tv = xtime;
- tv->tv_usec += do_gettimeoffset();
-
- // xtime is atomically updated in timer_bh, wall_jiffies is
- // updated in timer_bh, jiffies is updated in timer int, so this
- // will be nonzero if the timer bottom half hasn't executed yet:
- lost = jiffies - wall_jiffies;
-
- read_unlock_irqrestore(&xtime_lock, flags);
-
- while (lost--)
- tv->tv_usec += USECS_PER_JIFFY;
-
- while (tv->tv_usec >= 1000000) {
- tv->tv_usec -= 1000000;
- tv->tv_sec++;
- }
-}
-void do_settimeofday(struct timeval *tv)
+/*
+ * timer interrupt routine (wrapper)
+ *
+ * we need our own interrupt routine because we need to clear
+ * RTC1 interrupt.
+ */
+static void
+vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
- write_lock_irq(&xtime_lock);
- // undo whatever correction gettimeofday would have done
- tv->tv_usec -= do_gettimeoffset();
- tv->tv_usec -= (jiffies - wall_jiffies) * USECS_PER_JIFFY;
-
- if (tv->tv_usec < 0) {
- tv->tv_usec += 1000000;
- tv->tv_sec--;
- }
+ /* Clear the interrupt. */
+ *VR4181_RTCINTREG = 0x2;
- xtime = *tv;
- time_adjust = 0; // stop active adjtime()
- time_status |= STA_UNSYNC;
- time_maxerror = NTP_PHASE_LIMIT;
- time_esterror = NTP_PHASE_LIMIT;
- write_unlock_irq(&xtime_lock);
+ /* call the generic one */
+ timer_interrupt(irq, dev_id, regs);
}
-static unsigned long last_rtc_update;
/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "do_timer()" routine every clocktick
+ * vr4181_time_init:
+ *
+ * We pick the following choices:
+ * . we use elapsed timer as the RTC. We set some reasonable init data since
+ * it does not persist across reset
+ * . we use RTC1 as the system timer interrupt source.
+ * . we use CPU counter for fast_gettimeoffset and we calivrate the cpu
+ * frequency. In other words, we use calibrate_div64_gettimeoffset().
+ * . we use our own timer interrupt routine which clears the interrupt
+ * and then calls the generic high-level timer interrupt routine.
+ *
*/
-static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-{
- // Clear the interrupt.
- *VR4181_RTCINTREG = 0x2;
- do_timer(regs);
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
- // If we have an externally synchronized Linux clock, then update
- // CMOS clock accordingly every ~11 minutes.
- if ((time_status & STA_UNSYNC) == 0 &&
- xtime.tv_sec > last_rtc_update + 660) {
- set_rtc_time(xtime.tv_sec, VR4181_ETIMELREG);
- last_rtc_update = xtime.tv_sec;
- }
-}
+static void
+vr4181_timer_setup(struct irqaction *irq)
+{
+ /* over-write the handler to be our own one */
+ irq->handler = vr4181_timer_interrupt;
-struct irqaction timer_action = {
- timer_interrupt, SA_INTERRUPT, 0,
- "timer", NULL, NULL
-};
+ /* sets up the frequency */
+ *VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
+ *VR4181_RTCL1HREG = 0;
-#ifdef CONFIG_PM
-static int pm_time_request(struct pm_dev *dev, pm_request_t rqst, void *data)
-{
- unsigned long flags;
+ /* and ack any pending ints */
+ *VR4181_RTCINTREG = 0x2;
- switch (rqst) {
- case PM_SUSPEND:
- disable_irq(VR4181_IRQ_INT1);
- break;
- case PM_RESUME:
- write_lock_irqsave(&xtime_lock, flags);
- enable_irq(VR4181_IRQ_INT1);
- xtime.tv_sec = get_rtc_time(VR4181_ETIMELREG);
- xtime.tv_usec = 0;
- // this shouldn't be necessary, but just to be safe...
- *VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
- *VR4181_RTCL1HREG = 0;
- write_unlock_irqrestore(&xtime_lock, flags);
- break;
- }
- return 0;
-}
+ /* setup irqaction */
+ setup_irq(VR4181_IRQ_INT1, irq);
-static int __init pm_time_init(void)
-{
- pm_register(PM_SYS_DEV, PM_SYS_UNKNOWN, pm_time_request);
- return 0;
}
-__initcall(pm_time_init);
-#endif
-
-void __init time_init(void)
+void
+vr4181_init_time(void)
{
- // Set default time near beginning of Linux VR epoch.
- xtime.tv_sec = get_rtc_time(VR4181_ETIMELREG);
- xtime.tv_usec = 0;
-
- // Use RTCLong1 for the system timer.
- // It has it's own cpu interrupt, is not T-Clock dependent,
- // and has sufficient resolution.
-
- // Set the RTCLong1 counter (32.768kHz) to expire in 1 / HZ second
- *VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
- *VR4181_RTCL1HREG = 0;
+ /* setup hookup functions */
+ rtc_get_time = vr4181_rtc_get_time;
+ rtc_set_time = vr4181_rtc_set_time;
- // and ack any pending ints
- *VR4181_RTCINTREG = 0x2;
+ board_timer_setup = vr4181_timer_setup;
- // Grab the IRQ for the cpu interrupt, not the ICU interrupt
- // The RTCLong1 ICU interrupt is always left unmasked
- // This can't use request_irq() because it's too early for kmalloc
- setup_irq(VR4181_IRQ_INT1, &timer_action);
+ /* let us setup some reasonable start up time */
+ vr4181_rtc_set_time(mktime(2001, 10, 1, 12, 0, 0));
}
+
|
|
From: Jun S. <ju...@us...> - 2001-10-01 19:33:05
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv19857/arch/mips/vr4181/osprey
Modified Files:
setup.c
Log Message:
Move Osprey/vr4181 to use the new time.c file. Now the code is really
getting pretty ...
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- setup.c 2001/09/25 19:57:07 1.2
+++ setup.c 2001/10/01 19:33:00 1.3
@@ -79,6 +79,7 @@
#endif
extern void vr4181_init_serial(void);
+extern void vr4181_init_time(void);
void __init nec_osprey_setup(void)
{
@@ -86,6 +87,7 @@
isa_slot_offset = VR4181_ISAMEM_BASE;
vr4181_init_serial();
+ vr4181_init_time();
#ifdef CONFIG_BLK_DEV_IDE
ide_ops = &vr4181_ide_ops;
|
|
From: James S. <jsi...@us...> - 2001-10-01 18:33:07
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv3182 Modified Files: defconfig-cobalt Log Message: Small fix ups. Index: defconfig-cobalt =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-cobalt,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- defconfig-cobalt 2001/09/15 17:06:10 1.6 +++ defconfig-cobalt 2001/10/01 18:33:03 1.7 @@ -227,6 +227,7 @@ CONFIG_BLK_DEV_IDEPCI=y # CONFIG_IDEPCI_SHARE_IRQ is not set CONFIG_BLK_DEV_IDEDMA_PCI=y +CONFIG_BLK_DEV_ADMA=y # CONFIG_BLK_DEV_OFFBOARD is not set # CONFIG_IDEDMA_PCI_AUTO is not set CONFIG_BLK_DEV_IDEDMA=y @@ -236,8 +237,8 @@ # CONFIG_AEC62XX_TUNING is not set # CONFIG_BLK_DEV_ALI15X3 is not set # CONFIG_WDC_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD7409 is not set -# CONFIG_AMD7409_OVERRIDE is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_AMD74XX_OVERRIDE is not set # CONFIG_BLK_DEV_CMD64X is not set # CONFIG_BLK_DEV_CY82C693 is not set # CONFIG_BLK_DEV_CS5530 is not set @@ -248,7 +249,8 @@ # CONFIG_BLK_DEV_OPTI621 is not set # CONFIG_BLK_DEV_PDC202XX is not set # CONFIG_PDC202XX_BURST is not set -# CONFIG_BLK_DEV_OSB4 is not set +# CONFIG_PDC202XX_FORCE is not set +# CONFIG_BLK_DEV_SVWKS is not set # CONFIG_BLK_DEV_SIS5513 is not set # CONFIG_BLK_DEV_SLC90E66 is not set # CONFIG_BLK_DEV_TRM290 is not set |
|
From: Jun S. <ju...@us...> - 2001-09-29 00:42:28
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv20317/arch/mips/configs Modified Files: defconfig-osprey Log Message: Woohoo! Finally get rid of the ugly old irq code. How smooth ... Index: defconfig-osprey =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-osprey,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- defconfig-osprey 2001/09/25 19:57:07 1.2 +++ defconfig-osprey 2001/09/29 00:42:25 1.3 @@ -43,12 +43,14 @@ # CONFIG_SBUS is not set CONFIG_CPU_VR41XX=y CONFIG_VR4181=y -CONFIG_ISA=y CONFIG_SERIAL=y CONFIG_SERIAL_MANY_PORTS=y +CONFIG_NEW_IRQ=y +CONFIG_IRQ_CPU=y CONFIG_DUMMY_KEYB=y # CONFIG_SCSI is not set -CONFIG_EISA=y +# CONFIG_ISA is not set +# CONFIG_EISA is not set # CONFIG_PCI is not set # CONFIG_I8259 is not set @@ -98,13 +100,6 @@ CONFIG_SYSCTL=y # -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set @@ -235,20 +230,10 @@ # CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set -# CONFIG_HP100 is not set -CONFIG_NET_ISA=y -# CONFIG_E2100 is not set -# CONFIG_EWRK3 is not set -# CONFIG_EEXPRESS is not set -# CONFIG_EEXPRESS_PRO is not set -# CONFIG_HPLAN_PLUS is not set -# CONFIG_HPLAN is not set -# CONFIG_ETH16I is not set -CONFIG_NE2000=y +# CONFIG_NET_ISA is not set # CONFIG_NET_PCI is not set # CONFIG_NET_POCKET is not set +CONFIG_NE2000=y # # Ethernet (1000 Mbit) |
|
From: Jun S. <ju...@us...> - 2001-09-29 00:42:28
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv20317/drivers/net
Modified Files:
Config.in
Log Message:
Woohoo! Finally get rid of the ugly old irq code. How smooth ...
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Config.in,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- Config.in 2001/09/26 16:46:45 1.9
+++ Config.in 2001/09/29 00:42:25 1.10
@@ -203,6 +203,9 @@
if [ "$CONFIG_DECSTATION" = "y" ]; then
bool ' DEC LANCE ethernet controller support' CONFIG_DECLANCE
fi
+ if [ "$CONFIG_NEC_OSPREY" = "y" ]; then
+ bool ' Memory-mapped onboard NE2000-compatible ethernet' CONFIG_NE2000
+ fi
if [ "$CONFIG_NEC_KORVA" = "y" ]; then
bool ' NEC Memory-mapped onboard (Candy) Ethernet' CONFIG_NEC_CANDY
fi
|
|
From: Jun S. <ju...@us...> - 2001-09-29 00:42:28
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv20317/arch/mips/vr4181/common
Modified Files:
irq.c time.c int_handler.S
Log Message:
Woohoo! Finally get rid of the ugly old irq code. How smooth ...
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/irq.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- irq.c 2001/09/27 23:59:15 1.4
+++ irq.c 2001/09/29 00:42:25 1.5
@@ -1,19 +1,20 @@
/*
- * linux/arch/mips/vr41xx/irq.c
- *
- * Code to handle VR4181 IRQs plus some generic interrupt stuff.
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, js...@mv... or js...@ju...
*
- * Copyright (C) 1992 Linus Torvalds
- * Copyright (C) 1994, 1995, 1996, 1997 Ralf Baechle
- * Copyright (C) 1999 Bradley D. LaRonde
- * Copyright (C) 1999, 2000 Michael Klar
+ * linux/arch/mips/vr4181/common/irq.c
+ * Completely re-written to use the new irq.c
*
+ * Credits to Bradley D. LaRonde and Michael Klar for writing the original
+ * irq.c file which was derived from the common irq.c file.
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
+#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
@@ -21,517 +22,211 @@
#include <linux/interrupt.h>
#include <linux/malloc.h>
#include <linux/random.h>
-#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/gdb-stub.h>
#include <asm/vr4181/vr4181.h>
-
-/* [jsun] HACK */
-#define CONFIG_CPU_VR4181 y
-#define DEVICE_IRQ_MASKL 0xffff
-extern asmlinkage void vr4181_handle_irq(void);
-extern void breakpoint(void);
-
-// This is used elsewhere
-unsigned long spurious_count = 0;
-
-static unsigned short irq_mask_probe[(VR4181_IRQ_MAX + 9)/16];
+/*
+ * Strategy:
+ *
+ * We essentially have three irq controllers, CPU, system, and gpio.
+ *
+ * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and
+ * CONFIG_IRQ_CPU config option.
+ *
+ * We here provide sys_irq and gpio_irq controller code.
+ */
-#define BIT_MASK(bit) ( 1 << (bit) )
-#define MAKE_CP0_STATUS_IRQ_MASK(irq) ( BIT_MASK( (irq) + 8))
+static int sys_irq_base;
+static int gpio_irq_base;
-static inline void mask_irq(unsigned int irq)
+/* ---------------------- sys irq ------------------------ */
+static void
+sys_irq_enable(unsigned int irq)
{
- if (irq < 8) {
- // it's a cpu interrupt
- unsigned short newstatus = read_32bit_cp0_register(CP0_STATUS);
- newstatus &= ~((unsigned short)1 << (irq + 8));
- change_cp0_status(ST0_IM, newstatus);
+ irq -= sys_irq_base;
+ if (irq < 16) {
+ *VR4181_MSYSINT1REG |= (u16)(1 << irq);
} else {
- if (irq < 40) {
- // it's an ICU interrupt
- if (irq < 24) {
- *VR4181_MSYSINT1REG &= ~((unsigned short)1 << (irq - 8));
- } else {
- *VR4181_MSYSINT2REG &= ~((unsigned short)1 << (irq - 24));
- }
- } else {
- // it's a GPIO interrupt
-#ifdef CONFIG_CPU_VR4181
- *VR4181_GPINTMSK |= (unsigned short)1 << (irq - 40);
-#else
- if (irq < 56) {
- *VR4181_MGIUINTLREG &= ~((unsigned short)1 << (irq - 40));
- } else {
- *VR4181_MGIUINTHREG &= ~((unsigned short)1 << (irq - 56));
- }
-#endif
- }
+ irq -= 16;
+ *VR4181_MSYSINT2REG |= (u16)(1 << irq);
}
}
-static inline void unmask_irq(unsigned int irq)
+static void
+sys_irq_disable(unsigned int irq)
{
- if (irq < 8) {
- // it's a cpu interrupt
- unsigned short newstatus = read_32bit_cp0_register(CP0_STATUS);
- newstatus |= ((unsigned short)1 << (irq + 8));
- change_cp0_status(ST0_IM, newstatus);
+ irq -= sys_irq_base;
+ if (irq < 16) {
+ *VR4181_MSYSINT1REG &= ~((u16)(1 << irq));
} else {
- if (irq < 40) {
- // it's an ICU interrupt
- if (irq < 24) {
- *VR4181_MSYSINT1REG |= (unsigned short)1 << (irq - 8);
- } else {
- *VR4181_MSYSINT2REG |= (unsigned short)1 << (irq - 24);
- }
- } else {
- // it's a GPIO interrupt (also ack edge-triggered or hold ints)
-#ifdef CONFIG_CPU_VR4181
- if (!((irq < 48 ? *VR4181_GPINTTYPL : *VR4181_GPINTTYPH) &
- ((unsigned short)2 << ((irq & 0x7) * 2))))
- *VR4181_GPINTSTAT = (unsigned short)1 << (irq - 40);
- *VR4181_GPINTMSK &= ~((unsigned short)1 << (irq - 40));
-#else
- if (irq < 56) {
- if (*VR4181_GIUINTHTSELL & ((unsigned short)1 << (irq - 40)))
- *VR4181_GIUINTSTATL = (unsigned short)1 << (irq - 40);
- *VR4181_MGIUINTLREG |= (unsigned short)1 << (irq - 40);
- } else {
- if (*VR4181_GIUINTHTSELH & ((unsigned short)1 << (irq - 56)))
- *VR4181_GIUINTSTATH = (unsigned short)1 << (irq - 56);
- *VR4181_MGIUINTHREG |= (unsigned short)1 << (irq - 56);
- }
-#endif
- }
+ irq -= 16;
+ *VR4181_MSYSINT2REG &= ~((u16)(1 << irq));
}
-}
-/*
- * Per-IRQ information, by not initializing, this gets filled with NULLs:
- */
-typedef struct {
- struct irqaction* irq_action; // info on low-level handler
- int depth; // < 0: enabled, >= 0: disabled
-} irq_info_t;
-
-static irq_info_t irq_info[VR4181_IRQ_MAX + 1];
-
-void disable_irq(unsigned int irq_nr)
-{
- unsigned long flags;
-
- if (++irq_info[irq_nr].depth >= 0) {
- save_and_cli(flags);
- mask_irq(irq_nr);
- restore_flags(flags);
- }
}
-void enable_irq(unsigned int irq_nr)
+static unsigned int
+sys_irq_startup(unsigned int irq)
{
- unsigned long flags;
-
-#ifdef CONFIG_CPU_VR4122
- if (irq_nr == VR4181_IRQ_GPIO14)
- return;
-#endif
-
- if (--irq_info[irq_nr].depth < 0) {
- save_and_cli(flags);
- unmask_irq(irq_nr);
- restore_flags(flags);
- }
+ sys_irq_enable(irq);
+ return 0;
}
-int get_irq_list(char *buf)
-{
- // make a human-readable list of irq actions
- // used by /proc/interrupts
+#define sys_irq_shutdown sys_irq_disable
+#define sys_irq_ack sys_irq_disable
+#define sys_irq_end sys_irq_enable
- int i, len = 0;
- struct irqaction *action;
+static hw_irq_controller sys_irq_controller = {
+ "vr4181_sys_irq",
+ sys_irq_startup,
+ sys_irq_shutdown,
+ sys_irq_enable,
+ sys_irq_disable,
+ sys_irq_ack,
+ sys_irq_end,
+ NULL /* no affinity stuff for UP */
+};
- for (i = 0; i <= VR4181_IRQ_MAX; i++) {
- action = irq_info[i].irq_action;
- if (!action)
- continue;
- len += sprintf(buf + len, "%2d: %8d %c %s",
- i, kstat.irqs[0][i],
- (action->flags & SA_INTERRUPT) ? '+' : ' ',
- action->name);
- for (action = action->next; action; action = action->next) {
- len += sprintf(buf + len, ",%s %s",
- (action->flags & SA_INTERRUPT) ? " +" : "",
- action->name);
- }
- len += sprintf(buf + len, "\n");
- }
- return len;
+/* ---------------------- gpio irq ------------------------ */
+/* gpio irq lines use reverse logic */
+static void
+gpio_irq_enable(unsigned int irq)
+{
+ irq -= gpio_irq_base;
+ *VR4181_GPINTMSK &= ~((u16)(1 << irq));
}
-
-atomic_t __mips_bh_counter;
-asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
+static void
+gpio_irq_disable(unsigned int irq)
{
- // This handles all IRQ's that have been installed.
- // It is called from int-handler.S.
- // Actions without SA_INTERRUPT run with interrupts enabled
- // and use the full signal-handling return.
- // Actions with SA_INTERRUPT run with interrupts disabled.
-
- struct irqaction *action;
- int cpu = smp_processor_id();
-
- irq_enter(cpu, irq);
-
- kstat.irqs[cpu][irq]++;
-
- // don't interrupt on this same irq again until we're finished
- // also, it gets left masked if there is no action (see below)
- mask_irq(irq);
-
- action = irq_info[irq].irq_action;
-
- if (action != 0) {
- unsigned long flags = 0;
-
- if (!(action->flags & SA_INTERRUPT))
- __sti();
-
- do {
- // handle it
- action->handler(irq, action->dev_id, regs);
-
- flags |= action->flags;
- action = action->next;
- } while (action);
-
- if (flags & SA_SAMPLE_RANDOM)
- add_interrupt_randomness(irq);
-
- __cli();
-
- unmask_irq(irq);
- }
-
- irq_exit(cpu, irq);
-
- if (softirq_pending(cpu))
- do_softirq();
-
- // Unmasking and softirq handling is done for us
- // currently by ret_from_irq in entry.S.
+ irq -= gpio_irq_base;
+ *VR4181_GPINTMSK |= (u16)(1 << irq);
}
-int add_irq_action(int irq, struct irqaction *new)
+static unsigned int
+gpio_irq_startup(unsigned int irq)
{
- // put the specified action (new) at the end of the list of actions for this irq
-
- int shared = 0;
- struct irqaction *old, **p;
- unsigned long flags;
-
- p = &irq_info[irq].irq_action;
-
- if ((old = *p) != NULL) {
- if (!(old->flags & new->flags & SA_SHIRQ))
- return -EBUSY;
-
- // Shared interrupts must be all same type
- if ((old->flags ^ new->flags) & SA_INTERRUPT)
- return -EBUSY;
-
- do {
- p = &old->next;
- old = *p;
- } while (old);
-
- shared = 1;
- }
-
- if (new->flags & SA_SAMPLE_RANDOM)
- rand_initialize_irq(irq);
-
- save_and_cli(flags);
-
- *p = new;
-
- if (!shared) {
- irq_info[irq].depth = -1;
- unmask_irq(irq);
- }
+ gpio_irq_enable(irq);
- restore_flags(flags);
+ irq -= gpio_irq_base;
+ *VR4181_GPINTEN |= (u16)(1 << irq );
return 0;
}
-int request_irq(unsigned int irq,
- void (*handler)(int, void *, struct pt_regs *),
- unsigned long irqflags,
- const char *devname,
- void *dev_id)
+static void
+gpio_irq_shutdown(unsigned int irq)
{
- int retval;
- struct irqaction *action;
-
- // some assertiveness
- if (irq > VR4181_IRQ_MAX)
- return -EINVAL;
-
- if (!handler)
- return -EINVAL;
-
- // allocate a new action struct
- action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL);
- if (!action)
- return -ENOMEM;
-
- // initialize it
- action->handler = handler;
- action->flags = irqflags;
- action->mask = 0;
- action->name = devname;
- action->next = NULL;
- action->dev_id = dev_id;
-
- // add it to the list of actions for this irq
- retval = add_irq_action(irq, action);
- if (retval)
- kfree(action);
+ gpio_irq_disable(irq);
- return retval;
+ irq -= gpio_irq_base;
+ *VR4181_GPINTEN &= ~((u16)(1 << irq ));
}
-void free_irq(unsigned int irq, void *dev_id)
+static void
+gpio_irq_ack(unsigned int irq)
{
- struct irqaction *action, **p;
- unsigned long flags;
-
- if (irq > VR4181_IRQ_MAX) {
- printk("Error - trying to free invalid IRQ %d\n", irq);
- return;
- }
+ u16 irqtype;
+ u16 irqshift;
- for (p = &irq_info[irq].irq_action; (action = *p) != NULL; p = &action->next) {
- if (action->dev_id != dev_id)
- continue;
+ gpio_irq_disable(irq);
- // Found it - now free it
- save_and_cli(flags);
- *p = action->next;
- if (!irq_info[irq].irq_action) {
- irq_info[irq].depth = 0;
- mask_irq(irq);
- }
- restore_flags(flags);
- kfree(action);
- return;
+ /* we clear interrupt if it is edge triggered */
+ irq -= gpio_irq_base;
+ if (irq < 8) {
+ irqtype = *VR4181_GPINTTYPL;
+ irqshift = 2 << (irq*2);
+ } else {
+ irqtype = *VR4181_GPINTTYPH;
+ irqshift = 2 << ((irq-8)*2);
}
+ if ( ! (irqtype & irqshift) ) {
+ *VR4181_GPINTSTAT = (u16) (1 << irq);
+ }
}
-
-unsigned long probe_irq_on(void)
-{
- int i;
- unsigned long delay;
- // Note the lower 8 bits of irq_mask_probe[0] are not used. Also,
- // we don't probe for IRQ 0, since no way to report (0 = no IRQ found)
- irq_mask_probe[0] = read_32bit_cp0_register(CP0_STATUS);
- irq_mask_probe[1] = *VR4181_MSYSINT1REG;
- irq_mask_probe[2] = *VR4181_MSYSINT2REG;
-#ifdef CONFIG_CPU_VR4181
- irq_mask_probe[3] = ~*VR4181_GPINTMSK;
-#else
- irq_mask_probe[3] = *VR4181_MGIUINTLREG;
- irq_mask_probe[4] = *VR4181_MGIUINTHREG;
-#endif
+#define gpio_irq_end gpio_irq_enable
- for (i = VR4181_IRQ_MAX; i > 0; i--)
- if (!irq_info[i].irq_action && i != VR4181_IRQ_TIMER)
- enable_irq(i);
+static hw_irq_controller gpio_irq_controller = {
+ "vr4181_gpio_irq",
+ gpio_irq_startup,
+ gpio_irq_shutdown,
+ gpio_irq_enable,
+ gpio_irq_disable,
+ gpio_irq_ack,
+ gpio_irq_end,
+ NULL /* no affinity stuff for UP */
+};
- // Wait for spurious interrupts to mask themselves out again...
- for (delay = jiffies + HZ/10; time_before(jiffies, delay); )
- barrier(); // about 100ms of delay
+/* --------------------- IRQ init stuff ---------------------- */
- irq_mask_probe[0] |= ~read_32bit_cp0_register(CP0_STATUS);
- irq_mask_probe[1] |= ~*VR4181_MSYSINT1REG;
- irq_mask_probe[2] |= ~*VR4181_MSYSINT2REG;
-#ifdef CONFIG_CPU_VR4181
- irq_mask_probe[3] |= *VR4181_GPINTMSK;
-#else
- irq_mask_probe[3] |= ~*VR4181_MGIUINTLREG;
- irq_mask_probe[4] |= ~*VR4181_MGIUINTHREG;
-#endif
+extern asmlinkage void vr4181_handle_irq(void);
+extern void breakpoint(void);
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+extern void mips_cpu_irq_init(u32 irq_base);
- return 0x12345678;
-}
+static struct irqaction cascade =
+ { no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
+static struct irqaction reserved =
+ { no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
-int probe_irq_off(unsigned long unused)
+void __init init_IRQ(void)
{
- int i, irq_found, nr_irqs;
- unsigned short tmp;
- unsigned long flags;
-
- if (unused != 0x12345678)
- printk("Bad IRQ probe detected\n");
-
- // The following mess unmasks the interrupts we enabled to autoprobe
- // and finishes bit-processing irq_mask_probe at the same time
- save_and_cli(flags);
- tmp = read_32bit_cp0_register(CP0_STATUS);
- change_cp0_status(ST0_IM, tmp & irq_mask_probe[0]);
- irq_mask_probe[0] |= tmp;
- tmp = *VR4181_MSYSINT1REG;
- *VR4181_MSYSINT1REG = tmp & irq_mask_probe[1];
- irq_mask_probe[1] |= tmp;
- tmp = *VR4181_MSYSINT2REG;
- *VR4181_MSYSINT2REG = tmp & irq_mask_probe[2];
- irq_mask_probe[2] |= tmp;
-#ifdef CONFIG_CPU_VR4181
- tmp = ~*VR4181_GPINTMSK;
- *VR4181_GPINTMSK = ~(tmp & irq_mask_probe[3]);
- irq_mask_probe[3] |= tmp;
-#else
- tmp = *VR4181_MGIUINTLREG;
- *VR4181_MGIUINTLREG = tmp & irq_mask_probe[3];
- irq_mask_probe[3] |= tmp;
- tmp = *VR4181_MGIUINTHREG;
- *VR4181_MGIUINTHREG = tmp & irq_mask_probe[4];
- irq_mask_probe[4] |= tmp;
-#endif
- restore_flags(flags);
-
- nr_irqs = 0;
- irq_found = 0;
-
- for (i = VR4181_IRQ_MAX; i > 0; i--)
- if (!(irq_mask_probe[(i + 8)/16] & ((unsigned short)1 << ((i + 8) & 15)))) {
- irq_found = i;
- nr_irqs++;
- }
-
- if (nr_irqs > 1)
- irq_found = -irq_found;
- return irq_found;
-}
+ int i;
+ extern irq_desc_t irq_desc[];
-#ifdef CONFIG_PM
-//
-// Unlike the real pm_request callbacks, this one doesn't get registered
-// with PM, and only gets called from do_hibernate and do_wakeup, because
-// it has to happen in a certain order. It also assumes ints disabled.
-//
-void do_pm_irq_request(pm_request_t rqst)
-{
- static unsigned short irq_mask[(VR4181_IRQ_MAX + 9)/16];
- unsigned int status;
+ set_except_vector(0, vr4181_handle_irq);
- switch (rqst) {
- case PM_RESUME:
- status = read_32bit_cp0_register(CP0_STATUS) & 0xffff00ff;
- write_32bit_cp0_register(CP0_STATUS, status | irq_mask[0]);
- *VR4181_MSYSINT1REG = irq_mask[1];
- *VR4181_MSYSINT2REG = irq_mask[2];
-#ifdef CONFIG_CPU_VR4181
- *VR4181_GPINTMSK = irq_mask[3];
-#else
- *VR4181_MGIUINTLREG = irq_mask[3];
- *VR4181_MGIUINTHREG = irq_mask[4];
-#endif
- break;
- case PM_SUSPEND:
- irq_mask[0] = read_32bit_cp0_register(CP0_STATUS) & 0xff00;
- irq_mask[1] = *VR4181_MSYSINT1REG;
- irq_mask[2] = *VR4181_MSYSINT2REG;
-#ifdef CONFIG_CPU_VR4181
- irq_mask[3] = *VR4181_GPINTMSK;
-#else
- irq_mask[3] = *VR4181_MGIUINTLREG;
- irq_mask[4] = *VR4181_MGIUINTHREG;
-#endif
- break;
- }
-}
-#endif // CONFIG_PM
+ /* init CPU irqs */
+ mips_cpu_irq_init(VR4181_CPU_IRQ_BASE);
-static struct irqaction cascade = { NULL, SA_INTERRUPT, 0, "cascade", NULL, NULL };
-static struct irqaction reserved = { NULL, SA_INTERRUPT, 0, "reserved", NULL, NULL };
+ /* init sys irqs */
+ sys_irq_base = VR4181_SYS_IRQ_BASE;
+ for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &sys_irq_controller;
+ }
-void __init init_IRQ(void)
-{
- set_except_vector(0, vr4181_handle_irq);
+ /* init gpio irqs */
+ gpio_irq_base = VR4181_GPIO_IRQ_BASE;
+ for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &gpio_irq_controller;
+ }
- // Default all ICU IRQs to off ...
+ /* Default all ICU IRQs to off ... */
*VR4181_MSYSINT1REG = 0;
*VR4181_MSYSINT2REG = 0;
- // We initialize the level 2 ICU registers to all bits disabled.
- // After this, these registers are the resposibility of whatever
- // driver requests the IRQ of the corresponding level 1 ICU bit.
- // (except GIU, where each level 2 bit has its own IRQ)
-#ifdef CONFIG_CPU_VR4122
- *VR4181_MPCIINTREG = 0;
- *VR4181_MSCUINTREG = 0;
- *VR4181_MCSIINTREG = 0;
-#else
- *VR4181_MPIUINTREG = 0;
- *VR4181_MAIUINTREG = 0;
- *VR4181_MKIUINTREG = 0;
-#endif
-#ifdef CONFIG_CPU_VR4181
- *VR4181_GPINTMSK = 0xffff;
-#else
- *VR4181_MGIUINTLREG = 0;
- *VR4181_MDSIUINTREG = 0;
- *VR4181_MGIUINTHREG = 0;
- *VR4181_MFIRINTREG = 0;
-#endif
- barrier();
+ /* We initialize the level 2 ICU registers to all bits disabled. */
+ *VR4181_MPIUINTREG = 0;
+ *VR4181_MAIUINTREG = 0;
+ *VR4181_MKIUINTREG = 0;
-//
-// NOTE: This may break autodetection on some devices. If so, an IRQ mask needs
-// to be defined in vr41xx-platdep.h to disable some GPIO lines from interrupting,
-// or the broken autodetect IRQ needs to be defined explicitly. This define is
-// for documentation purposes, only turn it off for test/debug:
-//
-#define LET_ALL_GPIO_INPUTS_CAUSE_INTERRUPTS
-#ifdef LET_ALL_GPIO_INPUTS_CAUSE_INTERRUPTS
- // Initialize secondary IRQ mask to enable any GPIO line configured as an input.
- // Note that the int won't be active until enabled in the primary mask, too.
-#ifdef CONFIG_CPU_VR4181
- {
- unsigned int bits;
+ /* disable all GPIO intrs */
+ *VR4181_GPINTMSK = 0xffff;
- bits = (unsigned int)(*VR4181_GPMD1REG | 0xaaaa) << 16;
- bits |= *VR4181_GPMD0REG | 0xaaaa;
- bits &= bits >> 1;
- bits |= 0xcccccccc;
- bits &= bits >> 2;
- bits |= 0xf0f0f0f0;
- bits &= bits >> 4;
- bits |= 0xff00;
- bits &= bits >> 8;
- *VR4181_SECIRQMASKL = ~bits & DEVICE_IRQ_MASKL;
- }
-#else
- *VR4181_SECIRQMASKL = ~*VR4181_GIUIOSELL & DEVICE_IRQ_MASKL;
- *VR4181_SECIRQMASKH = ~*VR4181_GIUIOSELH & DEVICE_IRQ_MASKH;
-#endif
-#endif // LET_ALL_GPIO_INPUTS_CAUSE_INTERRUPTS
+ /* vector handler. What these do is register the IRQ as non-sharable */
+ setup_irq(VR4181_IRQ_INT0, &cascade);
+ setup_irq(VR4181_IRQ_GIU, &cascade);
- // These don't really add handlers, these IRQs are never reported by the int
- // vector handler. What these do is register the IRQ as non-sharable
- add_irq_action(VR4181_IRQ_INT0, &cascade);
- add_irq_action(VR4181_IRQ_GIU, &cascade);
- add_irq_action(VR4181_IRQ_RTCL1, &reserved);
- add_irq_action(VR4181_IRQ_RTCL2, &reserved);
+ /*
+ * RTC interrupts are interesting. They have two destinations.
+ * One is at sys irq controller, and the other is at CPU IP3 and IP4.
+ * RTC timer is used as system timer.
+ * We enable them here, but timer routine will register later
+ * with CPU IP3/IP4.
+ */
+ setup_irq(VR4181_IRQ_RTCL1, &reserved);
+ setup_irq(VR4181_IRQ_RTCL2, &reserved);
#ifdef CONFIG_REMOTE_DEBUG
printk("Setting debug traps - please connect the remote debugger.\n");
@@ -543,30 +238,3 @@
#endif
}
-#ifdef CONFIG_PCMCIA
-/*
- * dummy functions needed for PCMCIA support for non-ISA systems (vr4122) - mikemac
- *
- */
-
-/*
- * Return a mask of triggered interrupts (this
- * can handle only legacy ISA interrupts).
- */
-unsigned int
-probe_irq_mask(unsigned long val)
-{
- return val;
-}
-
-#ifndef CONFIG_ISA
-
-#define CS_IN_USE 0x1e
-
-int try_irq(u_int Attributes, int irq, int specific)
-{
- return CS_IN_USE;
-}
-#endif /* CONFIG_ISA */
-
-#endif /* CONFIG_PCMCIA */
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/time.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- time.c 2001/09/22 04:27:15 1.1
+++ time.c 2001/09/29 00:42:25 1.2
@@ -21,7 +21,7 @@
#include <linux/pm.h>
#include <asm/vr4181/vr4181.h>
-extern int add_irq_action(int irq, struct irqaction *new);
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
extern volatile unsigned long wall_jiffies;
extern rwlock_t xtime_lock;
@@ -224,5 +224,5 @@
// Grab the IRQ for the cpu interrupt, not the ICU interrupt
// The RTCLong1 ICU interrupt is always left unmasked
// This can't use request_irq() because it's too early for kmalloc
- add_irq_action(VR4181_IRQ_INT1, &timer_action);
+ setup_irq(VR4181_IRQ_INT1, &timer_action);
}
Index: int_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/int_handler.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- int_handler.S 2001/09/27 23:59:15 1.1
+++ int_handler.S 2001/09/29 00:42:25 1.2
@@ -52,15 +52,13 @@
and t0, t2
- /* we check IP2 first; it happens most frequently */
+ /* we check IP3 first; it happens most frequently */
+ andi t1, t0, STATUSF_IP3
+ bnez t1, ll_cpu_ip3
andi t1, t0, STATUSF_IP2
bnez t1, ll_cpu_ip2
-
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_cputimer_irq
-
- andi t1, t0, STATUSF_IP3
- bnez t1, ll_cpu_ip3
andi t1, t0, STATUSF_IP4
bnez t1, ll_cpu_ip4
andi t1, t0, STATUSF_IP5
|
|
From: Jun S. <ju...@us...> - 2001-09-29 00:42:28
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv20317/arch/mips
Modified Files:
Makefile config.in
Log Message:
Woohoo! Finally get rid of the ugly old irq code. How smooth ...
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- Makefile 2001/09/22 16:35:15 1.17
+++ Makefile 2001/09/29 00:42:25 1.18
@@ -214,7 +214,7 @@
SUBDIRS += arch/mips/vr4181/common arch/mips/vr4181/osprey
LIBS += arch/mips/vr4181/common/vr4181.o \
arch/mips/vr4181/osprey/osprey.o
-LOADADDR += 0x80014000
+LOADADDR += 0x80002000
endif
#
@@ -233,7 +233,7 @@
ifdef CONFIG_NEC_KORVA
SUBDIRS += arch/mips/korva
LIBS += arch/mips/korva/korva.a
-LOADADDR += 0x80014000
+LOADADDR += 0x80002000
endif
#
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -d -r1.26 -r1.27
--- config.in 2001/09/28 16:21:12 1.26
+++ config.in 2001/09/29 00:42:25 1.27
@@ -184,9 +184,10 @@
if [ "$CONFIG_NEC_OSPREY" = "y" ]; then
define_bool CONFIG_CPU_VR41XX y
define_bool CONFIG_VR4181 y
- define_bool CONFIG_ISA y
define_bool CONFIG_SERIAL y
define_bool CONFIG_SERIAL_MANY_PORTS y
+ define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_IRQ_CPU y
define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_SCSI n
fi
|
|
From: James S. <jsi...@us...> - 2001-09-28 16:28:02
|
Update of /cvsroot/linux-mips/linux/drivers/video In directory usw-pr-cvs1:/tmp/cvs-serv893 Modified Files: maxinefb.c pmag-ba-fb.c pmagb-b-fb.c Log Message: Fix slow scrolling on DECstations. Index: maxinefb.c =================================================================== RCS file: /cvsroot/linux-mips/linux/drivers/video/maxinefb.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- maxinefb.c 2001/09/06 17:00:46 1.1 +++ maxinefb.c 2001/09/28 16:27:59 1.2 @@ -301,7 +301,7 @@ display->next_line = fix.line_length; display->can_soft_blank = 0; display->inverse = 0; - + display->scrollmode = SCROLL_YREDRAW; display->dispsw = &fbcon_cfb8; } Index: pmag-ba-fb.c =================================================================== RCS file: /cvsroot/linux-mips/linux/drivers/video/pmag-ba-fb.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- pmag-ba-fb.c 2001/09/13 17:05:53 1.3 +++ pmag-ba-fb.c 2001/09/28 16:27:59 1.4 @@ -324,7 +324,7 @@ display->next_line = fix.line_length; display->can_soft_blank = 0; display->inverse = 0; - + display->scrollmode = SCROLL_YREDRAW; display->dispsw = &fbcon_cfb8; } Index: pmagb-b-fb.c =================================================================== RCS file: /cvsroot/linux-mips/linux/drivers/video/pmagb-b-fb.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- pmagb-b-fb.c 2001/09/13 17:05:53 1.3 +++ pmagb-b-fb.c 2001/09/28 16:27:59 1.4 @@ -327,7 +327,7 @@ display->next_line = fix.line_length; display->can_soft_blank = 0; display->inverse = 0; - + display->scrollmode = SCROLL_YREDRAW; display->dispsw = &fbcon_cfb8; } |
|
From: James S. <jsi...@us...> - 2001-09-28 16:24:44
|
Update of /cvsroot/linux-mips/linux/drivers/tc
In directory usw-pr-cvs1:/tmp/cvs-serv32582
Modified Files:
lk201.c
Log Message:
Get machines without keyboard to compile again.
Index: lk201.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/tc/lk201.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- lk201.c 2001/06/22 02:29:32 1.1.1.1
+++ lk201.c 2001/09/28 16:24:41 1.2
@@ -83,6 +83,13 @@
return 0;
}
+int kbd_rate(struct kbd_repeat *rep)
+{
+ return 0;
+}
+
+
+
void kbd_leds(unsigned char leds)
{
return;
|
|
From: James S. <jsi...@us...> - 2001-09-28 16:21:19
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv31649
Modified Files:
config.in
Log Message:
DDB5476 has selectable endianess, so remove hardwiring endianess to little endian.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.25
retrieving revision 1.26
diff -u -d -r1.25 -r1.26
--- config.in 2001/09/26 23:12:58 1.25
+++ config.in 2001/09/28 16:21:12 1.26
@@ -281,8 +281,8 @@
R4300 CONFIG_CPU_R4300 \
R4x00 CONFIG_CPU_R4X00 \
R5000 CONFIG_CPU_R5000 \
- R5900 CONFIG_CPU_R5900 \
R5432 CONFIG_CPU_R5432 \
+ R5900 CONFIG_CPU_R5900 \
RM7000 CONFIG_CPU_RM7000 \
R52xx CONFIG_CPU_NEVADA \
R10000 CONFIG_CPU_R10000 \
@@ -325,7 +325,6 @@
comment 'General setup'
if [ "$CONFIG_DECSTATION" = "y" -o \
"$CONFIG_DDB5074" = "y" -o \
- "$CONFIG_DDB5476" = "y" -o \
"$CONFIG_NINO" = "y" -o \
"$CONFIG_NEC_OSPREY" = "y" -o \
"$CONFIG_NEC_KORVA" = "y" ]; then
@@ -488,7 +487,7 @@
fi
bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
- int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 25
+ int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 256
fi
# if [ "$CONFIG_ACCESSBUS" = "y" ]; then
# bool 'MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE
@@ -500,9 +499,7 @@
if [ "$CONFIG_SGI_IP22" = "y" ]; then
mainmenu_option next_comment
comment 'SGI Character devices'
- bool 'Virtual terminal' CONFIG_VT
if [ "$CONFIG_VT" = "y" ]; then
- bool 'Support for console on virtual terminal' CONFIG_VT_CONSOLE
tristate 'SGI Newport Console support' CONFIG_SGI_NEWPORT_CONSOLE
if [ "$CONFIG_SGI_NEWPORT_CONSOLE" != "y" ]; then
define_bool CONFIG_DUMMY_CONSOLE y
|
|
From: Jun S. <ju...@us...> - 2001-09-27 23:59:17
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv12527/arch/mips/vr4181/common
Modified Files:
Makefile irq.c
Added Files:
int_handler.S
Log Message:
Re-write low-level irq dispatching code for vr4181/osprey. Pave the way for
the complete IRQ re-write.
--- NEW FILE: int_handler.S ---
/*
* linux/arch/mips/vr4181/common/int_handler.S
*
* Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
*
* Written by Ralf Baechle and Andreas Busse, modified for DECStation
* support by Paul Antoine and Harald Koerfgen.
*
* completly rewritten:
* Copyright (C) 1998 Harald Koerfgen
*
* Adapted to the VR4181 and almost entirely rewritten:
* Copyright (C) 1999 Bradley D. LaRonde and Michael Klar
*
* Clean up to conform to the new IRQ
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/vr4181/vr4181.h>
/*
* [jsun]
* See include/asm/vr4181/irq.h for IRQ assignment and strategy.
*/
.text
.set noreorder
.align 5
NESTED(vr4181_handle_irq, PT_SIZE, ra)
.set noat
SAVE_ALL
CLI
.set at
.set noreorder
mfc0 t0, CP0_CAUSE
mfc0 t2, CP0_STATUS
and t0, t2
/* we check IP2 first; it happens most frequently */
andi t1, t0, STATUSF_IP2
bnez t1, ll_cpu_ip2
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_cputimer_irq
andi t1, t0, STATUSF_IP3
bnez t1, ll_cpu_ip3
andi t1, t0, STATUSF_IP4
bnez t1, ll_cpu_ip4
andi t1, t0, STATUSF_IP5
bnez t1, ll_cpu_ip5
andi t1, t0, STATUSF_IP6
bnez t1, ll_cpu_ip6
andi t1, t0, STATUSF_IP0 /* software int 0 */
bnez t1, ll_cpu_ip0
andi t1, t0, STATUSF_IP1 /* software int 1 */
bnez t1, ll_cpu_ip1
nop
.set reorder
do_spurious:
j spurious_interrupt
/*
* regular CPU irqs
*/
ll_cputimer_irq:
li a0, VR4181_IRQ_TIMER
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip0:
li a0, VR4181_IRQ_SW1
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip1:
li a0, VR4181_IRQ_SW2
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip3:
li a0, VR4181_IRQ_INT1
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip4:
li a0, VR4181_IRQ_INT2
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip5:
li a0, VR4181_IRQ_INT3
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip6:
li a0, VR4181_IRQ_INT4
move a1, sp
jal do_IRQ
j ret_from_irq
/*
* One of the sys irq has happend.
*
* In the interest of speed, we first determine in the following order
* which 16-irq block have pending interrupts:
* sysint1 (16 sources, including cascading intrs from GPIO)
* sysint2
* gpio (16 intr sources)
*
* Then we do binary search to find the exact interrupt source.
*/
ll_cpu_ip2:
lui t3,%hi(VR4181_SYSINT1REG)
lhu t0,%lo(VR4181_SYSINT1REG)(t3)
lhu t2,%lo(VR4181_MSYSINT1REG)(t3)
and t0, 0xfffb /* hack - remove RTC Long 1 intr */
and t0, t2
beqz t0, check_sysint2
/* check for GPIO interrupts */
andi t1, t0, 0x0100
bnez t1, check_gpio_int
/* so we have an interrupt in sysint1 which is not gpio int */
li a0, VR4181_SYS_IRQ_BASE - 1
j check_16
check_sysint2:
lhu t0,%lo(VR4181_SYSINT2REG)(t3)
lhu t2,%lo(VR4181_MSYSINT2REG)(t3)
and t0, 0xfffe /* hack - remove RTC Long 2 intr */
and t0, t2
li a0, VR4181_SYS_IRQ_BASE + 16 - 1
j check_16
check_gpio_int:
lui t3,%hi(VR4181_GPINTMSK)
lhu t0,%lo(VR4181_GPINTMSK)(t3)
lhu t2,%lo(VR4181_GPINTSTAT)(t3)
xori t0, 0xffff /* why? reverse logic? */
and t0, t2
li a0, VR4181_GPIO_IRQ_BASE - 1
j check_16
/*
* When we reach check_16, we have 16-bit status in t0 and base irq number
* in a0.
*/
check_16:
andi t1, t0, 0xff
bnez t1, check_8
srl t0, 8
addi a0, 8
j check_8
/*
* When we reach check_8, we have 8-bit status in t0 and base irq number
* in a0.
*/
check_8:
andi t1, t0, 0xf
bnez t1, check_4
srl t0, 4
addi a0, 4
j check_4
/*
* When we reach check_4, we have 4-bit status in t0 and base irq number
* in a0.
*/
check_4:
andi t0, t0, 0xf
beqz t0, do_spurious
loop:
andi t2, t0, 0x1
srl t0, 1
addi a0, 1
beqz t2, loop
found_it:
move a1, sp
jal do_IRQ
j ret_from_irq
END(vr4181_handle_irq)
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile 2001/09/22 16:35:15 1.2
+++ Makefile 2001/09/27 23:59:15 1.3
@@ -13,6 +13,6 @@
O_TARGET:= vr4181.o
-obj-y := irq.o serial.o time.o
+obj-y := irq.o int_handler.o serial.o time.o
include $(TOPDIR)/Rules.make
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/irq.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- irq.c 2001/09/27 00:03:04 1.3
+++ irq.c 2001/09/27 23:59:15 1.4
@@ -26,13 +26,14 @@
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/gdb-stub.h>
+
#include <asm/vr4181/vr4181.h>
/* [jsun] HACK */
#define CONFIG_CPU_VR4181 y
#define DEVICE_IRQ_MASKL 0xffff
-extern asmlinkage void vr41xx_handle_irq(void);
+extern asmlinkage void vr4181_handle_irq(void);
extern void breakpoint(void);
// This is used elsewhere
@@ -465,7 +466,7 @@
void __init init_IRQ(void)
{
- set_except_vector(0, vr41xx_handle_irq);
+ set_except_vector(0, vr4181_handle_irq);
// Default all ICU IRQs to off ...
*VR4181_MSYSINT1REG = 0;
|
|
From: Jun S. <ju...@us...> - 2001-09-27 23:59:17
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv12527/arch/mips/vr4181/osprey
Modified Files:
Makefile prom.c
Removed Files:
int_handler.S
Log Message:
Re-write low-level irq dispatching code for vr4181/osprey. Pave the way for
the complete IRQ re-write.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile 2001/09/22 04:27:15 1.1
+++ Makefile 2001/09/27 23:59:15 1.2
@@ -13,6 +13,6 @@
O_TARGET:= osprey.o
-obj-y := setup.o prom.o reset.o int_handler.o dbg_io.o
+obj-y := setup.o prom.o reset.o dbg_io.o
include $(TOPDIR)/Rules.make
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/prom.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- prom.c 2001/09/22 16:35:15 1.2
+++ prom.c 2001/09/27 23:59:15 1.3
@@ -32,7 +32,7 @@
void __init prom_init()
{
strcpy(arcs_cmdline, "ip=bootp ");
- strcat(arcs_cmdline, "ether=0,0x03fe0300,eth0 ");
+ strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
// strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
// strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 ");
--- int_handler.S DELETED ---
|
|
From: Jun S. <ju...@us...> - 2001-09-27 23:59:17
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4181
In directory usw-pr-cvs1:/tmp/cvs-serv12527/include/asm-mips/vr4181
Modified Files:
vr4181.h
Added Files:
irq.h
Log Message:
Re-write low-level irq dispatching code for vr4181/osprey. Pave the way for
the complete IRQ re-write.
--- NEW FILE: irq.h ---
/*
* Copyright (C) 1999 by Michael Klar
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/*
* Strategy:
*
* Vr4181 has conceptually three levels of interrupt controllers:
* 1. the CPU itself with 8 intr level.
* 2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs
* 3. GPIO interrupts : forwarding external interrupts to sys intr controller
*/
/* decide the irq block assignment */
#define VR4181_NUM_CPU_IRQ 8
#define VR4181_NUM_SYS_IRQ 32
#define VR4181_NUM_GPIO_IRQ 16
#define VR4181_IRQ_BASE 0
#define VR4181_CPU_IRQ_BASE VR4181_IRQ_BASE
#define VR4181_SYS_IRQ_BASE (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ)
#define VR4181_GPIO_IRQ_BASE (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ)
/* CPU interrupts */
/*
IP0 - Software interrupt
IP1 - Software interrupt
IP2 - All but battery, high speed modem, and real time clock
IP3 - RTC Long1 (system timer)
IP4 - RTC Long2
IP5 - High Speed Modem (unused on VR4181)
IP6 - Unused
IP7 - Timer interrupt from CPO_COMPARE
*/
#define VR4181_IRQ_SW1 (VR4181_CPU_IRQ_BASE + 0)
#define VR4181_IRQ_SW2 (VR4181_CPU_IRQ_BASE + 1)
#define VR4181_IRQ_INT0 (VR4181_CPU_IRQ_BASE + 2)
#define VR4181_IRQ_INT1 (VR4181_CPU_IRQ_BASE + 3)
#define VR4181_IRQ_INT2 (VR4181_CPU_IRQ_BASE + 4)
#define VR4181_IRQ_INT3 (VR4181_CPU_IRQ_BASE + 5)
#define VR4181_IRQ_INT4 (VR4181_CPU_IRQ_BASE + 6)
#define VR4181_IRQ_TIMER (VR4181_CPU_IRQ_BASE + 7)
/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */
/*
IP2 - same as VR4181_IRQ_INT1
IP8 - This is a cascade to GPIO IRQ's. Do not use.
IP16 - same as VR4181_IRQ_INT2
IP18 - CompactFlash
*/
#define VR4181_IRQ_BATTERY (VR4181_SYS_IRQ_BASE + 0)
#define VR4181_IRQ_POWER (VR4181_SYS_IRQ_BASE + 1)
#define VR4181_IRQ_RTCL1 (VR4181_SYS_IRQ_BASE + 2)
#define VR4181_IRQ_ETIMER (VR4181_SYS_IRQ_BASE + 3)
#define VR4181_IRQ_RFU12 (VR4181_SYS_IRQ_BASE + 4)
#define VR4181_IRQ_PIU (VR4181_SYS_IRQ_BASE + 5)
#define VR4181_IRQ_AIU (VR4181_SYS_IRQ_BASE + 6)
#define VR4181_IRQ_KIU (VR4181_SYS_IRQ_BASE + 7)
#define VR4181_IRQ_GIU (VR4181_SYS_IRQ_BASE + 8)
#define VR4181_IRQ_SIU (VR4181_SYS_IRQ_BASE + 9)
#define VR4181_IRQ_RFU18 (VR4181_SYS_IRQ_BASE + 10)
#define VR4181_IRQ_SOFT (VR4181_SYS_IRQ_BASE + 11)
#define VR4181_IRQ_RFU20 (VR4181_SYS_IRQ_BASE + 12)
#define VR4181_IRQ_DOZEPIU (VR4181_SYS_IRQ_BASE + 13)
#define VR4181_IRQ_RFU22 (VR4181_SYS_IRQ_BASE + 14)
#define VR4181_IRQ_RFU23 (VR4181_SYS_IRQ_BASE + 15)
#define VR4181_IRQ_RTCL2 (VR4181_SYS_IRQ_BASE + 16)
#define VR4181_IRQ_LED (VR4181_SYS_IRQ_BASE + 17)
#define VR4181_IRQ_ECU (VR4181_SYS_IRQ_BASE + 18)
#define VR4181_IRQ_CSU (VR4181_SYS_IRQ_BASE + 19)
#define VR4181_IRQ_USB (VR4181_SYS_IRQ_BASE + 20)
#define VR4181_IRQ_DMA (VR4181_SYS_IRQ_BASE + 21)
#define VR4181_IRQ_LCD (VR4181_SYS_IRQ_BASE + 22)
#define VR4181_IRQ_RFU31 (VR4181_SYS_IRQ_BASE + 23)
#define VR4181_IRQ_RFU32 (VR4181_SYS_IRQ_BASE + 24)
#define VR4181_IRQ_RFU33 (VR4181_SYS_IRQ_BASE + 25)
#define VR4181_IRQ_RFU34 (VR4181_SYS_IRQ_BASE + 26)
#define VR4181_IRQ_RFU35 (VR4181_SYS_IRQ_BASE + 27)
#define VR4181_IRQ_RFU36 (VR4181_SYS_IRQ_BASE + 28)
#define VR4181_IRQ_RFU37 (VR4181_SYS_IRQ_BASE + 29)
#define VR4181_IRQ_RFU38 (VR4181_SYS_IRQ_BASE + 30)
#define VR4181_IRQ_RFU39 (VR4181_SYS_IRQ_BASE + 31)
/* Cascaded from VR4181_IRQ_GIU */
#define VR4181_IRQ_GPIO0 (VR4181_GPIO_IRQ_BASE + 0)
#define VR4181_IRQ_GPIO1 (VR4181_GPIO_IRQ_BASE + 1)
#define VR4181_IRQ_GPIO2 (VR4181_GPIO_IRQ_BASE + 2)
#define VR4181_IRQ_GPIO3 (VR4181_GPIO_IRQ_BASE + 3)
#define VR4181_IRQ_GPIO4 (VR4181_GPIO_IRQ_BASE + 4)
#define VR4181_IRQ_GPIO5 (VR4181_GPIO_IRQ_BASE + 5)
#define VR4181_IRQ_GPIO6 (VR4181_GPIO_IRQ_BASE + 6)
#define VR4181_IRQ_GPIO7 (VR4181_GPIO_IRQ_BASE + 7)
#define VR4181_IRQ_GPIO8 (VR4181_GPIO_IRQ_BASE + 8)
#define VR4181_IRQ_GPIO9 (VR4181_GPIO_IRQ_BASE + 9)
#define VR4181_IRQ_GPIO10 (VR4181_GPIO_IRQ_BASE + 10)
#define VR4181_IRQ_GPIO11 (VR4181_GPIO_IRQ_BASE + 11)
#define VR4181_IRQ_GPIO12 (VR4181_GPIO_IRQ_BASE + 12)
#define VR4181_IRQ_GPIO13 (VR4181_GPIO_IRQ_BASE + 13)
#define VR4181_IRQ_GPIO14 (VR4181_GPIO_IRQ_BASE + 14)
#define VR4181_IRQ_GPIO15 (VR4181_GPIO_IRQ_BASE + 15)
// Alternative to above GPIO IRQ defines
#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
#define VR4181_IRQ_MAX (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \
VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ)
Index: vr4181.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4181/vr4181.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- vr4181.h 2001/09/22 04:27:16 1.1
+++ vr4181.h 2001/09/27 23:59:15 1.2
@@ -12,73 +12,7 @@
#include <asm/addrspace.h>
-// CPU interrupts
-#define VR4181_IRQ_SW1 0 // IP0 - Software interrupt
-#define VR4181_IRQ_SW2 1 // IP1 - Software interrupt
-#define VR4181_IRQ_INT0 2 // IP2 - All but battery, high speed modem, and real time clock
-#define VR4181_IRQ_INT1 3 // IP3 - RTC Long1 (system timer)
-#define VR4181_IRQ_INT2 4 // IP4 - RTC Long2
-#define VR4181_IRQ_INT3 5 // IP5 - High Speed Modem (unused on VR4181)
-#define VR4181_IRQ_INT4 6 // IP6 - Unused
-#define VR4181_IRQ_TIMER 7 // IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.)
-
-// Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts)
-#define VR4181_IRQ_BATTERY 8
-#define VR4181_IRQ_POWER 9
-#define VR4181_IRQ_RTCL1 10 // Use VR4181_IRQ_INT1 instead.
-#define VR4181_IRQ_ETIMER 11
-#define VR4181_IRQ_RFU12 12
-#define VR4181_IRQ_PIU 13
-#define VR4181_IRQ_AIU 14
-#define VR4181_IRQ_KIU 15
-#define VR4181_IRQ_GIU 16 // This is a cascade to IRQs 40-71. Do not use.
-#define VR4181_IRQ_SIU 17
-#define VR4181_IRQ_RFU18 18
-#define VR4181_IRQ_SOFT 19
-#define VR4181_IRQ_RFU20 20
-#define VR4181_IRQ_DOZEPIU 21
-#define VR4181_IRQ_RFU22 22
-#define VR4181_IRQ_RFU23 23
-#define VR4181_IRQ_RTCL2 24 // Use VR4181_IRQ_INT2 instead.
-#define VR4181_IRQ_LED 25
-#define VR4181_IRQ_ECU 26 // (CompactFlash)
-#define VR4181_IRQ_CSU 27
-#define VR4181_IRQ_USB 28
-#define VR4181_IRQ_DMA 29
-#define VR4181_IRQ_LCD 30
-#define VR4181_IRQ_RFU31 31
-#define VR4181_IRQ_RFU32 32
-#define VR4181_IRQ_RFU33 33
-#define VR4181_IRQ_RFU34 34
-#define VR4181_IRQ_RFU35 35
-#define VR4181_IRQ_RFU36 36
-#define VR4181_IRQ_RFU37 37
-#define VR4181_IRQ_RFU38 38
-#define VR4181_IRQ_RFU39 39
-// Note: Still need to do the extra VR4181 IRQ definitions
-
-// Cascaded from VR4181_IRQ_GIU
-#define VR4181_IRQ_GPIO0 40
-#define VR4181_IRQ_GPIO1 41
-#define VR4181_IRQ_GPIO2 42
-#define VR4181_IRQ_GPIO3 43
-#define VR4181_IRQ_GPIO4 44
-#define VR4181_IRQ_GPIO5 45
-#define VR4181_IRQ_GPIO6 46
-#define VR4181_IRQ_GPIO7 47
-#define VR4181_IRQ_GPIO8 48
-#define VR4181_IRQ_GPIO9 49
-#define VR4181_IRQ_GPIO10 50
-#define VR4181_IRQ_GPIO11 51
-#define VR4181_IRQ_GPIO12 52
-#define VR4181_IRQ_GPIO13 53
-#define VR4181_IRQ_GPIO14 54
-#define VR4181_IRQ_GPIO15 55
-
-// Alternative to above GPIO IRQ defines
-#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
-
-#define VR4181_IRQ_MAX 55
+#include <asm/vr4181/irq.h>
#ifndef _LANGUAGE_ASSEMBLY
#define __preg8 (volatile unsigned char*)
|
|
From: James S. <jsi...@us...> - 2001-09-27 23:53:30
|
Update of /cvsroot/linux-mips/linux/arch/mips/dec
In directory usw-pr-cvs1:/tmp/cvs-serv8102
Modified Files:
irq.c
Log Message:
Handle softirqs in do_IRQ. Run whole file through indent.
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/dec/irq.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- irq.c 2001/06/22 02:29:31 1.1.1.1
+++ irq.c 2001/09/27 23:53:27 1.2
@@ -38,44 +38,48 @@
static inline void mask_irq(unsigned int irq_nr)
{
- unsigned int dummy;
+ unsigned int dummy;
- if (dec_interrupt[irq_nr].iemask) { /* This is an ASIC interrupt */
- *imr &= ~dec_interrupt[irq_nr].iemask;
- dummy = *imr;
- dummy = *imr;
- } else /* This is a cpu interrupt */
- change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) & ~dec_interrupt[irq_nr].cpu_mask);
+ if (dec_interrupt[irq_nr].iemask) { /* This is an ASIC interrupt */
+ *imr &= ~dec_interrupt[irq_nr].iemask;
+ dummy = *imr;
+ dummy = *imr;
+ } else /* This is a cpu interrupt */
+ change_cp0_status(ST0_IM,
+ read_32bit_cp0_register(CP0_STATUS) &
+ ~dec_interrupt[irq_nr].cpu_mask);
}
static inline void unmask_irq(unsigned int irq_nr)
{
- unsigned int dummy;
+ unsigned int dummy;
- if (dec_interrupt[irq_nr].iemask) { /* This is an ASIC interrupt */
- *imr |= dec_interrupt[irq_nr].iemask;
- dummy = *imr;
- dummy = *imr;
- }
- change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) | dec_interrupt[irq_nr].cpu_mask);
+ if (dec_interrupt[irq_nr].iemask) { /* This is an ASIC interrupt */
+ *imr |= dec_interrupt[irq_nr].iemask;
+ dummy = *imr;
+ dummy = *imr;
+ }
+ change_cp0_status(ST0_IM,
+ read_32bit_cp0_register(CP0_STATUS) |
+ dec_interrupt[irq_nr].cpu_mask);
}
void disable_irq(unsigned int irq_nr)
{
- unsigned long flags;
+ unsigned long flags;
- save_and_cli(flags);
- mask_irq(irq_nr);
- restore_flags(flags);
+ save_and_cli(flags);
+ mask_irq(irq_nr);
+ restore_flags(flags);
}
void enable_irq(unsigned int irq_nr)
{
- unsigned long flags;
+ unsigned long flags;
- save_and_cli(flags);
- unmask_irq(irq_nr);
- restore_flags(flags);
+ save_and_cli(flags);
+ unmask_irq(irq_nr);
+ restore_flags(flags);
}
/*
@@ -84,35 +88,35 @@
*/
extern void interrupt(void);
-static struct irqaction *irq_action[32] =
-{
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
+static struct irqaction *irq_action[32] = {
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
};
int get_irq_list(char *buf)
{
- int i, len = 0;
- struct irqaction *action;
+ int i, len = 0;
+ struct irqaction *action;
- for (i = 0; i < 32; i++) {
- action = irq_action[i];
- if (!action)
- continue;
- len += sprintf(buf + len, "%2d: %8d %c %s",
- i, kstat.irqs[0][i],
- (action->flags & SA_INTERRUPT) ? '+' : ' ',
- action->name);
- for (action = action->next; action; action = action->next) {
- len += sprintf(buf + len, ",%s %s",
- (action->flags & SA_INTERRUPT) ? " +" : "",
- action->name);
+ for (i = 0; i < 32; i++) {
+ action = irq_action[i];
+ if (!action)
+ continue;
+ len += sprintf(buf + len, "%2d: %8d %c %s",
+ i, kstat.irqs[0][i],
+ (action->flags & SA_INTERRUPT) ? '+' : ' ',
+ action->name);
+ for (action = action->next; action; action = action->next) {
+ len += sprintf(buf + len, ",%s %s",
+ (action->
+ flags & SA_INTERRUPT) ? " +" : "",
+ action->name);
+ }
+ len += sprintf(buf + len, "\n");
}
- len += sprintf(buf + len, "\n");
- }
- return len;
+ return len;
}
/*
@@ -124,33 +128,34 @@
*/
asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
{
- struct irqaction *action;
- int do_random, cpu;
+ struct irqaction *action;
+ int do_random, cpu;
- cpu = smp_processor_id();
- irq_enter(cpu, irq);
- kstat.irqs[cpu][irq]++;
+ cpu = smp_processor_id();
+ irq_enter(cpu, irq);
+ kstat.irqs[cpu][irq]++;
- mask_irq(irq);
- action = *(irq + irq_action);
- if (action) {
- if (!(action->flags & SA_INTERRUPT))
- __sti();
+ mask_irq(irq);
action = *(irq + irq_action);
- do_random = 0;
- do {
- do_random |= action->flags;
- action->handler(irq, action->dev_id, regs);
- action = action->next;
- } while (action);
- if (do_random & SA_SAMPLE_RANDOM)
- add_interrupt_randomness(irq);
- __cli();
- unmask_irq(irq);
- }
- irq_exit(cpu, irq);
+ if (action) {
+ if (!(action->flags & SA_INTERRUPT))
+ __sti();
+ action = *(irq + irq_action);
+ do_random = 0;
+ do {
+ do_random |= action->flags;
+ action->handler(irq, action->dev_id, regs);
+ action = action->next;
+ } while (action);
+ if (do_random & SA_SAMPLE_RANDOM)
+ add_interrupt_randomness(irq);
+ __cli();
+ unmask_irq(irq);
+ }
+ irq_exit(cpu, irq);
- /* unmasking and bottom half handling is done magically for us. */
+ if (softirq_pending(cpu))
+ do_softirq();
}
/*
@@ -159,139 +164,140 @@
*/
int setup_dec_irq(int irq, struct irqaction *new)
{
- int shared = 0;
- struct irqaction *old, **p;
- unsigned long flags;
+ int shared = 0;
+ struct irqaction *old, **p;
+ unsigned long flags;
- p = irq_action + irq;
- if ((old = *p) != NULL) {
- /* Can't share interrupts unless both agree to */
- if (!(old->flags & new->flags & SA_SHIRQ))
- return -EBUSY;
+ p = irq_action + irq;
+ if ((old = *p) != NULL) {
+ /* Can't share interrupts unless both agree to */
+ if (!(old->flags & new->flags & SA_SHIRQ))
+ return -EBUSY;
- /* Can't share interrupts unless both are same type */
- if ((old->flags ^ new->flags) & SA_INTERRUPT)
- return -EBUSY;
+ /* Can't share interrupts unless both are same type */
+ if ((old->flags ^ new->flags) & SA_INTERRUPT)
+ return -EBUSY;
- /* add new interrupt at end of irq queue */
- do {
- p = &old->next;
- old = *p;
- } while (old);
- shared = 1;
- }
- if (new->flags & SA_SAMPLE_RANDOM)
- rand_initialize_irq(irq);
+ /* add new interrupt at end of irq queue */
+ do {
+ p = &old->next;
+ old = *p;
+ } while (old);
+ shared = 1;
+ }
+ if (new->flags & SA_SAMPLE_RANDOM)
+ rand_initialize_irq(irq);
- save_and_cli(flags);
- *p = new;
+ save_and_cli(flags);
+ *p = new;
- if (!shared) {
- unmask_irq(irq);
- }
- restore_flags(flags);
- return 0;
+ if (!shared) {
+ unmask_irq(irq);
+ }
+ restore_flags(flags);
+ return 0;
}
int request_irq(unsigned int irq,
void (*handler) (int, void *, struct pt_regs *),
- unsigned long irqflags,
- const char *devname,
- void *dev_id)
+ unsigned long irqflags, const char *devname, void *dev_id)
{
- int retval;
- struct irqaction *action;
+ int retval;
+ struct irqaction *action;
- if (irq >= 32)
- return -EINVAL;
- if (!handler)
- return -EINVAL;
+ if (irq >= 32)
+ return -EINVAL;
+ if (!handler)
+ return -EINVAL;
- action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL);
- if (!action)
- return -ENOMEM;
+ action =
+ (struct irqaction *) kmalloc(sizeof(struct irqaction),
+ GFP_KERNEL);
+ if (!action)
+ return -ENOMEM;
- action->handler = handler;
- action->flags = irqflags;
- action->mask = 0;
- action->name = devname;
- action->next = NULL;
- action->dev_id = dev_id;
+ action->handler = handler;
+ action->flags = irqflags;
+ action->mask = 0;
+ action->name = devname;
+ action->next = NULL;
+ action->dev_id = dev_id;
- retval = setup_dec_irq(irq, action);
+ retval = setup_dec_irq(irq, action);
- if (retval)
- kfree(action);
- return retval;
+ if (retval)
+ kfree(action);
+ return retval;
}
void free_irq(unsigned int irq, void *dev_id)
{
- struct irqaction *action, **p;
- unsigned long flags;
+ struct irqaction *action, **p;
+ unsigned long flags;
- if (irq > 39) {
- printk("Trying to free IRQ%d\n", irq);
- return;
- }
- for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) {
- if (action->dev_id != dev_id)
- continue;
+ if (irq > 39) {
+ printk("Trying to free IRQ%d\n", irq);
+ return;
+ }
+ for (p = irq + irq_action; (action = *p) != NULL;
+ p = &action->next) {
+ if (action->dev_id != dev_id)
+ continue;
- /* Found it - now free it */
- save_and_cli(flags);
- *p = action->next;
- if (!irq[irq_action])
- mask_irq(irq);
- restore_flags(flags);
- kfree(action);
- return;
- }
- printk("Trying to free free IRQ%d\n", irq);
+ /* Found it - now free it */
+ save_and_cli(flags);
+ *p = action->next;
+ if (!irq[irq_action])
+ mask_irq(irq);
+ restore_flags(flags);
+ kfree(action);
+ return;
+ }
+ printk("Trying to free free IRQ%d\n", irq);
}
unsigned long probe_irq_on(void)
{
- /* TODO */
- return 0;
+ /* TODO */
+ return 0;
}
int probe_irq_off(unsigned long irqs)
{
- /* TODO */
- return 0;
+ /* TODO */
+ return 0;
}
void __init init_IRQ(void)
{
- switch (mips_machtype) {
- case MACH_DS23100:
- dec_init_kn01();
- break;
- case MACH_DS5100: /* DS5100 MIPSMATE */
- dec_init_kn230();
- break;
- case MACH_DS5000_200: /* DS5000 3max */
- dec_init_kn02();
- break;
- case MACH_DS5000_1XX: /* DS5000/100 3min */
- dec_init_kn02ba();
- break;
- case MACH_DS5000_2X0: /* DS5000/240 3max+ */
- dec_init_kn03();
- break;
- case MACH_DS5000_XX: /* Personal DS5000/2x */
- dec_init_kn02ca();
- break;
- case MACH_DS5800: /* DS5800 Isis */
- panic("Don't know how to set this up!");
- break;
- case MACH_DS5400: /* DS5400 MIPSfair */
- panic("Don't know how to set this up!");
- break;
- case MACH_DS5500: /* DS5500 MIPSfair-2 */
- panic("Don't know how to set this up!");
- break;
- }
- set_except_vector(0, decstation_handle_int);
+ switch (mips_machtype) {
+ case MACH_DS23100:
+ dec_init_kn01();
+ break;
+ case MACH_DS5100: /* DS5100 MIPSMATE */
+ dec_init_kn230();
+ break;
+ case MACH_DS5000_200: /* DS5000 3max */
+ dec_init_kn02();
+ break;
+ case MACH_DS5000_1XX: /* DS5000/100 3min */
+ dec_init_kn02ba();
+ break;
+ case MACH_DS5000_2X0: /* DS5000/240 3max+ */
+ dec_init_kn03();
+ break;
+ case MACH_DS5000_XX: /* Personal DS5000/2x */
+ dec_init_kn02ca();
+ break;
+ case MACH_DS5800: /* DS5800 Isis */
+ panic("Don't know how to set this up!");
+ break;
+ case MACH_DS5400: /* DS5400 MIPSfair */
+ panic("Don't know how to set this up!");
+ break;
+ case MACH_DS5500: /* DS5500 MIPSfair-2 */
+ panic("Don't know how to set this up!");
+ break;
+ }
+ set_except_vector(0, decstation_handle_int);
}
|
|
From: James S. <jsi...@us...> - 2001-09-27 22:36:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv20802 Modified Files: Makefile irq.c Log Message: Export probe_irq_mask. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/Makefile,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- Makefile 2001/09/26 23:19:53 1.7 +++ Makefile 2001/09/27 22:36:33 1.8 @@ -37,7 +37,7 @@ obj-$(CONFIG_SMP) += smp.o # Old style irq support, going to die in 2.5. -export-objs += old-irq.o +export-objs += irq.o old-irq.o obj-$(CONFIG_NEW_IRQ) += irq.o obj-$(CONFIG_ROTTEN_IRQ) += old-irq.o obj-$(CONFIG_I8259) += i8259.o Index: irq.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/irq.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- irq.c 2001/08/10 22:14:46 1.3 +++ irq.c 2001/09/27 22:36:33 1.4 @@ -705,3 +705,5 @@ irq_desc[i].handler = &no_irq_type; } } + +EXPORT_SYMBOL(probe_irq_mask); |
|
From: James S. <jsi...@us...> - 2001-09-27 17:27:52
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv26298
Modified Files:
traps.c
Log Message:
Handle NULL argument also.
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- traps.c 2001/09/26 23:21:32 1.17
+++ traps.c 2001/09/27 17:27:49 1.18
@@ -101,7 +101,7 @@
int i;
unsigned int *stack;
- stack = sp;
+ stack = sp ? sp : (unsigned int *)&sp;
i = 0;
printk("Stack:");
@@ -134,7 +134,7 @@
unsigned long module_start, module_end;
extern char _stext, _etext;
- stack = sp;
+ stack = sp ? sp : (unsigned int *)&sp;
i = 0;
kernel_start = (unsigned long) &_stext;
|
|
From: Jun S. <ju...@us...> - 2001-09-27 00:03:10
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common In directory usw-pr-cvs1:/tmp/cvs-serv17091/arch/mips/vr4181/common Modified Files: irq.c Log Message: Need to check for pending softirq in do_IRQ(). We need to move to the new irq, but this fix makes osprey happy for now. Index: irq.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/common/irq.c,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- irq.c 2001/09/22 16:35:15 1.2 +++ irq.c 2001/09/27 00:03:04 1.3 @@ -220,6 +220,9 @@ irq_exit(cpu, irq); + if (softirq_pending(cpu)) + do_softirq(); + // Unmasking and softirq handling is done for us // currently by ret_from_irq in entry.S. } |
|
From: James S. <jsi...@us...> - 2001-09-26 23:21:35
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv8109
Modified Files:
traps.c
Log Message:
Add \n back.
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- traps.c 2001/09/26 16:51:45 1.16
+++ traps.c 2001/09/26 23:21:32 1.17
@@ -142,7 +142,7 @@
module_start = VMALLOC_START;
module_end = module_start + MODULE_RANGE;
- printk("Call Trace:");
+ printk("\nCall Trace:");
while ((unsigned long) stack & (PAGE_SIZE -1)) {
unsigned long addr;
|
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