linux-mips-commits — CVS Commit Patches

[Linux-mips-commits]CVS: linux/include/asm-mips64 pci.h,1.6,1.7

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv6813

Modified Files:
	pci.h 
Log Message:
pci_map_page fixes.

Index: pci.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pci.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- pci.h	2001/11/06 09:10:22	1.6
+++ pci.h	2001/11/12 18:38:46	1.7
@@ -134,14 +134,17 @@
 				      unsigned long offset, size_t size,
                                       int direction)
 {
+	unsigned long addr;
+
 	if (direction == PCI_DMA_NONE)
 		BUG();
 
+	addr = (unsigned long) page_address(page) + offset;
 #ifndef CONFIG_COHERENT_IO
-	dma_cache_wback_inv((unsigned long) page_address(page), size);
+	dma_cache_wback_inv(addr, size);
 #endif
 
-	return page_to_bus(page);
+	return virt_to_bus(addr);
 }
 
 static inline void pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address,

[Linux-mips-commits]CVS: linux/include/asm-mips64 io.h,1.7,1.8

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv6506

Modified Files:
	io.h 
Log Message:
Fix base address for isa_* functions.

Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/io.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- io.h	2001/10/31 18:26:52	1.7
+++ io.h	2001/11/12 18:37:56	1.8
@@ -128,6 +128,26 @@
 extern unsigned long isa_slot_offset;
 
 /*
+ * ISA space is 'always mapped' on currently supported MIPS systems, no need
+ * to explicitly ioremap() it. The fact that the ISA IO space is mapped
+ * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
+ * are physical addresses. The following constant pointer can be
+ * used as the IO-area pointer (it can be iounmapped as well, so the
+ * analogy with PCI is quite large):
+ */
+#define __ISA_IO_base ((char *)(isa_slot_offset))
+
+#define isa_readb(a) readb(__ISA_IO_base + (a))
+#define isa_readw(a) readw(__ISA_IO_base + (a))
+#define isa_readl(a) readl(__ISA_IO_base + (a))
+#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
+#define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
+#define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
+#define isa_memset_io(a,b,c)		memset_io(__ISA_IO_base + (a),(b),(c))
+#define isa_memcpy_fromio(a,b,c)	memcpy_fromio((a),__ISA_IO_base + (b),(c))
+#define isa_memcpy_toio(a,b,c)		memcpy_toio(__ISA_IO_base + (a),(b),(c))
+
+/*
  * We don't have csum_partial_copy_fromio() yet, so we cheat here and
  * just copy it. The net code will then do the checksum later.
  */

[Linux-mips-commits]CVS: linux/include/asm-mips io.h,1.8,1.9

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv6277

Modified Files:
	io.h 
Log Message:
Fix base address for isa_* functions.

Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/io.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- io.h	2001/11/06 00:30:47	1.8
+++ io.h	2001/11/12 18:37:12	1.9
@@ -187,18 +187,17 @@
  * used as the IO-area pointer (it can be iounmapped as well, so the
  * analogy with PCI is quite large):
  */
-#define __ISA_IO_base ((char *)(PAGE_OFFSET))
-
-#define isa_readb(a) readb(a)
-#define isa_readw(a) readw(a)
-#define isa_readl(a) readl(a)
-#define isa_writeb(b,a) writeb(b,a)
-#define isa_writew(w,a) writew(w,a)
-#define isa_writel(l,a) writel(l,a)
+#define __ISA_IO_base ((char *)(isa_slot_offset))
 
-#define isa_memset_io(a,b,c)     memset_io((a),(b),(c))
-#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
-#define isa_memcpy_toio(a,b,c)   memcpy_toio((a),(b),(c))
+#define isa_readb(a) readb(__ISA_IO_base + (a))
+#define isa_readw(a) readw(__ISA_IO_base + (a)) 
+#define isa_readl(a) readl(__ISA_IO_base + (a))
+#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
+#define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
+#define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
+#define isa_memset_io(a,b,c)		memset_io(__ISA_IO_base + (a),(b),(c)) 
+#define isa_memcpy_fromio(a,b,c)	memcpy_fromio((a),__ISA_IO_base + (b),(c))
+#define isa_memcpy_toio(a,b,c)		memcpy_toio(__ISA_IO_base + (a),(b),(c))
 
 /*
  * We don't have csum_partial_copy_fromio() yet, so we cheat here and

[Linux-mips-commits]CVS: linux/arch/mips/kernel time.c,1.10,1.11

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv30291

Modified Files:
	time.c 
Log Message:
Months in struct tm are counted from 0-11, in the DS1386 from 1-12.

Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/time.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- time.c	2001/10/15 22:57:28	1.10
+++ time.c	2001/11/12 18:15:24	1.11
@@ -496,7 +496,7 @@
 	for (i = 1; day >= days_in_month(i); i++)
 	day -= days_in_month(i);
 	days_in_month(FEBRUARY) = 28;
-	tm->tm_mon = i;
+	tm->tm_mon = i-1;	/* tm_mon starts from 0 to 11 */
 
 	/* Days are what is left over (+1) from all that. */
 	tm->tm_mday = day + 1;

[Linux-mips-commits]CVS: linux/arch/mips/ddb5xxx/common rtc_ds1386.c,1.4,1.5

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/common
In directory usw-pr-cvs1:/tmp/cvs-serv30004

Modified Files:
	rtc_ds1386.c 
Log Message:
Months in struct tm are counted from 0-11, in the DS1386 from 1-12.

Index: rtc_ds1386.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/common/rtc_ds1386.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- rtc_ds1386.c	2001/10/11 20:45:25	1.4
+++ rtc_ds1386.c	2001/11/12 18:14:34	1.5
@@ -101,7 +101,7 @@
 	}
 
 	temp = READ_RTC(0x9);
-	month = BIN_TO_BCD(tm.tm_mon);
+	month = BIN_TO_BCD(tm.tm_mon+1);	/* tm_mon starts from 0 to 11 */
 	if (month != (temp & 0x1f)) {
 		WRITE_RTC( 0x9,
 			   (month & 0x1f) | (temp & ~0x1f) );

[Linux-mips-commits]CVS: linux/arch/mips/kernel i8259.c,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv27097

Added Files:
	i8259.c 
Log Message:
Fix endianess bug.

[Linux-mips-commits]CVS: linux/include/asm-mips reg.h,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv26340

Added Files:
	reg.h 
Log Message:
Correct value of EF_CP0_CAUSE.

--- NEW FILE: reg.h ---
/*
 * Various register offset definitions for debuggers, core file
 * examiners and whatnot.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1995, 1999 by Ralf Baechle
 */
#ifndef __ASM_MIPS_REG_H
#define __ASM_MIPS_REG_H

/*
 * This defines/structures correspond to the register layout on stack -
 * if the order here is changed, it needs to be updated in
 * include/asm-mips/stackframe.h
 */
#define EF_REG0			6
#define EF_REG1			7
#define EF_REG2			8
#define EF_REG3			9
#define EF_REG4			10
#define EF_REG5			11
#define EF_REG6			12
#define EF_REG7			13
#define EF_REG8			14
#define EF_REG9			15
#define EF_REG10		16
#define EF_REG11		17
#define EF_REG12		18
#define EF_REG13		19
#define EF_REG14		20
#define EF_REG15		21
#define EF_REG16		22
#define EF_REG17		23
#define EF_REG18		24
#define EF_REG19		25
#define EF_REG20		26
#define EF_REG21		27
#define EF_REG22		28
#define EF_REG23		29
#define EF_REG24		30
#define EF_REG25		31
/*
 * k0/k1 unsaved
 */
#define EF_REG28		34
#define EF_REG29		35
#define EF_REG30		36
#define EF_REG31		37

/*
 * Saved special registers
 */
#define EF_LO			38
#define EF_HI			39

#define EF_CP0_EPC		40
#define EF_CP0_BADVADDR		41
#define EF_CP0_STATUS		42
#define EF_CP0_CAUSE		43

#define EF_SIZE			180	/* size in bytes */

#endif /* __ASM_MIPS_REG_H */

[Linux-mips-commits]CVS: linux/drivers/char tty_io.c,1.7,1.8

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv25269

Added Files:
	tty_io.c 
Log Message:
Adding txx927 serial support.

[Linux-mips-commits]CVS: linux/arch/mips/lib dump_tlb.c,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/lib
In directory usw-pr-cvs1:/tmp/cvs-serv23977

Added Files:
	dump_tlb.c 
Log Message:
Added swarm support.

--- NEW FILE: dump_tlb.c ---
/*
 * Dump R4x00 TLB for debugging purposes.
 *
 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
 * Copyright (C) 1999 by Silicon Graphics, Inc.
 */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/string.h>

#include <asm/bootinfo.h>
#include <asm/cachectl.h>
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>

#define mips_tlb_entries 48

void
dump_tlb(int first, int last)
{
	int	i;
	unsigned int pagemask, c0, c1, asid;
	unsigned long entryhi, entrylo0, entrylo1;

	asid = get_entryhi() & 0xff;

	for(i=first;i<=last;i++)
	{
		write_32bit_cp0_register(CP0_INDEX, i);
		__asm__ __volatile__(
			".set\tmips3\n\t"
			".set\tnoreorder\n\t"
			"nop;nop;nop;nop\n\t"
			"tlbr\n\t"
			"nop;nop;nop;nop\n\t"
			".set\treorder\n\t"
			".set\tmips0\n\t");
		pagemask = read_32bit_cp0_register(CP0_PAGEMASK);
		entryhi  = read_32bit_cp0_register(CP0_ENTRYHI);
		entrylo0 = read_32bit_cp0_register(CP0_ENTRYLO0);
		entrylo1 = read_32bit_cp0_register(CP0_ENTRYLO1);

		/* Unused entries have a virtual address of KSEG0.  */
		if ((entryhi & 0xffffe000) != 0x80000000
		    && (entryhi & 0xff) == asid) {
			/*
			 * Only print entries in use
			 */
			printk("Index: %2d pgmask=%08x ", i, pagemask);

			c0 = (entrylo0 >> 3) & 7;
			c1 = (entrylo1 >> 3) & 7;

			printk("va=%08lx asid=%08lx"
			       "  [pa=%06lx c=%d d=%d v=%d g=%ld]"
			       "  [pa=%06lx c=%d d=%d v=%d g=%ld]",
			       (entryhi & 0xffffe000),
			       entryhi & 0xff,
			       entrylo0 & PAGE_MASK, c0,
			       (entrylo0 & 4) ? 1 : 0,
			       (entrylo0 & 2) ? 1 : 0,
			       (entrylo0 & 1),
			       entrylo1 & PAGE_MASK, c1,
			       (entrylo1 & 4) ? 1 : 0,
			       (entrylo1 & 2) ? 1 : 0,
			       (entrylo1 & 1));
			       
		}
	}
	printk("\n");

	set_entryhi(asid);
}

void
dump_tlb_all(void)
{
	dump_tlb(0, mips_tlb_entries - 1);
}

void
dump_tlb_wired(void)
{
	int	wired;

	wired = read_32bit_cp0_register(CP0_WIRED);
	printk("Wired: %d", wired);
	dump_tlb(0, read_32bit_cp0_register(CP0_WIRED));
}

#define BARRIER						\
	__asm__ __volatile__(				\
		".set\tnoreorder\n\t"			\
		"nop;nop;nop;nop;nop;nop;nop\n\t"	\
		".set\treorder");

void
dump_tlb_addr(unsigned long addr)
{
	unsigned int flags, oldpid;
	int index;

	__save_and_cli(flags);
	oldpid = get_entryhi() & 0xff;
	BARRIER;
	set_entryhi((addr & PAGE_MASK) | oldpid);
	BARRIER;
	tlb_probe();
	BARRIER;
	index = get_index();
	set_entryhi(oldpid);
	__restore_flags(flags);

	if (index < 0) {
		printk("No entry for address 0x%08lx in TLB\n", addr);
		return;
	}

	printk("Entry %d maps address 0x%08lx\n", index, addr);
	dump_tlb(index, index);
}

void
dump_tlb_nonwired(void)
{
	dump_tlb(read_32bit_cp0_register(CP0_WIRED), mips_tlb_entries - 1);
}

void
dump_list_process(struct task_struct *t, void *address)
{
	pgd_t	*page_dir, *pgd;
	pmd_t	*pmd;
	pte_t	*pte, page;
	unsigned int addr;
	unsigned long val;

	addr = (unsigned int) address;

	printk("Addr                 == %08x\n", addr);
	printk("tasks->mm.pgd        == %08x\n", (unsigned int) t->mm->pgd);

	page_dir = pgd_offset(t->mm, 0);
	printk("page_dir == %08x\n", (unsigned int) page_dir);

	pgd = pgd_offset(t->mm, addr);
	printk("pgd == %08x, ", (unsigned int) pgd);

	pmd = pmd_offset(pgd, addr);
	printk("pmd == %08x, ", (unsigned int) pmd);

	pte = pte_offset(pmd, addr);
	printk("pte == %08x, ", (unsigned int) pte);

	page = *pte;
	printk("page == %08x\n", (unsigned int) pte_val(page));

	val = pte_val(page);
	if (val & _PAGE_PRESENT) printk("present ");
	if (val & _PAGE_READ) printk("read ");
	if (val & _PAGE_WRITE) printk("write ");
	if (val & _PAGE_ACCESSED) printk("accessed ");
	if (val & _PAGE_MODIFIED) printk("modified ");
	if (val & _PAGE_R4KBUG) printk("r4kbug ");
	if (val & _PAGE_GLOBAL) printk("global ");
	if (val & _PAGE_VALID) printk("valid ");
	printk("\n");
}

void
dump_list_current(void *address)
{
	dump_list_process(current, address);
}

unsigned int
vtop(void *address)
{
	pgd_t	*pgd;
	pmd_t	*pmd;
	pte_t	*pte;
	unsigned int addr, paddr;

	addr = (unsigned long) address;
	pgd = pgd_offset(current->mm, addr);
	pmd = pmd_offset(pgd, addr);
	pte = pte_offset(pmd, addr);
	paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
	paddr |= (addr & ~PAGE_MASK);

	return paddr;
}

void
dump16(unsigned long *p)
{
	int i;

	for(i=0;i<8;i++)
	{
		printk("*%08lx == %08lx, ",
		       (unsigned long)p, (unsigned long)*p++);
		printk("*%08lx == %08lx\n",
		       (unsigned long)p, (unsigned long)*p++);
	}
}

[Linux-mips-commits]CVS: linux/drivers/char au1000_gpio.c,1.4,1.5

[Pete P. <pp...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv13556/drivers/char

Modified Files:
	au1000_gpio.c 
Log Message:
Include file is in a different directory.


Index: au1000_gpio.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/au1000_gpio.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- au1000_gpio.c	2001/11/06 20:23:55	1.4
+++ au1000_gpio.c	2001/11/12 17:26:03	1.5
@@ -39,7 +39,7 @@
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/au1000.h>
-#include <asm/au1000_gpio.h>
+#include <linux/au1000_gpio.h>
 
 #define VERSION "0.01"
 

[Linux-mips-commits]CVS: linux/drivers/net gt96100eth.c,1.4,1.5 gt96100eth.h,1.4,1.5

[Pete P. <pp...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv12683/drivers/net

Added Files:
	gt96100eth.c gt96100eth.h 
Log Message:
Added EV96100A support.

Differences between EV96100A and EV96100:

* boot code does not enable gt pci master (ev96100A)
* interrupt lines are routed differently
* gt96100eth ethernet driver required modifications to make it work with
both system controllers.

[Linux-mips-commits]CVS: linux/arch/mips/galileo-boards/ev96100 irq.c,1.5,1.6 pci_fixups.c,1.3,1.4 pci_ops.c,1.1,1.2 setup.c,1.3,1.4

[Pete P. <pp...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100
In directory usw-pr-cvs1:/tmp/cvs-serv12683/arch/mips/galileo-boards/ev96100

Modified Files:
	irq.c pci_fixups.c pci_ops.c setup.c 
Log Message:
Added EV96100A support.

Differences between EV96100A and EV96100:

* boot code does not enable gt pci master (ev96100A)
* interrupt lines are routed differently
* gt96100eth ethernet driver required modifications to make it work with
both system controllers.



Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100/irq.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- irq.c	2001/08/25 02:19:27	1.5
+++ irq.c	2001/11/11 00:24:38	1.6
@@ -56,8 +56,6 @@
 
 #ifdef CONFIG_REMOTE_DEBUG
 extern void breakpoint(void);
-extern int ev96100_remote_debug;
-extern int ev96100_remote_debug_line;
 #endif
 
 extern void puts(unsigned char *cp);
@@ -320,11 +318,9 @@
 
 #ifdef CONFIG_REMOTE_DEBUG
 	/* If local serial I/O used for debug port, enter kgdb at once */
-	if (ev96100_remote_debug) {
-		puts("Waiting for kgdb to connect...");
-		set_debug_traps();
-		breakpoint(); 
-	}
+	puts("Waiting for kgdb to connect...");
+	set_debug_traps();
+	breakpoint(); 
 #endif
 }
 

Index: pci_fixups.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100/pci_fixups.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci_fixups.c	2001/09/07 18:43:41	1.3
+++ pci_fixups.c	2001/11/11 00:24:38	1.4
@@ -35,76 +35,67 @@
 #include <linux/pci.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/pci_ids.h>
 
 #include <asm/gt64120.h>
 #include <asm/galileo-boards/ev96100.h>
 
+extern unsigned short get_gt_devid(void);
+
 void __init pcibios_fixup_resources(struct pci_dev *dev)
 {
 }
 
 void __init pcibios_fixup(void)
 {
-	/* 
-	 * Due to a bug in the Galileo system controller, we need to setup 
-	 * the PCI BAR for the Galileo internal registers.
-	 * This should be done in the bios/bootprom and will be fixed in
-	 * a later revision of YAMON (the MIPS boards boot prom).
-	 */
-	GT_WRITE(GT_PCI0_CFGADDR_OFS, cpu_to_le32(
-		 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF)   |  /* Local bus */
-		 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF)   |  /* GT64120 device */
-		 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |  /* Function 0 */
-		 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) |  /* BAR 4 */
-		 GT_PCI0_CFGADDR_CONFIGEN_BIT ));
-
-	/* Perform the write */
-	GT_WRITE( GT_PCI0_CFGDATA_OFS, cpu_to_le32(PHYSADDR(MIPS_GT_BASE))); 
 }
 
 void __init pcibios_fixup_irqs(void)
 {
 	struct pci_dev *dev;
 	unsigned int slot;
-	unsigned char irq;
-	unsigned long vendor;
+	u32 vendor;
+	unsigned short gt_devid = get_gt_devid();
 
 	/*
-	** EV96100 interrupt routing for pci bus 0
-	** NOTE: this are my experimental findings, since I do not
-	** have Galileo's latest PLD equations.
-	**
-	** The functions in irq.c assume the following irq numbering:
-	** irq 2: CPU cause register bit IP2
-	** irq 3: CPU cause register bit IP3
-	** irq 4: CPU cause register bit IP4
-	** irq 5: CPU cause register bit IP5
-	** irq 6: CPU cause register bit IP6
-	** irq 7: CPU cause register bit IP7
+	** EV96100/A interrupt routing for pci bus 0
 	**
+	** Note: EV96100A board with irq jumper set on 'linux'
 	*/
 
-
 	pci_for_each_dev(dev) {
 		if (dev->bus->number != 0)
 			return;
 
 		slot = PCI_SLOT(dev->devfn);
-		pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
+		pci_read_config_dword(dev, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
 
 //#ifdef DEBUG
-		printk("devfn %x, slot %d vendor %x\n", dev->devfn, slot, vendor);
+		printk("devfn %x, slot %d devid %x\n", 
+				dev->devfn, slot, gt_devid);
 //#endif
 
 		/* fixup irq line based on slot # */
 
 		if (slot == 8) {
-		    dev->irq = 5;
-		    pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+			if (gt_devid == PCI_DEVICE_ID_GALILEO_GT96100) 
+				dev->irq = 5;
+			else if (gt_devid == PCI_DEVICE_ID_GALILEO_GT96100A)
+				dev->irq = 3;
+			else {
+				printk(KERN_ERR "unknown GT controller id %x\n",
+						gt_devid);
+				pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 
+						0xff);
+				continue;
+			}
+			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 
+					dev->irq);
 		}
 		else if (slot == 9) {
-		    dev->irq = 2;
-		    pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+			dev->irq = 2;
+			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 
+					dev->irq);
 		}
 	}
 }

Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100/pci_ops.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- pci_ops.c	2001/07/06 01:25:33	1.1
+++ pci_ops.c	2001/11/11 00:24:38	1.2
@@ -42,6 +42,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
+#include <asm/delay.h>
 #include <asm//gt64120.h>
 #include <asm/galileo-boards/ev96100.h>
 #include <asm/pci_channel.h>
@@ -80,8 +81,8 @@
 	{ NULL, NULL, NULL, NULL, NULL}
 };
 
-static int
-gt96100_config_access(unsigned char access_type, struct pci_dev *dev,
+int
+static gt96100_config_access(unsigned char access_type, struct pci_dev *dev,
                            unsigned char where, u32 *data)
 {
 	unsigned char bus = dev->bus->number;
@@ -103,21 +104,24 @@
 		 (dev_fn      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
 		 ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
 		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+	udelay(2);
 
 
 	if (access_type == PCI_ACCESS_WRITE) {
-            if (dev_fn != 0) {
-                *data = le32_to_cpu(*data);
-            }
-            GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
+		if (dev_fn != 0) {
+		*data = le32_to_cpu(*data);
+		}
+		GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
 	} 
         else {
-            GT_READ(GT_PCI0_CFGDATA_OFS, *data);
-            if (dev_fn != 0) {
-                *data = le32_to_cpu(*data);
-            }
+		GT_READ(GT_PCI0_CFGDATA_OFS, *data);
+		if (dev_fn != 0) {
+		*data = le32_to_cpu(*data);
+		}
 	}
 
+	udelay(2);
+
 	/* Check for master or target abort */
 	GT_READ(GT_INTRCAUSE_OFS, intr);
 
@@ -266,31 +270,5 @@
 	write_config_word,
 	write_config_dword
 };
-
-#if 0
-void __init pcibios_init(void)
-{
-
-	DBG("PCI: Probing PCI hardware on host bus 0.\n");
-	pci_scan_bus(0, &mips_pci_ops, NULL);
-
-	/* 
-	 * Due to a bug in the Galileo system controller, we need to setup 
-	 * the PCI BAR for the Galileo internal registers.
-	 * This should be done in the bios/bootprom and will be fixed in
-	 * a later revision of YAMON (the MIPS boards boot prom).
-	 */
-	GT_WRITE(GT_PCI0_CFGADDR_OFS, cpu_to_le32(
-		 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF)   |  /* Local bus */
-		 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF)   |  /* GT64120 device */
-		 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |  /* Function 0 */
-		 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) |  /* BAR 4 */
-		 GT_PCI0_CFGADDR_CONFIGEN_BIT ));
-
-	/* Perform the write */
-	GT_WRITE( GT_PCI0_CFGDATA_OFS, cpu_to_le32(PHYSADDR(MIPS_GT_BASE))); 
-
-}
-#endif
 
 #endif /* CONFIG_PCI */

Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c	2001/08/25 02:19:27	1.3
+++ setup.c	2001/11/11 00:24:38	1.4
@@ -40,11 +40,13 @@
 #include <linux/mc146818rtc.h>
 #include <linux/string.h>
 #include <linux/ctype.h>
+#include <linux/pci.h>
 
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
 #include <asm/mipsregs.h>
 #include <asm/irq.h>
+#include <asm/delay.h>
 #include <asm/gt64120.h>
 #include <asm/galileo-boards/ev96100.h>
 #include <asm/galileo-boards/ev96100int.h>
@@ -57,14 +59,6 @@
 char serial_console[20];
 #endif
 
-#ifdef CONFIG_REMOTE_DEBUG
-extern void breakpoint(void);
-int ev96100_remote_debug;
-int ev96100_remote_debug_line;
-#endif
-
-void (*board_time_init)(struct irqaction *irq);
-extern void ev96100_time_init(struct irqaction *irq);
 extern char * __init prom_getcmdline(void);
 
 extern void mips_reboot_setup(void);
@@ -78,12 +72,13 @@
 
 unsigned char mac_0_1[12];
 
+
 void __init ev96100_setup(void)
 {
-
 	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
 	unsigned long status = read_32bit_cp0_register(CP0_STATUS);
 	unsigned long info = read_32bit_cp0_register(CP0_INFO);
+	u32 tmp;
 
 	char *argptr;
 
@@ -151,25 +146,6 @@
 	}
 #endif	  
 
-
-#ifdef CONFIG_REMOTE_DEBUG
-	if (strstr(argptr, "kgdb=ttyS") != NULL) {
-		int line;
-		argptr += strlen("kgdb=ttyS");
-		if (*argptr == '0')
-			ev96100_remote_debug_line = 0;
-		else if (*argptr == '1')
-			ev96100_remote_debug_line = 1;
-		else
-			puts("Unknown serial line /dev/ttyS%c\n", *argptr);
-
-		debugInitUart(ev96100_remote_debug_line);
-		ev96100_remote_debug = 1;
-		/* Breakpoints and stuff are in init_IRQ() */
-	}
-#endif
-
-	board_time_init = ev96100_time_init;
 	rtc_ops = &no_rtc_ops;
 	mips_reboot_setup();
 	mips_io_port_base = KSEG1;
@@ -179,4 +155,59 @@
 #ifdef CONFIG_BLK_DEV_INITRD
 	ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
 #endif
+
+
+	/* 
+	 * setup gt controller master bit so we can do config cycles 
+	 */
+
+	/* Clear cause register bits */
+	GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | 
+	                             GT_INTRCAUSE_TARABORT0_BIT));
+	/* Setup address */
+	GT_WRITE(GT_PCI0_CFGADDR_OFS,  
+		 (0      << GT_PCI0_CFGADDR_BUSNUM_SHF)   |
+		 (0      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
+		 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
+		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+
+	udelay(2);
+	tmp = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS));
+
+	tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 
+		PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+	GT_WRITE(GT_PCI0_CFGADDR_OFS,  
+		 (0      << GT_PCI0_CFGADDR_BUSNUM_SHF)   |
+		 (0      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
+		 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
+		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+	udelay(2);
+	*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS) = cpu_to_le32(tmp);
+
+	/* Setup address */
+	GT_WRITE(GT_PCI0_CFGADDR_OFS,  
+		 (0      << GT_PCI0_CFGADDR_BUSNUM_SHF)   |
+		 (0      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
+		 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
+		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+
+	udelay(2);
+	tmp = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS));
+}
+
+unsigned short get_gt_devid() 
+{
+	u32 gt_devid;
+
+	/* Figure out if this is a gt96100 or gt96100A */
+	GT_WRITE(GT_PCI0_CFGADDR_OFS,  
+		 (0      << GT_PCI0_CFGADDR_BUSNUM_SHF)   |
+		 (0      << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
+		 ((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
+		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
+
+	udelay(4);
+	gt_devid = le32_to_cpu(*(volatile u32 *)
+			(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS));
+	return (unsigned short)(gt_devid>>16);
 }

[Linux-mips-commits]CVS: linux/arch/mips/mm tlb-r4k.c,1.2,1.3

[Pete P. <pp...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv644/arch/mips/mm

Modified Files:
	tlb-r4k.c 
Log Message:
Quick rm7k bug fix. The rm7k config register uses bit 31 to report
secondary cache. Thus, the cpu is mistaken as a mips32 CPU.


Index: tlb-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r4k.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- tlb-r4k.c	2001/10/23 23:51:03	1.2
+++ tlb-r4k.c	2001/11/11 00:10:32	1.3
@@ -337,6 +337,10 @@
 {
 	unsigned long config1;
 
+#ifdef CONFIG_CPU_RM7000
+	return;
+#endif
+
 	if (!(config & (1 << 31)))
 	        /* 
 		 * Not a MIPS32 complianant CPU.  Config 1 register not

[Linux-mips-commits]CVS: linux/arch/mips/mm c-r5900.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv15514

Added Files:
	c-r5900.c 
Log Message:
Add proper r5900 cache management routines..



--- NEW FILE: c-r5900.c ---
/* $Id: c-r5900.c,v 1.1 2001/11/10 21:23:45 lethal Exp $
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * r5900.c: R5900 processor specific MMU/Cache routines.
 *
 * Copyright (C) 2000 Sony Computer Entertainment Inc.
 * Copyright (C) 2001 Paul Mundt (le...@ch...)
 *
 * This file is based on r4xx0.c:
 *
 * Copyright (C) 1996 David S. Miller (dm...@en...)
 * Copyright (C) 1997, 1998 Ralf Baechle ra...@gn...
 *
 * To do:
 *
 *  - this code is a overbloated pig
 *  - many of the bug workarounds are not efficient at all, but at
 *    least they are functional ...
 */
#include <linux/autoconf.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/bcache.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>

/* CP0 hazard avoidance. */
#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
				     ".word 0x0000040f;\n\t" \
				     ".set reorder\n\t")

/* Primary cache parameters. */
static int icache_size, dcache_size; /* Size in bytes */
static int ic_lsize, dc_lsize;       /* LineSize in bytes */

#include <asm/r5900_cacheops.h>
#include <asm/r5900_cache.h>

#undef DEBUG_CACHE

static inline void r5900_flush_cache_all_d64i64(void)
{
	unsigned long flags;

	save_and_cli(flags);
	blast_dcache64(); blast_icache64();
	restore_flags(flags);
}

static void r5900_flush_cache_range_d64i64(struct mm_struct *mm,
					 unsigned long start,
					 unsigned long end)
{
	if(mm->context != 0) {
		unsigned long flags;

#ifdef DEBUG_CACHE
		printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
#endif
		save_and_cli(flags);
		blast_dcache64(); blast_icache64();
		restore_flags(flags);
	}
}

static void r5900_flush_icache_range_i64(unsigned long start,
					    unsigned long end)
{
	unsigned long flags;

#ifdef DEBUG_CACHE
	printk("irange[%08lx,%08lx]", start, end);
#endif
	save_and_cli(flags);
	blast_icache64();
	restore_flags(flags);
}


static void r5900_flush_cache_mm_d64i64(struct mm_struct *mm)
{
	if(mm->context != 0) {
#ifdef DEBUG_CACHE
		printk("cmm[%d]", (int)mm->context);
#endif
		r5900_flush_cache_all_d64i64();
	}
}

static void r5900_flush_cache_page_d64i64(struct vm_area_struct *vma,
					unsigned long page)
{
	struct mm_struct *mm = vma->vm_mm;
	unsigned long flags;
	pgd_t *pgdp;
	pmd_t *pmdp;
	pte_t *ptep;
	int text;

	/*
	 * If ownes no valid ASID yet, cannot possibly have gotten
	 * this page into the cache.
	 */
	if(mm->context == 0)
		return;

#ifdef DEBUG_CACHE
	printk("cpage[%d,%08lx]", (int)mm->context, page);
#endif
	save_and_cli(flags);
	page &= PAGE_MASK;
	pgdp = pgd_offset(mm, page);
	pmdp = pmd_offset(pgdp, page);
	ptep = pte_offset(pmdp, page);

	/* If the page isn't marked valid, the page cannot possibly be
	 * in the cache.
	 */
	if(!(pte_val(*ptep) & _PAGE_VALID))
		goto out;

	text = (vma->vm_flags & VM_EXEC);
	/*
	 * Doing flushes for another ASID than the current one is
	 * too difficult since stupid R4k caches do a TLB translation
	 * for every cache flush operation.  So we do indexed flushes
	 * in that case, which doesn't overly flush the cache too much.
	 */
	if(mm == current->mm) {
		blast_dcache64_page(page);
		if(text)
			blast_icache64_page(page);
	} else {
		/* Do indexed flush, too much work to get the (possible)
		 * tlb refills to work correctly.
		 */
		page = (KSEG0 + (page & (dcache_size - 1)));
		blast_dcache64_page_indexed(page);
		if(text)
			blast_icache64_page_indexed(page);
	}
out:
	restore_flags(flags);
}

static void r5900_flush_icache_page_i64(struct vm_area_struct *vma,
					struct page * page)
{
	if (!(vma->vm_flags & VM_EXEC))
		return;

	flush_cache_all();
}

static void r5900_flush_page_to_ram_d64i64(struct page * page)
{
	unsigned long addr = (unsigned long) page_address(page) & PAGE_MASK;
	if((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
		unsigned long flags;

#ifdef DEBUG_CACHE
		printk("cram[%08lx]", addr);
#endif
		save_and_cli(flags);
		blast_dcache64_page(addr);
		restore_flags(flags);
	}
}

/*
 * Writeback and invalidate the primary cache dcache before DMA.
 */
static void
r5900_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size)
{
	if (size >= dcache_size)
		flush_cache_all();

	bc_wback_inv(addr, size);
}

static void
r5900_dma_cache_inv_pc(unsigned long addr, unsigned long size)
{
	if (size >= dcache_size)
		flush_cache_all();

	bc_inv(addr, size);
}

/*
 * While we're protected against bad userland addresses we don't care
 * very much about what happens in that case.  Usually a segmentation
 * fault will dump the process later on anyway ...
 */
static void r5900_flush_cache_sigtramp(unsigned long addr)
{
	/*
	 * FIXME: What's the point of daddr and iaddr? I don't see any need
	 * for doing the flush on both the addresses _and_ the addresses + the
	 * line size. Am I missing something?
	 */
	unsigned long daddr, iaddr;

	daddr = addr & ~(dc_lsize - 1);

	protected_writeback_dcache_line(daddr);
	protected_writeback_dcache_line(daddr + dc_lsize);
	iaddr = addr & ~(ic_lsize - 1);
	protected_flush_icache_line(iaddr);
	protected_flush_icache_line(iaddr + ic_lsize);
}

static void r5900_update_mmu_cache(struct vm_area_struct * vma,
				   unsigned long address, pte_t pte)
{
	unsigned long flags;
	pgd_t *pgdp;
	pmd_t *pmdp;
	pte_t *ptep;
	int idx, pid;

	pid = (get_entryhi() & 0xff);

#ifdef DEBUG_TLB
	if((pid != (vma->vm_mm->context & 0xff)) || (vma->vm_mm->context == 0)) {
		printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n",
		       (int) (vma->vm_mm->context & 0xff), pid);
	}
#endif

	save_and_cli(flags);
	address &= (PAGE_MASK << 1);
	set_entryhi(address | (pid));
	pgdp = pgd_offset(vma->vm_mm, address);
	BARRIER;
	tlb_probe();
	BARRIER;
	pmdp = pmd_offset(pgdp, address);
	idx = get_index();
	ptep = pte_offset(pmdp, address);
	BARRIER;
	if ((signed long)pte_val(*ptep) < 0) {
	    /* scratchpad RAM mapping */
	    address &= (PAGE_MASK << 2);	/* must be 16KB aligned */
	    set_entryhi(address | (pid));
	    BARRIER;
	    tlb_probe();
	    BARRIER;
	    idx = get_index();
	    BARRIER;
	    set_entrylo0(0x80000006);	/* S, D, V */
	    set_entrylo1(0x00000006);	/*    D, V */
	    set_entryhi(address | (pid));
	} else {
	    set_entrylo0(pte_val(*ptep++) >> 6);
	    set_entrylo1(pte_val(*ptep) >> 6);
	    set_entryhi(address | (pid));
	}
	BARRIER;
	if(idx < 0) {
		tlb_write_random();
	} else {
		tlb_write_indexed();
	}
	BARRIER;
	set_entryhi(pid);
	BARRIER;
	restore_flags(flags);
}

/* Detect and size the various r4k caches. */
static void __init probe_icache(unsigned long config)
{
	icache_size = 1 << (12 + ((config >> 9) & 7));
	ic_lsize = 64;	/* fixed */

	printk("Primary instruction cache %dkb, linesize %d bytes\n",
	       icache_size >> 10, 64);
}

static void __init probe_dcache(unsigned long config)
{
	dcache_size = 1 << (12 + ((config >> 6) & 7));
	dc_lsize = 64;	/* fixed */

	printk("Primary data cache %dkb, linesize %d bytes\n",
	       dcache_size >> 10, 64);
}

static void __init setup_noscache_funcs(void)
{
	_clear_page = r5900_clear_page_d16;
	_copy_page = r5900_copy_page_d16;
	_flush_cache_all = r5900_flush_cache_all_d64i64;
	_flush_cache_mm = r5900_flush_cache_mm_d64i64;
	_flush_cache_range = r5900_flush_cache_range_d64i64;
	_flush_cache_page = r5900_flush_cache_page_d64i64;

	___flush_cache_all = _flush_cache_all;
	_flush_icache_range = r5900_flush_icache_range_i64;
	_flush_icache_page = r5900_flush_icache_page_i64; /* FIXME */

	_flush_page_to_ram = r5900_flush_page_to_ram_d64i64;
	_dma_cache_wback_inv = r5900_dma_cache_wback_inv_pc;
	_dma_cache_inv = r5900_dma_cache_inv_pc;
}

static inline void setup_scache(unsigned int config)
{
	setup_noscache_funcs();
}

void __init ld_mmu_r5900(void)
{
	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);

	printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID));

	/*
	 * Display CP0 config reg. to verify the workaround 
	 * for branch prediction bug is done, or not.
	 * R5900 has a problem of branch prediction.
	 */
	printk("  Branch Prediction  : %s\n",  
		(config & CONF_R5900_BPE)? "on":"off");
	printk("  Double Issue       : %s\n",  
		(config & CONF_R5900_DIE)? "on":"off");

	clear_cp0_config(CONF_CM_CMASK);
	set_cp0_config(CONF_CM_CACHABLE_NONCOHERENT);

	probe_icache(config);
	probe_dcache(config);
	setup_scache(config);

	_flush_cache_sigtramp = r5900_flush_cache_sigtramp;
	update_mmu_cache = r5900_update_mmu_cache;

	flush_cache_all();
	write_32bit_cp0_register(CP0_WIRED, 0);

	/*
	 * You should never change this register:
	 *   - On R4600 1.7 the tlbp never hits for pages smaller than
	 *     the value in the c0_pagemask register.
	 *   - The entire mm handling assumes the c0_pagemask register to
	 *     be set for 4kb pages.
	 */
	write_32bit_cp0_register(CP0_PAGEMASK, PM_4K);
	flush_tlb_all();
}

[Linux-mips-commits]CVS: linux/arch/mips/jmr3927/rbhma3100 Makefile,NONE,1.1 init.c,NONE,1.1 int-handler.S,NONE,1.1 irq.c,NONE,1.1 kgdb_io.c,NONE,1.1 pci_fixup.c,NONE,1.1 pci_ops.c,NONE,1.1 rtc.c,NONE,1.1 setup.c,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/jmr3927/rbhma3100
In directory usw-pr-cvs1:/tmp/cvs-serv22117/jmr3927/rbhma3100

Added Files:
	Makefile init.c int-handler.S irq.c kgdb_io.c pci_fixup.c 
	pci_ops.c rtc.c setup.c 
Log Message:
Imported support for JMR-TX3927 by Alice Hennessy. Thank you.

--- NEW FILE: Makefile ---
#
# Makefile for TOSHIBA JMR-TX3927 board
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

.S.s:
	$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
	$(CC) $(CFLAGS) -c $< -o $*.o

O_TARGET:= jmr3927.o

obj-y	 += init.o int-handler.o irq.o setup.o rtc.o pci_fixup.o pci_ops.o

obj-$(CONFIG_LL_DEBUG) 		+= debug.o
obj-$(CONFIG_REMOTE_DEBUG)	+= kgdb_io.o

include $(TOPDIR)/Rules.make

--- NEW FILE: init.c ---
/***********************************************************************
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahe...@mv...       
 *
 * arch/mips/jmr3927/common/init.c
 *
 * Copyright (C) 2000-2001 Toshiba Corporation 
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 ***********************************************************************
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>

#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <asm/jmr3927/jmr3927.h>

int prom_argc;
char **prom_argv, **prom_envp;
extern void  __init prom_init_cmdline(void);
extern char *prom_getenv(char *envname);
unsigned long mips_nofpu = 0;

extern void puts(unsigned char *cp);
int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
{
#ifdef CONFIG_TOSHIBA_JMR3927
	/* CCFG */
	if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
		puts("Warning: TX3927 TLB off\n");
#endif
	prom_argc = argc;
	prom_argv = argv;
	prom_envp = envp;     

	mips_machgroup = MACH_GROUP_TOSHIBA;

#ifdef CONFIG_TOSHIBA_JMR3927
	mips_machtype = MACH_TOSHIBA_JMR3927;
#endif

	prom_init_cmdline();
	add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
	return 0;
}

--- NEW FILE: int-handler.S ---
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahe...@mv...       
 *
 * Based on arch/mips/tsdb/kernel/int-handler.S
 *
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * $Id: int-handler.S,v 1.1 2001/11/10 03:56:05 jsimmons Exp $
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/jmr3927/jmr3927.h>

	/* A lot of complication here is taken away because:
	 *
	 * 1) We handle one interrupt and return, sitting in a loop
	 *    and moving across all the pending IRQ bits in the cause
	 *    register is _NOT_ the answer, the common case is one
	 *    pending IRQ so optimize in that direction.
	 *
	 * 2) We need not check against bits in the status register
	 *    IRQ mask, that would make this routine slow as hell.
	 *
	 * 3) Linux only thinks in terms of all IRQs on or all IRQs
	 *    off, nothing in between like BSD spl() brain-damage.
	 *
	 */

/* Flush write buffer (needed?)
 * NOTE: TX39xx performs "non-blocking load", so explicitly use the target
 * register of LBU to flush immediately.
 */
#define FLUSH_WB(tmp)	\
	la	tmp, JMR3927_IOC_REV_ADDR; \
	lbu	tmp, (tmp); \
	move	tmp, zero;

	.text
	.set	noreorder
	.set	noat
	.align	5
	NESTED(jmr3927_IRQ, PT_SIZE, sp)
	SAVE_ALL
	CLI
	.set	at
	jal	jmr3927_irc_irqdispatch
	 move	a0, sp
	FLUSH_WB(t0)
	j	ret_from_irq
	 nop
	END(jmr3927_IRQ)

--- NEW FILE: irq.c ---
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahe...@mv...       
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * $Id: irq.c,v 1.1 2001/11/10 03:56:05 jsimmons Exp $
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/config.h>
#include <linux/init.h>

#include <linux/errno.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/malloc.h>
#include <linux/random.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/irq.h>

#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>

#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/jmr3927/irq.h>
#include <asm/debug.h>
#include <asm/jmr3927/jmr3927.h>

#if JMR3927_IRQ_END > NR_IRQS
#error JMR3927_IRQ_END > NR_IRQS
#endif

struct tb_irq_space* tb_irq_spaces;

unsigned int local_bh_count[NR_CPUS];
unsigned int local_irq_count[NR_CPUS];

static int jmr3927_irq_base=-1;

#ifdef CONFIG_PCI
static int jmr3927_gen_iack(void)
{
	/* generate ACK cycle */
#ifdef __BIG_ENDIAN
	return (tx3927_pcicptr->iiadp >> 24) & 0xff;
#else
	return tx3927_pcicptr->iiadp & 0xff;
#endif
}
#endif

extern asmlinkage void jmr3927_IRQ(void);

#define irc_dlevel	0
#define irc_elevel	1
static unsigned char irc_level[TX3927_NUM_IR] = {
	5, 5, 5, 5, 5, 5,	/* INT[5:0] */
	7, 7,			/* SIO */
	5, 5, 5, 0, 0,		/* DMA, PIO, PCI */
	6, 6, 6			/* TMR */
};

static inline void mask_irq(unsigned int irq_nr)
{
	struct tb_irq_space* sp;
	for (sp = tb_irq_spaces; sp; sp = sp->next) {
		if (sp->start_irqno <= irq_nr &&
		    irq_nr < sp->start_irqno + sp->nr_irqs) {
			if (sp->mask_func)
				sp->mask_func(irq_nr - sp->start_irqno,
					      sp->space_id);
			break;
		}
	}
}

static inline void unmask_irq(unsigned int irq_nr)
{
	struct tb_irq_space* sp;
	for (sp = tb_irq_spaces; sp; sp = sp->next) {
		if (sp->start_irqno <= irq_nr &&
		    irq_nr < sp->start_irqno + sp->nr_irqs) {
			if (sp->unmask_func)
				sp->unmask_func(irq_nr - sp->start_irqno,
						sp->space_id);
			break;
		}
	}
}

static void jmr3927_irq_disable(unsigned int irq_nr);
static void jmr3927_irq_enable(unsigned int irq_nr);

static unsigned int jmr3927_irq_startup(unsigned int irq)
{
	jmr3927_irq_enable(irq);
	return 0;
}

#define	jmr3927_irq_shutdown	jmr3927_irq_disable

static void jmr3927_irq_ack(unsigned int irq)
{
	db_assert(jmr3927_irq_base != -1);
	db_assert(irq >= jmr3927_irq_base);
	db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);

	if (irq == JMR3927_IRQ_IRC_TMR0) {
		jmr3927_tmrptr->tisr = 0;       /* ack interrupt */  
	}

	jmr3927_irq_disable(irq);
}

static void jmr3927_irq_end(unsigned int irq)
{
	db_assert(jmr3927_irq_base != -1);
	db_assert(irq >= jmr3927_irq_base);
	db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);

	jmr3927_irq_enable(irq);
}

static void jmr3927_irq_disable(unsigned int irq_nr)
{
	unsigned long flags;

	db_assert(jmr3927_irq_base != -1);
	db_assert(irq >= jmr3927_irq_base);
	db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);

	save_and_cli(flags);
	mask_irq(irq_nr);
	restore_flags(flags);
}

static void jmr3927_irq_enable(unsigned int irq_nr)
{
	unsigned long flags;

	db_assert(jmr3927_irq_base != -1);
	db_assert(irq >= jmr3927_irq_base);
	db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);

	save_and_cli(flags);
	unmask_irq(irq_nr);
	restore_flags(flags);
}

/*
 * CP0_STATUS is a thread's resource (saved/restored on context switch).
 * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
 */
static void mask_irq_isac(int irq_nr, int space_id)
{
	/* 0: mask */
	unsigned char imask =
		jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
	unsigned int bit  = 1 << irq_nr;
	jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
	/* flush write buffer */
	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}
static void unmask_irq_isac(int irq_nr, int space_id)
{
	/* 0: mask */
	unsigned char imask =
		jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
	unsigned int bit  = 1 << irq_nr;
	jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
	/* flush write buffer */
	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}

static void mask_irq_ioc(int irq_nr, int space_id)
{
	/* 0: mask */
	unsigned char imask =
		jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	unsigned int bit = 1 << irq_nr;
	jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
	/* flush write buffer */
	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}
static void unmask_irq_ioc(int irq_nr, int space_id)
{
	/* 0: mask */
	unsigned char imask =
		jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	unsigned int bit = 1 << irq_nr;
	jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
	/* flush write buffer */
	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}

static void mask_irq_irc(int irq_nr, int space_id)
{
	volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
	if (irq_nr & 1)
		*ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
	else
		*ilrp = (*ilrp & 0xff00) | irc_dlevel;
	/* update IRCSR */
	tx3927_ircptr->imr = 0;
	tx3927_ircptr->imr = irc_elevel;
}
static void unmask_irq_irc(int irq_nr, int space_id)
{
	volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
	if (irq_nr & 1)
		*ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
	else
		*ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
	/* update IRCSR */
	tx3927_ircptr->imr = 0;
	tx3927_ircptr->imr = irc_elevel;
}

struct tb_irq_space jmr3927_isac_irqspace = {
	next: NULL,
	start_irqno: JMR3927_IRQ_ISAC,
	nr_irqs : JMR3927_NR_IRQ_ISAC,
	mask_func: mask_irq_isac,
	unmask_func: unmask_irq_isac,
	name: "ISAC",
	space_id: 0,
	can_share : 0
};
struct tb_irq_space jmr3927_ioc_irqspace = {
	next: NULL,
	start_irqno: JMR3927_IRQ_IOC,
	nr_irqs : JMR3927_NR_IRQ_IOC,
	mask_func: mask_irq_ioc,
	unmask_func: unmask_irq_ioc,
	name: "IOC",
	space_id: 0,
	can_share : 1
};
struct tb_irq_space jmr3927_irc_irqspace = {
	next: NULL,
	start_irqno: JMR3927_IRQ_IRC,
	nr_irqs : JMR3927_NR_IRQ_IRC,
	mask_func: mask_irq_irc,
	unmask_func: unmask_irq_irc,
	name: "on-chip",
	space_id: 0,
	can_share : 0
};

void jmr3927_spurious(struct pt_regs *regs)
{
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
	tx_branch_likely_bug_fixup(regs);
#endif
	printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
	       regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
}

extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
void jmr3927_irc_irqdispatch(struct pt_regs *regs)
{
	int irq;
	
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
	tx_branch_likely_bug_fixup(regs);
#endif
	if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
#if 0
		jmr3927_spurious(regs);
#endif
		return;
	}
	irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;

	do_IRQ(irq + JMR3927_IRQ_IRC, regs);
}

static void jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
	int i;

	for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
		if (istat & (1 << i)) {
			irq = JMR3927_IRQ_IOC + i;
			do_IRQ(irq, regs);
		}
	}
}

static struct irqaction ioc_action = {
	jmr3927_ioc_interrupt, 0, 0, "IOC", NULL, NULL,
};

static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
	int i;

	for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
		if (istat & (1 << i)) {
			irq = JMR3927_IRQ_ISAC + i;
			do_IRQ(irq, regs);
		}
	}
}

static struct irqaction isac_action = {
	jmr3927_isac_interrupt, 0, 0, "ISAC", NULL, NULL,
};


static void jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
{
	printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
}
static struct irqaction isaerr_action = {
	jmr3927_isaerr_interrupt, 0, 0, "ISA error", NULL, NULL,
};

static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
{
	printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
	printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
	       tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
}
static struct irqaction pcierr_action = {
	jmr3927_pcierr_interrupt, 0, 0, "PCI error", NULL, NULL,
};

int jmr3927_ether1_irq = 0;

void jmr3927_irq_init(u32 irq_base);
void jmr3927_irq_setup(void)
{
	/* look for io board's presence */
	int have_isac = jmr3927_have_isac();

	/* Now, interrupt control disabled, */
	/* all IRC interrupts are masked, */
	/* all IRC interrupt mode are Low Active. */

	if (have_isac) {

		/* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
		/* temporary enable interrupt control */
		tx3927_ircptr->cer = 1;
		/* ETHER1 Int. Is High-Active. */
		if (tx3927_ircptr->ssr & (1 << 0))
			jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
#if 0	/* INT3 may be asserted by ether0 (even after reboot...) */
		else if (tx3927_ircptr->ssr & (1 << 3))
			jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
#endif
		/* disable interrupt control */
		tx3927_ircptr->cer = 0;

		/* Ether1: High Active */
		if (jmr3927_ether1_irq) {
			int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
			tx3927_ircptr->cr[ether1_irc / 8] |=
				TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
		}
	}

	/* mask all IOC interrupts */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
	/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
	jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);

	if (have_isac) {
		/* mask all ISAC interrupts */
		jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
		/* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
		jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
	}

	/* clear PCI Soft interrupts */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
	/* clear PCI Reset interrupts */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);

	/* enable interrupt control */
	tx3927_ircptr->cer = TX3927_IRCER_ICE;
	tx3927_ircptr->imr = irc_elevel;

	jmr3927_irq_init(NR_ISA_IRQS);

	set_except_vector(0, jmr3927_IRQ);

	/* setup irq space */
	add_tb_irq_space(&jmr3927_isac_irqspace);
	add_tb_irq_space(&jmr3927_ioc_irqspace);
	add_tb_irq_space(&jmr3927_irc_irqspace);

	/* setup IOC interrupt 1 (PCI, MODEM) */
	setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);

	if (have_isac) {
		setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
		setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
	}

#ifdef CONFIG_PCI
	setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
#endif

	/* enable all CPU interrupt bits. */
	set_cp0_status(ST0_IM);	/* IE bit is still 0. */
}

void (*irq_setup)(void);
void __init init_IRQ(void)
{

#ifdef CONFIG_REMOTE_DEBUG
        extern void breakpoint(void);
        extern void set_debug_traps(void);

        puts("Wait for gdb client connection ...\n");
        set_debug_traps();
        breakpoint();
#endif

        /* invoke board-specific irq setup */
        irq_setup();
}

hw_irq_controller jmr3927_irq_controller = {
	"jmr3927_irq",
	jmr3927_irq_startup,
	jmr3927_irq_shutdown,
	jmr3927_irq_enable,
	jmr3927_irq_disable,
	jmr3927_irq_ack,
	jmr3927_irq_end,
	NULL			/* no affinity stuff for UP */
};

void 
jmr3927_irq_init(u32 irq_base)
{
	extern irq_desc_t irq_desc[];
	u32 i;

	for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		irq_desc[i].depth = 1;
		irq_desc[i].handler = &jmr3927_irq_controller;
	}
	
	jmr3927_irq_base = irq_base;
}

#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
static int tx_branch_likely_bug_count = 0;
static int have_tx_branch_likely_bug = 0;
void tx_branch_likely_bug_fixup(struct pt_regs *regs)
{
	/* TX39/49-BUG: Under this condition, the insn in delay slot
           of the branch likely insn is executed (not nullified) even
           the branch condition is false. */
	if (!have_tx_branch_likely_bug)
		return;
	if ((regs->cp0_epc & 0xfff) == 0xffc &&
	    KSEGX(regs->cp0_epc) != KSEG0 &&
	    KSEGX(regs->cp0_epc) != KSEG1) {
		unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
		/* beql,bnel,blezl,bgtzl */
		/* bltzl,bgezl,blezall,bgezall */
		/* bczfl, bcztl */
		if ((insn & 0xf0000000) == 0x50000000 ||
		    (insn & 0xfc0e0000) == 0x04020000 ||
		    (insn & 0xf3fe0000) == 0x41020000) {
			regs->cp0_epc -= 4;
			tx_branch_likely_bug_count++;
			printk(KERN_INFO
			       "fix branch-likery bug in %s (insn %08x)\n",
			       current->comm, insn);
		}
	}
}
#endif

--- NEW FILE: kgdb_io.c ---
/*
 * BRIEF MODULE DESCRIPTION
 *	Low level uart routines to directly access a TX[34]927 SIO.
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	ahe...@mv... or so...@mv...
 *
 * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c
 *
 * Copyright (C) 2000-2001 Toshiba Corporation 
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/types.h>
#include <asm/jmr3927/txx927.h>
#include <asm/jmr3927/tx3927.h>
#include <asm/jmr3927/jmr3927.h>

#define TIMEOUT       0xffffff
#define SLOW_DOWN

static const char digits[16] = "0123456789abcdef";

#ifdef SLOW_DOWN
#define slow_down() { int k; for (k=0; k<10000; k++); }
#else
#define slow_down()
#endif

static int remoteDebugInitialized = 0;

int putDebugChar(unsigned char c)
{
        int i = 0;
	
	if (!remoteDebugInitialized) {
		remoteDebugInitialized = 1;
		debugInit(38400);
	}

        do {
            slow_down();
            i++;
            if (i>TIMEOUT) {
                break;
            }
        } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS));
	tx3927_sioptr(0)->tfifo = c;

	return 1;
}

unsigned char getDebugChar(void)
{
        int i = 0;
	int dicr;
	char c;
	
	if (!remoteDebugInitialized) {
		remoteDebugInitialized = 1;
		debugInit(38400);
	}

	/* diable RX int. */
	dicr = tx3927_sioptr(0)->dicr;
	tx3927_sioptr(0)->dicr = 0;

        do {
            slow_down();
            i++;
            if (i>TIMEOUT) {
                break;
            }
        } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID)
		;
	c = tx3927_sioptr(0)->rfifo;

	/* clear RX int. status */
	tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS;
	/* enable RX int. */
	tx3927_sioptr(0)->dicr = dicr;

	return c;
}

void debugInit(int baud)
{
	/*
	volatile unsigned long lcr;
	volatile unsigned long dicr;
	volatile unsigned long disr;
	volatile unsigned long cisr;
	volatile unsigned long fcr;
	volatile unsigned long flcr;
	volatile unsigned long bgr;
	volatile unsigned long tfifo;
	volatile unsigned long rfifo;
	*/

	tx3927_sioptr(0)->lcr = 0x020;
	tx3927_sioptr(0)->dicr = 0;
	tx3927_sioptr(0)->disr = 0x4100;
	tx3927_sioptr(0)->cisr = 0x014;
	tx3927_sioptr(0)->fcr = 0;
	tx3927_sioptr(0)->flcr = 0x02;
	tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
		TXx927_SIBGR_BCLK_T0;
#if 0
	/*
	 * Reset the UART.
	 */
	tx3927_sioptr(0)->fcr = TXx927_SIFCR_SWRST;
	while (tx3927_sioptr(0)->fcr & TXx927_SIFCR_SWRST)
		;

	/*
	 * and set the speed of the serial port
	 * (currently hardwired to 9600 8N1
	 */

	tx3927_sioptr(0)->lcr = TXx927_SILCR_UMODE_8BIT |
		TXx927_SILCR_USBL_1BIT |
		TXx927_SILCR_SCS_IMCLK_BG;
	tx3927_sioptr(0)->bgr =
		((JMR3927_BASE_BAUD + baud / 2) / baud) |
		TXx927_SIBGR_BCLK_T0;

	/* HW RTS/CTS control */
	if (ser->flags & ASYNC_HAVE_CTS_LINE)
		tx3927_sioptr(0)->flcr = TXx927_SIFLCR_RCS | TXx927_SIFLCR_TES |
			TXx927_SIFLCR_RTSTL_MAX /* 15 */;
	/* Enable RX/TX */
	tx3927_sioptr(0)->flcr &= ~(TXx927_SIFLCR_RSDE | TXx927_SIFLCR_TSDE);
#endif
}

--- NEW FILE: pci_fixup.c ---
/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Board specific pci fixups.
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	pp...@mv... or so...@mv...
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/config.h>

#ifdef CONFIG_PCI

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>

#include <asm/jmr3927/jmr3927.h>

#undef	DEBUG
#ifdef 	DEBUG
#define	DBG(x...)	printk(x)
#else
#define	DBG(x...)	
#endif

void __init pcibios_fixup_resources(struct pci_dev *dev)
{
	/* will need to fixup IO resources */
}

void __init pcibios_fixup(void)
{
	/* nothing to do here */
}

int pci_get_irq(struct pci_dev *dev, int pin)
{
	unsigned char irq = pin;

	/* IRQ rotation (PICMG) */
	irq--;	/* 0-3 */
	if (dev->bus->parent == NULL &&
	    PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
		/* PCI CardSlot (IDSEL=A23, DevNu=12) */
		/* PCIA => PCIC (IDSEL=A23) */
		/* NOTE: JMR3927 JP1 must be set to OPEN */
		irq = (irq + 2) % 4;
	} else if (dev->bus->parent == NULL &&
		   PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
		/* PCI CardSlot (IDSEL=A22, DevNu=11) */
		/* PCIA => PCIA (IDSEL=A22) */
		/* NOTE: JMR3927 JP1 must be set to OPEN */
		irq = (irq + 0) % 4;
	} else {
		/* PCI Backplane */
		irq = (irq + 3 + PCI_SLOT(dev->devfn)) % 4;
#if 0	/* ??? */
		for (bus = dev->bus; bus->parent != NULL; bus = bus->parent) {
			irq = (irq + 3 + PCI_SLOT(bus->self->devfn)) % 4;
		}
#endif
	}
	irq++;	/* 1-4 */

	switch (irq) {
	case 1:
		irq = JMR3927_IRQ_IOC_PCIA;
		break;
	case 2:
		// wrong for backplane irq = JMR3927_IRQ_IOC_PCIB;
		irq = JMR3927_IRQ_IOC_PCID;
		break;
	case 3:
		irq = JMR3927_IRQ_IOC_PCIC;
		break;
	case 4:
		// wrong for backplane irq = JMR3927_IRQ_IOC_PCID;
		irq = JMR3927_IRQ_IOC_PCIB;
		break;
	}

	/* Check OnBoard Ethernet (IDSEL=A24, DevNu=13) */
	if (dev->bus->parent == NULL &&
	    PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(24)) {
		extern int jmr3927_ether1_irq;
		/* check this irq line was reserved for ether1 */
		if (jmr3927_ether1_irq != JMR3927_IRQ_ETHER0)
			irq = JMR3927_IRQ_ETHER0;
		else
			irq = 0;	/* disable */
	}
	return irq;
}

void __init pcibios_fixup_irqs(void)
{
	unsigned char irq;
        struct pci_dev *dev;

	pci_for_each_dev(dev) {
		pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
		if (irq == 0)
			return;

		/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
		if (!(dev->vendor == PCI_VENDOR_ID_EFAR &&
		      dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1)) {
			irq = pci_get_irq(dev, irq);
			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
		}

		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		printk(KERN_INFO "PCI: %02x:%02x IRQ %02x\n",
		       dev->bus->number, dev->devfn, irq);
		dev->irq = irq;
	}
}
#endif

--- NEW FILE: pci_ops.c ---
/***********************************************************************
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahe...@mv...       
 *
 * Copyright (C) 2000-2001 Toshiba Corporation 
 *
 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
 *
 *     Define the pci_ops for JMR3927.
 *
 * Much of the code is derived from the original DDB5074 port by 
 * Geert Uytterhoeven <ge...@so...>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 ***********************************************************************
 */
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/config.h>

#include <asm/addrspace.h>
#include <asm/pci_channel.h>
#include <asm/jmr3927/jmr3927.h>
#include <asm/debug.h>

struct resource pci_io_resource = {
	"pci IO space", 
	0x1000,  /* reserve regacy I/O space */
	0x1000 + JMR3927_PCIIO_SIZE -1,
	IORESOURCE_IO};

struct resource pci_mem_resource = {
	"pci memory space", 
	JMR3927_PCIMEM,
	JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE -1,
	IORESOURCE_MEM};

extern struct pci_ops jmr3927_pci_ops;

struct pci_channel mips_pci_channels[] = {
	{ &jmr3927_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 0xff },
	{ NULL, NULL, NULL, NULL, NULL}
};

unsigned int pcibios_assign_all_busses(void)
{
	return 1;
}                           

static int
mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where, int *flagsp)
{
	if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
		return -1;

	tx3927_pcicptr->ica = ((bus    & 0xff) << 0x10) |
	                      ((dev_fn & 0xff) << 0x08) |
	                      (where  & 0xfc);
	/* clear M_ABORT and Disable M_ABORT Int. */
	tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
	tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
	return 0;
}

static int
check_abort(int flags)
{
	int code = PCIBIOS_SUCCESSFUL;
	if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
		tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
		tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
		code =PCIBIOS_DEVICE_NOT_FOUND;
	}
	return code;
}

/*
 * We can't address 8 and 16 bit words directly.  Instead we have to
 * read/write a 32bit word and mask/modify the data we actually want.
 */
static int jmr3927_pcibios_read_config_byte (struct pci_dev *dev,
					     int where,
					     unsigned char *val)
{
	int flags;
	unsigned char bus, func_num;

	db_assert((where & 3) == 0);
	db_assert(where < (1 << 8));  

	/* check if the bus is top-level */
	if (dev->bus->parent != NULL) {
		bus = dev->bus->number;
		db_assert(bus != 0);
	} else {
		bus = 0;
	}                               

	func_num = PCI_FUNC(dev->devfn);
	if (mkaddr(bus, dev->devfn, where, &flags))
		return -1;
	*val = *(volatile u8 *)((ulong)&tx3927_pcicptr->icd | (where&3));
	return check_abort(flags);
}

static int jmr3927_pcibios_read_config_word (struct pci_dev *dev,
					     int where,
					     unsigned short *val)
{
	int flags;
	unsigned char bus, func_num;

	if (where & 1)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	db_assert((where & 3) == 0);
	db_assert(where < (1 << 8));  

	/* check if the bus is top-level */
	if (dev->bus->parent != NULL) {
		bus = dev->bus->number;
		db_assert(bus != 0);
	} else {
		bus = 0;
	}                               

	func_num = PCI_FUNC(dev->devfn);
	if (mkaddr(bus, dev->devfn, where, &flags))
		return -1;
	*val = le16_to_cpu(*(volatile u16 *)((ulong)&tx3927_pcicptr->icd | (where&3)));
	return check_abort(flags);
}

static int jmr3927_pcibios_read_config_dword (struct pci_dev *dev,
					      int where,
					      unsigned int *val)
{
	int flags;
	unsigned char bus, func_num;

	if (where & 3)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	db_assert((where & 3) == 0);
	db_assert(where < (1 << 8));  

	/* check if the bus is top-level */
	if (dev->bus->parent != NULL) {
		bus = dev->bus->number;
		db_assert(bus != 0);
	} else {
		bus = 0;
	}                               

	func_num = PCI_FUNC(dev->devfn);
	if (mkaddr(bus, dev->devfn, where, &flags))
		return -1;
	*val = le32_to_cpu(tx3927_pcicptr->icd);
	return check_abort(flags);
}

static int jmr3927_pcibios_write_config_byte (struct pci_dev *dev,
					      int where,
					      unsigned char val)
{
	int flags;
	unsigned char bus, func_num;

	/* check if the bus is top-level */
	if (dev->bus->parent != NULL) {
		bus = dev->bus->number;
		db_assert(bus != 0);
	} else {
		bus = 0;
	}                               

	func_num = PCI_FUNC(dev->devfn);
	if (mkaddr(bus, dev->devfn, where, &flags))
		return -1;
	*(volatile u8 *)((ulong)&tx3927_pcicptr->icd | (where&3)) = val;
	return check_abort(flags);
}

static int jmr3927_pcibios_write_config_word (struct pci_dev *dev,
					      int where,
					      unsigned short val)
{
	int flags;
	unsigned char bus, func_num;

	if (where & 1)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	/* check if the bus is top-level */
	if (dev->bus->parent != NULL) {
		bus = dev->bus->number;
		db_assert(bus != 0);
	} else {
		bus = 0;
	}                               

	func_num = PCI_FUNC(dev->devfn);
	if (mkaddr(bus, dev->devfn, where, &flags))
		return -1;
	*(volatile u16 *)((ulong)&tx3927_pcicptr->icd | (where&3)) = cpu_to_le16(val);
	return check_abort(flags);
}

static int jmr3927_pcibios_write_config_dword (struct pci_dev *dev,
					       int where,
					       unsigned int val)
{
	int flags;
	unsigned char bus, func_num;

	if (where & 3)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	/* check if the bus is top-level */
	if (dev->bus->parent != NULL) {
		bus = dev->bus->number;
		db_assert(bus != 0);
	} else {
		bus = 0;
	}                               

	func_num = PCI_FUNC(dev->devfn);
	if (mkaddr(bus, dev->devfn, where, &flags))
		return -1;
	tx3927_pcicptr->icd = cpu_to_le32(val);
	return check_abort(flags);
}
struct pci_ops jmr3927_pci_ops = {
	jmr3927_pcibios_read_config_byte,
	jmr3927_pcibios_read_config_word,
	jmr3927_pcibios_read_config_dword,
	jmr3927_pcibios_write_config_byte,
	jmr3927_pcibios_write_config_word,
	jmr3927_pcibios_write_config_dword
};

#ifndef JMR3927_INIT_INDIRECT_PCI
inline unsigned long tc_readl(volatile __u32 *addr)
{
	return readl(addr);
}
inline void tc_writel(unsigned long data, volatile __u32 *addr)
{
	writel(data, addr);
}
#else
unsigned long tc_readl(volatile __u32 *addr)
{
	unsigned long val;

	addr = PHYSADDR(addr);
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)addr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
	    (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
	val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
	return val;
}
void tc_writel(unsigned long data, volatile __u32 *addr)
{
	addr = PHYSADDR(addr);
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = cpu_to_le32(data);
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)addr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
	    (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT)  | PCI_IPCIBE_IBE_LONG;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}
unsigned char tx_ioinb(unsigned char *addr)
{
	unsigned long val;
	__u32 ioaddr;
	int offset;
	int byte;

	ioaddr = (unsigned long)addr;
        offset = ioaddr & 0x3;
	if (offset == 0)
		byte = 0x7;
	else if (offset == 1)
		byte = 0xb;
	else if (offset == 2)
		byte = 0xd;
	else if (offset == 3)
		byte = 0xe;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
	    (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
	val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
	val = val & 0xff;
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
	return val;
}
void tx_iooutb(unsigned long data, unsigned char *addr)
{
	__u32 ioaddr;
	int offset;
	int byte;

	data = data | (data << 8) | (data << 16) | (data << 24);
	ioaddr = (unsigned long)addr;
        offset = ioaddr & 0x3;
	if (offset == 0)
		byte = 0x7;
	else if (offset == 1)
		byte = 0xb;
	else if (offset == 2)
		byte = 0xd;
	else if (offset == 3)
		byte = 0xe;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = data;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
	    (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT)  | byte;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}
unsigned short tx_ioinw(unsigned short *addr)
{
	unsigned long val;
	__u32 ioaddr;
	int offset;
	int byte;

	ioaddr = (unsigned long)addr;
        offset = ioaddr & 0x3;
	if (offset == 0)
		byte = 0x3;
	else if (offset == 2)
		byte = 0xc;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
	    (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
	val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
	val = val & 0xffff;
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
	return val;

}
void tx_iooutw(unsigned long data, unsigned short *addr)
{
	__u32 ioaddr;
	int offset;
	int byte;

	data = data | (data << 16);
	ioaddr = (unsigned long)addr;
        offset = ioaddr & 0x3;
	if (offset == 0)
		byte = 0x3;
	else if (offset == 2)
		byte = 0xc;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = data;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
	    (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT)  | byte;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}
unsigned long tx_ioinl(unsigned int *addr)
{
	unsigned long val;
	__u32 ioaddr;

	ioaddr = (unsigned long)addr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
	    (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
	val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata);
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
	return val;
}
void tx_iooutl(unsigned long data, unsigned int *addr)
{
	__u32 ioaddr;

	ioaddr = (unsigned long)addr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = cpu_to_le32(data);
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr =  (unsigned long)ioaddr;
	*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe =  
	    (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT)  | PCI_IPCIBE_IBE_LONG;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ;
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}
void tx_insbyte(unsigned char *addr,void *buffer,unsigned int count)
{
	unsigned char *ptr = (unsigned char *) buffer;

	while (count--) {
		*ptr++ = tx_ioinb(addr);
	}
}
void tx_insword(unsigned short *addr,void *buffer,unsigned int count)
{
	unsigned short *ptr = (unsigned short *) buffer;

	while (count--) {
		*ptr++ = tx_ioinw(addr);
	}
}
void tx_inslong(unsigned int *addr,void *buffer,unsigned int count)
{
	unsigned long *ptr = (unsigned long *) buffer;

	while (count--) {
		*ptr++ = tx_ioinl(addr);
	}
}
void tx_outsbyte(unsigned char *addr,void *buffer,unsigned int count)
{
	unsigned char *ptr = (unsigned char *) buffer;

	while (count--) {
		tx_iooutb(*ptr++,addr);
	}
}
void tx_outsword(unsigned short *addr,void *buffer,unsigned int count)
{
	unsigned short *ptr = (unsigned short *) buffer;

	while (count--) {
		tx_iooutw(*ptr++,addr);
	}
}
void tx_outslong(unsigned int *addr,void *buffer,unsigned int count)
{
	unsigned long *ptr = (unsigned long *) buffer;

	while (count--) {
		tx_iooutl(*ptr++,addr);
	}
}
#endif

--- NEW FILE: rtc.c ---
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahe...@mv...       
 *
 * $Id: rtc.c,v 1.1 2001/11/10 03:56:05 jsimmons Exp $
 *
 * RTC routines for Dallas chip.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 200-2001 Toshiba Corporation
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <asm/mc146818rtc.h>	/* bad name... */
#include <asm/jmr3927/jmr3927.h>

static unsigned char jmr3927_rtc_read_data(unsigned long addr)
{
	return jmr3927_nvram_in(addr);
}

static void jmr3927_rtc_write_data(unsigned char data, unsigned long addr)
{
	jmr3927_nvram_out(data, addr);
}

static int jmr3927_rtc_bcd_mode(void)
{
	return 1;
}

struct rtc_ops jmr3927_rtc_ops = {
	&jmr3927_rtc_read_data,
	&jmr3927_rtc_write_data,
	&jmr3927_rtc_bcd_mode
};

--- NEW FILE: setup.c ---
/***********************************************************************
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahe...@mv...       
 *
 * Based on arch/mips/ddb5xxx/ddb5477/setup.c
 *
 *     Setup file for JMR3927.
 *
 * Copyright (C) 2000-2001 Toshiba Corporation 
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 ***********************************************************************
 */

#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/console.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/fs.h>		/* for ROOT_DEV */
#include <linux/ioport.h>
#include <linux/param.h>	/* for HZ */
#include <linux/delay.h>

#include <asm/addrspace.h>
#include <asm/time.h>
#include <asm/bcache.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/jmr3927/jmr3927.h>
#include <asm/mipsregs.h>

/* Tick Timer divider */
#define JMR3927_TIMER_CCD	0	/* 1/2 */
#define JMR3927_TIMER_CLK	(JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))

unsigned char led_state = 0xf;

struct {
    struct resource ram0;
    struct resource ram1;
    struct resource pcimem;
    struct resource iob;
    struct resource ioc;
    struct resource pciio;
    struct resource jmy1394;
    struct resource rom1;
    struct resource rom0;
    struct resource sio0;
    struct resource sio1;
} jmr3927_resources = {
    { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
    { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
    { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
    { "IOB",           0x10000000, 0x13FFFFFF                  },
    { "IOC",           0x14000000, 0x14FFFFFF                  },
    { "PCIIO",         0x15000000, 0x15FFFFFF                  },
    { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
    { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
    { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
    { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
    { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
};

/* don't enable - see errata */
int jmr3927_ccfg_toeon = 0;

static inline void do_reset(void)
{
#ifdef CONFIG_TC35815
	extern void tc35815_killall(void);
	tc35815_killall();
#endif
#if 1	/* Resetting PCI bus */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
	jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
	(void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);	/* flush WB */
	mdelay(1);
	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
#endif
	jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
}

static void jmr3927_machine_restart(char *command)
{
	cli();
	puts("Rebooting...");
	do_reset();
}

static void jmr3927_machine_halt(void)
{
	puts("JMR-TX3927 halted.\n");
	while (1);
}

static void jmr3927_machine_power_off(void)
{
	puts("JMR-TX3927 halted. Please turn off the power.\n");
	while (1);
}

#define USE_RTC_DS1742
#ifdef USE_RTC_DS1742
extern void rtc_ds1742_init(unsigned long base);
#endif
static void __init jmr3927_time_init(void)
{
#ifdef USE_RTC_DS1742
	if (jmr3927_have_nvram()) {
	        rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
	}
#endif
}

unsigned long jmr3927_do_gettimeoffset(void);
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void __init jmr3927_timer_setup(struct irqaction *irq)
{
	do_gettimeoffset = jmr3927_do_gettimeoffset;

	jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
	jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
	jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
	jmr3927_tmrptr->tcr =
		TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;

	setup_irq(JMR3927_IRQ_TICK, irq);
}

#define USECS_PER_JIFFY (1000000/HZ)
unsigned long jmr3927_do_gettimeoffset(void)
{
       unsigned long count;
       unsigned long res = 0;

       /* MUST read TRR before TISR. */
       count = jmr3927_tmrptr->trr;

       if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
               /* timer interrupt is pending.  use Max value. */
               res = USECS_PER_JIFFY - 1;
       } else {
               /* convert to usec */
               /* res = count / (JMR3927_TIMER_CLK / 1000000); */
               res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);

               /*
                * Due to possible jiffies inconsistencies, we need to check
                * the result so that we'll get a timer that is monotonic.
                */
               if (res >= USECS_PER_JIFFY)
                       res = USECS_PER_JIFFY-1;
       }

       return res;
}                                         

#if defined(CONFIG_BLK_DEV_INITRD)
extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
#endif 

//#undef DO_WRITE_THROUGH
#define DO_WRITE_THROUGH
#define DO_ENABLE_CACHE

extern char * __init prom_getcmdline(void);
static void jmr3927_board_init(void);
extern void jmr3927_irq_setup(void);
extern struct resource pci_io_resource;
extern struct resource pci_mem_resource;
void __init jmr3927_setup(void)
{
	extern int panic_timeout;
	char *argptr;

	irq_setup = jmr3927_irq_setup;
	mips_io_port_base = JMR3927_PORT_BASE + JMR3927_PCIIO;

	board_time_init = jmr3927_time_init;
	board_timer_setup = jmr3927_timer_setup;

	_machine_restart = jmr3927_machine_restart;
	_machine_halt = jmr3927_machine_halt;
	_machine_power_off = jmr3927_machine_power_off;

	/*
	 * IO/MEM resources. 
	 */
	ioport_resource.start = 0;
	ioport_resource.end = 0xffffffff;
	iomem_resource.start = 0;
	iomem_resource.end = 0xffffffff;
	
	/* Reboot on panic */
	panic_timeout = 180;

	{
		unsigned int conf;
		conf = read_32bit_cp0_register(CP0_CONF);
	}

#if 1
	/* cache setup */
	{
		unsigned int conf;
#ifdef DO_ENABLE_CACHE
		int mips_ic_disable = 0, mips_dc_disable = 0;
#else
		int mips_ic_disable = 1, mips_dc_disable = 1;
#endif
#ifdef DO_WRITE_THROUGH
		int mips_config_cwfon = 0;
		int mips_config_wbon = 0;
#else
		int mips_config_cwfon = 1;
		int mips_config_wbon = 1;
#endif

		clear_cp0_status(ST0_BEV);

		conf = read_32bit_cp0_register(CP0_CONF);
		conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
		conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
		conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
		conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
		conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;

		write_32bit_cp0_register(CP0_CONF, conf);
		write_32bit_cp0_register(CP0_TX39_CACHE, 0);
	}
#endif

	/* initialize board */
	jmr3927_board_init();

	argptr = prom_getcmdline();

	if ((argptr = strstr(argptr, "toeon")) != NULL) {
			jmr3927_ccfg_toeon = 1;
	}
	argptr = prom_getcmdline();
	if ((argptr = strstr(argptr, "ip=")) == NULL) {
		argptr = prom_getcmdline();
		strcat(argptr, " ip=bootp");
	}

#ifdef CONFIG_TXX927_SERIAL_CONSOLE
	argptr = prom_getcmdline();
	if ((argptr = strstr(argptr, "console=")) == NULL) {
		argptr = prom_getcmdline();
		strcat(argptr, " console=ttyS1,115200");
	}
#endif                                             
}
 

static void tx3927_setup(void);

#ifdef CONFIG_PCI
unsigned long mips_pci_io_base;
unsigned long mips_pci_io_size;
unsigned long mips_pci_mem_base;
unsigned long mips_pci_mem_size;
/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
unsigned long mips_pci_io_pciaddr = 0;
#endif
extern struct rtc_ops *rtc_ops;
extern struct rtc_ops jmr3927_rtc_ops;
static void jmr3927_board_init()
{
	char *argptr;

#ifdef CONFIG_PCI
	mips_pci_io_base = JMR3927_PCIIO;
	mips_pci_io_size = JMR3927_PCIIO_SIZE;
	mips_pci_mem_base = JMR3927_PCIMEM;
	mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
#endif

	tx3927_setup();

#ifdef CONFIG_VT
	conswitchp = &dummy_con;
#endif

	if (jmr3927_have_isac()) {

#ifdef CONFIG_FB_E1355
		argptr = prom_getcmdline();
		if ((argptr = strstr(argptr, "video=")) == NULL) {
			argptr = prom_getcmdline();
			strcat(argptr, " video=e1355fb:crt16h");
		}
#endif

#ifdef CONFIG_BLK_DEV_IDE
		/* overrides PCI-IDE */
#endif

#ifdef CONFIG_PC_KEYB
		//not yet kbd_ops = &jmr3927_kbd_ops;
#endif
	}
#ifdef USE_RTC_DS1742
	if (jmr3927_have_nvram()) {
		rtc_ops = &jmr3927_rtc_ops;
	}
#endif

	/* SIO0 DTR on */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);

	jmr3927_led_set(0);


	if (jmr3927_have_isac()) 
		jmr3927_io_led_set(0);
	printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
	       jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
	       jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
	       jmr3927_dipsw1(), jmr3927_dipsw2(),
	       jmr3927_dipsw3(), jmr3927_dipsw4());
	if (jmr3927_have_isac())
		printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
		       jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
		       jmr3927_io_dipsw());
}
static void tx3927_setup(void)
{
	int i;

	/* SDRAMC are configured by PROM */

	/* ROMC */
	tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
	tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
	tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
	tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;

	/* CCFG */
	/* enable Timeout BusError */
	if (jmr3927_ccfg_toeon)
		tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;

	/* clear BusErrorOnWrite flag */
	tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
	/* Disable PCI snoop */
	tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;

#ifdef DO_WRITE_THROUGH
	/* Enable PCI SNOOP - with write through only */
	tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
#endif

	/* Pin selection */
	tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
	tx3927_ccfgptr->pcfg |=
		TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
		(TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));

	printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
	       tx3927_ccfgptr->crir,
	       tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);

	/* IRC */
	/* disable interrupt control */
	tx3927_ircptr->cer = 0;
	/* mask all IRC interrupts */
	tx3927_ircptr->imr = 0;
	for (i = 0; i < TX3927_NUM_IR / 2; i++) {
		tx3927_ircptr->ilr[i] = 0;
	}
	/* setup IRC interrupt mode (Low Active) */
	for (i = 0; i < TX3927_NUM_IR / 8; i++) {
		tx3927_ircptr->cr[i] = 0;
	}

	/* TMR */
	/* disable all timers */
	for (i = 0; i < TX3927_NR_TMR; i++) {
		tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
		tx3927_tmrptr(i)->tisr = 0;
		tx3927_tmrptr(i)->cpra = 0xffffffff;
		tx3927_tmrptr(i)->itmr = 0;
		tx3927_tmrptr(i)->ccdr = 0;
		tx3927_tmrptr(i)->pgmr = 0;
	}

	/* DMA */
	tx3927_dmaptr->mcr = 0;
	for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
		/* reset channel */
		tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
		tx3927_dmaptr->ch[i].ccr = 0;
	}
	/* enable DMA */
#ifdef __BIG_ENDIAN
	tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
#else
	tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
#endif

#ifdef CONFIG_PCI
	/* PCIC */
	printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
	       tx3927_pcicptr->did, tx3927_pcicptr->vid,
	       tx3927_pcicptr->rid);
	if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
		printk("External\n");
		/* XXX */
	} else {
		printk("Internal\n");

		/* Reset PCI Bus */
		jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
		udelay(100);
		jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
				    JMR3927_IOC_RESET_ADDR);
		udelay(100);
		jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);


		/* Disable External PCI Config. Access */
		tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
#ifdef __BIG_ENDIAN
		tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
			TX3927_PCIC_LBC_TIBSE |
			TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
#endif
		/* LB->PCI mappings */
		tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
		tx3927_pcicptr->ilbioma = mips_pci_io_base;
		tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
		tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
		tx3927_pcicptr->ilbmma = mips_pci_mem_base;
		tx3927_pcicptr->ipbmma = mips_pci_mem_base;
		/* PCI->LB mappings */
		tx3927_pcicptr->iobas = 0xffffffff;
		tx3927_pcicptr->ioba = 0;
		tx3927_pcicptr->tlbioma = 0;
		tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
		tx3927_pcicptr->mba = 0;
		tx3927_pcicptr->tlbmma = 0;
#ifndef JMR3927_INIT_INDIRECT_PCI
		/* Enable Direct mapping Address Space Decoder */
		tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
#endif

		/* Clear All Local Bus Status */
		tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
		/* Enable All Local Bus Interrupts */
		tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
		/* Clear All PCI Status Error */
		tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
		/* Enable All PCI Status Error Interrupts */
		tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;

		/* PCIC Int => IRC IRQ10 */
		tx3927_pcicptr->il = TX3927_IR_PCI;
#if 1
		/* Target Control (per errata) */
		tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
#endif

		/* Enable Bus Arbiter */
#if 0
		tx3927_pcicptr->req_trace = 0x73737373;
#endif
		tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;

		tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
			PCI_COMMAND_MEMORY |
#if 1
			PCI_COMMAND_IO |
#endif
			PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
	}
#endif /* CONFIG_PCI */

	/* PIO */
	/* PIO[15:12] connected to LEDs */
	tx3927_pioptr->dir = 0x0000f000;
	tx3927_pioptr->maskcpu = 0;
	tx3927_pioptr->maskext = 0;
	{
		unsigned int conf;

	conf = read_32bit_cp0_register(CP0_CONF);
               if (!(conf & TX39_CONF_ICE))
                       printk("TX3927 I-Cache disabled.\n");
               if (!(conf & TX39_CONF_DCE))
                       printk("TX3927 D-Cache disabled.\n");
               else if (!(conf & TX39_CONF_WBON))
                       printk("TX3927 D-Cache WriteThrough.\n");
               else if (!(conf & TX39_CONF_CWFON))
                       printk("TX3927 D-Cache WriteBack.\n");
               else
                       printk("TX3927 D-Cache WriteBack (CWF) .\n");
	}
}

[Linux-mips-commits]CVS: linux/arch/mips/jmr3927/common Makefile,NONE,1.1 prom.c,NONE,1.1 puts.c,NONE,1.1 rtc_ds1742.c,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/jmr3927/common
In directory usw-pr-cvs1:/tmp/cvs-serv22117/jmr3927/common

Added Files:
	Makefile prom.c puts.c rtc_ds1742.c 
Log Message:
Imported support for JMR-TX3927 by Alice Hennessy. Thank you.

--- NEW FILE: Makefile ---
#
# Makefile for the common code of TOSHIBA JMR-TX3927 board
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

.S.s:
	$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
	$(CC) $(CFLAGS) -c $< -o $*.o

O_TARGET:= tx3927.o

obj-y	 += prom.o puts.o rtc_ds1742.o

include $(TOPDIR)/Rules.make

--- NEW FILE: prom.c ---
/*
 *
 * BRIEF MODULE DESCRIPTION
 *    PROM library initialisation code, assuming a version of
 *    pmon is the boot code.
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahe...@mv...       
 *
 * Based on arch/mips/au1000/common/prom.c
 *
 * This file was derived from Carsten Langgaard's 
 * arch/mips/mips-boards/xx files.
 *
 * Carsten Langgaard, car...@mi...
 * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/string.h>

#include <asm/bootinfo.h>

/* #define DEBUG_CMDLINE */

char arcs_cmdline[COMMAND_LINE_SIZE];
extern int prom_argc;
extern char **prom_argv, **prom_envp;

typedef struct
{
    char *name;
/*    char *val; */
}t_env_var;


char * __init prom_getcmdline(void)
{
	return &(arcs_cmdline[0]);
}

void  __init prom_init_cmdline(void)
{
	char *cp;
	int actr;

	actr = 1; /* Always ignore argv[0] */

	cp = &(arcs_cmdline[0]);
	while(actr < prom_argc) {
	        strcpy(cp, prom_argv[actr]);
		cp += strlen(prom_argv[actr]);
		*cp++ = ' ';
		actr++;
	}
	if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
		--cp;
	*cp = '\0';
}

int __init page_is_ram(unsigned long pagenr)
{
    return 1;
}

void prom_free_prom_memory (void)
{
}

--- NEW FILE: puts.c ---
/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Low level uart routines to directly access a TX[34]927 SIO.
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	ahe...@mv... or so...@mv...
 *
 * Copyright (C) 2000-2001 Toshiba Corporation 
 *
 * Based on arch/mips/au1000/common/puts.c
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/types.h>
#include <asm/jmr3927/txx927.h>
#include <asm/jmr3927/tx3927.h>
#include <asm/jmr3927/jmr3927.h>

#define TIMEOUT       0xffffff
#define SLOW_DOWN

static const char digits[16] = "0123456789abcdef";

#ifdef SLOW_DOWN
#define slow_down() { int k; for (k=0; k<10000; k++); }
#else
#define slow_down()
#endif

void
putch(const unsigned char c)
{
        int i = 0;
	
        do {
            slow_down();
            i++;
            if (i>TIMEOUT) {
                break;
            }
        } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
	tx3927_sioptr(1)->tfifo = c;
	return;
}

unsigned char getch(void)
{
        int i = 0;
	int dicr;
	char c;
	
	/* diable RX int. */
	dicr = tx3927_sioptr(1)->dicr;
	tx3927_sioptr(1)->dicr = 0;

        do {
            slow_down();
            i++;
            if (i>TIMEOUT) {
                break;
            }
        } while (tx3927_sioptr(1)->disr & TXx927_SIDISR_UVALID)
		;
	c = tx3927_sioptr(1)->rfifo;

	/* clear RX int. status */
	tx3927_sioptr(1)->disr &= ~TXx927_SIDISR_RDIS;
	/* enable RX int. */
	tx3927_sioptr(1)->dicr = dicr;

	return c;
}
void
do_jmr3927_led_set(char n)
{
    /* and with current leds */
    jmr3927_led_and_set(n);
}

void
puts(unsigned char *cp)
{
    int i = 0;

    while (*cp) {
        do {
            slow_down();
            i++;
            if (i>TIMEOUT) {
                break;
            }
        } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
	tx3927_sioptr(1)->tfifo = *cp++;
    }
    putch('\r');
    putch('\n');
}

void
fputs(unsigned char *cp)
{
    int i = 0;

    while (*cp) {
        do {
             slow_down();
            i++;
            if (i>TIMEOUT) {
                break;
            }
        } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
	tx3927_sioptr(1)->tfifo = *cp++;
    }
}


void
put64(uint64_t ul)
{
    int cnt;
    unsigned ch;

    cnt = 16;            /* 16 nibbles in a 64 bit long */
    putch('0');
    putch('x');
    do {
        cnt--;
        ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
                putch(digits[ch]);
    } while (cnt > 0);
}

void
put32(unsigned u)
{
    int cnt;
    unsigned ch;

    cnt = 8;            /* 8 nibbles in a 32 bit long */
    putch('0');
    putch('x');
    do {
        cnt--;
        ch = (unsigned char)(u >> cnt * 4) & 0x0F;
                putch(digits[ch]);
    } while (cnt > 0);
}

--- NEW FILE: rtc_ds1742.c ---
/***********************************************************************
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahe...@mv...       
 *
 * arch/mips/jmr3927/common/rtc_ds1742.c
 * Based on arch/mips/ddb5xxx/common/rtc_ds1386.c
 *     low-level RTC hookups for s for Dallas 1742 chip.
 *
 * Copyright (C) 2000-2001 Toshiba Corporation 
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 ***********************************************************************
 */


/*
 * This file exports a function, rtc_ds1386_init(), which expects an
 * uncached base address as the argument.  It will set the two function
 * pointers expected by the MIPS generic timer code.
 */

#include <linux/types.h>
#include <linux/time.h>
#include <linux/rtc.h>

#include <asm/time.h>
#include <asm/addrspace.h>

#include <asm/jmr3927/ds1742rtc.h>
#include <asm/debug.h>

#define	EPOCH		2000

#undef BCD_TO_BIN
#define BCD_TO_BIN(val) (((val)&15) + ((val)>>4)*10)

#undef BIN_TO_BCD
#define BIN_TO_BCD(val) ((((val)/10)<<4) + (val)%10)

static unsigned long rtc_base;

static unsigned long
rtc_ds1742_get_time(void)
{
	unsigned int year, month, day, hour, minute, second;
	unsigned int century;

	CMOS_WRITE(RTC_READ, RTC_CONTROL);
	second = BCD_TO_BIN(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
	minute = BCD_TO_BIN(CMOS_READ(RTC_MINUTES));
	hour = BCD_TO_BIN(CMOS_READ(RTC_HOURS));
	day = BCD_TO_BIN(CMOS_READ(RTC_DATE));
	month = BCD_TO_BIN(CMOS_READ(RTC_MONTH));
	year = BCD_TO_BIN(CMOS_READ(RTC_YEAR));
	century = BCD_TO_BIN(CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK);
	CMOS_WRITE(0, RTC_CONTROL);

	year += century * 100;

	return mktime(year, month, day, hour, minute, second);
}
extern void to_tm(unsigned long tim, struct rtc_time * tm);

static int 
rtc_ds1742_set_time(unsigned long t)
{
	struct rtc_time tm;
	u8 year, month, day, hour, minute, second;
	u8 cmos_year, cmos_month, cmos_day, cmos_hour, cmos_minute, cmos_second;
	int cmos_century;

	CMOS_WRITE(RTC_READ, RTC_CONTROL);
	cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
	cmos_minute = (u8)CMOS_READ(RTC_MINUTES);
	cmos_hour = (u8)CMOS_READ(RTC_HOURS);
	cmos_day = (u8)CMOS_READ(RTC_DATE);
	cmos_month = (u8)CMOS_READ(RTC_MONTH);
	cmos_year = (u8)CMOS_READ(RTC_YEAR);
	cmos_century = CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK;

	CMOS_WRITE(RTC_WRITE, RTC_CONTROL);

	/* convert */
	to_tm(t, &tm);

	/* check each field one by one */
	year = BIN_TO_BCD(tm.tm_year - EPOCH);
	if (year != cmos_year) {
		CMOS_WRITE(year,RTC_YEAR);
	}

	month = BIN_TO_BCD(tm.tm_mon);
	if (month != (cmos_month & 0x1f)) {
		CMOS_WRITE((month & 0x1f) | (cmos_month & ~0x1f),RTC_MONTH);
	}

	day = BIN_TO_BCD(tm.tm_mday);
	if (day != cmos_day) {
	
		CMOS_WRITE(day, RTC_DATE);
	}

	if (cmos_hour & 0x40) {
		/* 12 hour format */
		hour = 0x40;
		if (tm.tm_hour > 12) {
			hour |= 0x20 | (BIN_TO_BCD(hour-12) & 0x1f);
		} else {
			hour |= BIN_TO_BCD(tm.tm_hour);
		}
	} else {
		/* 24 hour format */
		hour = BIN_TO_BCD(tm.tm_hour) & 0x3f;
	}
	if (hour != cmos_hour) CMOS_WRITE(hour, RTC_HOURS);

	minute = BIN_TO_BCD(tm.tm_min);
	if (minute !=  cmos_minute) {
		CMOS_WRITE(minute, RTC_MINUTES);
	}

	second = BIN_TO_BCD(tm.tm_sec);
	if (second !=  cmos_second) {
		CMOS_WRITE(second & RTC_SECONDS_MASK,RTC_SECONDS);
	}
	
	/* RTC_CENTURY and RTC_CONTROL share same address... */
	CMOS_WRITE(cmos_century, RTC_CONTROL);

	return 0;
}

void
rtc_ds1742_init(unsigned long base)
{
	u8  cmos_second;

	/* remember the base */
	rtc_base = base;
	db_assert((rtc_base & 0xe0000000) == KSEG1);

	/* set the function pointers */
	rtc_get_time = rtc_ds1742_get_time;
	rtc_set_time = rtc_ds1742_set_time;

	/* clear oscillator stop bit */
	CMOS_WRITE(RTC_READ, RTC_CONTROL);
	cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
	CMOS_WRITE(RTC_WRITE, RTC_CONTROL);
	CMOS_WRITE(cmos_second, RTC_SECONDS); /* clear msb */
	CMOS_WRITE(0, RTC_CONTROL);
}

[Linux-mips-commits]CVS: linux/arch/mips/jmr3927/rbhma3100 - New directory

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/jmr3927/rbhma3100
In directory usw-pr-cvs1:/tmp/cvs-serv21566/rbhma3100

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/jmr3927/rbhma3100 added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/jmr3927/common - New directory

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/jmr3927/common
In directory usw-pr-cvs1:/tmp/cvs-serv21566/common

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/jmr3927/common added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/jmr3927 - New directory

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/jmr3927
In directory usw-pr-cvs1:/tmp/cvs-serv21462/jmr3927

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/jmr3927 added to the repository

[Linux-mips-commits]CVS: linux/include/asm-mips/jmr3927 ds1742rtc.h,NONE,1.1 irq.h,NONE,1.1 jmr3927.h,NONE,1.1 pci.h,NONE,1.1 tx3927.h,NONE,1.1 txx927.h,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/jmr3927
In directory usw-pr-cvs1:/tmp/cvs-serv21221

Added Files:
	ds1742rtc.h irq.h jmr3927.h pci.h tx3927.h txx927.h 
Log Message:
Imported support for JMR-TX3927 by Alice Hennessy. Thank you.

--- NEW FILE: ds1742rtc.h ---
/* $Id: ds1742rtc.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
 *
 * ds1742rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
 *
 *   Based on include/asm-mips/ds1643rtc.h.
 *
 * Copyright (C) 1999-2001 Toshiba Corporation
 * It was written to be part of the Linux operating system.
 */
/* permission is hereby granted to copy, modify and redistribute this code
 * in terms of the GNU Library General Public License, Version 2 or later,
 * at your option.
 */
#ifndef _DS1742RTC_H
#define _DS1742RTC_H

#include <linux/rtc.h>
#include <asm/mc146818rtc.h>	/* bad name... */

#define RTC_BRAM_SIZE		0x800
#define RTC_OFFSET		0x7f8

/**********************************************************************
 * register summary
 **********************************************************************/
#define RTC_CONTROL		(RTC_OFFSET + 0)
#define RTC_CENTURY		(RTC_OFFSET + 0)
#define RTC_SECONDS		(RTC_OFFSET + 1)
#define RTC_MINUTES		(RTC_OFFSET + 2)
#define RTC_HOURS		(RTC_OFFSET + 3)
#define RTC_DAY			(RTC_OFFSET + 4)
#define RTC_DATE		(RTC_OFFSET + 5)
#define RTC_MONTH		(RTC_OFFSET + 6)
#define RTC_YEAR		(RTC_OFFSET + 7)

#define RTC_CENTURY_MASK	0x3f
#define RTC_SECONDS_MASK	0x7f
#define RTC_DAY_MASK		0x07

/*
 * Bits in the Control/Century register
 */
#define RTC_WRITE		0x80
#define RTC_READ		0x40

/*
 * Bits in the Seconds register
 */
#define RTC_STOP		0x80

/*
 * Bits in the Day register
 */
#define RTC_BATT_FLAG		0x80
#define RTC_FREQ_TEST		0x40

/*
 * Conversion between binary and BCD.
 */
#ifndef BCD_TO_BIN
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
#endif

#ifndef BIN_TO_BCD
#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
#endif

#endif /* _DS1742RTC_H */

--- NEW FILE: irq.h ---
/*
 *  linux/include/asm-mips/tx3927/irq.h
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2001 Toshiba Corporation
 *
 * $Id: irq.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
 */
#ifndef __ASM_MIPS_TX3927_IRQ_H
#define __ASM_MIPS_TX3927_IRQ_H

#ifndef _LANGUAGE_ASSEMBLY
#include <asm/irq.h>

struct tb_irq_space {
	struct tb_irq_space* next;
	int start_irqno;
	int nr_irqs;
	void (*mask_func)(int irq_nr, int space_id);
	void (*unmask_func)(int irq_no, int space_id);
	const char *name;
	int space_id;
	int can_share;
};
extern struct tb_irq_space* tb_irq_spaces;

static __inline__ void add_tb_irq_space(struct tb_irq_space* sp)
{
	sp->next = tb_irq_spaces;
	tb_irq_spaces = sp;
}


struct pt_regs;
extern void
toshibaboards_spurious(struct pt_regs *regs, int irq);
extern void
toshibaboards_irqdispatch(struct pt_regs *regs, int irq);

extern struct irqaction *
toshibaboards_get_irq_action(int irq);
extern int
toshibaboards_setup_irq(int irq, struct irqaction * new);


#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
extern void tx_branch_likely_bug_fixup(struct pt_regs *regs);
#endif

extern int (*toshibaboards_gen_iack)(void);

#endif /* _LANGUAGE_ASSEMBLY */

#define NR_ISA_IRQS 16
#define TB_IRQ_IS_ISA(irq)	\
	(0 <= (irq) && (irq) < NR_ISA_IRQS)
#define TB_IRQ_TO_ISA_IRQ(irq)	(irq)

#endif /* __ASM_MIPS_TX3927_IRQ_H */

--- NEW FILE: jmr3927.h ---
/* $Id: jmr3927.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
 *
 * Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000-2001 Toshiba Corporation
 */
#ifndef __ASM_MIPS_TX3927_JMR3927_H 
#define __ASM_MIPS_TX3927_JMR3927_H 

#include <asm/jmr3927/tx3927.h>
#include <asm/addrspace.h>
#include <asm/jmr3927/irq.h>
#ifndef _LANGUAGE_ASSEMBLY
#include <asm/system.h>
#endif

/* CS */
#define JMR3927_ROMCE0	0x1fc00000	/* 4M */
#define JMR3927_ROMCE1	0x1e000000	/* 4M */
#define JMR3927_ROMCE2	0x14000000	/* 16M */
#define JMR3927_ROMCE3	0x10000000	/* 64M */
#define JMR3927_ROMCE5	0x1d000000	/* 4M */
#define JMR3927_SDCS0	0x00000000	/* 32M */
#define JMR3927_SDCS1	0x02000000	/* 32M */
/* PCI Direct Mappings */

#define JMR3927_PCIMEM	0x08000000
#define JMR3927_PCIMEM_SIZE	0x08000000	/* 128M */
#define JMR3927_PCIIO	0x15000000
#define JMR3927_PCIIO_SIZE	0x01000000	/* 16M */

#define JMR3927_SDRAM_SIZE	0x02000000	/* 32M */
#define JMR3927_PORT_BASE	KSEG1

/* select indirect initiator access per errata */
#define JMR3927_INIT_INDIRECT_PCI 
#define PCI_ISTAT_IDICC           0x1000
#define PCI_IPCIBE_IBE_LONG       0
#define PCI_IPCIBE_ICMD_IOREAD    2 
#define PCI_IPCIBE_ICMD_IOWRITE   3
#define PCI_IPCIBE_ICMD_MEMREAD   6 
#define PCI_IPCIBE_ICMD_MEMWRITE  7
#define PCI_IPCIBE_ICMD_SHIFT     4 

/* Address map (virtual address) */
#define JMR3927_ROM0_BASE	(KSEG1 + JMR3927_ROMCE0)
#define JMR3927_ROM1_BASE	(KSEG1 + JMR3927_ROMCE1)
#define JMR3927_IOC_BASE	(KSEG1 + JMR3927_ROMCE2)
#define JMR3927_IOB_BASE	(KSEG1 + JMR3927_ROMCE3)
#define JMR3927_ISAMEM_BASE	(JMR3927_IOB_BASE)
#define JMR3927_ISAIO_BASE	(JMR3927_IOB_BASE + 0x01000000)
#define JMR3927_ISAC_BASE	(JMR3927_IOB_BASE + 0x02000000)
#define JMR3927_LCDVGA_REG_BASE	(JMR3927_IOB_BASE + 0x03000000)
#define JMR3927_LCDVGA_MEM_BASE	(JMR3927_IOB_BASE + 0x03800000)
#define JMR3927_JMY1394_BASE	(KSEG1 + JMR3927_ROMCE5)
#define JMR3927_PREMIER3_BASE	(JMR3927_JMY1394_BASE + 0x00100000)
#define JMR3927_PCIMEM_BASE	(KSEG1 + JMR3927_PCIMEM)
#define JMR3927_PCIIO_BASE	(KSEG1 + JMR3927_PCIIO)

#define JMR3927_IOC_REV_ADDR	(JMR3927_IOC_BASE + 0x00000000)
#define JMR3927_IOC_NVRAMB_ADDR	(JMR3927_IOC_BASE + 0x00010000)
#define JMR3927_IOC_LED_ADDR	(JMR3927_IOC_BASE + 0x00020000)
#define JMR3927_IOC_DIPSW_ADDR	(JMR3927_IOC_BASE + 0x00030000)
#define JMR3927_IOC_BREV_ADDR	(JMR3927_IOC_BASE + 0x00040000)
#define JMR3927_IOC_DTR_ADDR	(JMR3927_IOC_BASE + 0x00050000)
#define JMR3927_IOC_INTS1_ADDR	(JMR3927_IOC_BASE + 0x00080000)
#define JMR3927_IOC_INTS2_ADDR	(JMR3927_IOC_BASE + 0x00090000)
#define JMR3927_IOC_INTM_ADDR	(JMR3927_IOC_BASE + 0x000a0000)
#define JMR3927_IOC_INTP_ADDR	(JMR3927_IOC_BASE + 0x000b0000)
#define JMR3927_IOC_RESET_ADDR	(JMR3927_IOC_BASE + 0x000f0000)

#define JMR3927_ISAC_REV_ADDR	(JMR3927_ISAC_BASE + 0x00000000)
#define JMR3927_ISAC_EINTS_ADDR	(JMR3927_ISAC_BASE + 0x00200000)
#define JMR3927_ISAC_EINTM_ADDR	(JMR3927_ISAC_BASE + 0x00300000)
#define JMR3927_ISAC_NMI_ADDR	(JMR3927_ISAC_BASE + 0x00400000)
#define JMR3927_ISAC_LED_ADDR	(JMR3927_ISAC_BASE + 0x00500000)
#define JMR3927_ISAC_INTP_ADDR	(JMR3927_ISAC_BASE + 0x00800000)
#define JMR3927_ISAC_INTS1_ADDR	(JMR3927_ISAC_BASE + 0x00900000)
#define JMR3927_ISAC_INTS2_ADDR	(JMR3927_ISAC_BASE + 0x00a00000)
#define JMR3927_ISAC_INTM_ADDR	(JMR3927_ISAC_BASE + 0x00b00000)

/* Flash ROM */
#define JMR3927_FLASH_BASE	(JMR3927_ROM0_BASE)
#define JMR3927_FLASH_SIZE	0x00400000

/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */
#define JMR3927_IDT_MASK	0xfc
#define JMR3927_REV_MASK	0x03
#define JMR3927_IOC_IDT		0xe0
#define JMR3927_ISAC_IDT	0x20

/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
#define JMR3927_IOC_INTB_PCIA	0
#define JMR3927_IOC_INTB_PCIB	1
#define JMR3927_IOC_INTB_PCIC	2
#define JMR3927_IOC_INTB_PCID	3
#define JMR3927_IOC_INTB_MODEM	4
#define JMR3927_IOC_INTB_INT6	5
#define JMR3927_IOC_INTB_INT7	6
#define JMR3927_IOC_INTB_SOFT	7
#define JMR3927_IOC_INTF_PCIA	(1 << JMR3927_IOC_INTF_PCIA)
#define JMR3927_IOC_INTF_PCIB	(1 << JMR3927_IOC_INTB_PCIB)
#define JMR3927_IOC_INTF_PCIC	(1 << JMR3927_IOC_INTB_PCIC)
#define JMR3927_IOC_INTF_PCID	(1 << JMR3927_IOC_INTB_PCID)
#define JMR3927_IOC_INTF_MODEM	(1 << JMR3927_IOC_INTB_MODEM)
#define JMR3927_IOC_INTF_INT6	(1 << JMR3927_IOC_INTB_INT6)
#define JMR3927_IOC_INTF_INT7	(1 << JMR3927_IOC_INTB_INT7)
#define JMR3927_IOC_INTF_SOFT	(1 << JMR3927_IOC_INTB_SOFT)

/* bits for IOC_RESET (high byte) */
#define JMR3927_IOC_RESET_CPU	1
#define JMR3927_IOC_RESET_PCI	2

/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */
#define JMR3927_ISAC_EINTB_IOCHK	2
#define JMR3927_ISAC_EINTB_BWTH	4
#define JMR3927_ISAC_EINTF_IOCHK	(1 << JMR3927_ISAC_EINTB_IOCHK)
#define JMR3927_ISAC_EINTF_BWTH	(1 << JMR3927_ISAC_EINTB_BWTH)

/* bits for ISAC_LED (high byte) */
#define JMR3927_ISAC_LED_ISALED	0x01
#define JMR3927_ISAC_LED_USRLED	0x02

/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */
#define JMR3927_ISAC_INTB_IRQ5	0
#define JMR3927_ISAC_INTB_IRQKB	1
#define JMR3927_ISAC_INTB_IRQMOUSE	2
#define JMR3927_ISAC_INTB_IRQ4	3
#define JMR3927_ISAC_INTB_IRQ12	4
#define JMR3927_ISAC_INTB_IRQ3	5
#define JMR3927_ISAC_INTB_IRQ10	6
#define JMR3927_ISAC_INTB_ISAER	7
#define JMR3927_ISAC_INTF_IRQ5	(1 << JMR3927_ISAC_INTB_IRQ5)
#define JMR3927_ISAC_INTF_IRQKB	(1 << JMR3927_ISAC_INTB_IRQKB)
#define JMR3927_ISAC_INTF_IRQMOUSE	(1 << JMR3927_ISAC_INTB_IRQMOUSE)
#define JMR3927_ISAC_INTF_IRQ4	(1 << JMR3927_ISAC_INTB_IRQ4)
#define JMR3927_ISAC_INTF_IRQ12	(1 << JMR3927_ISAC_INTB_IRQ12)
#define JMR3927_ISAC_INTF_IRQ3	(1 << JMR3927_ISAC_INTB_IRQ3)
#define JMR3927_ISAC_INTF_IRQ10	(1 << JMR3927_ISAC_INTB_IRQ10)
#define JMR3927_ISAC_INTF_ISAER	(1 << JMR3927_ISAC_INTB_ISAER)

#ifndef _LANGUAGE_ASSEMBLY

#if 0
#define jmr3927_ioc_reg_out(d, a)	((*(volatile unsigned short *)(a)) = (d) << 8)
#define jmr3927_ioc_reg_in(a)		(((*(volatile unsigned short *)(a)) >> 8) & 0xff)
#else
#if defined(__BIG_ENDIAN)
#define jmr3927_ioc_reg_out(d, a)	((*(volatile unsigned char *)(a)) = (d))
#define jmr3927_ioc_reg_in(a)		(*(volatile unsigned char *)(a))
#elif defined(__LITTLE_ENDIAN)
#define jmr3927_ioc_reg_out(d, a)	((*(volatile unsigned char *)((a)^1)) = (d))
#define jmr3927_ioc_reg_in(a)		(*(volatile unsigned char *)((a)^1))
#else
#error "No Endian"
#endif
#endif
#define jmr3927_isac_reg_out(d, a)	((*(volatile unsigned char *)(a)) = (d))
#define jmr3927_isac_reg_in(a)		(*(volatile unsigned char *)(a))

extern inline int jmr3927_have_isac(void)
{
	unsigned char idt;
	unsigned long flags;
	unsigned long romcr3;
	save_and_cli(flags);
	romcr3 = tx3927_romcptr->cr[3];
	tx3927_romcptr->cr[3] &= 0xffffefff;	/* do not wait infinitely */
	idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK;
	tx3927_romcptr->cr[3] = romcr3;
	restore_flags(flags);
	return idt == JMR3927_ISAC_IDT;
}
#define jmr3927_have_nvram() \
	((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT)

/* NVRAM macro */
#define jmr3927_nvram_in(ofs) \
	jmr3927_ioc_reg_in(JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))
#define jmr3927_nvram_out(d, ofs) \
	jmr3927_ioc_reg_out(d, JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))

/* LED macro */
#define jmr3927_led_set(n/*0-16*/)	jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
#define jmr3927_io_led_set(n/*0-3*/)	jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)

#define jmr3927_led_and_set(n/*0-16*/)	jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)

/* DIPSW4 macro */
#define jmr3927_dipsw1()	((tx3927_pioptr->din & (1 << 11)) == 0)
#define jmr3927_dipsw2()	((tx3927_pioptr->din & (1 << 10)) == 0)
#define jmr3927_dipsw3()	((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
#define jmr3927_dipsw4()	((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
#define jmr3927_io_dipsw()	(jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4)


#endif /* _LANGUAGE_ASSEMBLY */

/*
 * UART defines for serial.h
 */

/* use Pre-scaler T0 (1/2) */
#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)

#define UART0_ADDR   0xfffef300
#define UART1_ADDR   0xfffef400
#define UART0_INT    JMR3927_IRQ_IRC_SIO0
#define UART1_INT    JMR3927_IRQ_IRC_SIO1
#define UART0_FLAGS  ASYNC_BOOT_AUTOCONF
#define UART1_FLAGS  0

/*
 * IRQ mappings
 */

/* These are the virtual IRQ numbers, we divide all IRQ's into
 * 'spaces', the 'space' determines where and how to enable/disable
 * that particular IRQ on an JMR machine.  Add new 'spaces' as new
 * IRQ hardware is supported.
 */
#define JMR3927_NR_IRQ_IRC	16	/* On-Chip IRC */
#define JMR3927_NR_IRQ_IOC	8	/* PCI/MODEM/INT[6:7] */
#define JMR3927_NR_IRQ_ISAC	8	/* ISA */


#define JMR3927_IRQ_IRC	NR_ISA_IRQS
#define JMR3927_IRQ_IOC	(JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
#define JMR3927_IRQ_ISAC	(JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
#define JMR3927_IRQ_END	(JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC)
#define JMR3927_IRQ_IS_IRC(irq)	(JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC)
#define JMR3927_IRQ_IS_IOC(irq)		(JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC)
#define JMR3927_IRQ_IS_ISAC(irq)	(JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END)

#define JMR3927_IRQ_IRC_INT0	(JMR3927_IRQ_IRC + TX3927_IR_INT0)
#define JMR3927_IRQ_IRC_INT1	(JMR3927_IRQ_IRC + TX3927_IR_INT1)
#define JMR3927_IRQ_IRC_INT2	(JMR3927_IRQ_IRC + TX3927_IR_INT2)
#define JMR3927_IRQ_IRC_INT3	(JMR3927_IRQ_IRC + TX3927_IR_INT3)
#define JMR3927_IRQ_IRC_INT4	(JMR3927_IRQ_IRC + TX3927_IR_INT4)
#define JMR3927_IRQ_IRC_INT5	(JMR3927_IRQ_IRC + TX3927_IR_INT5)
#define JMR3927_IRQ_IRC_SIO0	(JMR3927_IRQ_IRC + TX3927_IR_SIO0)
#define JMR3927_IRQ_IRC_SIO1	(JMR3927_IRQ_IRC + TX3927_IR_SIO1)
#define JMR3927_IRQ_IRC_SIO(ch)	(JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
#define JMR3927_IRQ_IRC_DMA	(JMR3927_IRQ_IRC + TX3927_IR_DMA)
#define JMR3927_IRQ_IRC_PIO	(JMR3927_IRQ_IRC + TX3927_IR_PIO)
#define JMR3927_IRQ_IRC_PCI	(JMR3927_IRQ_IRC + TX3927_IR_PCI)
#define JMR3927_IRQ_IRC_TMR0	(JMR3927_IRQ_IRC + TX3927_IR_TMR0)
#define JMR3927_IRQ_IRC_TMR1	(JMR3927_IRQ_IRC + TX3927_IR_TMR1)
#define JMR3927_IRQ_IRC_TMR2	(JMR3927_IRQ_IRC + TX3927_IR_TMR2)
#define JMR3927_IRQ_IOC_PCIA	(JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
#define JMR3927_IRQ_IOC_PCIB	(JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
#define JMR3927_IRQ_IOC_PCIC	(JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
#define JMR3927_IRQ_IOC_PCID	(JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
#define JMR3927_IRQ_IOC_MODEM	(JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
#define JMR3927_IRQ_IOC_INT6	(JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
#define JMR3927_IRQ_IOC_INT7	(JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
#define JMR3927_IRQ_IOC_SOFT	(JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
#define JMR3927_IRQ_ISAC_IRQ5	(JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5)
#define JMR3927_IRQ_ISAC_IRQKB	(JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB)
#define JMR3927_IRQ_ISAC_IRQMOUSE	(JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE)
#define JMR3927_IRQ_ISAC_IRQ4	(JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4)
#define JMR3927_IRQ_ISAC_IRQ12	(JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12)
#define JMR3927_IRQ_ISAC_IRQ3	(JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3)
#define JMR3927_IRQ_ISAC_IRQ10	(JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10)
#define JMR3927_IRQ_ISAC_ISAER	(JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER)

#if 0	/* auto detect */
/* RTL8019AS 10M Ether (JMI-3927IO2:JPW2:1-2 Short) */
#define JMR3927_IRQ_ETHER1	JMR3927_IRQ_IRC_INT0
#endif
/* IOC (PCI, MODEM) */
#define JMR3927_IRQ_IOCINT	JMR3927_IRQ_IRC_INT1
/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */
#define JMR3927_IRQ_ISACINT	JMR3927_IRQ_IRC_INT2
/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
#define JMR3927_IRQ_ETHER0	JMR3927_IRQ_IRC_INT3
/* Clock Tick (10ms) */
#define JMR3927_IRQ_TICK	JMR3927_IRQ_IRC_TMR0
#define JMR3927_IRQ_IDE		JMR3927_IRQ_ISAC_IRQ12

/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */
#define JMR3927_IRQ_PREMIER3	JMR3927_IRQ_IRC_INT0

/* I/O Ports */
/* RTL8019AS 10M Ether */
#define JMR3927_ETHER1_PORT	(JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280)
#define JMR3927_KBD_PORT	(JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060)
#define JMR3927_IDE_PORT	(JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0)

/* Clocks */
#define JMR3927_CORECLK	132710400	/* 132.7MHz */
#define JMR3927_GBUSCLK	(JMR3927_CORECLK / 2)	/* 66.35MHz */
#define JMR3927_IMCLK	(JMR3927_CORECLK / 4)	/* 33.17MHz */

#define jmr3927_tmrptr		tx3927_tmrptr(0)	/* TMR0 */


/*
 * TX3927 Pin Configuration:
 *
 *	PCFG bits		Avail			Dead
 *	SELSIO[1:0]:11		RXD[1:0], TXD[1:0]	PIO[6:3]
 *	SELSIOC[0]:1		CTS[0], RTS[0]		INT[5:4]
 *	SELSIOC[1]:0,SELDSF:0,	GSDAO[0],GPCST[3]	CTS[1], RTS[1],DSF,
 *	  GDBGE*					  PIO[2:1]
 *	SELDMA[2]:1		DMAREQ[2],DMAACK[2]	PIO[13:12]
 *	SELTMR[2:0]:000					TIMER[1:0]
 *	SELCS:0,SELDMA[1]:0	PIO[11;10]		SDCS_CE[7:6],
 *							  DMAREQ[1],DMAACK[1]
 *	SELDMA[0]:1		DMAREQ[0],DMAACK[0]	PIO[9:8]
 *	SELDMA[3]:1		DMAREQ[3],DMAACK[3]	PIO[15:14]
 *	SELDONE:1		DMADONE			PIO[7]
 *
 * Usable pins are:
 *	RXD[1;0],TXD[1:0],CTS[0],RTS[0],
 *	DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
 *	INT[3:0]
 */

#endif /* __ASM_MIPS_TX3927_JMR3927_H */

--- NEW FILE: pci.h ---
/***********************************************************************
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahe...@mv...       
 *
 * include/asm-mips/jmr3927/pci.h
 * Based on include/asm-mips/ddb5xxx/pci.h
 *
 * This file essentially defines the interface between board
 * specific PCI code and MIPS common PCI code.  Should potentially put
 * into include/asm/pci.h file.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 ***********************************************************************
 */

#ifndef __ASM_TX3927_PCI_H
#define __ASM_TX3927__PCI_H

#include <linux/ioport.h>
#include <linux/pci.h>

/*
 * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
 * multiple PCI channels may have multiple PCI host controllers or a
 * single controller supporting multiple channels.
 */
struct pci_channel {
	struct pci_ops *pci_ops;
	struct resource *io_resource;
	struct resource *mem_resource;
};

/* 
 * each board defines an array of pci_channels, that ends with all NULL entry
 */
extern struct pci_channel mips_pci_channels[];

/*
 * board supplied pci irq fixup routine
 */
extern void pcibios_fixup_irqs(void);

#endif  /* __ASM_TX3927_PCI_H */

--- NEW FILE: tx3927.h ---
/* $Id: tx3927.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Toshiba Corporation
 */
#ifndef __ASM_MIPS_TX3927_H 
#define __ASM_MIPS_TX3927_H 

#include <asm/jmr3927/txx927.h>

#define TX3927_SDRAMC_REG	0xfffe8000
#define TX3927_ROMC_REG		0xfffe9000
#define TX3927_DMA_REG		0xfffeb000
#define TX3927_IRC_REG		0xfffec000
#define TX3927_PCIC_REG		0xfffed000
#define TX3927_CCFG_REG		0xfffee000
#define TX3927_NR_TMR	3
#define TX3927_TMR_REG(ch)	(0xfffef000 + (ch) * 0x100)
#define TX3927_NR_SIO	2
#define TX3927_SIO_REG(ch)	(0xfffef300 + (ch) * 0x100)
#define TX3927_PIO_REG		0xfffef500

#ifndef _LANGUAGE_ASSEMBLY

struct tx3927_sdramc_reg {
	volatile unsigned long cr[8];
	volatile unsigned long tr[3];
	volatile unsigned long cmd;
	volatile unsigned long smrs[2];
};

struct tx3927_romc_reg {
	volatile unsigned long cr[8];
};

struct tx3927_dma_reg {
	struct tx3927_dma_ch_reg {
		volatile unsigned long cha;
		volatile unsigned long sar;
		volatile unsigned long dar;
		volatile unsigned long cntr;
		volatile unsigned long sair;
		volatile unsigned long dair;
		volatile unsigned long ccr;
		volatile unsigned long csr;
	} ch[4];
	volatile unsigned long dbr[8];
	volatile unsigned long tdhr;
	volatile unsigned long mcr;
	volatile unsigned long unused0;
};

struct tx3927_irc_reg {
	volatile unsigned long cer;
	volatile unsigned long cr[2];
	volatile unsigned long unused0;
	volatile unsigned long ilr[8];
	volatile unsigned long unused1[4];
	volatile unsigned long imr;
	volatile unsigned long unused2[7];
	volatile unsigned long scr;
	volatile unsigned long unused3[7];
	volatile unsigned long ssr;
	volatile unsigned long unused4[7];
	volatile unsigned long csr;
};

#include <asm/byteorder.h>

#ifdef __BIG_ENDIAN
#define endian_def_s2(e1,e2)	\
	volatile unsigned short e1,e2
#define endian_def_sb2(e1,e2,e3)	\
	volatile unsigned short e1;volatile unsigned char e2,e3
#define endian_def_b2s(e1,e2,e3)	\
	volatile unsigned char e1,e2;volatile unsigned short e3
#define endian_def_b4(e1,e2,e3,e4)	\
	volatile unsigned char e1,e2,e3,e4
#else
#define endian_def_s2(e1,e2)	\
	volatile unsigned short e2,e1
#define endian_def_sb2(e1,e2,e3)	\
	volatile unsigned char e3,e2;volatile unsigned short e1
#define endian_def_b2s(e1,e2,e3)	\
	volatile unsigned short e3;volatile unsigned char e2,e1
#define endian_def_b4(e1,e2,e3,e4)	\
	volatile unsigned char e4,e3,e2,e1
#endif

struct tx3927_pcic_reg {
	endian_def_s2(did, vid);
	endian_def_s2(pcistat, pcicmd);
	endian_def_b4(cc, scc, rpli, rid);
	endian_def_b4(unused0, ht, mlt, cls);
	volatile unsigned long ioba;		/* +10 */
	volatile unsigned long mba;
	volatile unsigned long unused1[5];
	endian_def_s2(svid, ssvid);
	volatile unsigned long unused2;		/* +30 */
	endian_def_sb2(unused3, unused4, capptr);
	volatile unsigned long unused5;
	endian_def_b4(ml, mg, ip, il);
	volatile unsigned long unused6;		/* +40 */
	volatile unsigned long istat;
	volatile unsigned long iim;
	volatile unsigned long rrt;
	volatile unsigned long unused7[3];		/* +50 */
	volatile unsigned long ipbmma;
	volatile unsigned long ipbioma;		/* +60 */
	volatile unsigned long ilbmma;
	volatile unsigned long ilbioma;
	volatile unsigned long unused8[9];
	volatile unsigned long tc;		/* +90 */
	volatile unsigned long tstat;
	volatile unsigned long tim;
	volatile unsigned long tccmd;
	volatile unsigned long pcirrt;		/* +a0 */
	volatile unsigned long pcirrt_cmd;
	volatile unsigned long pcirrdt;
	volatile unsigned long unused9[3];
	volatile unsigned long tlboap;
	volatile unsigned long tlbiap;
	volatile unsigned long tlbmma;		/* +c0 */
	volatile unsigned long tlbioma;
	volatile unsigned long sc_msg;
	volatile unsigned long sc_be;
	volatile unsigned long tbl;		/* +d0 */
	volatile unsigned long unused10[3];
	volatile unsigned long pwmng;		/* +e0 */
	volatile unsigned long pwmngs;
	volatile unsigned long unused11[6];
	volatile unsigned long req_trace;		/* +100 */
	volatile unsigned long pbapmc;
	volatile unsigned long pbapms;
	volatile unsigned long pbapmim;
	volatile unsigned long bm;		/* +110 */
	volatile unsigned long cpcibrs;
	volatile unsigned long cpcibgs;
	volatile unsigned long pbacs;
	volatile unsigned long iobas;		/* +120 */
	volatile unsigned long mbas;
	volatile unsigned long lbc;
	volatile unsigned long lbstat;
	volatile unsigned long lbim;		/* +130 */
	volatile unsigned long pcistatim;
	volatile unsigned long ica;
	volatile unsigned long icd;
	volatile unsigned long iiadp;		/* +140 */
	volatile unsigned long iscdp;
	volatile unsigned long mmas;
	volatile unsigned long iomas;
	volatile unsigned long ipciaddr;		/* +150 */
	volatile unsigned long ipcidata;
	volatile unsigned long ipcibe;
};

struct tx3927_ccfg_reg {
	volatile unsigned long ccfg;
	volatile unsigned long crir;
	volatile unsigned long pcfg;
	volatile unsigned long tear;
	volatile unsigned long pdcr;
};

#endif /* _LANGUAGE_ASSEMBLY */

/*
 * SDRAMC
 */

/*
 * ROMC
 */

/*
 * DMA
 */
/* bits for MCR */
#define TX3927_DMA_MCR_EIS(ch)	(0x10000000<<(ch))
#define TX3927_DMA_MCR_DIS(ch)	(0x01000000<<(ch))
#define TX3927_DMA_MCR_RSFIF	0x00000080
#define TX3927_DMA_MCR_FIFUM(ch)	(0x00000008<<(ch))
#define TX3927_DMA_MCR_LE	0x00000004
#define TX3927_DMA_MCR_RPRT	0x00000002
#define TX3927_DMA_MCR_MSTEN	0x00000001

/* bits for CCRn */
#define TX3927_DMA_CCR_DBINH	0x04000000
#define TX3927_DMA_CCR_SBINH	0x02000000
#define TX3927_DMA_CCR_CHRST	0x01000000
#define TX3927_DMA_CCR_RVBYTE	0x00800000
#define TX3927_DMA_CCR_ACKPOL	0x00400000
#define TX3927_DMA_CCR_REQPL	0x00200000
#define TX3927_DMA_CCR_EGREQ	0x00100000
#define TX3927_DMA_CCR_CHDN	0x00080000
#define TX3927_DMA_CCR_DNCTL	0x00060000
#define TX3927_DMA_CCR_EXTRQ	0x00010000
#define TX3927_DMA_CCR_INTRQD	0x0000e000
#define TX3927_DMA_CCR_INTENE	0x00001000
#define TX3927_DMA_CCR_INTENC	0x00000800
#define TX3927_DMA_CCR_INTENT	0x00000400
#define TX3927_DMA_CCR_CHNEN	0x00000200
#define TX3927_DMA_CCR_XFACT	0x00000100
#define TX3927_DMA_CCR_SNOP	0x00000080
#define TX3927_DMA_CCR_DSTINC	0x00000040
#define TX3927_DMA_CCR_SRCINC	0x00000020
#define TX3927_DMA_CCR_XFSZ(order)	(((order) << 2) & 0x0000001c)
#define TX3927_DMA_CCR_XFSZ_1W	TX3927_DMA_CCR_XFSZ(2)
#define TX3927_DMA_CCR_XFSZ_4W	TX3927_DMA_CCR_XFSZ(4)
#define TX3927_DMA_CCR_XFSZ_8W	TX3927_DMA_CCR_XFSZ(5)
#define TX3927_DMA_CCR_XFSZ_16W	TX3927_DMA_CCR_XFSZ(6)
#define TX3927_DMA_CCR_XFSZ_32W	TX3927_DMA_CCR_XFSZ(7)
#define TX3927_DMA_CCR_MEMIO	0x00000002
#define TX3927_DMA_CCR_ONEAD	0x00000001

/* bits for CSRn */
#define TX3927_DMA_CSR_CHNACT	0x00000100
#define TX3927_DMA_CSR_ABCHC	0x00000080
#define TX3927_DMA_CSR_NCHNC	0x00000040
#define TX3927_DMA_CSR_NTRNFC	0x00000020
#define TX3927_DMA_CSR_EXTDN	0x00000010
#define TX3927_DMA_CSR_CFERR	0x00000008
#define TX3927_DMA_CSR_CHERR	0x00000004
#define TX3927_DMA_CSR_DESERR	0x00000002
#define TX3927_DMA_CSR_SORERR	0x00000001

/*
 * IRC
 */
#define TX3927_IR_MAX_LEVEL	7

/* IRCER : Int. Control Enable */
#define TX3927_IRCER_ICE	0x00000001

/* IRCR : Int. Control */
#define TX3927_IRCR_LOW	0x00000000
#define TX3927_IRCR_HIGH	0x00000001
#define TX3927_IRCR_DOWN	0x00000002
#define TX3927_IRCR_UP	0x00000003

/* IRSCR : Int. Status Control */
#define TX3927_IRSCR_EIClrE	0x00000100
#define TX3927_IRSCR_EIClr_MASK	0x0000000f

/* IRCSR : Int. Current Status */
#define TX3927_IRCSR_IF	0x00010000
#define TX3927_IRCSR_ILV_MASK	0x00000700
#define TX3927_IRCSR_IVL_MASK	0x0000001f

#define TX3927_IR_INT0	0
#define TX3927_IR_INT1	1
#define TX3927_IR_INT2	2
#define TX3927_IR_INT3	3
#define TX3927_IR_INT4	4
#define TX3927_IR_INT5	5
#define TX3927_IR_SIO0	6
#define TX3927_IR_SIO1	7
#define TX3927_IR_SIO(ch)	(6 + (ch))
#define TX3927_IR_DMA	8
#define TX3927_IR_PIO	9
#define TX3927_IR_PCI	10
#define TX3927_IR_TMR0	13
#define TX3927_IR_TMR1	14
#define TX3927_IR_TMR2	15
#define TX3927_NUM_IR	16

/*
 * PCIC
 */
/* bits for PCICMD */
/* see PCI_COMMAND_XXX in linux/pci.h */

/* bits for PCISTAT */
/* see PCI_STATUS_XXX in linux/pci.h */
#define PCI_STATUS_NEW_CAP	0x0010

/* bits for TC */
#define TX3927_PCIC_TC_OF16E	0x00000020
#define TX3927_PCIC_TC_IF8E	0x00000010
#define TX3927_PCIC_TC_OF8E	0x00000008

/* bits for IOBA/MBA */
/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */

/* bits for PBAPMC */
#define TX3927_PCIC_PBAPMC_RPBA	0x00000004
#define TX3927_PCIC_PBAPMC_PBAEN	0x00000002
#define TX3927_PCIC_PBAPMC_BMCEN	0x00000001

/* bits for LBSTAT/LBIM */
#define TX3927_PCIC_LBIM_ALL	0x0000003e

/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
#define TX3927_PCIC_PCISTATIM_ALL	0x0000f900

/* bits for LBC */
#define TX3927_PCIC_LBC_IBSE	0x00004000
#define TX3927_PCIC_LBC_TIBSE	0x00002000
#define TX3927_PCIC_LBC_TMFBSE	0x00001000
#define TX3927_PCIC_LBC_HRST	0x00000800
#define TX3927_PCIC_LBC_SRST	0x00000400
#define TX3927_PCIC_LBC_EPCAD	0x00000200
#define TX3927_PCIC_LBC_MSDSE	0x00000100
#define TX3927_PCIC_LBC_CRR	0x00000080
#define TX3927_PCIC_LBC_ILMDE	0x00000040
#define TX3927_PCIC_LBC_ILIDE	0x00000020

#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad)	((ad) - 11)
#define TX3927_PCIC_MAX_DEVNU	TX3927_PCIC_IDSEL_AD_TO_SLOT(32)

/*
 * CCFG
 */
/* CCFG : Chip Configuration */
#define TX3927_CCFG_TLBOFF	0x00020000
#define TX3927_CCFG_BEOW	0x00010000
#define TX3927_CCFG_WR	0x00008000
#define TX3927_CCFG_TOE	0x00004000
#define TX3927_CCFG_PCIXARB	0x00002000
#define TX3927_CCFG_PCI3	0x00001000
#define TX3927_CCFG_PSNP	0x00000800
#define TX3927_CCFG_PPRI	0x00000400
#define TX3927_CCFG_PLLM	0x00000030
#define TX3927_CCFG_ENDIAN	0x00000004
#define TX3927_CCFG_HALT	0x00000002
#define TX3927_CCFG_ACEHOLD	0x00000001

/* PCFG : Pin Configuration */
#define TX3927_PCFG_SYSCLKEN	0x08000000
#define TX3927_PCFG_SDRCLKEN_ALL	0x07c00000
#define TX3927_PCFG_SDRCLKEN(ch)	(0x00400000<<(ch))
#define TX3927_PCFG_PCICLKEN_ALL	0x003c0000
#define TX3927_PCFG_PCICLKEN(ch)	(0x00040000<<(ch))
#define TX3927_PCFG_SELALL	0x0003ffff
#define TX3927_PCFG_SELCS	0x00020000
#define TX3927_PCFG_SELDSF	0x00010000
#define TX3927_PCFG_SELSIOC_ALL	0x0000c000
#define TX3927_PCFG_SELSIOC(ch)	(0x00004000<<(ch))
#define TX3927_PCFG_SELSIO_ALL	0x00003000
#define TX3927_PCFG_SELSIO(ch)	(0x00001000<<(ch))
#define TX3927_PCFG_SELTMR_ALL	0x00000e00
#define TX3927_PCFG_SELTMR(ch)	(0x00000200<<(ch))
#define TX3927_PCFG_SELDONE	0x00000100
#define TX3927_PCFG_INTDMA_ALL	0x000000f0
#define TX3927_PCFG_INTDMA(ch)	(0x00000010<<(ch))
#define TX3927_PCFG_SELDMA_ALL	0x0000000f
#define TX3927_PCFG_SELDMA(ch)	(0x00000001<<(ch))

#ifndef _LANGUAGE_ASSEMBLY

#define tx3927_sdramcptr	((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
#define tx3927_romcptr		((struct tx3927_romc_reg *)TX3927_ROMC_REG)
#define tx3927_dmaptr		((struct tx3927_dma_reg *)TX3927_DMA_REG)
#define tx3927_ircptr		((struct tx3927_irc_reg *)TX3927_IRC_REG)
#define tx3927_pcicptr		((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
#define tx3927_ccfgptr		((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
#define tx3927_tmrptr(ch)	((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
#define tx3927_sioptr(ch)	((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
#define tx3927_pioptr		((struct txx927_pio_reg *)TX3927_PIO_REG)

#endif /* _LANGUAGE_ASSEMBLY */

#endif /* __ASM_MIPS_TX3927_H */

--- NEW FILE: txx927.h ---
/* $Id: txx927.h,v 1.1 2001/11/10 03:54:08 jsimmons Exp $
 * Common difinitins for TX3927/TX4927
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Toshiba Corporation
 */
#ifndef __ASM_MIPS_TXX927_H 
#define __ASM_MIPS_TXX927_H 

#ifndef _LANGUAGE_ASSEMBLY

struct txx927_tmr_reg {
	volatile unsigned long tcr;
	volatile unsigned long tisr;
	volatile unsigned long cpra;
	volatile unsigned long cprb;
	volatile unsigned long itmr;
	volatile unsigned long unused0[3];
	volatile unsigned long ccdr;
	volatile unsigned long unused1[3];
	volatile unsigned long pgmr;
	volatile unsigned long unused2[3];
	volatile unsigned long wtmr;
	volatile unsigned long unused3[43];
	volatile unsigned long trr;
};

struct txx927_sio_reg {
	volatile unsigned long lcr;
	volatile unsigned long dicr;
	volatile unsigned long disr;
	volatile unsigned long cisr;
	volatile unsigned long fcr;
	volatile unsigned long flcr;
	volatile unsigned long bgr;
	volatile unsigned long tfifo;
	volatile unsigned long rfifo;
};

struct txx927_pio_reg {
	volatile unsigned long dout;
	volatile unsigned long din;
	volatile unsigned long dir;
	volatile unsigned long od;
	volatile unsigned long flag[2];
	volatile unsigned long pol;
	volatile unsigned long intc;
	volatile unsigned long maskcpu;
	volatile unsigned long maskext;
};

#endif /* _LANGUAGE_ASSEMBLY */


/*
 * TMR
 */
/* TMTCR : Timer Control */
#define TXx927_TMTCR_TCE	0x00000080
#define TXx927_TMTCR_CCDE	0x00000040
#define TXx927_TMTCR_CRE	0x00000020
#define TXx927_TMTCR_ECES	0x00000008
#define TXx927_TMTCR_CCS	0x00000004
#define TXx927_TMTCR_TMODE_MASK	0x00000003
#define TXx927_TMTCR_TMODE_ITVL	0x00000000

/* TMTISR : Timer Int. Status */
#define TXx927_TMTISR_TPIBS	0x00000004
#define TXx927_TMTISR_TPIAS	0x00000002
#define TXx927_TMTISR_TIIS	0x00000001

/* TMTITMR : Interval Timer Mode */
#define TXx927_TMTITMR_TIIE	0x00008000
#define TXx927_TMTITMR_TZCE	0x00000001

/*
 * SIO
 */
/* SILCR : Line Control */
#define TXx927_SILCR_SCS_MASK	0x00000060
#define TXx927_SILCR_SCS_IMCLK	0x00000000
#define TXx927_SILCR_SCS_IMCLK_BG	0x00000020
#define TXx927_SILCR_SCS_SCLK	0x00000040
#define TXx927_SILCR_SCS_SCLK_BG	0x00000060
#define TXx927_SILCR_UEPS	0x00000010
#define TXx927_SILCR_UPEN	0x00000008
#define TXx927_SILCR_USBL_MASK	0x00000004
#define TXx927_SILCR_USBL_1BIT	0x00000004
#define TXx927_SILCR_USBL_2BIT	0x00000000
#define TXx927_SILCR_UMODE_MASK	0x00000003
#define TXx927_SILCR_UMODE_8BIT	0x00000000
#define TXx927_SILCR_UMODE_7BIT	0x00000001

/* SIDICR : DMA/Int. Control */
#define TXx927_SIDICR_TDE	0x00008000
#define TXx927_SIDICR_RDE	0x00004000
#define TXx927_SIDICR_TIE	0x00002000
#define TXx927_SIDICR_RIE	0x00001000
#define TXx927_SIDICR_SPIE	0x00000800
#define TXx927_SIDICR_CTSAC	0x00000600
#define TXx927_SIDICR_STIE_MASK	0x0000003f
#define TXx927_SIDICR_STIE_OERS		0x00000020
#define TXx927_SIDICR_STIE_CTSS		0x00000010
#define TXx927_SIDICR_STIE_RBRKD	0x00000008
#define TXx927_SIDICR_STIE_TRDY		0x00000004
#define TXx927_SIDICR_STIE_TXALS	0x00000002
#define TXx927_SIDICR_STIE_UBRKD	0x00000001

/* SIDISR : DMA/Int. Status */
#define TXx927_SIDISR_UBRK	0x00008000
#define TXx927_SIDISR_UVALID	0x00004000
#define TXx927_SIDISR_UFER	0x00002000
#define TXx927_SIDISR_UPER	0x00001000
#define TXx927_SIDISR_UOER	0x00000800
#define TXx927_SIDISR_ERI	0x00000400
#define TXx927_SIDISR_TOUT	0x00000200
#define TXx927_SIDISR_TDIS	0x00000100
#define TXx927_SIDISR_RDIS	0x00000080
#define TXx927_SIDISR_STIS	0x00000040
#define TXx927_SIDISR_RFDN_MASK	0x0000001f

/* SICISR : Change Int. Status */
#define TXx927_SICISR_OERS	0x00000020
#define TXx927_SICISR_CTSS	0x00000010
#define TXx927_SICISR_RBRKD	0x00000008
#define TXx927_SICISR_TRDY	0x00000004
#define TXx927_SICISR_TXALS	0x00000002
#define TXx927_SICISR_UBRKD	0x00000001

/* SIFCR : FIFO Control */
#define TXx927_SIFCR_SWRST	0x00008000
#define TXx927_SIFCR_RDIL_MASK	0x00000180
#define TXx927_SIFCR_RDIL_1	0x00000000
#define TXx927_SIFCR_RDIL_4	0x00000080
#define TXx927_SIFCR_RDIL_8	0x00000100
#define TXx927_SIFCR_RDIL_12	0x00000180
#define TXx927_SIFCR_RDIL_MAX	0x00000180
#define TXx927_SIFCR_TDIL_MASK	0x00000018
#define TXx927_SIFCR_TDIL_MASK	0x00000018
#define TXx927_SIFCR_TDIL_1	0x00000000
#define TXx927_SIFCR_TDIL_4	0x00000001
#define TXx927_SIFCR_TDIL_8	0x00000010
#define TXx927_SIFCR_TDIL_MAX	0x00000010
#define TXx927_SIFCR_TFRST	0x00000004
#define TXx927_SIFCR_RFRST	0x00000002
#define TXx927_SIFCR_FRSTE	0x00000001
#define TXx927_SIO_TX_FIFO	8
#define TXx927_SIO_RX_FIFO	16

/* SIFLCR : Flow Control */
#define TXx927_SIFLCR_RCS	0x00001000
#define TXx927_SIFLCR_TES	0x00000800
#define TXx927_SIFLCR_RTSSC	0x00000200
#define TXx927_SIFLCR_RSDE	0x00000100
#define TXx927_SIFLCR_TSDE	0x00000080
#define TXx927_SIFLCR_RTSTL_MASK	0x0000001e
#define TXx927_SIFLCR_RTSTL_MAX	0x0000001e
#define TXx927_SIFLCR_TBRK	0x00000001

/* SIBGR : Baudrate Control */
#define TXx927_SIBGR_BCLK_MASK	0x00000300
#define TXx927_SIBGR_BCLK_T0	0x00000000
#define TXx927_SIBGR_BCLK_T2	0x00000100
#define TXx927_SIBGR_BCLK_T4	0x00000200
#define TXx927_SIBGR_BCLK_T6	0x00000300
#define TXx927_SIBGR_BRD_MASK	0x000000ff

/*
 * PIO
 */

#endif /* __ASM_MIPS_TXX927_H */

[Linux-mips-commits]CVS: linux/include/asm-mips/jmr3927 - New directory

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/jmr3927
In directory usw-pr-cvs1:/tmp/cvs-serv21042/jmr3927

Log Message:
Directory /cvsroot/linux-mips/linux/include/asm-mips/jmr3927 added to the repository

[Linux-mips-commits]CVS: linux/include/asm-mips bootinfo.h,1.11,1.12 serial.h,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv20843/include/asm-mips

Modified Files:
	bootinfo.h serial.h 
Log Message:
Imported support for JMR-TX3927 by Alice Hennessy. Thank you.

Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- bootinfo.h	2001/10/31 17:28:54	1.11
+++ bootinfo.h	2001/11/10 03:52:49	1.12
@@ -187,8 +187,9 @@
 #define MACH_PALLAS		0
 #define MACH_TOPAS		1
 #define MACH_JMR		2
+#define MACH_TOSHIBA_JMR3927    3      /* JMR-TX3927 CPU/IO board */
 
-#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR" }
+#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927" }
 
 /*
  * Valid machtype for group Alchemy

Index: serial.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/serial.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- serial.h	2001/10/26 22:36:04	1.3
+++ serial.h	2001/11/10 03:52:49	1.4
@@ -160,6 +160,17 @@
 #define AU1000_SERIAL_PORT_DEFNS
 #endif
 
+#ifdef CONFIG_TOSHIBA_JMR3927
+#include <asm/jmr3927/jmr3927.h>
+#define TXX927_SERIAL_PORT_DEFNS                              \
+    { baud_base: JMR3927_BASE_BAUD, port: UART0_ADDR, irq: UART0_INT,  \
+      flags: UART0_FLAGS, type: 1 },                        \
+    { baud_base: JMR3927_BASE_BAUD, port: UART1_ADDR, irq: UART1_INT,  \
+      flags: UART1_FLAGS, type: 1 },     
+#else
+#define TXX927_SERIAL_PORT_DEFNS
+#endif
+
 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
 #define STD_SERIAL_PORT_DEFNS			\
 	/* UART CLK   PORT IRQ     FLAGS        */			\
@@ -281,4 +292,5 @@
 	HUB6_SERIAL_PORT_DFNS		\
 	MOMENCO_OCELOT_SERIAL_PORT_DEFNS\
 	AU1000_SERIAL_PORT_DEFNS	\
+        TXX927_SERIAL_PORT_DEFNS        \
 	DDB5477_SERIAL_PORT_DEFNS

[Linux-mips-commits]CVS: linux/drivers/net tc35815.c,NONE,1.1 Config.in,1.14,1.15 Makefile,1.8,1.9

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv20843/drivers/net

Modified Files:
	Config.in Makefile 
Added Files:
	tc35815.c 
Log Message:
Imported support for JMR-TX3927 by Alice Hennessy. Thank you.

--- NEW FILE: tc35815.c ---
/* tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc. 
 *                ahe...@mv...
 *
 * Based on skelton.c by Donald Becker.
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
[...1740 lines suppressed...]
		return 0;
}

static void __exit tc35815_cleanup_module(void)
{
	struct net_device *next_dev;

	/* No need to check MOD_IN_USE, as sys_delete_module() checks. */
	while (root_tc35815_dev) {
		struct net_device *dev = root_tc35815_dev;
		next_dev = ((struct tc35815_local *)dev->priv)->next_module;
		kfree(dev->priv);
		iounmap((void *)(dev->base_addr));
		unregister_netdev(dev);
		kfree(dev);
		root_tc35815_dev = next_dev;
	}
}
module_init(tc35815_init_module);
module_exit(tc35815_cleanup_module);

Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Config.in,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- Config.in	2001/11/07 20:00:55	1.14
+++ Config.in	2001/11/10 03:52:49	1.15
@@ -171,6 +171,7 @@
          tristate '    Generic DECchip & DIGITAL EtherWORKS PCI/EISA' CONFIG_DE4X5
          tristate '    Digi Intl. RightSwitch SE-X support' CONFIG_DGRS
       fi
+      dep_tristate '    TOSHIBA TC35815 Ethernet support' CONFIG_TC35815
       dep_tristate '    Davicom DM910x/DM980x support' CONFIG_DM9102 $CONFIG_PCI
       dep_tristate '    EtherExpressPro/100 support' CONFIG_EEPRO100 $CONFIG_PCI
       dep_tristate '    Mylex EISA LNE390A/B support (EXPERIMENTAL)' CONFIG_LNE390 $CONFIG_EISA $CONFIG_EXPERIMENTAL

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Makefile,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- Makefile	2001/11/07 20:00:55	1.8
+++ Makefile	2001/11/10 03:52:49	1.9
@@ -79,6 +79,7 @@
 obj-$(CONFIG_NS83820) += ns83820.o
 obj-$(CONFIG_STNIC) += stnic.o 8390.o
 obj-$(CONFIG_FEALNX) += fealnx.o
+obj-$(CONFIG_TC35815) += tc35815.o
 
 ifeq ($(CONFIG_SK98LIN),y)
 obj-y += sk98lin/sk98lin.o

[Linux-mips-commits]CVS: linux/drivers/char serial_txx927.c,NONE,1.1 Config.in,1.23,1.24 Makefile,1.19,1.20

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv20843/drivers/char

Modified Files:
	Config.in Makefile 
Added Files:
	serial_txx927.c 
Log Message:
Imported support for JMR-TX3927 by Alice Hennessy. Thank you.

--- NEW FILE: serial_txx927.c ---
/*
 *  drivers/char/serial_txx927.c
 *  driver for TX[34]927 SIO
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc. 
 *                ahe...@mv...
 *
 * Based on drivers/char/serial.c
 *
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
[...2323 lines suppressed...]
}

static struct console sercons = {
	name:           TXX927_TTY_NAME,
	write:          serial_console_write,
	device:	        serial_console_device,
	wait_key:	serial_console_wait_key,
	setup:	        serial_console_setup,
	flags:	        CON_PRINTBUFFER,
	index:	        -1,
};

/*
 *	Register console.
 */
void __init txx927_console_init(void)
{
	register_console(&sercons);
}
#endif

Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Config.in,v
retrieving revision 1.23
retrieving revision 1.24
diff -u -d -r1.23 -r1.24
--- Config.in	2001/11/06 20:23:55	1.23
+++ Config.in	2001/11/10 03:52:49	1.24
@@ -62,9 +62,13 @@
    bool '  TMPTX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
    dep_bool '     Console on TMPTX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
    bool '  Enable Au1000 UART Support' CONFIG_AU1000_UART
-     if [ "$CONFIG_AU1000_UART" = "y" ]; then
-         bool '        Enable Au1000 serial console' CONFIG_AU1000_SERIAL_CONSOLE
-     fi
+   if [ "$CONFIG_AU1000_UART" = "y" ]; then
+      bool '        Enable Au1000 serial console' CONFIG_AU1000_SERIAL_CONSOLE
+   fi
+   bool 'TXx927 SIO support' CONFIG_TXX927_SERIAL
+   if [ "$CONFIG_TXX927_SERIAL" = "y" ]; then
+      bool 'TXx927 SIO Console support' CONFIG_TXX927_SERIAL_CONSOLE
+   fi
 fi
 if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
    tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Makefile,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -d -r1.19 -r1.20
--- Makefile	2001/11/06 22:17:23	1.19
+++ Makefile	2001/11/10 03:52:49	1.20
@@ -169,6 +169,7 @@
 obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o
 obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o
 obj-$(CONFIG_SERIAL_TX3912) += generic_serial.o serial_tx3912.o
+obj-$(CONFIG_TXX927_SERIAL) += serial_txx927.o
 
 subdir-$(CONFIG_RIO) += rio
 subdir-$(CONFIG_INPUT) += joystick

[Linux-mips-commits]CVS: linux/include/linux pci_ids.h,1.11,1.12

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/linux
In directory usw-pr-cvs1:/tmp/cvs-serv20843/include/linux

Modified Files:
	pci_ids.h 
Log Message:
Imported support for JMR-TX3927 by Alice Hennessy. Thank you.

Index: pci_ids.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/linux/pci_ids.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- pci_ids.h	2001/11/06 09:10:22	1.11
+++ pci_ids.h	2001/11/10 03:52:49	1.12
@@ -1092,6 +1092,11 @@
 #define PCI_DEVICE_ID_TOSHIBA_TOPIC95	0x060a
 #define PCI_DEVICE_ID_TOSHIBA_TOPIC97	0x060f
 
+#define PCI_VENDOR_ID_TOSHIBA_2		0x102f
+#define PCI_DEVICE_ID_TOSHIBA_TX3927	0x000a
+#define PCI_DEVICE_ID_TOSHIBA_TC35815CF	0x0030
+#define PCI_DEVICE_ID_TOSHIBA_TX4927	0x0180
+
 #define PCI_VENDOR_ID_RICOH		0x1180
 #define PCI_DEVICE_ID_RICOH_RL5C465	0x0465
 #define PCI_DEVICE_ID_RICOH_RL5C466	0x0466