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From: James S. <jsi...@us...> - 2001-11-19 17:58:55
|
Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250 In directory usw-pr-cvs1:/tmp/cvs-serv29238 Modified Files: lib_hssubr.S Log Message: Various cleanups. Index: lib_hssubr.S =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250/lib_hssubr.S,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- lib_hssubr.S 2001/11/08 17:42:08 1.1 +++ lib_hssubr.S 2001/11/19 17:58:52 1.2 @@ -16,12 +16,13 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#include "asm/sibyte/sb1250_defs.h" -#include "asm/sibyte/sbmips.h" +#include <asm/sibyte/sb1250_defs.h> +#include <asm/sibyte/sbmips.h> +#include <asm/asm.h> - .set mips64 + .set mips64 -#define HAZARD ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop +#define HAZARD SSNOP ; SSNOP ; SSNOP ; SSNOP ; SSNOP ; SSNOP ; SSNOP /* ********************************************************************* @@ -195,9 +196,3 @@ HAZARD j ra END(hs_write64) - - -/* ********************************************************************* - * End - ********************************************************************* */ - |
|
From: James S. <jsi...@us...> - 2001-11-19 17:57:42
|
Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv28978/arch/mips64/mm
Modified Files:
andes.c r4xx0.c
Log Message:
get_new_cpu_mmu_context is get_cpu_mmu_context now.
Index: andes.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/andes.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- andes.c 2001/11/06 00:30:43 1.6
+++ andes.c 2001/11/19 17:57:38 1.7
@@ -170,7 +170,7 @@
printk("[tlbmm<%d>]", mm->context);
#endif
__save_and_cli(flags);
- get_new_cpu_mmu_context(mm, smp_processor_id());
+ get_new_mmu_context(mm, smp_processor_id());
if(mm == current->mm)
set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 0xff);
__restore_flags(flags);
@@ -214,7 +214,7 @@
}
set_entryhi(oldpid);
} else {
- get_new_cpu_mmu_context(mm, smp_processor_id());
+ get_new_mmu_context(mm, smp_processor_id());
if(mm == current->mm)
set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) &
0xff);
Index: r4xx0.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/r4xx0.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- r4xx0.c 2001/11/06 00:30:43 1.7
+++ r4xx0.c 2001/11/19 17:57:38 1.8
@@ -1900,7 +1900,7 @@
printk("[tlbmm<%d>]", mm->context);
#endif
__save_and_cli(flags);
- get_new_cpu_mmu_context(mm, smp_processor_id());
+ get_new_mmu_context(mm, smp_processor_id());
if(mm == current->mm)
set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 0xff);
__restore_flags(flags);
@@ -1948,7 +1948,7 @@
}
set_entryhi(oldpid);
} else {
- get_new_cpu_mmu_context(mm, smp_processor_id());
+ get_new_mmu_context(mm, smp_processor_id());
if(mm == current->mm)
set_entryhi(CPU_CONTEXT(smp_processor_id(),
mm) & 0xff);
|
|
From: James S. <jsi...@us...> - 2001-11-19 17:57:42
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv28978/arch/mips/mm
Modified Files:
tlb-r3k.c tlb-r4k.c tlb-sb1.c
Log Message:
get_new_cpu_mmu_context is get_cpu_mmu_context now.
Index: tlb-r3k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r3k.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- tlb-r3k.c 2001/10/26 16:10:17 1.4
+++ tlb-r3k.c 2001/11/19 17:57:38 1.5
@@ -66,7 +66,7 @@
printk("[tlbmm<%lu>]", (unsigned long) mm->context);
#endif
save_and_cli(flags);
- get_new_cpu_mmu_context(mm, smp_processor_id());
+ get_new_mmu_context(mm, smp_processor_id());
if (mm == current->active_mm)
set_entryhi(mm->context & 0xfc0);
restore_flags(flags);
@@ -108,7 +108,7 @@
}
set_entryhi(oldpid);
} else {
- get_new_cpu_mmu_context(mm, smp_processor_id());
+ get_new_mmu_context(mm, smp_processor_id());
if (mm == current->active_mm)
set_entryhi(mm->context & 0xfc0);
}
Index: tlb-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r4k.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- tlb-r4k.c 2001/11/16 00:25:59 1.5
+++ tlb-r4k.c 2001/11/19 17:57:38 1.6
@@ -80,7 +80,7 @@
printk("[tlbmm<%d>]", mm->context);
#endif
__save_and_cli(flags);
- get_new_cpu_mmu_context(mm, smp_processor_id());
+ get_new_mmu_context(mm, smp_processor_id());
if (mm == current->active_mm)
set_entryhi(mm->context & 0xff);
__restore_flags(flags);
@@ -130,7 +130,7 @@
}
set_entryhi(oldpid);
} else {
- get_new_cpu_mmu_context(mm, smp_processor_id());
+ get_new_mmu_context(mm, smp_processor_id());
if (mm == current->active_mm)
set_entryhi(mm->context & 0xff);
}
Index: tlb-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-sb1.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- tlb-sb1.c 2001/11/07 17:29:03 1.1
+++ tlb-sb1.c 2001/11/19 17:57:38 1.2
@@ -189,7 +189,7 @@
}
set_entryhi(oldpid);
} else {
- get_new_mmu_context(mm);
+ get_new_mmu_context(mm, smp_processor_id());
if (mm == current->active_mm)
set_entryhi(CPU_CONTEXT(cpu, mm) & 0xff);
}
@@ -242,7 +242,7 @@
__save_and_cli(flags);
cpu = smp_processor_id();
if (CPU_CONTEXT(cpu, mm) != 0) {
- get_new_mmu_context(mm);
+ get_new_mmu_context(mm, smp_processor_id());
if (mm == current->active_mm) {
set_entryhi(CPU_CONTEXT(cpu, mm) & 0xff);
}
|
|
From: James S. <jsi...@us...> - 2001-11-19 17:57:42
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv28978/include/asm-mips
Modified Files:
mmu_context.h
Log Message:
get_new_cpu_mmu_context is get_cpu_mmu_context now.
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mmu_context.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- mmu_context.h 2001/10/31 18:26:52 1.6
+++ mmu_context.h 2001/11/19 17:57:38 1.7
@@ -61,7 +61,7 @@
#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
static inline void
-get_new_cpu_mmu_context(struct mm_struct *mm, unsigned long cpu)
+get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
{
unsigned long asid = ASID_CACHE(cpu);
@@ -101,7 +101,7 @@
{
/* Check if our ASID is of an older version and thus invalid */
if ((CPU_CONTEXT(cpu, next) ^ ASID_CACHE(cpu)) & ASID_VERSION_MASK)
- get_new_cpu_mmu_context(next, cpu);
+ get_new_mmu_context(next, cpu);
set_entryhi(CPU_CONTEXT(cpu, next));
TLBMISS_HANDLER_SETUP_PGD(next->pgd);
@@ -127,7 +127,7 @@
activate_mm(struct mm_struct *prev, struct mm_struct *next)
{
/* Unconditionally get a new ASID. */
- get_new_cpu_mmu_context(next, smp_processor_id());
+ get_new_mmu_context(next, smp_processor_id());
set_entryhi(CPU_CONTEXT(smp_processor_id(), next));
TLBMISS_HANDLER_SETUP_PGD(next->pgd);
|
|
From: James S. <jsi...@us...> - 2001-11-19 17:53:03
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv27698 Modified Files: cpu.h Log Message: Add PRID_COMP_BROADCOM. Index: cpu.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v retrieving revision 1.12 retrieving revision 1.13 diff -u -d -r1.12 -r1.13 --- cpu.h 2001/10/31 17:28:54 1.12 +++ cpu.h 2001/11/19 17:53:00 1.13 @@ -26,10 +26,8 @@ #define PRID_COMP_LEGACY 0x000000 #define PRID_COMP_MIPS 0x010000 +#define PRID_COMP_BROADCOM 0x020000 #define PRID_COMP_ALCHEMY 0x030000 -/* - * Don't know who should be here...QED and Sandcraft, maybe? - */ #define PRID_COMP_SIBYTE 0x040000 /* |
|
From: James S. <jsi...@us...> - 2001-11-19 17:49:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm In directory usw-pr-cvs1:/tmp/cvs-serv26853 Modified Files: Makefile Log Message: Reformat. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/Makefile,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- Makefile 2001/11/08 17:42:08 1.1 +++ Makefile 2001/11/19 17:49:33 1.2 @@ -1,4 +1,3 @@ - .S.s: $(CPP) $(AFLAGS) $< -o $@ .S.o: |
|
From: James S. <jsi...@us...> - 2001-11-19 17:48:30
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv26647
Modified Files:
bootinfo.h
Log Message:
Reformat.
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- bootinfo.h 2001/11/10 03:52:49 1.12
+++ bootinfo.h 2001/11/19 17:48:27 1.13
@@ -32,12 +32,12 @@
#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */
#define MACH_GROUP_ALCHEMY 18 /* Alchemy Semi Eval Boards*/
#define MACH_GROUP_NEC_VR41XX 19 /* NEC Vr41xx based boards/gadgets */
-#define MACH_GROUP_EE 20 /* Emotion Engine (Sony PlayStation 2) */
-
+#define MACH_GROUP_HP_LASERJET 20 /* Hewlett Packard LaserJet */
+#define MACH_GROUP_EE 20 /* Emotion Engine (Sony PlayStation 2) */
#define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", "SNI", "ACN", \
"SGI", "Cobalt", "NEC DDB", "Baget", "Cosine", "Galileo", "Momentum", \
"ITE", "Philips", "Globepspan", "SiByte", "Toshiba", "Alchemy", \
- "NEC Vr41xx", "Emotion Engine" }
+ "NEC Vr41xx", "HP LaserJet", "Emotion Engine" }
/*
* Valid machtype values for group unknown (low order halfword of mips_machtype)
@@ -187,7 +187,7 @@
#define MACH_PALLAS 0
#define MACH_TOPAS 1
#define MACH_JMR 2
-#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */
+#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */
#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927" }
@@ -202,7 +202,7 @@
* Valid machtype for group NEC_VR41XX
*/
#define MACH_NEC_OSPREY 0 /* Osprey eval board */
-#define MACH_NEC_EAGLE 1 /* NEC Eagle board */
+#define MACH_NEC_EAGLE 1 /* NEC Eagle board */
#define MACH_NEC_KORVA 2 /* NEC korva board */
#define MACH_VADEM_CLIO_1000 3 /* Vadem Clio 1000 */
@@ -263,9 +263,8 @@
#define CPU_R5500 41
#define CPU_TX49XX 42
#define CPU_TX39XX 43
-#define CPU_R5900 44
+#define CPU_R5900 44
#define CPU_LAST 44
-
#define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \
"R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC", \
|
|
From: James S. <jsi...@us...> - 2001-11-19 17:42:41
|
Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250 In directory usw-pr-cvs1:/tmp/cvs-serv25300 Modified Files: Makefile Log Message: Use same implicit make rules as elsewhere. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250/Makefile,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- Makefile 2001/11/08 17:42:08 1.1 +++ Makefile 2001/11/19 17:42:38 1.2 @@ -1,5 +1,8 @@ +.S.s: + $(CPP) $(AFLAGS) $< -o $@ +.S.o: + $(CC) $(AFLAGS) -c $< -o $@ -#all: sb1250.a O_TARGET := sb1250.o obj-y := setup.o irq.o irq_handler.o time.o pci.o lib_hssubr.o |
|
From: James S. <jsi...@us...> - 2001-11-19 17:41:27
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv25066
Modified Files:
pg-sb1.c
Log Message:
Include <asm/page.h> for PAGE_SIZE. Export page_clear / copy_page.
Index: pg-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/pg-sb1.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pg-sb1.c 2001/11/07 17:29:03 1.2
+++ pg-sb1.c 2001/11/19 17:41:24 1.3
@@ -21,6 +21,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/config.h>
+#include <asm/page.h>
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
#define SB1_PREF_LOAD_STREAMED_HINT "0"
@@ -31,7 +32,7 @@
#endif
/* These are the functions hooked by the memory management function pointers */
-static void sb1_clear_page(void *page)
+void sb1_clear_page(void *page)
{
/* JDCXXX - This should be bottlenecked by the write buffer, but these
things tend to be mildly unpredictable...should check this on the
@@ -65,7 +66,7 @@
}
-static void sb1_copy_page(void *to, void *from)
+void sb1_copy_page(void *to, void *from)
{
/* This should be optimized in assembly...can't use ld/sd, though,
|
|
From: James S. <jsi...@us...> - 2001-11-19 17:40:29
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv24809 Modified Files: page.h Log Message: Declare SB1 page_clear / copy_page functions. Index: page.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/page.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- page.h 2001/10/08 16:30:42 1.1 +++ page.h 2001/11/19 17:40:26 1.2 @@ -40,6 +40,7 @@ void r4k_clear_page_s128(void * page); void r5432_clear_page_d32(void * page); void rm7k_clear_page(void * page); +void sb1_clear_page(void * page); void andes_copy_page(void * to, void * from); void mips32_copy_page_dc(unsigned long to, unsigned long from); void mips32_copy_page_sc(unsigned long to, unsigned long from); @@ -54,6 +55,7 @@ void r4k_copy_page_s128(void * to, void * from); void r5432_copy_page_d32(void * to, void * from); void rm7k_copy_page(void * to, void * from); +void sb1_copy_page(void * to, void * from); extern void (*_clear_page)(void * page); extern void (*_copy_page)(void * to, void * from); |
|
From: James S. <jsi...@us...> - 2001-11-19 17:38:50
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv24374
Modified Files:
loadmmu.c
Log Message:
SB1 uses it's own TLB code for now.
Index: loadmmu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/loadmmu.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- loadmmu.c 2001/10/24 23:32:54 1.7
+++ loadmmu.c 2001/11/19 17:38:47 1.8
@@ -51,6 +51,7 @@
extern void ld_mmu_mips32(void);
extern void r3k_tlb_init(void);
extern void r4k_tlb_init(void);
+extern void sb1_tlb_init(void);
void __init loadmmu(void)
{
@@ -113,7 +114,7 @@
#ifdef CONFIG_CPU_SB1
case CPU_SB1:
ld_mmu_sb1();
- r4k_tlb_init();
+ sb1_tlb_init();
break;
#endif
default:
|
|
From: James S. <jsi...@us...> - 2001-11-19 17:38:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm In directory usw-pr-cvs1:/tmp/cvs-serv24212 Modified Files: init.c Log Message: Add missing definitions of mmu_gathers. Index: init.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/init.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- init.c 2001/06/22 02:29:31 1.1.1.1 +++ init.c 2001/11/19 17:38:14 1.2 @@ -41,7 +41,9 @@ #include <asm/sgialib.h> #endif #include <asm/mmu_context.h> +#include <asm/tlb.h> +mmu_gather_t mmu_gathers[NR_CPUS]; static unsigned long totalram_pages; extern void prom_free_prom_memory(void); |
|
From: James S. <jsi...@us...> - 2001-11-19 17:37:07
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv23927
Modified Files:
setup.c
Log Message:
Use same CPU detection code as 32-bit kernel.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/setup.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- setup.c 2001/10/29 17:42:46 1.4
+++ setup.c 2001/11/19 17:37:04 1.5
@@ -124,38 +124,328 @@
check_wait();
}
+/*
+ * Probe whether cpu has config register by trying to play with
+ * alternate cache bit and see whether it matters.
+ * It's used by cpu_probe to distinguish between R3000A and R3081.
+ */
+static inline int cpu_has_confreg(void)
+{
+#ifdef CONFIG_CPU_R3000
+ extern unsigned long r3k_cache_size(unsigned long);
+ unsigned long size1, size2;
+ unsigned long cfg = read_32bit_cp0_register(CP0_CONF);
+
+ size1 = r3k_cache_size(ST0_ISC);
+ write_32bit_cp0_register(CP0_CONF, cfg^CONF_AC);
+ size2 = r3k_cache_size(ST0_ISC);
+ write_32bit_cp0_register(CP0_CONF, cfg);
+ return size1 != size2;
+#else
+ return 0;
+#endif
+}
+
+/* declaration of the global struct */
+struct mips_cpu mips_cpu = {PRID_IMP_UNKNOWN, CPU_UNKNOWN, 0, 0, 0,
+ {0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0}};
+
+#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
+ | MIPS_CPU_COUNTER | MIPS_CPU_CACHE_CDEX)
+
static inline void cpu_probe(void)
{
- unsigned int prid = read_32bit_cp0_register(CP0_PRID);
+#ifdef CONFIG_CPU_MIPS32
+ unsigned long config1;
+#endif
- switch(prid & 0xff00) {
- case PRID_IMP_R4000:
- if((prid & 0xff) == PRID_REV_R4400)
- mips_cputype = CPU_R4400SC;
- else
- mips_cputype = CPU_R4000SC;
- break;
- case PRID_IMP_R4600:
- mips_cputype = CPU_R4600;
- break;
- case PRID_IMP_R4700:
- mips_cputype = CPU_R4700;
- break;
- case PRID_IMP_R5000:
- mips_cputype = CPU_R5000;
+ mips_cpu.processor_id = read_32bit_cp0_register(CP0_PRID);
+ switch (mips_cpu.processor_id & 0xff0000) {
+ case PRID_COMP_LEGACY:
+ switch (mips_cpu.processor_id & 0xff00) {
+ case PRID_IMP_R2000:
+ mips_cpu.cputype = CPU_R2000;
+ mips_cpu.isa_level = MIPS_CPU_ISA_I;
+ mips_cpu.options = MIPS_CPU_TLB;
+ mips_cpu.tlbsize = 64;
+ break;
+ case PRID_IMP_R3000:
+ if ((mips_cpu.processor_id & 0xff) == PRID_REV_R3000A)
+ if (cpu_has_confreg())
+ mips_cpu.cputype = CPU_R3081E;
+ else
+ mips_cpu.cputype = CPU_R3000A;
+ else
+ mips_cpu.cputype = CPU_R3000;
+ mips_cpu.isa_level = MIPS_CPU_ISA_I;
+ mips_cpu.options = MIPS_CPU_TLB;
+ mips_cpu.tlbsize = 64;
+ break;
+ case PRID_IMP_R4000:
+ if ((mips_cpu.processor_id & 0xff) == PRID_REV_R4400)
+ mips_cpu.cputype = CPU_R4400SC;
+ else
+ mips_cpu.cputype = CPU_R4000SC;
+ mips_cpu.isa_level = MIPS_CPU_ISA_III;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR | MIPS_CPU_WATCH |
+ MIPS_CPU_VCE;
+ mips_cpu.tlbsize = 48;
+ break;
+ case PRID_IMP_VR41XX:
+ mips_cpu.cputype = CPU_VR41XX;
+ mips_cpu.isa_level = MIPS_CPU_ISA_III;
+ mips_cpu.options = R4K_OPTS;
+ mips_cpu.tlbsize = 32;
+ break;
+ case PRID_IMP_R4300:
+ mips_cpu.cputype = CPU_R4300;
+ mips_cpu.isa_level = MIPS_CPU_ISA_III;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ mips_cpu.tlbsize = 32;
+ break;
+ case PRID_IMP_R4600:
+ mips_cpu.cputype = CPU_R4600;
+ mips_cpu.isa_level = MIPS_CPU_ISA_III;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
+ mips_cpu.tlbsize = 48;
+ break;
+ #if 0
+ case PRID_IMP_R4650:
+ /*
+ * This processor doesn't have an MMU, so it's not
+ * "real easy" to run Linux on it. It is left purely
+ * for documentation. Commented out because it shares
+ * it's c0_prid id number with the TX3900.
+ */
+ mips_cpu.cputype = CPU_R4650;
+ mips_cpu.isa_level = MIPS_CPU_ISA_III;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
+ mips_cpu.tlbsize = 48;
+ break;
+ #endif
+ case PRID_IMP_TX39:
+ mips_cpu.isa_level = MIPS_CPU_ISA_I;
+ mips_cpu.options = MIPS_CPU_TLB;
+
+ switch (mips_cpu.processor_id & 0xff) {
+ case PRID_REV_TX3912:
+ mips_cpu.cputype = CPU_TX3912;
+ mips_cpu.tlbsize = 32;
+ break;
+ case PRID_REV_TX3922:
+ mips_cpu.cputype = CPU_TX3922;
+ mips_cpu.tlbsize = 64;
+ break;
+ case PRID_REV_TX3927:
+ case PRID_REV_TX3927B:
+ /* check core-mode */
+ if ((*(volatile u32 *)0xfffee004 >> 16) == 0x3927)
+ mips_cpu.cputype = CPU_TX3927;
+ else
+ mips_cpu.cputype = CPU_TX39XX;
+ mips_cpu.tlbsize = 64;
+ mips_cpu.icache.ways = 2;
+ mips_cpu.dcache.ways = 2;
+ break;
+ case PRID_REV_TX39H3TEG:
+ /* support core-mode only */
+ mips_cpu.cputype = CPU_TX39XX;
+ mips_cpu.tlbsize = 32;
+ mips_cpu.icache.ways = 2;
+ mips_cpu.dcache.ways = 2;
+ break;
+ default:
+ mips_cpu.cputype = CPU_UNKNOWN;
+ break;
+ }
+ break;
+ case PRID_IMP_R4700:
+ mips_cpu.cputype = CPU_R4700;
+ mips_cpu.isa_level = MIPS_CPU_ISA_III;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
+ mips_cpu.tlbsize = 48;
+ break;
+ case PRID_IMP_TX49:
+ mips_cpu.cputype = CPU_TX49XX;
+ mips_cpu.isa_level = MIPS_CPU_ISA_III;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
+ mips_cpu.tlbsize = 48;
+ mips_cpu.icache.ways = 4;
+ mips_cpu.dcache.ways = 4;
+ break;
+ case PRID_IMP_R5000:
+ mips_cpu.cputype = CPU_R5000;
+ mips_cpu.isa_level = MIPS_CPU_ISA_IV;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
+ mips_cpu.tlbsize = 48;
+ break;
+ case PRID_IMP_R5432:
+ mips_cpu.cputype = CPU_R5432;
+ mips_cpu.isa_level = MIPS_CPU_ISA_IV;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
+ mips_cpu.tlbsize = 48;
+ break;
+ case PRID_IMP_R5500:
+ mips_cpu.cputype = CPU_R5500;
+ mips_cpu.isa_level = MIPS_CPU_ISA_IV;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
+ mips_cpu.tlbsize = 48;
+ break;
+ case PRID_IMP_NEVADA:
+ mips_cpu.cputype = CPU_NEVADA;
+ mips_cpu.isa_level = MIPS_CPU_ISA_IV;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
+ mips_cpu.tlbsize = 48;
+ mips_cpu.icache.ways = 2;
+ mips_cpu.dcache.ways = 2;
+ break;
+ case PRID_IMP_R6000:
+ mips_cpu.cputype = CPU_R6000;
+ mips_cpu.isa_level = MIPS_CPU_ISA_II;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
+ mips_cpu.tlbsize = 32;
+ break;
+ case PRID_IMP_R6000A:
+ mips_cpu.cputype = CPU_R6000A;
+ mips_cpu.isa_level = MIPS_CPU_ISA_II;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
+ mips_cpu.tlbsize = 32;
+ break;
+ case PRID_IMP_RM7000:
+ mips_cpu.cputype = CPU_RM7000;
+ mips_cpu.isa_level = MIPS_CPU_ISA_IV;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
+ MIPS_CPU_32FPR;
+ /*
+ * Undocumented RM7000: Bit 29 in the info register of
+ * the RM7000 v2.0 indicates if the TLB has 48 or 64
+ * entries.
+ *
+ * 29 1 => 64 entry JTLB
+ * 0 => 48 entry JTLB
+ */
+ mips_cpu.tlbsize = (get_info() & (1 << 29)) ? 64 : 48;
+ break;
+ case PRID_IMP_R8000:
+ mips_cpu.cputype = CPU_R8000;
+ mips_cpu.isa_level = MIPS_CPU_ISA_IV;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_FPU | MIPS_CPU_32FPR;
+ mips_cpu.tlbsize = 384; /* has wierd TLB: 3-way x 128 */
+ break;
+ case PRID_IMP_R10000:
+ mips_cpu.cputype = CPU_R10000;
+ mips_cpu.isa_level = MIPS_CPU_ISA_IV;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_FPU | MIPS_CPU_32FPR |
+ MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
+ mips_cpu.tlbsize = 64;
+ break;
+ default:
+ mips_cpu.cputype = CPU_UNKNOWN;
+ break;
+ }
break;
- case PRID_IMP_NEVADA:
- mips_cputype = CPU_NEVADA;
+#ifdef CONFIG_CPU_MIPS32
+ case PRID_COMP_MIPS:
+ switch (mips_cpu.processor_id & 0xff00) {
+ case PRID_IMP_4KC:
+ mips_cpu.cputype = CPU_4KC;
+ goto cpu_4kc;
+ case PRID_IMP_4KEC:
+ mips_cpu.cputype = CPU_4KEC;
+ goto cpu_4kc;
+ case PRID_IMP_4KSC:
+ mips_cpu.cputype = CPU_4KSC;
+cpu_4kc:
+ /*
+ * Why do we set all these options by default, THEN
+ * query them??
+ */
+ mips_cpu.isa_level = MIPS_CPU_ISA_M32;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
+ MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
+ config1 = read_mips32_cp0_config1();
+ if (config1 & (1 << 3))
+ mips_cpu.options |= MIPS_CPU_WATCH;
+ if (config1 & (1 << 2))
+ mips_cpu.options |= MIPS_CPU_MIPS16;
+ if (config1 & 1)
+ mips_cpu.options |= MIPS_CPU_FPU;
+ mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+ break;
+ case PRID_IMP_5KC:
+ mips_cpu.cputype = CPU_5KC;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M64;
+ /* See comment above about querying options */
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
+ MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
+ config1 = read_mips32_cp0_config1();
+ if (config1 & (1 << 3))
+ mips_cpu.options |= MIPS_CPU_WATCH;
+ if (config1 & (1 << 2))
+ mips_cpu.options |= MIPS_CPU_MIPS16;
+ if (config1 & 1)
+ mips_cpu.options |= MIPS_CPU_FPU;
+ break;
+ mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+ default:
+ mips_cpu.cputype = CPU_UNKNOWN;
+ break;
+ }
break;
- case PRID_IMP_R8000:
- mips_cputype = CPU_R8000;
+ case PRID_COMP_ALCHEMY:
+ switch (mips_cpu.processor_id & 0xff00) {
+ case PRID_IMP_AU1_REV1:
+ case PRID_IMP_AU1_REV2:
+ mips_cpu.cputype = CPU_AU1000;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M32;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
+ MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
+ config1 = read_mips32_cp0_config1();
+ if (config1 & (1 << 3))
+ mips_cpu.options |= MIPS_CPU_WATCH;
+ if (config1 & (1 << 2))
+ mips_cpu.options |= MIPS_CPU_MIPS16;
+ if (config1 & 1)
+ mips_cpu.options |= MIPS_CPU_FPU;
+ mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+ break;
+ default:
+ mips_cpu.cputype = CPU_UNKNOWN;
+ break;
+ }
break;
- case PRID_IMP_R10000:
- case PRID_IMP_R12000:
- mips_cputype = CPU_R10000;
+#endif /* CONFIG_CPU_MIPS32 */
+ case PRID_COMP_SIBYTE:
+ switch (mips_cpu.processor_id & 0xff00) {
+ case PRID_IMP_SB1:
+ mips_cpu.cputype = CPU_SB1;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M64;
+ mips_cpu.options = (MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_COUNTER | MIPS_CPU_DIVEC);
+#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
+ /* FPU in pass1 is known to have issues. */
+ mips_cpu.options |= MIPS_CPU_FPU;
+#endif
+ break;
+ default:
+ mips_cpu.cputype = CPU_UNKNOWN;
+ break;
+ }
break;
default:
- mips_cputype = CPU_UNKNOWN;
+ mips_cpu.cputype = CPU_UNKNOWN;
}
}
|
|
From: James S. <jsi...@us...> - 2001-11-19 17:36:18
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel In directory usw-pr-cvs1:/tmp/cvs-serv23685 Modified Files: branch.c Log Message: Include <asm/cpu.h>. Index: branch.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/branch.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- branch.c 2001/11/08 17:15:36 1.3 +++ branch.c 2001/11/19 17:36:15 1.4 @@ -11,6 +11,7 @@ #include <linux/sched.h> #include <linux/signal.h> #include <asm/branch.h> +#include <asm/cpu.h> #include <asm/inst.h> #include <asm/ptrace.h> #include <asm/uaccess.h> |
|
From: James S. <jsi...@us...> - 2001-11-19 17:35:12
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv23403
Modified Files:
bootinfo.h mipsregs.h mmu_context.h processor.h
Log Message:
Update from 32-bit versions. A few other synced to OSS tree.
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bootinfo.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- bootinfo.h 2001/10/27 17:28:55 1.3
+++ bootinfo.h 2001/11/19 17:35:09 1.4
@@ -134,13 +134,32 @@
#define CPU_R5000A 25
#define CPU_R4640 26
#define CPU_NEVADA 27 /* RM5230, RM5260 */
-#define CPU_LAST 27
+#define CPU_RM7000 28
+#define CPU_R5432 29
+#define CPU_4KC 30
+#define CPU_5KC 31
+#define CPU_R4310 32
+#define CPU_SB1 33
+#define CPU_TX3912 34
+#define CPU_TX3922 35
+#define CPU_TX3927 36
+#define CPU_AU1000 37
+#define CPU_4KEC 38
+#define CPU_4KSC 39
+#define CPU_VR41XX 40
+#define CPU_R5500 41
+#define CPU_TX49XX 42
+#define CPU_TX39XX 43
+#define CPU_LAST 43
#define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \
"R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC", \
"R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000", \
"R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000", \
- "R5000A", "R4640", "Nevada" }
+ "R5000A", "R4640", "Nevada", "RM7000", "R5432", "MIPS 4Kc", \
+ "MIPS 5Kc", "R4310", "SiByte SB1", "TX3912", "TX3922", "TX3927", \
+ "Au1000", "MIPS 4KEc", "MIPS 4KSc", "NEC Vr41xx", "R5500", "TX49xx", \
+ "TX39xx" }
#define CL_SIZE (80)
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- mipsregs.h 2001/10/31 18:26:52 1.5
+++ mipsregs.h 2001/11/19 17:35:09 1.6
@@ -301,6 +301,24 @@
".set\tmips0" \
: : "r" (value))
+/*
+ * This should be changed when we get a compiler that support the MIPS32 ISA.
+ */
+#define read_mips32_cp0_config1() \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tnoreorder\n\t" \
+ ".set\tnoat\n\t" \
+ "#.set\tmips64\n\t" \
+ "#mfc0\t$1, $16, 1\n\t" \
+ "#.set\tmips0\n\t" \
+ ".word\t0x40018001\n\t" \
+ "move\t%0,$1\n\t" \
+ ".set\tat\n\t" \
+ ".set\treorder" \
+ :"=r" (__res)); \
+ __res;})
+
/* TLB operations. */
static inline void tlb_probe(void)
{
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mmu_context.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- mmu_context.h 2001/10/31 18:26:52 1.2
+++ mmu_context.h 2001/11/19 17:35:09 1.3
@@ -52,7 +52,7 @@
#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
static inline void
-get_new_cpu_mmu_context(struct mm_struct *mm, unsigned long cpu)
+get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
{
unsigned long asid = ASID_CACHE(cpu);
@@ -92,7 +92,7 @@
{
/* Check if our ASID is of an older version and thus invalid */
if ((CPU_CONTEXT(cpu, next) ^ ASID_CACHE(cpu)) & ASID_VERSION_MASK)
- get_new_cpu_mmu_context(next, cpu);
+ get_new_mmu_context(next, cpu);
set_entryhi(CPU_CONTEXT(cpu, next));
TLBMISS_HANDLER_SETUP_PGD(next->pgd);
@@ -118,7 +118,7 @@
activate_mm(struct mm_struct *prev, struct mm_struct *next)
{
/* Unconditionally get a new ASID. */
- get_new_cpu_mmu_context(next, smp_processor_id());
+ get_new_mmu_context(next, smp_processor_id());
set_entryhi(CPU_CONTEXT(smp_processor_id(), next));
TLBMISS_HANDLER_SETUP_PGD(next->pgd);
Index: processor.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/processor.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- processor.h 2001/11/06 00:30:47 1.6
+++ processor.h 2001/11/19 17:35:09 1.7
@@ -157,11 +157,17 @@
};
/*
- * FIXME: no fpu emulator yet (but who cares anyway?)
+ * It would be nice to add some more fields for emulator statistics, but there
+ * are a number of fixed offsets in offset.h and elsewhere that would have to
+ * be recalculated by hand. So the additional information will be private to
+ * the FPU emulator for now. See asm-mips/fpu_emulator.h.
*/
+typedef u64 fpureg_t;
struct mips_fpu_soft_struct {
- long dummy;
+ fpureg_t regs[NUM_FPU_REGS];
+ unsigned int sr;
};
+
union mips_fpu_union {
struct mips_fpu_hard_struct hard;
|
|
From: James S. <jsi...@us...> - 2001-11-19 17:30:19
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64 In directory usw-pr-cvs1:/tmp/cvs-serv21830/asm-mips64 Modified Files: asm.h Log Message: Define SSNOP. Index: asm.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/asm.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- asm.h 2001/09/09 20:17:15 1.6 +++ asm.h 2001/11/19 17:30:16 1.7 @@ -361,4 +361,6 @@ #define MTC0 dmtc0 #endif +#define SSNOP sll zero, zero, 1 + #endif /* __ASM_ASM_H */ |
|
From: James S. <jsi...@us...> - 2001-11-19 17:30:18
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv21830/asm-mips Modified Files: asm.h Log Message: Define SSNOP. Index: asm.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/asm.h,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- asm.h 2001/09/09 20:17:15 1.3 +++ asm.h 2001/11/19 17:30:16 1.4 @@ -384,4 +384,6 @@ #define MTC0 dmtc0 #endif +#define SSNOP sll zero, zero, 1 + #endif /* __ASM_ASM_H */ |
|
From: James S. <jsi...@us...> - 2001-11-19 17:28:35
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv21157 Added Files: smp.h Log Message: Copy a few missing definitions from include/asm-mips64/smp.h. |
|
From: James S. <jsi...@us...> - 2001-11-19 17:27:03
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/hp-lj In directory usw-pr-cvs1:/tmp/cvs-serv20675/hp-lj Log Message: Directory /cvsroot/linux-mips/linux/include/asm-mips/hp-lj added to the repository |
|
From: James S. <jsi...@us...> - 2001-11-19 17:26:26
|
Update of /cvsroot/linux-mips/linux/arch/mips/hp-lj In directory usw-pr-cvs1:/tmp/cvs-serv20471/hp-lj Log Message: Directory /cvsroot/linux-mips/linux/arch/mips/hp-lj added to the repository |
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From: James S. <jsi...@us...> - 2001-11-19 17:25:59
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Update of /cvsroot/linux-mips/linux/include/linux In directory usw-pr-cvs1:/tmp/cvs-serv20274 Modified Files: threads.h Log Message: On MIPS for the sake of 32-bit machines define NR_CPUS as the number of bits in a long. Index: threads.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/linux/threads.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- threads.h 2001/06/22 02:29:32 1.1.1.1 +++ threads.h 2001/11/19 17:25:56 1.2 @@ -9,7 +9,11 @@ */ #ifdef CONFIG_SMP +#ifdef __mips__ +#define NR_CPUS _MIPS_SZLONG +#else #define NR_CPUS 64 /* Max processors that can be running in SMP */ +#endif #else #define NR_CPUS 1 #endif |
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From: Bradley D. L. <br...@us...> - 2001-11-19 15:49:04
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Update of /cvsroot/linux-mips/linux/drivers/pcmcia
In directory usw-pr-cvs1:/tmp/cvs-serv21191/drivers/pcmcia
Modified Files:
au1000_generic.c
Log Message:
Check for valid pointer before memsetting.
Index: au1000_generic.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/pcmcia/au1000_generic.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- au1000_generic.c 2001/10/03 22:49:23 1.4
+++ au1000_generic.c 2001/11/19 15:48:59 1.5
@@ -170,12 +170,12 @@
pcmcia_socket =
kmalloc(sizeof(struct au1000_pcmcia_socket) * socket_count,
GFP_KERNEL);
- memset(pcmcia_socket, 0,
- sizeof(struct au1000_pcmcia_socket) * socket_count);
if (!pcmcia_socket) {
printk(KERN_ERR "Card Services can't get memory \n");
return -1;
}
+ memset(pcmcia_socket, 0,
+ sizeof(struct au1000_pcmcia_socket) * socket_count);
for(i=0; i < socket_count; i++) {
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From: Pete P. <pp...@us...> - 2001-11-16 23:10:55
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Update of /cvsroot/linux-mips/linux/arch/mips/galileo-boards/generic
In directory usw-pr-cvs1:/tmp/cvs-serv4596/arch/mips/galileo-boards/generic
Modified Files:
reset.c
Log Message:
* fixed the serial.h settings so the serial console works again
* added the reset/reboot/halt code
Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/generic/reset.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- reset.c 2001/06/22 02:29:31 1.1.1.1
+++ reset.c 2001/11/16 23:10:53 1.2
@@ -34,6 +34,13 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
#include <asm/reboot.h>
#include <asm/galileo-boards/ev96100.h>
@@ -43,14 +50,21 @@
static void mips_machine_restart(char *command)
{
- printk("mips_machine_restart: not implemented\n");
+ set_cp0_status(ST0_BEV | ST0_ERL);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+ flush_cache_all();
+ write_32bit_cp0_register(CP0_WIRED, 0);
+ __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
while (1);
}
static void mips_machine_halt(void)
{
- printk("mips_machine_halt: not implemented\n");
- while (1);
+ printk(KERN_NOTICE "You can safely turn off the power\n");
+ while (1)
+ __asm__(".set\tmips3\n\t"
+ "wait\n\t"
+ ".set\tmips0");
}
void mips_reboot_setup(void)
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From: Pete P. <pp...@us...> - 2001-11-16 23:10:55
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Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv4596/include/asm-mips
Modified Files:
serial.h
Log Message:
* fixed the serial.h settings so the serial console works again
* added the reset/reboot/halt code
Index: serial.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/serial.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- serial.h 2001/11/10 03:52:49 1.4
+++ serial.h 2001/11/16 23:10:53 1.5
@@ -101,12 +101,12 @@
#include <asm/galileo-boards/ev96100.h>
#include <asm/galileo-boards/ev96100int.h>
#define EV96100_SERIAL_PORT_DEFNS \
- { baud_base: EV96100_BASE_BAUD, port: EV96100_UART0_REGS_BASE, \
- irq: EV96100INT_UART_0, flags: STD_COM_FLAGS, type: 0x3, \
+ { baud_base: EV96100_BASE_BAUD, irq: EV96100INT_UART_0, \
+ flags: STD_COM_FLAGS, \
iomem_base: EV96100_UART0_REGS_BASE, iomem_reg_shift: 2, \
io_type: SERIAL_IO_MEM }, \
- { baud_base: EV96100_BASE_BAUD, port: EV96100_UART1_REGS_BASE, \
- irq: EV96100INT_UART_0, flags: STD_COM_FLAGS, type: 0x3, \
+ { baud_base: EV96100_BASE_BAUD, irq: EV96100INT_UART_0, \
+ flags: STD_COM_FLAGS, \
iomem_base: EV96100_UART1_REGS_BASE, iomem_reg_shift: 2, \
io_type: SERIAL_IO_MEM },
#else
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From: James S. <jsi...@us...> - 2001-11-16 17:22:13
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Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477
In directory usw-pr-cvs1:/tmp/cvs-serv24015
Modified Files:
pci_ops.c
Log Message:
Type 1 config cycles are working now.
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/pci_ops.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pci_ops.c 2001/10/11 20:45:26 1.2
+++ pci_ops.c 2001/11/16 17:22:10 1.3
@@ -73,9 +73,6 @@
u32 virt_addr = swap->config_base;
u32 option;
- /* [jsun] hack for testing */
- // if (slot_num == 4) slot_num = 0;
-
/* minimum pdar (window) size is 2MB */
db_assert(swap->config_size >= (2 << 20));
@@ -104,7 +101,6 @@
} else {
/* type 1 config */
pci_addr = (bus << 16) | (slot_num << 11);
- panic("ddb_access_config_base: we don't support type 1 config Yet");
}
/*
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