Menu
▾
▴
linux-mips-commits — CVS Commit Patches
You can subscribe to this list here.
| 2001 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
(165) |
Sep
(240) |
Oct
(424) |
Nov
(526) |
Dec
(293) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2002 |
Jan
(242) |
Feb
(149) |
Mar
(143) |
Apr
(143) |
May
(76) |
Jun
(59) |
Jul
(20) |
Aug
(2) |
Sep
(49) |
Oct
(1) |
Nov
(4) |
Dec
|
| 2003 |
Jan
(1) |
Feb
|
Mar
|
Apr
(1) |
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
| 2004 |
Jan
|
Feb
|
Mar
|
Apr
(2) |
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
|
Nov
|
Dec
|
| 2008 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
(3) |
Nov
|
Dec
|
| 2009 |
Jan
|
Feb
|
Mar
|
Apr
|
May
(1) |
Jun
(72) |
Jul
(36) |
Aug
(9) |
Sep
(16) |
Oct
(23) |
Nov
(9) |
Dec
(3) |
| 2010 |
Jan
|
Feb
(1) |
Mar
(35) |
Apr
(44) |
May
(56) |
Jun
(71) |
Jul
(41) |
Aug
(41) |
Sep
(22) |
Oct
(3) |
Nov
(1) |
Dec
(1) |
| 2011 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
(1) |
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
| 2012 |
Jan
(1) |
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
(1) |
| 2013 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
|
Nov
|
Dec
|
| 2014 |
Jan
(1) |
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
| 2015 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
(1) |
Sep
|
Oct
(1) |
Nov
(1) |
Dec
|
| 2016 |
Jan
|
Feb
|
Mar
|
Apr
|
May
(1) |
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
(1) |
Dec
|
| 2017 |
Jan
|
Feb
|
Mar
(1) |
Apr
(1) |
May
(1) |
Jun
|
Jul
(1) |
Aug
|
Sep
(1) |
Oct
|
Nov
|
Dec
|
| 2021 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
(1) |
Aug
(1) |
Sep
(25) |
Oct
(105) |
Nov
(15) |
Dec
|
| 2025 |
Jan
(1) |
Feb
|
Mar
|
Apr
|
May
(4) |
Jun
|
Jul
(1) |
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
|
From: <fra...@ce...> - 2001-11-16 08:40:37
|
Hi there, This is a patch for Casio Cassiopeia E15. It is called linux-mips-2.4.13... but can be safely apply to current release I think. (New Files are meanly located in arch/mips/vr4111/casio and come from linux-vr project tree). If somenone want to have a look and/or add them to the tree. Unfortunalty, booting fails in error: <<Kernel panic: Aiee, killing interrupt handler! In interrupt handler - not syncing>> The file boot.log join to this e-mail show the exact start-up process and error message. help welcome! Regards. |
|
From: Pete P. <pp...@us...> - 2001-11-16 00:26:05
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv21271/arch/mips/mm
Modified Files:
tlb-r4k.c
Log Message:
PRID mask was wrong.
Index: tlb-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r4k.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- tlb-r4k.c 2001/11/14 16:15:41 1.4
+++ tlb-r4k.c 2001/11/16 00:25:59 1.5
@@ -337,7 +337,7 @@
{
unsigned int prid, config1;
- prid = read_32bit_cp0_register(CP0_PRID) & 0xff0000;
+ prid = read_32bit_cp0_register(CP0_PRID) & 0xff00;
if (prid == PRID_IMP_RM7000 || !(config & (1 << 31)))
/*
* Not a MIPS32 complianant CPU. Config 1 register not
|
|
From: James S. <jsi...@us...> - 2001-11-15 17:02:54
|
Update of /cvsroot/linux-mips/linux/drivers/sgi/char In directory usw-pr-cvs1:/tmp/cvs-serv24731 Added Files: Makefile Log Message: Add rrm.o to export-objs. --- NEW FILE: Makefile --- # # Makefile for the linux kernel. # # Note! Dependencies are done automagically by 'make dep', which also # removes any old dependencies. DON'T put your own dependencies here # unless it's something special (ie not a .c file). # # Note 2! The CFLAGS definitions are now in the main makefile... O_TARGET := sgichar.o export-objs := newport.o rrm.o shmiq.o sgicons.o usema.o obj-y := newport.o shmiq.o sgicons.o usema.o streamable.o obj-$(CONFIG_SGI_SERIAL) += sgiserial.o obj-$(CONFIG_SGI_DS1286) += ds1286.o obj-$(CONFIG_SGI_NEWPORT_GFX) += graphics.o rrm.o include $(TOPDIR)/Rules.make |
|
From: James S. <jsi...@us...> - 2001-11-15 17:01:33
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/lexra In directory usw-pr-cvs1:/tmp/cvs-serv24387/lexra Log Message: Directory /cvsroot/linux-mips/linux/include/asm-mips/lexra added to the repository |
|
From: James S. <jsi...@us...> - 2001-11-15 17:01:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/lx In directory usw-pr-cvs1:/tmp/cvs-serv24241/lx Log Message: Directory /cvsroot/linux-mips/linux/arch/mips/lx added to the repository |
|
From: James S. <jsi...@us...> - 2001-11-14 16:18:02
|
Update of /cvsroot/linux-mips/linux/arch/mips/sgi/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv6732
Modified Files:
indy_int.c
Log Message:
Some trivial Indy cleanup.
Index: indy_int.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sgi/kernel/indy_int.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- indy_int.c 2001/10/23 17:20:14 1.3
+++ indy_int.c 2001/11/14 16:17:58 1.4
@@ -75,7 +75,10 @@
* 8 --> 15 == local 1 interrupts
* 16 --> 23 == vectored level 2 interrupts
* 24 --> 31 == vectored level 3 interrupts (not used)
+ * 32 --> 40 == vectored GIO interrupts
+ * 41 --> 52 == vectored HPCDMA interrupts
*/
+
static void enable_local0_irq(unsigned int irq)
{
unsigned long flags;
@@ -218,7 +221,7 @@
save_and_cli(flags);
printk("Yeeee, got passed irq_nr %d at enable_local3_irq\n", irq);
- panic("INVALID IRQ level!");
+ panic("Invalid IRQ level!");
restore_flags(flags);
}
@@ -236,10 +239,10 @@
save_and_cli(flags);
/*
* This way we'll see if anyone would ever want vectored level 3
- * interrupts. Highly unlikely.
+ * interrupts. Highly unlikely.
*/
printk("Yeeee, got passed irq_nr %d at disable_local3_irq\n", irq);
- panic("INVALID IRQ level!");
+ panic("Invalid IRQ level!");
restore_flags(flags);
}
@@ -337,21 +340,6 @@
NULL
};
-static struct irqaction r4ktimer_action = {
- NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
-};
-
-static struct irqaction indy_berr_action = {
- NULL, 0, 0, "IP22 Bus Error", NULL, NULL,
-};
-
-static struct irqaction *irq_action[16] = {
- NULL, NULL, NULL, NULL,
- NULL, NULL, &indy_berr_action, &r4ktimer_action,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL
-};
-
void indy_local0_irqdispatch(struct pt_regs *regs)
{
unsigned char mask = ioc_icontrol->istat0;
@@ -368,16 +356,8 @@
}
/* if irq == 0, then the interrupt has already been cleared */
- if (irq == 0)
- goto end;
-
- do_IRQ(irq, regs);
- goto end;
-
-no_handler:
- printk("No handler for local0 irq: %i\n", irq);
-
-end:
+ if (irq)
+ do_IRQ(irq, regs);
return;
}
@@ -399,16 +379,8 @@
/* if irq == 0, then the interrupt has already been cleared */
/* not sure if it is needed here, but it is needed for local0 */
- if (irq == 0)
- goto end;
-
- do_IRQ(irq, regs);
- goto end;
-
-no_handler:
- printk("No handler for local1 irq: %i\n", irq);
-
-end:
+ if (irq)
+ do_IRQ(irq, regs);
return;
}
|
|
From: James S. <jsi...@us...> - 2001-11-14 16:17:20
|
Update of /cvsroot/linux-mips/linux/arch/mips/lib
In directory usw-pr-cvs1:/tmp/cvs-serv6584
Added Files:
Makefile r3k_dump_tlb.c
Log Message:
Fix TLB dump code for R39xx.
--- NEW FILE: r3k_dump_tlb.c ---
/*
* Dump R3000 TLB for debugging purposes.
*
* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 1999 by Harald Koerfgen
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
#include <asm/cachectl.h>
#include <asm/cpu.h>
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#define mips_tlb_entries mips_cpu.tlbsize
extern int r3k_have_wired_reg; /* defined in tlb-r3k.c */
void
dump_tlb(int first, int last)
{
int i;
unsigned int asid;
unsigned long entryhi, entrylo0;
asid = get_entryhi() & 0xfc0;
for(i=first;i<=last;i++)
{
write_32bit_cp0_register(CP0_INDEX, i<<8);
__asm__ __volatile__(
".set\tnoreorder\n\t"
"tlbr\n\t"
"nop\n\t"
".set\treorder");
entryhi = read_32bit_cp0_register(CP0_ENTRYHI);
entrylo0 = read_32bit_cp0_register(CP0_ENTRYLO0);
/* Unused entries have a virtual address of KSEG0. */
if ((entryhi & 0xffffe000) != 0x80000000
&& (entryhi & 0xfc0) == asid) {
/*
* Only print entries in use
*/
printk("Index: %2d ", i);
printk("va=%08lx asid=%08lx"
" [pa=%06lx n=%d d=%d v=%d g=%d]",
(entryhi & 0xffffe000),
entryhi & 0xfc0,
entrylo0 & PAGE_MASK,
(entrylo0 & (1 << 11)) ? 1 : 0,
(entrylo0 & (1 << 10)) ? 1 : 0,
(entrylo0 & (1 << 9)) ? 1 : 0,
(entrylo0 & (1 << 8)) ? 1 : 0);
}
}
printk("\n");
set_entryhi(asid);
}
void
dump_tlb_all(void)
{
dump_tlb(0, mips_tlb_entries - 1);
}
void
dump_tlb_wired(void)
{
int wired = r3k_have_wired_reg ? get_wired() : 8;
printk("Wired: %d", wired);
dump_tlb(0, wired - 1);
}
void
dump_tlb_addr(unsigned long addr)
{
unsigned int flags, oldpid;
int index;
__save_and_cli(flags);
oldpid = get_entryhi() & 0xff;
set_entryhi((addr & PAGE_MASK) | oldpid);
tlb_probe();
index = get_index();
set_entryhi(oldpid);
__restore_flags(flags);
if (index < 0) {
printk("No entry for address 0x%08lx in TLB\n", addr);
return;
}
printk("Entry %d maps address 0x%08lx\n", index, addr);
dump_tlb(index, index);
}
void
dump_tlb_nonwired(void)
{
int wired = r3k_have_wired_reg ? get_wired() : 8;
dump_tlb(wired, mips_tlb_entries - 1);
}
void
dump_list_process(struct task_struct *t, void *address)
{
pgd_t *page_dir, *pgd;
pmd_t *pmd;
pte_t *pte, page;
unsigned int addr;
unsigned long val;
addr = (unsigned int) address;
printk("Addr == %08x\n", addr);
printk("tasks->mm.pgd == %08x\n", (unsigned int) t->mm->pgd);
page_dir = pgd_offset(t->mm, 0);
printk("page_dir == %08x\n", (unsigned int) page_dir);
pgd = pgd_offset(t->mm, addr);
printk("pgd == %08x, ", (unsigned int) pgd);
pmd = pmd_offset(pgd, addr);
printk("pmd == %08x, ", (unsigned int) pmd);
pte = pte_offset(pmd, addr);
printk("pte == %08x, ", (unsigned int) pte);
page = *pte;
printk("page == %08x\n", (unsigned int) pte_val(page));
val = pte_val(page);
if (val & _PAGE_PRESENT) printk("present ");
if (val & _PAGE_READ) printk("read ");
if (val & _PAGE_WRITE) printk("write ");
if (val & _PAGE_ACCESSED) printk("accessed ");
if (val & _PAGE_MODIFIED) printk("modified ");
if (val & _PAGE_GLOBAL) printk("global ");
if (val & _PAGE_VALID) printk("valid ");
printk("\n");
}
void
dump_list_current(void *address)
{
dump_list_process(current, address);
}
unsigned int
vtop(void *address)
{
pgd_t *pgd;
pmd_t *pmd;
pte_t *pte;
unsigned int addr, paddr;
addr = (unsigned long) address;
pgd = pgd_offset(current->mm, addr);
pmd = pmd_offset(pgd, addr);
pte = pte_offset(pmd, addr);
paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
paddr |= (addr & ~PAGE_MASK);
return paddr;
}
void
dump16(unsigned long *p)
{
int i;
for(i=0;i<8;i++)
{
printk("*%08lx == %08lx, ",
(unsigned long)p, (unsigned long)*p++);
printk("*%08lx == %08lx\n",
(unsigned long)p, (unsigned long)*p++);
}
}
|
|
From: James S. <jsi...@us...> - 2001-11-14 16:15:45
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv6111
Modified Files:
tlb-r4k.c
Log Message:
Don't misstreat RM7000 as MIPS32.
Index: tlb-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r4k.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- tlb-r4k.c 2001/11/11 00:10:32 1.3
+++ tlb-r4k.c 2001/11/14 16:15:41 1.4
@@ -335,14 +335,11 @@
static void __init probe_tlb(unsigned long config)
{
- unsigned long config1;
-
-#ifdef CONFIG_CPU_RM7000
- return;
-#endif
+ unsigned int prid, config1;
- if (!(config & (1 << 31)))
- /*
+ prid = read_32bit_cp0_register(CP0_PRID) & 0xff0000;
+ if (prid == PRID_IMP_RM7000 || !(config & (1 << 31)))
+ /*
* Not a MIPS32 complianant CPU. Config 1 register not
* supported, we assume R4k style. Cpu probing already figured
* out the number of tlb entries.
|
|
From: Pete P. <pp...@us...> - 2001-11-14 02:17:20
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv6920/include/asm-mips
Modified Files:
string.h
Log Message:
memscan bug fix for today's patch.
Index: string.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/string.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- string.h 2001/11/14 00:51:42 1.3
+++ string.h 2001/11/14 02:16:57 1.4
@@ -136,7 +136,7 @@
extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
{
char *__end = (char *)__addr + __size;
- unsigned char * __uc = (unsigned char) __c;
+ unsigned char __uc = (unsigned char) __c;
__asm__(".set\tpush\n\t"
".set\tnoat\n\t"
|
|
From: James S. <jsi...@us...> - 2001-11-14 00:51:45
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv23323/include/asm-mips
Modified Files:
string.h
Log Message:
Handle characters > 127 correctly in memscan.
Index: string.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/string.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- string.h 2001/10/08 16:18:38 1.2
+++ string.h 2001/11/14 00:51:42 1.3
@@ -136,17 +136,18 @@
extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
{
char *__end = (char *)__addr + __size;
+ unsigned char * __uc = (unsigned char) __c;
__asm__(".set\tpush\n\t"
".set\tnoat\n\t"
".set\treorder\n\t"
"1:\tbeq\t%0,%1,2f\n\t"
"addiu\t%0,1\n\t"
- "lb\t$1,-1(%0)\n\t"
+ "lbu\t$1,-1(%0)\n\t"
"bne\t$1,%z4,1b\n"
"2:\t.set\tpop"
: "=r" (__addr), "=r" (__end)
- : "0" (__addr), "1" (__end), "Jr" (__c));
+ : "0" (__addr), "1" (__end), "Jr" (__uc));
return __addr;
}
|
|
From: James S. <jsi...@us...> - 2001-11-14 00:50:34
|
Update of /cvsroot/linux-mips/linux/lib
In directory usw-pr-cvs1:/tmp/cvs-serv23101
Modified Files:
string.c
Log Message:
Handle characters > 127 correctly in memscan.
Index: string.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/lib/string.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- string.c 2001/06/22 02:29:31 1.1.1.1
+++ string.c 2001/11/14 00:50:32 1.2
@@ -477,7 +477,7 @@
unsigned char * e = p + size;
while (p != e) {
- if (*p == c)
+ if (*p == (unsigned char)c)
return (void *) p;
p++;
}
|
|
From: James S. <jsi...@us...> - 2001-11-13 23:37:03
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000 In directory usw-pr-cvs1:/tmp/cvs-serv6904 Modified Files: setup.c Log Message: Its iomem, not ioport. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/setup.c,v retrieving revision 1.12 retrieving revision 1.13 diff -u -d -r1.12 -r1.13 --- setup.c 2001/10/31 22:02:45 1.12 +++ setup.c 2001/11/13 23:37:00 1.13 @@ -101,7 +101,7 @@ ioport_resource.start = 0; ioport_resource.end = 0xffffffff; iomem_resource.start = 0; - ioport_resource.end = 0xffffffff; + iomem_resource.end = 0xffffffff; #ifdef CONFIG_BLK_DEV_INITRD ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); |
|
From: James S. <jsi...@us...> - 2001-11-13 23:35:02
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv6444
Modified Files:
traps.c
Log Message:
Some cleanup.
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.23
retrieving revision 1.24
diff -u -d -r1.23 -r1.24
--- traps.c 2001/11/06 00:30:42 1.23
+++ traps.c 2001/11/13 23:34:59 1.24
@@ -77,12 +77,9 @@
*/
#define MODULE_RANGE (8*1024*1024)
-#ifndef CONFIG_CPU_HAS_LLSC
/*
* This stuff is needed for the userland ll-sc emulation for R2300
*/
-void simulate_ll(struct pt_regs *regs, unsigned int opcode);
-void simulate_sc(struct pt_regs *regs, unsigned int opcode);
#define OPCODE 0xfc000000
#define BASE 0x03e00000
@@ -90,8 +87,97 @@
#define OFFSET 0x0000ffff
#define LL 0xc0000000
#define SC 0xe0000000
+
+/*
+ * The ll_bit is cleared by r*_switch.S
+ */
+
+unsigned long ll_bit;
+#ifdef CONFIG_PROC_FS
+extern unsigned long ll_ops;
+extern unsigned long sc_ops;
#endif
+static struct task_struct *ll_task = NULL;
+
+static inline void simulate_ll(struct pt_regs *regp, unsigned int opcode)
+{
+ unsigned long value, *vaddr;
+ long offset;
+ int signal = 0;
+
+ /*
+ * analyse the ll instruction that just caused a ri exception
+ * and put the referenced address to addr.
+ */
+
+ /* sign extend offset */
+ offset = opcode & OFFSET;
+ offset <<= 16;
+ offset >>= 16;
+
+ vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset);
+
+#ifdef CONFIG_PROC_FS
+ ll_ops++;
+#endif
+
+ if ((unsigned long)vaddr & 3)
+ signal = SIGBUS;
+ else if (get_user(value, vaddr))
+ signal = SIGSEGV;
+ else {
+ if (ll_task == NULL || ll_task == current) {
+ ll_bit = 1;
+ } else {
+ ll_bit = 0;
+ }
+ ll_task = current;
+ regp->regs[(opcode & RT) >> 16] = value;
+ }
+ if (compute_return_epc(regp))
+ return;
+ if (signal)
+ send_sig(signal, current, 1);
+}
+
+static inline void simulate_sc(struct pt_regs *regp, unsigned int opcode)
+{
+ unsigned long *vaddr, reg;
+ long offset;
+ int signal = 0;
+
+ /*
+ * analyse the sc instruction that just caused a ri exception
+ * and put the referenced address to addr.
+ */
+
+ /* sign extend offset */
+ offset = opcode & OFFSET;
+ offset <<= 16;
+ offset >>= 16;
+
+ vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset);
+ reg = (opcode & RT) >> 16;
+
+#ifdef CONFIG_PROC_FS
+ sc_ops++;
+#endif
+
+ if ((unsigned long)vaddr & 3)
+ signal = SIGBUS;
+ else if (ll_bit == 0 || ll_task != current)
+ regp->regs[reg] = 0;
+ else if (put_user(regp->regs[reg], vaddr))
+ signal = SIGSEGV;
+ else
+ regp->regs[reg] = 1;
+ if (compute_return_epc(regp))
+ return;
+ if (signal)
+ send_sig(signal, current, 1);
+}
+
/*
* This routine abuses get_user()/put_user() to reference pointers
* with at least a bit of error checking ...
@@ -516,12 +602,6 @@
force_sig(SIGSEGV, current);
}
-#ifndef CONFIG_CPU_HAS_LLSC
-
-#ifdef CONFIG_SMP
-#error "ll/sc emulation is not SMP safe"
-#endif
-
/*
* userland emulation for R2300 CPUs
* needed for the multithreading part of glibc
@@ -531,11 +611,19 @@
*/
asmlinkage void do_ri(struct pt_regs *regs)
{
- unsigned int opcode;
if (!user_mode(regs))
BUG();
+#ifndef CONFIG_CPU_HAS_LLSC
+
+#ifdef CONFIG_SMP
+#error "ll/sc emulation is not SMP safe"
+#endif
+
+ {
+ unsigned int opcode;
+
if (!get_insn_opcode(regs, &opcode)) {
if ((opcode & OPCODE) == LL) {
simulate_ll(regs, opcode);
@@ -546,113 +634,13 @@
return;
}
}
-
- if (compute_return_epc(regs))
- return;
- force_sig(SIGILL, current);
-}
-
-/*
- * The ll_bit is cleared by r*_switch.S
- */
-
-unsigned long ll_bit;
-#ifdef CONFIG_PROC_FS
-extern unsigned long ll_ops;
-extern unsigned long sc_ops;
-#endif
-
-static struct task_struct *ll_task = NULL;
-
-void simulate_ll(struct pt_regs *regp, unsigned int opcode)
-{
- unsigned long value, *vaddr;
- long offset;
- int signal = 0;
-
- /*
- * analyse the ll instruction that just caused a ri exception
- * and put the referenced address to addr.
- */
-
- /* sign extend offset */
- offset = opcode & OFFSET;
- offset <<= 16;
- offset >>= 16;
-
- vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset);
-
-#ifdef CONFIG_PROC_FS
- ll_ops++;
-#endif
-
- if ((unsigned long)vaddr & 3)
- signal = SIGBUS;
- else if (get_user(value, vaddr))
- signal = SIGSEGV;
- else {
- if (ll_task == NULL || ll_task == current) {
- ll_bit = 1;
- } else {
- ll_bit = 0;
- }
- ll_task = current;
- regp->regs[(opcode & RT) >> 16] = value;
}
- if (compute_return_epc(regp))
- return;
- if (signal)
- send_sig(signal, current, 1);
-}
-
-void simulate_sc(struct pt_regs *regp, unsigned int opcode)
-{
- unsigned long *vaddr, reg;
- long offset;
- int signal = 0;
-
- /*
- * analyse the sc instruction that just caused a ri exception
- * and put the referenced address to addr.
- */
-
- /* sign extend offset */
- offset = opcode & OFFSET;
- offset <<= 16;
- offset >>= 16;
-
- vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset);
- reg = (opcode & RT) >> 16;
-
-#ifdef CONFIG_PROC_FS
- sc_ops++;
-#endif
-
- if ((unsigned long)vaddr & 3)
- signal = SIGBUS;
- else if (ll_bit == 0 || ll_task != current)
- regp->regs[reg] = 0;
- else if (put_user(regp->regs[reg], vaddr))
- signal = SIGSEGV;
- else
- regp->regs[reg] = 1;
- if (compute_return_epc(regp))
- return;
- if (signal)
- send_sig(signal, current, 1);
-}
-
-#else /* MIPS 2 or higher */
+#endif /* CONFIG_CPU_HAS_LLSC */
-asmlinkage void do_ri(struct pt_regs *regs)
-{
if (compute_return_epc(regs))
return;
-
force_sig(SIGILL, current);
}
-
-#endif
asmlinkage void do_cpu(struct pt_regs *regs)
{
|
|
From: Paul M. <le...@us...> - 2001-11-13 22:12:02
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv14652/drivers/net
Modified Files:
Config.in
Log Message:
Require CONFIG_PCI for Toshiba TC35815.
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Config.in,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- Config.in 2001/11/10 03:52:49 1.15
+++ Config.in 2001/11/13 22:11:59 1.16
@@ -171,7 +171,7 @@
tristate ' Generic DECchip & DIGITAL EtherWORKS PCI/EISA' CONFIG_DE4X5
tristate ' Digi Intl. RightSwitch SE-X support' CONFIG_DGRS
fi
- dep_tristate ' TOSHIBA TC35815 Ethernet support' CONFIG_TC35815
+ dep_tristate ' TOSHIBA TC35815 Ethernet support' CONFIG_TC35815 $CONFIG_PCI
dep_tristate ' Davicom DM910x/DM980x support' CONFIG_DM9102 $CONFIG_PCI
dep_tristate ' EtherExpressPro/100 support' CONFIG_EEPRO100 $CONFIG_PCI
dep_tristate ' Mylex EISA LNE390A/B support (EXPERIMENTAL)' CONFIG_LNE390 $CONFIG_EISA $CONFIG_EXPERIMENTAL
|
|
From: James S. <jsi...@us...> - 2001-11-13 17:10:12
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv26774/include/asm-mips Modified Files: tx3912.h Log Message: Nino updates. Index: tx3912.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/tx3912.h,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- tx3912.h 2001/10/31 18:30:14 1.4 +++ tx3912.h 2001/11/13 17:10:09 1.5 @@ -7,572 +7,342 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Register includes for TMPR3912/05 and PR31700 processors + * Registers for TMPR3912/05 and PR31700 processors */ #ifndef _TX3912_H_ #define _TX3912_H_ - -#include <asm/addrspace.h> - -#define inb(addr) (*(volatile unsigned char *)(addr)) -#define inw(addr) (*(volatile unsigned short *)(addr)) -#define inl(addr) (*(volatile unsigned int *)(addr)) -#define outb(b,addr) (*(volatile unsigned char *)(addr)) = (b) -#define outw(b,addr) (*(volatile unsigned short *)(addr)) = (b) -#define outl(b,addr) (*(volatile unsigned int *)(addr)) = (b) - -/****************************************************************************** -* -* 01 General macro definitions -* -******************************************************************************/ - -#define REGISTER_BASE 0xb0c00000 - -#ifndef _LANGUAGE_ASSEMBLY - - #define REG_AT(x) (*((volatile unsigned long *)(REGISTER_BASE + x))) - -#else - - #define REG_AT(x) (REGISTER_BASE + x) - -#endif - -#define BIT(x) (1 << x) - -/****************************************************************************** -* -* 02 Bus Interface Unit -* -******************************************************************************/ - -#define MemConfig0 REG_AT(0x000) -#define MemConfig1 REG_AT(0x004) -#define MemConfig2 REG_AT(0x008) -#define MemConfig3 REG_AT(0x00c) -#define MemConfig4 REG_AT(0x010) -#define MemConfig5 REG_AT(0x014) -#define MemConfig6 REG_AT(0x018) -#define MemConfig7 REG_AT(0x01c) -#define MemConfig8 REG_AT(0x020) - -/* Memory config register 1 */ -#define MEM1_ENCS1USER BIT(21) - -/* Memory config register 3 */ -#define MEM3_CARD1ACCVAL_MASK (BIT(24) | BIT(25) | BIT(26) | BIT(27)) -#define MEM3_CARD1IOEN BIT(4) - -/* Memory config register 4 */ -#define MEM4_ARBITRATIONEN BIT(29) -#define MEM4_MEMPOWERDOWN BIT(16) -#define MEM4_ENREFRESH1 BIT(15) -#define MEM4_ENREFRESH0 BIT(14) -#define MEM4_ENWATCH BIT(24) -#define MEM4_WATCHTIMEVAL_MASK (0xf) -#define MEM4_WATCHTIMEVAL_SHIFT (20) -#define MEM4_WATCHTIME_VALUE (0xf) +/***************************************************************************** + * Clock Subsystem * + * --------------- * + * Chapter 6 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals * + *****************************************************************************/ +#define TX3912_CLK_CTRL 0x01c0 /* - *********************************************************************** - * * - * 06 Clock Module * - * * - *********************************************************************** + * Clock control register values */ -#define TX3912_CLK_CTRL_BASE (REGISTER_BASE + 0x1c0) - -#define TX3912_CLK_CTRL_CHICLKDIV_MASK 0xff000000 -#define TX3912_CLK_CTRL_CHICLKDIV_SHIFT 24 -#define TX3912_CLK_CTRL_ENCLKTEST 0x00800000 -#define TX3912_CLK_CTRL_CLKTESTSELSIB 0x00400000 -#define TX3912_CLK_CTRL_CHIMCLKSEL 0x00200000 -#define TX3912_CLK_CTRL_CHICLKDIR 0x00100000 -#define TX3912_CLK_CTRL_ENCHIMCLK 0x00080000 -#define TX3912_CLK_CTRL_ENVIDCLK 0x00040000 -#define TX3912_CLK_CTRL_ENMBUSCLK 0x00020000 -#define TX3912_CLK_CTRL_ENSPICLK 0x00010000 -#define TX3912_CLK_CTRL_ENTIMERCLK 0x00008000 -#define TX3912_CLK_CTRL_ENFASTTIMERCLK 0x00004000 -#define TX3912_CLK_CTRL_SIBMCLKDIR 0x00002000 -#define TX3912_CLK_CTRL_RESERVED 0x00001000 -#define TX3912_CLK_CTRL_ENSIBMCLK 0x00000800 -#define TX3912_CLK_CTRL_SIBMCLKDIV_MASK 0x00000700 -#define TX3912_CLK_CTRL_SIBMCLKDIV_SHIFT 8 -#define TX3912_CLK_CTRL_CSERSEL 0x00000080 -#define TX3912_CLK_CTRL_CSERDIV_MASK 0x00000070 -#define TX3912_CLK_CTRL_CSERDIV_SHIFT 4 -#define TX3912_CLK_CTRL_ENCSERCLK 0x00000008 -#define TX3912_CLK_CTRL_ENIRCLK 0x00000004 -#define TX3912_CLK_CTRL_ENUARTACLK 0x00000002 -#define TX3912_CLK_CTRL_ENUARTBCLK 0x00000001 - - - - -/****************************************************************************** -* -* 07 CHI module -* -******************************************************************************/ - -#define CHIControl REG_AT(0x1D8) -#define CHIPointerEnable REG_AT(0x1DC) -#define CHIReceivePtrA REG_AT(0x1E0) -#define CHIReceivePtrB REG_AT(0x1E4) -#define CHITransmitPtrA REG_AT(0x1E8) -#define CHITransmitPtrB REG_AT(0x1EC) -#define CHISize REG_AT(0x1F0) -#define CHIReceiveStart REG_AT(0x1F4) -#define CHITransmitStart REG_AT(0x1F8) -#define CHIHoldingReg REG_AT(0x1FC) - -/* CHI Control Register */ -/* <incomplete!> */ -#define CHI_RXEN BIT(2) -#define CHI_TXEN BIT(1) -#define CHI_ENCHI BIT(0) - -/****************************************************************************** -* -* 08 Interrupt module -* -******************************************************************************/ - -/* Register locations */ - -#define IntStatus1 REG_AT(0x100) -#define IntStatus2 REG_AT(0x104) -#define IntStatus3 REG_AT(0x108) -#define IntStatus4 REG_AT(0x10c) -#define IntStatus5 REG_AT(0x110) -#define IntStatus6 REG_AT(0x114) - -#define IntClear1 REG_AT(0x100) -#define IntClear2 REG_AT(0x104) -#define IntClear3 REG_AT(0x108) -#define IntClear4 REG_AT(0x10c) -#define IntClear5 REG_AT(0x110) -#define IntClear6 REG_AT(0x114) - -#define IntEnable1 REG_AT(0x118) -#define IntEnable2 REG_AT(0x11c) -#define IntEnable3 REG_AT(0x120) -#define IntEnable4 REG_AT(0x124) -#define IntEnable5 REG_AT(0x128) -#define IntEnable6 REG_AT(0x12c) - -/* Interrupt Status Register 1 at offset 100 */ -#define INT1_LCDINT BIT(31) -#define INT1_DFINT BIT(30) -#define INT1_CHIDMAHALF BIT(29) -#define INT1_CHIDMAFULL BIT(28) -#define INT1_CHIDMACNTINT BIT(27) -#define INT1_CHIRXAINT BIT(26) -#define INT1_CHIRXBINT BIT(25) -#define INT1_CHIACTINT BIT(24) -#define INT1_CHIERRINT BIT(23) -#define INT1_SND0_5INT BIT(22) -#define INT1_SND1_0INT BIT(21) -#define INT1_TEL0_5INT BIT(20) -#define INT1_TEL1_0INT BIT(19) -#define INT1_SNDDMACNTINT BIT(18) -#define INT1_TELDMACNTINT BIT(17) -#define INT1_LSNDCLIPINT BIT(16) -#define INT1_RSNDCLIPINT BIT(15) -#define INT1_VALSNDPOSINT BIT(14) -#define INT1_VALSNDNEGINT BIT(13) -#define INT1_VALTELPOSINT BIT(12) -#define INT1_VALTELNEGINT BIT(11) -#define INT1_SNDININT BIT(10) -#define INT1_TELININT BIT(9) -#define INT1_SIBSF0INT BIT(8) -#define INT1_SIBSF1INT BIT(7) -#define INT1_SIBIRQPOSINT BIT(6) -#define INT1_SIBIRQNEGINT BIT(5) - -/* Interrupt Status Register 2 at offset 104 */ -#define INT2_UARTARXINT BIT(31) -#define INT2_UARTARXOVERRUN BIT(30) -#define INT2_UARTAFRAMEINT BIT(29) -#define INT2_UARTABREAKINT BIT(28) -#define INT2_UARTATXINT BIT(26) -#define INT2_UARTATXOVERRUN BIT(25) -#define INT2_UARTAEMPTY BIT(24) - -#define INT2_UARTBRXINT BIT(21) -#define INT2_UARTBRXOVERRUN BIT(20) -#define INT2_UARTBFRAMEINT BIT(29) -#define INT2_UARTBBREAKINT BIT(18) -#define INT2_UARTBTXINT BIT(16) -#define INT2_UARTBTXOVERRUN BIT(15) -#define INT2_UARTBEMPTY BIT(14) - -#define INT2_UARTA_RX (BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27)) -#define INT2_UARTA_TX (BIT(26) | BIT(25) | BIT(24)) -#define INT2_UARTA_DMA (BIT(23) | BIT(22)) - -#define INT2_UARTB_RX (BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17)) -#define INT2_UARTB_TX (BIT(16) | BIT(15) | BIT(14)) -#define INT2_UARTB_DMA (BIT(13) | BIT(12)) - -/* Interrupt Status Register 5 */ -#define INT5_RTCINT BIT(31) -#define INT5_ALARMINT BIT(30) -#define INT5_PERIODICINT BIT(29) -#define INT5_POSPWRINT BIT(27) -#define INT5_NEGPWRINT BIT(26) -#define INT5_POSPWROKINT BIT(25) -#define INT5_NEGPWROKINT BIT(24) -#define INT5_POSONBUTINT BIT(23) -#define INT5_NEGONBUTINT BIT(22) -#define INT5_SPIAVAILINT BIT(21) /* 0x0020 0000 */ -#define INT5_SPIERRINT BIT(20) /* 0x0010 0000 */ -#define INT5_SPIRCVINT BIT(19) /* 0x0008 0000 */ -#define INT5_SPIEMPTYINT BIT(18) /* 0x0004 0000 */ -#define INT5_IOPOSINT6 BIT(13) -#define INT5_IOPOSINT5 BIT(12) -#define INT5_IOPOSINT4 BIT(11) -#define INT5_IOPOSINT3 BIT(10) -#define INT5_IOPOSINT2 BIT(9) -#define INT5_IOPOSINT1 BIT(8) -#define INT5_IOPOSINT0 BIT(7) -#define INT5_IONEGINT6 BIT(6) -#define INT5_IONEGINT5 BIT(5) -#define INT5_IONEGINT4 BIT(4) -#define INT5_IONEGINT3 BIT(3) -#define INT5_IONEGINT2 BIT(2) -#define INT5_IONEGINT1 BIT(1) -#define INT5_IONEGINT0 BIT(0) - -#define INT5_IONEGINT_SHIFT 0 -#define INT5_IONEGINT_MASK (0x7F<<INT5_IONEGINT_SHIFT) -#define INT5_IOPOSINT_SHIFT 7 -#define INT5_IOPOSINT_MASK (0x7F<<INT5_IOPOSINT_SHIFT) - -/* Interrupt Status Register 6 */ -#define INT6_IRQHIGH BIT(31) -#define INT6_IRQLOW BIT(30) -#define INT6_INTVECT (BIT(5) | BIT(4) | BIT(3) | BIT(2)) - - -/* Interrupt Enable Register 6 */ -#define INT6_GLOBALEN BIT(18) -#define INT6_PWROKINT BIT(15) -#define INT6_ALARMINT BIT(14) -#define INT6_PERIODICINT BIT(13) -#define INT6_MBUSINT BIT(12) -#define INT6_UARTARXINT BIT(11) -#define INT6_UARTBRXINT BIT(10) -#define INT6_MFIOPOSINT1619 BIT(9) -#define INT6_IOPOSINT56 BIT(8) -#define INT6_MFIONEGINT1619 BIT(7) -#define INT6_IONEGINT56 BIT(6) -#define INT6_MBUSDMAFULLINT BIT(5) -#define INT6_SNDDMACNTINT BIT(4) -#define INT6_TELDMACNTINT BIT(3) -#define INT6_CHIDMACNTINT BIT(2) -#define INT6_IOPOSNEGINT0 BIT(1) - -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) - -/****************************************************************************** -* -* 09 GPIO and MFIO modules -* -******************************************************************************/ - -#define IOControl REG_AT(0x180) -#define MFIOOutput REG_AT(0x184) -#define MFIODirection REG_AT(0x188) -#define MFIOInput REG_AT(0x18c) -#define MFIOSelect REG_AT(0x190) -#define IOPowerDown REG_AT(0x194) -#define MFIOPowerDown REG_AT(0x198) - -#define IODIN_MASK 0x0000007f -#define IODIN_SHIFT 0 -#define IODOUT_MASK 0x00007f00 -#define IODOUT_SHIFT 8 -#define IODIREC_MASK 0x007f0000 -#define IODIREC_SHIFT 16 -#define IODEBSEL_MASK 0x7f000000 -#define IODEBSEL_SHIFT 24 - -/****************************************************************************** -* -* 10 IR module -* -******************************************************************************/ - -#define IRControl1 REG_AT(0x0a0) -#define IRControl2 REG_AT(0x0a4) - -/* IR Control 1 Register */ -#define IR_CARDRET BIT(24) -#define IR_BAUDVAL_MASK 0x00ff0000 -#define IR_BAUDVAL_SHIFT 16 -#define IR_TESTIR BIT(4) -#define IR_DTINVERT BIT(3) -#define IR_RXPWR BIT(2) -#define IR_ENSTATE BIT(1) -#define IR_ENCONSM BIT(0) - -/* IR Control 2 Register */ -#define IR_PER_MASK 0xff000000 -#define IR_PER_SHIFT 24 -#define IR_ONTIME_MASK 0x00ff0000 -#define IR_ONTIME_SHIFT 16 -#define IR_DELAYVAL_MASK 0x0000ff00 -#define IR_DELAYVAL_SHIFT 8 -#define IR_WAITVAL_MASK 0x000000ff -#define IR_WAITVAL_SHIFT 0 - -/****************************************************************************** -* -* 11 Magicbus Module -* -******************************************************************************/ - -#define MbusCntrl1 REG_AT(0x0e0) -#define MbusCntrl2 REG_AT(0x0e4) -#define MbusDMACntrl1 REG_AT(0x0e8) -#define MbusDMACntrl2 REG_AT(0x0ec) -#define MbusDMACount REG_AT(0x0f0) -#define MbusTxReg REG_AT(0x0f4) -#define MbusRxReg REG_AT(0x0f8) - -#define MBUS_CLKPOL BIT(4) -#define MBUS_SLAVE BIT(3) -#define MBUS_FSLAVE BIT(2) -#define MBUS_LONG BIT(1) -#define MBUS_ENMBUS BIT(0) - -/****************************************************************************** -* -* 12 Power module -* -******************************************************************************/ - -#define PowerControl REG_AT(0x1C4) +#define TX3912_CLK_CTRL_CHICLKDIV_MASK 0xff000000 +#define TX3912_CLK_CTRL_CHICLKDIV_SHIFT 24 +#define TX3912_CLK_CTRL_ENCLKTEST 0x00800000 +#define TX3912_CLK_CTRL_CLKTESTSELSIB 0x00400000 +#define TX3912_CLK_CTRL_CHIMCLKSEL 0x00200000 +#define TX3912_CLK_CTRL_CHICLKDIR 0x00100000 +#define TX3912_CLK_CTRL_ENCHIMCLK 0x00080000 +#define TX3912_CLK_CTRL_ENVIDCLK 0x00040000 +#define TX3912_CLK_CTRL_ENMBUSCLK 0x00020000 +#define TX3912_CLK_CTRL_ENSPICLK 0x00010000 +#define TX3912_CLK_CTRL_ENTIMERCLK 0x00008000 +#define TX3912_CLK_CTRL_ENFASTTIMERCLK 0x00004000 +#define TX3912_CLK_CTRL_SIBMCLKDIR 0x00002000 +#define TX3912_CLK_CTRL_RESERVED 0x00001000 +#define TX3912_CLK_CTRL_ENSIBMCLK 0x00000800 +#define TX3912_CLK_CTRL_SIBMCLKDIV_MASK 0x00000700 +#define TX3912_CLK_CTRL_SIBMCLKDIV_SHIFT 8 +#define TX3912_CLK_CTRL_CSERSEL 0x00000080 +#define TX3912_CLK_CTRL_CSERDIV_MASK 0x00000070 +#define TX3912_CLK_CTRL_CSERDIV_SHIFT 4 +#define TX3912_CLK_CTRL_ENCSERCLK 0x00000008 +#define TX3912_CLK_CTRL_ENIRCLK 0x00000004 +#define TX3912_CLK_CTRL_ENUARTACLK 0x00000002 +#define TX3912_CLK_CTRL_ENUARTBCLK 0x00000001 -#define PWR_ONBUTN BIT(31) -#define PWR_PWRINT BIT(30) -#define PWR_PWROK BIT(29) -#define PWR_VIDRF_MASK (BIT(28) | BIT(27)) -#define PWR_VIDRF_SHIFT 27 -#define PWR_SLOWBUS BIT(26) -#define PWR_DIVMOD BIT(25) -#define PWR_STPTIMERVAL_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) -#define PWR_STPTIMERVAL_SHIFT 12 -#define PWR_ENSTPTIMER BIT(11) -#define PWR_ENFORCESHUTDWN BIT(10) -#define PWR_FORCESHUTDWN BIT(9) -#define PWR_FORCESHUTDWNOCC BIT(8) -#define PWR_SELC2MS BIT(7) -#define PWR_BPDBVCC3 BIT(5) -#define PWR_STOPCPU BIT(4) -#define PWR_DBNCONBUTN BIT(3) -#define PWR_COLDSTART BIT(2) -#define PWR_PWRCS BIT(1) -#define PWR_VCCON BIT(0) -/****************************************************************************** -* -* 13 SIB (Serial Interconnect Bus) Module -* -******************************************************************************/ +/***************************************************************************** + * Interrupt Subsystem * + * ------------------- * + * Chapter 8 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals * + *****************************************************************************/ +#define TX3912_INT1_CLEAR 0x0100 +#define TX3912_INT2_CLEAR 0x0104 +#define TX3912_INT3_CLEAR 0x0108 +#define TX3912_INT4_CLEAR 0x010c +#define TX3912_INT5_CLEAR 0x0110 +#define TX3912_INT1_ENABLE 0x0118 +#define TX3912_INT2_ENABLE 0x011c +#define TX3912_INT3_ENABLE 0x0120 +#define TX3912_INT4_ENABLE 0x0124 +#define TX3912_INT5_ENABLE 0x0128 +#define TX3912_INT6_ENABLE 0x012c +#define TX3912_INT1_STATUS 0x0100 +#define TX3912_INT2_STATUS 0x0104 +#define TX3912_INT3_STATUS 0x0108 +#define TX3912_INT4_STATUS 0x010c +#define TX3912_INT5_STATUS 0x0110 +#define TX3912_INT6_STATUS 0x0114 -/* Register locations */ -#define SIBSize REG_AT(0x060) -#define SIBSoundRXStart REG_AT(0x064) -#define SIBSoundTXStart REG_AT(0x068) -#define SIBTelecomRXStart REG_AT(0x06C) -#define SIBTelecomTXStart REG_AT(0x070) -#define SIBControl REG_AT(0x074) -#define SIBSoundTXRXHolding REG_AT(0x078) -#define SIBTelecomTXRXHolding REG_AT(0x07C) -#define SIBSubFrame0Control REG_AT(0x080) -#define SIBSubFrame1Control REG_AT(0x084) -#define SIBSubFrame0Status REG_AT(0x088) -#define SIBSubFrame1Status REG_AT(0x08C) -#define SIBDMAControl REG_AT(0x090) +/* + * Interrupt 2 register values + */ +#define TX3912_INT2_UARTARXINT 0x80000000 +#define TX3912_INT2_UARTARXOVERRUNINT 0x40000000 +#define TX3912_INT2_UARTAFRAMEERRINT 0x20000000 +#define TX3912_INT2_UARTABREAKINT 0x10000000 +#define TX3912_INT2_UARTAPARITYINT 0x08000000 +#define TX3912_INT2_UARTATXINT 0x04000000 +#define TX3912_INT2_UARTATXOVERRUNINT 0x02000000 +#define TX3912_INT2_UARTAEMPTYINT 0x01000000 +#define TX3912_INT2_UARTADMAFULLINT 0x00800000 +#define TX3912_INT2_UARTADMAHALFINT 0x00400000 +#define TX3912_INT2_UARTBRXINT 0x00200000 +#define TX3912_INT2_UARTBRXOVERRUNINT 0x00100000 +#define TX3912_INT2_UARTBFRAMEERRINT 0x00080000 +#define TX3912_INT2_UARTBBREAKINT 0x00040000 +#define TX3912_INT2_UARTBPARITYINT 0x00020000 +#define TX3912_INT2_UARTBTXINT 0x00010000 +#define TX3912_INT2_UARTBTXOVERRUNINT 0x00008000 +#define TX3912_INT2_UARTBEMPTYINT 0x00004000 +#define TX3912_INT2_UARTBDMAFULLINT 0x00002000 +#define TX3912_INT2_UARTBDMAHALFINT 0x00001000 +#define TX3912_INT2_UARTA_RX_BITS 0xf8000000 +#define TX3912_INT2_UARTA_TX_BITS 0x07c00000 +#define TX3912_INT2_UARTB_RX_BITS 0x003e0000 +#define TX3912_INT2_UARTB_TX_BITS 0x0001f000 -/* SIB Size Register */ -#define SIB_SNDSIZE_MASK 0x3ffc0000 -#define SIB_SNDSIZE_SHIFT 18 -#define SIB_TELSIZE_MASK 0x00003ffc -#define SIB_TELSIZE_SHIFT 2 +/* + * Interrupt 5 register values + */ +#define TX3912_INT5_RTCINT 0x80000000 +#define TX3912_INT5_ALARMINT 0x40000000 +#define TX3912_INT5_PERINT 0x20000000 +#define TX3912_INT5_STPTIMERINT 0x10000000 +#define TX3912_INT5_POSPWRINT 0x08000000 +#define TX3912_INT5_NEGPWRINT 0x04000000 +#define TX3912_INT5_POSPWROKINT 0x02000000 +#define TX3912_INT5_NEGPWROKINT 0x01000000 +#define TX3912_INT5_POSONBUTINT 0x00800000 +#define TX3912_INT5_NEGONBUTINT 0x00400000 +#define TX3912_INT5_SPIBUFAVAILINT 0x00200000 +#define TX3912_INT5_SPIERRINT 0x00100000 +#define TX3912_INT5_SPIRCVINT 0x00080000 +#define TX3912_INT5_SPIEMPTYINT 0x00040000 +#define TX3912_INT5_IRCONSMINT 0x00020000 +#define TX3912_INT5_CARSTINT 0x00010000 +#define TX3912_INT5_POSCARINT 0x00008000 +#define TX3912_INT5_NEGCARINT 0x00004000 +#define TX3912_INT5_IOPOSINT6 0x00002000 +#define TX3912_INT5_IOPOSINT5 0x00001000 +#define TX3912_INT5_IOPOSINT4 0x00000800 +#define TX3912_INT5_IOPOSINT3 0x00000400 +#define TX3912_INT5_IOPOSINT2 0x00000200 +#define TX3912_INT5_IOPOSINT1 0x00000100 +#define TX3912_INT5_IOPOSINT0 0x00000080 +#define TX3912_INT5_IONEGINT6 0x00000040 +#define TX3912_INT5_IONEGINT5 0x00000020 +#define TX3912_INT5_IONEGINT4 0x00000010 +#define TX3912_INT5_IONEGINT3 0x00000008 +#define TX3912_INT5_IONEGINT2 0x00000004 +#define TX3912_INT5_IONEGINT1 0x00000002 +#define TX3912_INT5_IONEGINT0 0x00000001 -/* SIB Control Register */ -#define SIB_SIBIRQ BIT(31) -#define SIB_ENCNTTEST BIT(30) -#define SIB_ENDMATEST BIT(29) -#define SIB_SNDMONO BIT(28) -#define SIB_RMONOSNDIN BIT(27) -#define SIB_SIBSCLKDIV_MASK (BIT(26) | BIT(25) | BIT(24)) -#define SIB_SIBSCLKDIV_SHIFT 24 -#define SIB_TEL16 BIT(23) -#define SIB_TELFSDIV_MASK 0x007f0000 -#define SIB_TELFSDIV_SHIFT 16 -#define SIB_SND16 BIT(15) -#define SIB_SNDFSDIV_MASK 0x00007f00 -#define SIB_SNDFSDIV_SHIFT 8 -#define SIB_SELTELSF1 BIT(7) -#define SIB_SELSNDSF1 BIT(6) -#define SIB_ENTEL BIT(5) -#define SIB_ENSND BIT(4) -#define SIB_SIBLOOP BIT(3) -#define SIB_ENSF1 BIT(2) -#define SIB_ENSF0 BIT(1) -#define SIB_ENSIB BIT(0) +/* + * Interrupt 6 status register values + */ +#define TX3912_INT6_STATUS_IRQHIGH 0x80000000 +#define TX3912_INT6_STATUS_IRQLOW 0x40000000 +#define TX3912_INT6_STATUS_reserved2 0x3fffffc0 +#define TX3912_INT6_STATUS_INTVEC_POSNEGPWROKINT 0x0000003c +#define TX3912_INT6_STATUS_INTVEC_ALARMINT 0x00000038 +#define TX3912_INT6_STATUS_INTVEC_PERINT 0x00000034 +#define TX3912_INT6_STATUS_INTVEC_reserved5 0x00000030 +#define TX3912_INT6_STATUS_INTVEC_UARTARXINT 0x0000002c +#define TX3912_INT6_STATUS_INTVEC_UARTBRXINT 0x00000028 +#define TX3912_INT6_STATUS_INTVEC_reserved4 0x00000024 +#define TX3912_INT6_STATUS_INTVEC_IOPOSINT65 0x00000020 +#define TX3912_INT6_STATUS_INTVEC_reserved3 0x0000001c +#define TX3912_INT6_STATUS_INTVEC_IONEGINT65 0x00000018 +#define TX3912_INT6_STATUS_INTVEC_reserved2 0x00000014 +#define TX3912_INT6_STATUS_INTVEC_SNDDMACNTINT 0x00000010 +#define TX3912_INT6_STATUS_INTVEC_TELDMACNTINT 0x0000000c +#define TX3912_INT6_STATUS_INTVEC_CHIDMACNTINT 0x00000008 +#define TX3912_INT6_STATUS_INTVEC_IOPOSNEGINT0 0x00000004 +#define TX3912_INT6_STATUS_INTVEC_STDHANDLER 0x00000000 +#define TX3912_INT6_STATUS_reserved1 0x00000003 -/* SIB Frame Format (SIBSubFrame0Status and SIBSubFrame1Status) */ -#define SIB_REGISTER_EXT BIT(31) /* Must be zero */ -#define SIB_ADDRESS_MASK 0x78000000 -#define SIB_ADDRESS_SHIFT 27 -#define SIB_WRITE BIT(26) -#define SIB_AUD_VALID BIT(17) -#define SIB_TEL_VALID BIT(16) -#define SIB_DATA_MASK 0x00ff -#define SIB_DATA_SHIFT 0 +/* + * Interrupt 6 enable register values + */ +#define TX3912_INT6_ENABLE_reserved5 0xfff80000 +#define TX3912_INT6_ENABLE_GLOBALEN 0x00040000 +#define TX3912_INT6_ENABLE_IRQPRITEST 0x00020000 +#define TX3912_INT6_ENABLE_IRQTEST 0x00010000 +#define TX3912_INT6_ENABLE_PRIORITYMASK_POSNEGPWROKINT 0x00008000 +#define TX3912_INT6_ENABLE_PRIORITYMASK_ALARMINT 0x00004000 +#define TX3912_INT6_ENABLE_PRIORITYMASK_PERINT 0x00002000 +#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved4 0x00001000 +#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTARXINT 0x00000800 +#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTBRXINT 0x00000400 +#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved3 0x00000200 +#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSINT65 0x00000100 +#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved2 0x00000080 +#define TX3912_INT6_ENABLE_PRIORITYMASK_IONEGINT65 0x00000040 +#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved1 0x00000020 +#define TX3912_INT6_ENABLE_PRIORITYMASK_SNDDMACNTINT 0x00000010 +#define TX3912_INT6_ENABLE_PRIORITYMASK_TELDMACNTINT 0x00000008 +#define TX3912_INT6_ENABLE_PRIORITYMASK_CHIDMACNTINT 0x00000004 +#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSNEGINT0 0x00000002 +#define TX3912_INT6_ENABLE_PRIORITYMASK_STDHANDLER 0x00000001 +#define TX3912_INT6_ENABLE_HIGH_PRIORITY 0x0000ffff -/* SIB DMA Control Register */ -#define SIB_SNDBUFF1TIME BIT(31) -#define SIB_SNDDMALOOP BIT(30) -#define SIB_SNDDMAPTR_MASK 0x3ffc0000 -#define SIB_SNDDMAPTR_SHIFT 18 -#define SIB_ENDMARXSND BIT(17) -#define SIB_ENDMATXSND BIT(16) -#define SIB_TELBUFF1TIME BIT(15) -#define SIB_TELDMALOOP BIT(14) -#define SIB_TELDMAPTR_MASK 0x00003ffc -#define SIB_TELDMAPTR_SHIFT 2 -#define SIB_ENDMARXTEL BIT(1) -#define SIB_ENDMATXTEL BIT(0) -/****************************************************************************** -* -* 14 SPI module -* -******************************************************************************/ +/***************************************************************************** + * Power Subsystem * + * --------------- * + * Chapter 11 in Philips PR31700 User Manual * + * Chapter 12 in Toshiba TMPR3905/12 User Manual * + *****************************************************************************/ +#define TX3912_POWER_CTRL 0x01c4 -#define SPIControl REG_AT(0x160) -#define SPITransmit REG_AT(0x164) -#define SPIReceive REG_AT(0x164) +/* + * Power control register values + */ +#define TX3912_POWER_CTRL_ONBUTN 0x80000000 +#define TX3912_POWER_CTRL_PWRINT 0x40000000 +#define TX3912_POWER_CTRL_PWROK 0x20000000 +#define TX3912_POWER_CTRL_VIDRF_MASK 0x18000000 +#define TX3912_POWER_CTRL_SLOWBUS 0x04000000 +#define TX3912_POWER_CTRL_DIVMOD 0x02000000 +#define TX3912_POWER_CTRL_reserved2 0x01ff0000 +#define TX3912_POWER_CTRL_STPTIMERVAL_MASK 0x0000f000 +#define TX3912_POWER_CTRL_ENSTPTIMER 0x00000800 +#define TX3912_POWER_CTRL_ENFORCESHUTDWN 0x00000400 +#define TX3912_POWER_CTRL_FORCESHUTDWN 0x00000200 +#define TX3912_POWER_CTRL_FORCESHUTDWNOCC 0x00000100 +#define TX3912_POWER_CTRL_SELC2MS 0x00000080 +#define TX3912_POWER_CTRL_reserved1 0x00000040 +#define TX3912_POWER_CTRL_BPDBVCC3 0x00000020 +#define TX3912_POWER_CTRL_STOPCPU 0x00000010 +#define TX3912_POWER_CTRL_DBNCONBUTN 0x00000008 +#define TX3912_POWER_CTRL_COLDSTART 0x00000004 +#define TX3912_POWER_CTRL_PWRCS 0x00000002 +#define TX3912_POWER_CTRL_VCCON 0x00000001 -#define SPI_SPION BIT(17) -#define SPI_EMPTY BIT(16) -#define SPI_DELAYVAL_MASK (BIT(12) | BIT(13) | BIT(14) | BIT(15)) -#define SPI_DELAYVAL_SHIFT 12 -#define SPI_BAUDRATE_MASK (BIT(8) | BIT(9) | BIT(10) | BIT(11)) -#define SPI_BAUDRATE_SHIFT 8 -#define SPI_PHAPOL BIT(5) -#define SPI_CLKPOL BIT(4) -#define SPI_WORD BIT(2) -#define SPI_LSB BIT(1) -#define SPI_ENSPI BIT(0) -/****************************************************************************** -* -* 15 Timer module -* -******************************************************************************/ +/***************************************************************************** + * Timer Subsystem * + * --------------- * + * Chapter 14 in Philips PR31700 User Manual * + * Chapter 15 in Toshiba TMPR3905/12 User Manual * + *****************************************************************************/ +#define TX3912_RTC_HIGH 0x0140 +#define TX3912_RTC_LOW 0x0144 +#define TX3912_RTC_ALARM_HIGH 0x0148 +#define TX3912_RTC_ALARM_LOW 0x014c +#define TX3912_TIMER_CTRL 0x0150 +#define TX3912_TIMER_PERIOD 0x0154 -#define RTChigh REG_AT(0x140) -#define RTClow REG_AT(0x144) -#define RTCalarmHigh REG_AT(0x148) -#define RTCalarmLow REG_AT(0x14c) -#define RTCtimerControl REG_AT(0x150) -#define RTCperiodTimer REG_AT(0x154) +/* + * Timer control register values + */ +#define TX3912_TIMER_CTRL_FREEZEPRE 0x00000080 +#define TX3912_TIMER_CTRL_FREEZERTC 0x00000040 +#define TX3912_TIMER_CTRL_FREEZETIMER 0x00000020 +#define TX3912_TIMER_CTRL_ENPERTIMER 0x00000010 +#define TX3912_TIMER_CTRL_RTCCLEAR 0x00000008 +#define TX3912_TIMER_CTRL_TESTC8MS 0x00000004 +#define TX3912_TIMER_CTRL_ENTESTCLK 0x00000002 +#define TX3912_TIMER_CTRL_ENRTCTST 0x00000001 -/* RTC Timer Control */ -#define TIM_FREEZEPRE BIT(7) -#define TIM_FREEZERTC BIT(6) -#define TIM_FREEZETIMER BIT(5) -#define TIM_ENPERTIMER BIT(4) -#define TIM_RTCCLEAR BIT(3) +/* + * The periodic timer has granularity of 868 nanoseconds which + * results in a count of (1.152 x 10^6 / 100) in order to achieve + * a 10 millisecond periodic system clock. + */ +#define TX3912_SYS_TIMER_VALUE (1152000/HZ) -#define RTC_HIGHMASK (0xFF) -/* RTC Periodic Timer */ -#define TIM_PERCNT 0xFFFF0000 -#define TIM_PERVAL 0x0000FFFF +/***************************************************************************** + * UART Subsystem * + * -------------- * + * Chapter 15 in Philips PR31700 User Manual * + * Chapter 16 in Toshiba TMPR3905/12 User Manual * + *****************************************************************************/ +#define TX3912_UARTA_BASE 0x00b0 +#define TX3912_UARTB_BASE 0x00c8 -/* For a system clock frequency of 36.864MHz, the timer counts at one tick - every 868nS (ie CLK/32). Therefore 11520 counts gives a 10mS interval - */ -#define PER_TIMER_COUNT (1152000/HZ) +#define TX3912_UARTA_CTRL1 0x00b0 +#define TX3912_UARTA_CTRL2 0x00b4 +#define TX3912_UARTA_DMA_CTRL1 0x00b8 +#define TX3912_UARTA_DMA_CTRL2 0x00bc +#define TX3912_UARTA_DMA_CNT 0x00c0 +#define TX3912_UARTA_DATA 0x00c4 +#define TX3912_UARTB_CTRL1 0x00c8 +#define TX3912_UARTB_CTRL2 0x00cc +#define TX3912_UARTB_DMA_CTRL1 0x00d0 +#define TX3912_UARTB_DMA_CTRL2 0x00d4 +#define TX3912_UARTB_DMA_CNT 0x00d8 +#define TX3912_UARTB_DATA 0x00dc /* - *********************************************************************** - * * - * 15 UART Module * - * * - *********************************************************************** + * UART register offsets */ -#define TX3912_UARTA_BASE (REGISTER_BASE + 0x0b0) -#define TX3912_UARTB_BASE (REGISTER_BASE + 0x0c8) +#define TX3912_UART_CTRL1 0x0000 +#define TX3912_UART_CTRL2 0x0004 +#define TX3912_UART_DMA_CTRL1 0x0008 +#define TX3912_UART_DMA_CTRL2 0x000c +#define TX3912_UART_DMA_CNT 0x0010 +#define TX3912_UART_DATA 0x0014 /* - * TX3912 UART register offsets + * UART Control Register 1 values */ -#define TX3912_UART_CTRL1 0x00 -#define TX3912_UART_CTRL2 0x04 -#define TX3912_UART_DMA_CTRL1 0x08 -#define TX3912_UART_DMA_CTRL2 0x0c -#define TX3912_UART_DMA_CNT 0x10 -#define TX3912_UART_DATA 0x14 - -#define UartA_Ctrl1 REG_AT(0x0b0) -#define UartA_Data REG_AT(0x0c4) +#define TX3912_UART_CTRL1_UARTON 0x80000000 +#define TX3912_UART_CTRL1_EMPTY 0x40000000 +#define TX3912_UART_CTRL1_PRXHOLDFULL 0x20000000 +#define TX3912_UART_CTRL1_RXHOLDFULL 0x10000000 +#define TX3912_UART_CTRL1_reserved 0x0fff0000 +#define TX3912_UART_CTRL1_ENDMARX 0x00008000 +#define TX3912_UART_CTRL1_ENDMATX 0x00004000 +#define TX3912_UART_CTRL1_TESTMODE 0x00002000 +#define TX3912_UART_CTRL1_ENBREAKHALT 0x00001000 +#define TX3912_UART_CTRL1_ENDMATEST 0x00000800 +#define TX3912_UART_CTRL1_ENDMALOOP 0x00000400 +#define TX3912_UART_CTRL1_PULSEOPT1 0x00000200 +#define TX3912_UART_CTRL1_PULSEOPT1 0x00000100 +#define TX3912_UART_CTRL1_DTINVERT 0x00000080 +#define TX3912_UART_CTRL1_DISTXD 0x00000040 +#define TX3912_UART_CTRL1_TWOSTOP 0x00000020 +#define TX3912_UART_CTRL1_LOOPBACK 0x00000010 +#define TX3912_UART_CTRL1_BIT_7 0x00000008 +#define TX3912_UART_CTRL1_EVENPARITY 0x00000004 +#define TX3912_UART_CTRL1_ENPARITY 0x00000002 +#define TX3912_UART_CTRL1_ENUART 0x00000001 /* - * Defines for UART Control Register 1 + * UART Control Register 2 values */ -#define TX3912_UART_CTRL1_UARTON 0x80000000 -#define UART_TX_EMPTY BIT(30) -#define UART_PRX_HOLD_FULL BIT(29) -#define UART_RX_HOLD_FULL BIT(28) -#define UART_EN_DMA_RX BIT(15) -#define UART_EN_DMA_TX BIT(14) -#define UART_BREAK_HALT BIT(12) -#define UART_DMA_LOOP BIT(10) -#define UART_PULSE_THREE BIT(9) -#define UART_PULSE_SIX BIT(8) -#define UART_DT_INVERT BIT(7) -#define UART_DIS_TXD BIT(6) -#define UART_LOOPBACK BIT(4) -#define TX3912_UART_CTRL1_ENUART 0x00000001 - -#define SER_SEVEN_BIT BIT(3) -#define SER_EIGHT_BIT 0 -#define SER_EVEN_PARITY (BIT(2) | BIT(1)) -#define SER_ODD_PARITY BIT(1) -#define SER_NO_PARITY 0 -#define SER_TWO_STOP BIT(5) -#define SER_ONE_STOP 0 +#define TX3912_UART_CTRL2_B230400 0x0000 /* 0 */ +#define TX3912_UART_CTRL2_B115200 0x0001 /* 1 */ +#define TX3912_UART_CTRL2_B76800 0x0002 /* 2 */ +#define TX3912_UART_CTRL2_B57600 0x0003 /* 3 */ +#define TX3912_UART_CTRL2_B38400 0x0005 /* 5 */ +#define TX3912_UART_CTRL2_B19200 0x000b /* 11 */ +#define TX3912_UART_CTRL2_B9600 0x0016 /* 22 */ +#define TX3912_UART_CTRL2_B4800 0x002f /* 47 */ +#define TX3912_UART_CTRL2_B2400 0x005f /* 95 */ +#define TX3912_UART_CTRL2_B1200 0x00bf /* 191 */ +#define TX3912_UART_CTRL2_B600 0x017f /* 383 */ +#define TX3912_UART_CTRL2_B300 0x02ff /* 767 */ -/* - * Defines for UART Control Register 2 - * - * 3.6864MHz - * divisors = ----------- - 1 - * (baud * 16) - */ -#define TX3912_UART_CTRL2_B230400 0x000 /* 0 */ -#define TX3912_UART_CTRL2_B115200 0x001 /* 1 */ -#define TX3912_UART_CTRL2_B76800 0x002 /* 2 */ -#define TX3912_UART_CTRL2_B57600 0x003 /* 3 */ -#define TX3912_UART_CTRL2_B38400 0x005 /* 5 */ -#define TX3912_UART_CTRL2_B19200 0x00b /* 11 */ -#define TX3912_UART_CTRL2_B9600 0x016 /* 22 */ -#define TX3912_UART_CTRL2_B4800 0x02f /* 47 */ -#define TX3912_UART_CTRL2_B2400 0x05f /* 95 */ -#define TX3912_UART_CTRL2_B1200 0x0bf /* 191 */ -#define TX3912_UART_CTRL2_B600 0x17f /* 383 */ -#define TX3912_UART_CTRL2_B300 0x2ff /* 767 */ +/***************************************************************************** + * Video Subsystem * + * --------------- * + * Chapter 16 in Philips PR31700 User Manual * + * Chapter 17 in Toshiba TMPR3905/12 User Manual * + *****************************************************************************/ +#define TX3912_VIDEO_CTRL1 0x0028 +#define TX3912_VIDEO_CTRL2 0x002c +#define TX3912_VIDEO_CTRL3 0x0030 +#define TX3912_VIDEO_CTRL4 0x0034 +#define TX3912_VIDEO_CTRL5 0x0038 +#define TX3912_VIDEO_CTRL6 0x003c +#define TX3912_VIDEO_CTRL7 0x0040 +#define TX3912_VIDEO_CTRL8 0x0044 +#define TX3912_VIDEO_CTRL9 0x0048 +#define TX3912_VIDEO_CTRL10 0x004c +#define TX3912_VIDEO_CTRL11 0x0050 +#define TX3912_VIDEO_CTRL12 0x0054 +#define TX3912_VIDEO_CTRL13 0x0058 +#define TX3912_VIDEO_CTRL14 0x005c #endif /* _TX3912_H_ */ |
|
From: James S. <jsi...@us...> - 2001-11-13 17:10:12
|
Update of /cvsroot/linux-mips/linux/drivers/video
In directory usw-pr-cvs1:/tmp/cvs-serv26774/drivers/video
Modified Files:
fbmem.c
Added Files:
tx3912fb.c tx3912fb.h
Log Message:
Nino updates.
Index: fbmem.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/video/fbmem.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- fbmem.c 2001/11/06 00:43:17 1.12
+++ fbmem.c 2001/11/13 17:10:09 1.13
@@ -285,9 +285,6 @@
#ifdef CONFIG_FB_TX3912
{ "tx3912", tx3912fb_init, NULL },
#endif
-#ifdef CONFIG_FB_TX3912
- { "tx3912", tx3912fb_init, NULL },
-#endif
#ifdef CONFIG_FB_E1355
{ "e1355fb", e1355fb_init, e1355fb_setup },
#endif
|
|
From: James S. <jsi...@us...> - 2001-11-13 17:10:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv26774/arch/mips/configs Modified Files: defconfig-nino Log Message: Nino updates. Index: defconfig-nino =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-nino,v retrieving revision 1.13 retrieving revision 1.14 diff -u -d -r1.13 -r1.14 --- defconfig-nino 2001/11/07 20:50:10 1.13 +++ defconfig-nino 2001/11/13 17:10:09 1.14 @@ -46,6 +46,7 @@ # CONFIG_MCA is not set # CONFIG_SBUS is not set CONFIG_NEW_IRQ=y +CONFIG_NEW_TIME_C=y CONFIG_PC_KEYB=y # CONFIG_ISA is not set # CONFIG_EISA is not set @@ -91,8 +92,8 @@ CONFIG_ELF_KERNEL=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=y -# CONFIG_NET is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_NET=y # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set CONFIG_SYSVIPC=y @@ -121,8 +122,8 @@ # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=2048 -# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_RAM_SIZE=512 +CONFIG_BLK_DEV_INITRD=y # # Multi-device support (RAID and LVM) @@ -137,6 +138,49 @@ # CONFIG_BLK_DEV_LVM is not set # +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# # Telephony Support # # CONFIG_PHONE is not set @@ -160,17 +204,29 @@ # # CONFIG_I2O is not set # CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set # +# Network device support +# +# CONFIG_NETDEVICES is not set + +# # Amateur Radio support # # CONFIG_HAMRADIO is not set # +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# # ISDN subsystem # +# CONFIG_ISDN is not set # # Old CD-ROM drivers (not SCSI, not IDE) @@ -180,7 +236,8 @@ # # Character devices # -# CONFIG_VT is not set +CONFIG_VT=y +CONFIG_VT_CONSOLE=y # CONFIG_SERIAL is not set # CONFIG_SERIAL_EXTENDED is not set CONFIG_SERIAL_NONSTANDARD=y @@ -299,8 +356,28 @@ # CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set # CONFIG_UFS_FS_WRITE is not set -# CONFIG_NCPFS_NLS is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_NFS_FS is not set +# CONFIG_NFS_V3 is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +# CONFIG_SUNRPC is not set +# CONFIG_LOCKD is not set # CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set # CONFIG_ZISOFS_FS is not set # CONFIG_ZLIB_FS_INFLATE is not set @@ -313,6 +390,42 @@ # CONFIG_NLS is not set # +# Console drivers +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set + +# +# Frame-buffer support +# +CONFIG_FB=y +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FB_CYBER2000 is not set +CONFIG_FB_TX3912=y +# CONFIG_FB_VIRTUAL is not set +CONFIG_FBCON_ADVANCED=y +CONFIG_FBCON_MFB=y +# CONFIG_FBCON_CFB2 is not set +# CONFIG_FBCON_CFB4 is not set +# CONFIG_FBCON_CFB8 is not set +# CONFIG_FBCON_CFB16 is not set +# CONFIG_FBCON_CFB24 is not set +# CONFIG_FBCON_CFB32 is not set +# CONFIG_FBCON_AFB is not set +# CONFIG_FBCON_ILBM is not set +# CONFIG_FBCON_IPLAN2P2 is not set +# CONFIG_FBCON_IPLAN2P4 is not set +# CONFIG_FBCON_IPLAN2P8 is not set +# CONFIG_FBCON_MAC is not set +# CONFIG_FBCON_VGA_PLANES is not set +# CONFIG_FBCON_VGA is not set +# CONFIG_FBCON_HGA is not set +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set +# CONFIG_FBCON_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y + +# # Sound # # CONFIG_SOUND is not set @@ -373,11 +486,12 @@ # # USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support # +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDCETHER is not set +# CONFIG_USB_USBNET is not set # # USB port drivers |
|
From: James S. <jsi...@us...> - 2001-11-13 17:10:11
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv26774/drivers/char
Modified Files:
serial_tx3912.c
Log Message:
Nino updates.
Index: serial_tx3912.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/serial_tx3912.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- serial_tx3912.c 2001/10/26 22:30:51 1.6
+++ serial_tx3912.c 2001/11/13 17:10:09 1.7
@@ -1,8 +1,6 @@
/*
* drivers/char/serial_tx3912.c
*
- * Copyright (C) 1999 Harald Koerfgen
- * Copyright (C) 2000 Jim Pick <ji...@ji...>
* Copyright (C) 2001 Steven J. Hill (sj...@re...)
*
* This program is free software; you can redistribute it and/or modify
@@ -101,7 +99,7 @@
/* While there are characters, get them ... */
while (counter>0) {
- if (!(inl(port->base + TX3912_UART_CTRL1) & UART_RX_HOLD_FULL))
+ if (!(inl(port->base + TX3912_UART_CTRL1) & TX3912_UART_CTRL1_RXHOLDFULL))
break;
ch = inb(port->base + TX3912_UART_DATA);
if (tty->flip.count < TTY_FLIPBUF_SIZE) {
@@ -172,7 +170,7 @@
{
/* While I'm able to transmit ... */
for (;;) {
- if (!(inl(port->base + TX3912_UART_CTRL1) & UART_TX_EMPTY))
+ if (!(inl(port->base + TX3912_UART_CTRL1) & TX3912_UART_CTRL1_EMPTY))
break;
else if (port->x_char) {
outb(port->x_char, port->base + TX3912_UART_DATA);
@@ -240,19 +238,17 @@
port = (struct rs_port *)dev_id;
rs_dprintk (TX3912_UART_DEBUG_INTERRUPTS, "rs_interrupt (port %p, shift %d)...", port, intshift);
- /* Get the interrrupts we have enabled */
- int2status = IntStatus2 & IntEnable2;
+ /* Get the interrupts we have enabled */
+ int2status = inl(TX3912_INT2_STATUS) & inl(TX3912_INT2_ENABLE);
/* Get interrupts in easy to use form */
ints = int2status >> intshift;
/* Clear any interrupts we might be about to handle */
- IntClear2 = int2status & (
- (INTTYPE(UART_RXOVERRUN_INT) |
- INTTYPE(UART_FRAMEERR_INT) |
- INTTYPE(UART_BREAK_INT) |
- INTTYPE(UART_PARITYERR_INT) |
- INTTYPE(UART_RX_INT)) << intshift);
+ if (port->base == TX3912_UARTA_BASE)
+ outl(TX3912_INT2_UARTA_RX_BITS, TX3912_INT2_CLEAR);
+ else
+ outl(TX3912_INT2_UARTB_RX_BITS, TX3912_INT2_CLEAR);
if (!port || !port->gs.tty) {
restore_flags(flags);
@@ -306,8 +302,8 @@
port = (struct rs_port *)dev_id;
rs_dprintk (TX3912_UART_DEBUG_INTERRUPTS, "rs_interrupt (port %p, shift %d)...", port, intshift);
- /* Get the interrrupts we have enabled */
- int2status = IntStatus2 & IntEnable2;
+ /* Get the interrupts we have enabled */
+ int2status = inl(TX3912_INT2_STATUS) & inl(TX3912_INT2_ENABLE);
if (!port || !port->gs.tty) {
restore_flags(flags);
@@ -318,10 +314,10 @@
ints = int2status >> intshift;
/* Clear any interrupts we might be about to handle */
- IntClear2 = int2status & (
- (INTTYPE(UART_TX_INT) |
- INTTYPE(UART_EMPTY_INT) |
- INTTYPE(UART_TXOVERRUN_INT)) << intshift);
+ if (port->base == TX3912_UARTA_BASE)
+ outl(TX3912_INT2_UARTA_TX_BITS, TX3912_INT2_CLEAR);
+ else
+ outl(TX3912_INT2_UARTB_TX_BITS, TX3912_INT2_CLEAR);
/* TX holding register empty, so transmit byte (non-DMA) */
if (ints & (INTTYPE(UART_TX_INT) | INTTYPE(UART_EMPTY_INT))) {
@@ -367,14 +363,17 @@
save_and_cli(flags);
port->gs.flags &= ~GS_TX_INTEN;
-
- IntEnable2 &= ~((INTTYPE(UART_TX_INT) |
- INTTYPE(UART_EMPTY_INT) |
- INTTYPE(UART_TXOVERRUN_INT)) << port->intshift);
- IntClear2 = (INTTYPE(UART_TX_INT) |
- INTTYPE(UART_EMPTY_INT) |
- INTTYPE(UART_TXOVERRUN_INT)) << port->intshift;
+ if (port->base == TX3912_UARTA_BASE) {
+ outl(inl(TX3912_INT2_ENABLE) & ~TX3912_INT2_UARTA_TX_BITS,
+ TX3912_INT2_ENABLE);
+ outl(TX3912_INT2_UARTA_TX_BITS, TX3912_INT2_CLEAR);
+ }
+ else {
+ outl(inl(TX3912_INT2_ENABLE) & ~TX3912_INT2_UARTB_TX_BITS,
+ TX3912_INT2_ENABLE);
+ outl(TX3912_INT2_UARTB_TX_BITS, TX3912_INT2_CLEAR);
+ }
restore_flags(flags);
}
@@ -385,14 +384,17 @@
unsigned long flags;
save_and_cli(flags);
-
- IntClear2 = (INTTYPE(UART_TX_INT) |
- INTTYPE(UART_EMPTY_INT) |
- INTTYPE(UART_TXOVERRUN_INT)) << port->intshift;
- IntEnable2 |= (INTTYPE(UART_TX_INT) |
- INTTYPE(UART_EMPTY_INT) |
- INTTYPE(UART_TXOVERRUN_INT)) << port->intshift;
+ if (port->base == TX3912_UARTA_BASE) {
+ outl(TX3912_INT2_UARTA_TX_BITS, TX3912_INT2_CLEAR);
+ outl(inl(TX3912_INT2_ENABLE) | TX3912_INT2_UARTA_TX_BITS,
+ TX3912_INT2_ENABLE);
+ }
+ else {
+ outl(TX3912_INT2_UARTB_TX_BITS, TX3912_INT2_CLEAR);
+ outl(inl(TX3912_INT2_ENABLE) | TX3912_INT2_UARTB_TX_BITS,
+ TX3912_INT2_ENABLE);
+ }
/* Send a char to start TX interrupts happening */
transmit_char_pio(port);
@@ -407,17 +409,16 @@
save_and_cli(flags);
- IntEnable2 &= ~((INTTYPE(UART_RX_INT) |
- INTTYPE(UART_RXOVERRUN_INT) |
- INTTYPE(UART_FRAMEERR_INT) |
- INTTYPE(UART_BREAK_INT) |
- INTTYPE(UART_PARITYERR_INT)) << port->intshift);
-
- IntClear2 = (INTTYPE(UART_RX_INT) |
- INTTYPE(UART_RXOVERRUN_INT) |
- INTTYPE(UART_FRAMEERR_INT) |
- INTTYPE(UART_BREAK_INT) |
- INTTYPE(UART_PARITYERR_INT)) << port->intshift;
+ if (port->base == TX3912_UARTA_BASE) {
+ outl(inl(TX3912_INT2_ENABLE) & ~TX3912_INT2_UARTA_RX_BITS,
+ TX3912_INT2_ENABLE);
+ outl(TX3912_INT2_UARTA_TX_BITS, TX3912_INT2_CLEAR);
+ }
+ else {
+ outl(inl(TX3912_INT2_ENABLE) & ~TX3912_INT2_UARTB_RX_BITS,
+ TX3912_INT2_ENABLE);
+ outl(TX3912_INT2_UARTB_TX_BITS, TX3912_INT2_CLEAR);
+ }
restore_flags(flags);
}
@@ -428,23 +429,21 @@
unsigned long flags;
save_and_cli(flags);
-
- IntEnable2 |= (INTTYPE(UART_RX_INT) |
- INTTYPE(UART_RXOVERRUN_INT) |
- INTTYPE(UART_FRAMEERR_INT) |
- INTTYPE(UART_BREAK_INT) |
- INTTYPE(UART_PARITYERR_INT)) << port->intshift;
- /* Empty the input buffer - apparently this is *vital* */
- while (inl(port->base + TX3912_UART_CTRL1) & UART_RX_HOLD_FULL) {
- inb(port->base + TX3912_UART_DATA);
+ if (port->base == TX3912_UARTA_BASE) {
+ outl(inl(TX3912_INT2_ENABLE) | TX3912_INT2_UARTA_RX_BITS,
+ TX3912_INT2_ENABLE);
+ while (inl(port->base + TX3912_UART_CTRL1) & TX3912_UART_CTRL1_RXHOLDFULL)
+ inb(port->base + TX3912_UART_DATA);
+ outl(TX3912_INT2_UARTA_RX_BITS, TX3912_INT2_CLEAR);
}
-
- IntClear2 = (INTTYPE(UART_RX_INT) |
- INTTYPE(UART_RXOVERRUN_INT) |
- INTTYPE(UART_FRAMEERR_INT) |
- INTTYPE(UART_BREAK_INT) |
- INTTYPE(UART_PARITYERR_INT)) << port->intshift;
+ else {
+ outl(inl(TX3912_INT2_ENABLE) | TX3912_INT2_UARTB_RX_BITS,
+ TX3912_INT2_ENABLE);
+ while (inl(port->base + TX3912_UART_CTRL1) & TX3912_UART_CTRL1_RXHOLDFULL)
+ inb(port->base + TX3912_UART_DATA);
+ outl(TX3912_INT2_UARTB_RX_BITS, TX3912_INT2_CLEAR);
+ }
restore_flags(flags);
}
@@ -488,36 +487,43 @@
}
#undef e
if (t >= 0) {
- /* Jim: Set Hardware Baud rate - there is some good
- code in drivers/char/serial.c */
-
/* Program hardware for parity, data bits, stop bits (note: these are hardcoded to 8N1 */
- UartA_Ctrl1 &= 0xf000000f;
- UartA_Ctrl1 &= ~(UART_DIS_TXD | SER_SEVEN_BIT | SER_EVEN_PARITY | SER_TWO_STOP);
+ outl(inl(TX3912_UARTA_CTRL1) & 0xf000000f,TX3912_UARTA_CTRL1);
+ outl(inl(TX3912_UARTA_CTRL1) & ~(TX3912_UART_CTRL1_DISTXD | TX3912_UART_CTRL1_BIT_7 |
+ TX3912_UART_CTRL1_ENPARITY |TX3912_UART_CTRL1_EVENPARITY | TX3912_UART_CTRL1_TWOSTOP), TX3912_UARTA_CTRL1);
#define CFLAG port->gs.tty->termios->c_cflag
if (C_PARENB(port->gs.tty)) {
if (!C_PARODD(port->gs.tty))
- UartA_Ctrl1 |= SER_EVEN_PARITY;
+ outl(inl(TX3912_UARTA_CTRL1) |
+ TX3912_UART_CTRL1_ENPARITY | TX3912_UART_CTRL1_EVENPARITY,
+ TX3912_UARTA_CTRL1);
else
- UartA_Ctrl1 |= SER_ODD_PARITY;
+ outl(inl(TX3912_UARTA_CTRL1) &
+ ~TX3912_UART_CTRL1_EVENPARITY,
+ TX3912_UARTA_CTRL1);
}
if ((CFLAG & CSIZE)==CS6)
printk(KERN_ERR "6 bits not supported\n");
if ((CFLAG & CSIZE)==CS5)
printk(KERN_ERR "5 bits not supported\n");
if ((CFLAG & CSIZE)==CS7)
- UartA_Ctrl1 |= SER_SEVEN_BIT;
+ outl(inl(TX3912_UARTA_CTRL1) |
+ TX3912_UART_CTRL1_BIT_7,
+ TX3912_UARTA_CTRL1);
if (C_CSTOPB(port->gs.tty))
- UartA_Ctrl1 |= SER_TWO_STOP;
+ outl(inl(TX3912_UARTA_CTRL1) |
+ TX3912_UART_CTRL1_TWOSTOP,
+ TX3912_UARTA_CTRL1);
outl(t, port->base + TX3912_UART_CTRL2);
outl(0, port->base + TX3912_UART_DMA_CTRL1);
outl(0, port->base + TX3912_UART_DMA_CTRL2);
- UartA_Ctrl1 |= TX3912_UART_CTRL1_UARTON;
+ outl(inl(TX3912_UARTA_CTRL1) | TX3912_UART_CTRL1_UARTON,
+ TX3912_UARTA_CTRL1);
- /* wait until UARTA is stable */
- while (~UartA_Ctrl1 & TX3912_UART_CTRL1_UARTON);
+ /* wait until UARTA is stable */
+ while (~inl(TX3912_UARTA_CTRL1) & TX3912_UART_CTRL1_UARTON);
}
func_exit ();
@@ -531,7 +537,7 @@
scratch = inl(port->base + TX3912_UART_CTRL1);
- return ((scratch & UART_TX_EMPTY) ? 0 : 1);
+ return ((scratch & TX3912_UART_CTRL1_EMPTY) ? 0 : 1);
}
/* ********************************************************************** *
@@ -589,7 +595,6 @@
/* Jim: Initialize port hardware here */
/* Enable high-priority interrupts for UARTA */
- IntEnable6 |= INT6_UARTARXINT;
rs_enable_rx_interrupts(&rs_ports[0]);
retval = gs_block_til_ready(&port->gs, filp);
@@ -922,22 +927,22 @@
unsigned int scratch = 0;
/* Setup master clock for UART */
- scratch = inl(TX3912_CLK_CTRL_BASE);
+ scratch = inl(TX3912_CLK_CTRL);
scratch &= ~TX3912_CLK_CTRL_SIBMCLKDIV_MASK;
scratch |= ((0x2 << TX3912_CLK_CTRL_SIBMCLKDIV_SHIFT) &
TX3912_CLK_CTRL_SIBMCLKDIV_MASK)
| TX3912_CLK_CTRL_SIBMCLKDIR
| TX3912_CLK_CTRL_ENSIBMCLK
| TX3912_CLK_CTRL_CSERSEL;
- outl(scratch, TX3912_CLK_CTRL_BASE);
+ outl(scratch, TX3912_CLK_CTRL);
/* Configure UARTA clock */
- scratch = inl(TX3912_CLK_CTRL_BASE);
+ scratch = inl(TX3912_CLK_CTRL);
scratch |= ((0x3 << TX3912_CLK_CTRL_CSERDIV_SHIFT) &
TX3912_CLK_CTRL_CSERDIV_MASK)
| TX3912_CLK_CTRL_ENCSERCLK
| TX3912_CLK_CTRL_ENUARTACLK;
- outl(scratch, TX3912_CLK_CTRL_BASE);
+ outl(scratch, TX3912_CLK_CTRL);
/* Setup UARTA for 115200,8N1 */
outl(0, TX3912_UARTA_BASE + TX3912_UART_CTRL1);
@@ -968,50 +973,48 @@
{
int i;
unsigned long int2;
- #define BUSY_WAIT 10000
- /*
- * Turn UARTA interrupts off
- */
- int2 = IntEnable2;
- IntEnable2 &=
- ~(INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY);
+ /* Disable UARTA_TX interrupts */
+ int2 = inl(TX3912_INT2_ENABLE);
+ outl(inl(TX3912_INT2_ENABLE) & ~TX3912_INT2_UARTA_TX_BITS,
+ TX3912_INT2_ENABLE);
- /*
- * The UART_TX_EMPTY bit in UartA_Ctrl1 seems
- * not to be very reliable :-(
- *
- * Wait for the Tx register to become empty
- */
- for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < BUSY_WAIT); i++);
+ /* Wait for UARTA_TX register to empty */
+ i = 10000;
+ while(!(inl(TX3912_INT2_STATUS) & TX3912_INT2_UARTATXINT) && i--);
+ outl(TX3912_INT2_UARTA_TX_BITS, TX3912_INT2_CLEAR);
- IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY;
- UartA_Data = c;
- for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < BUSY_WAIT); i++);
- IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY;
+ /* Send the character */
+ outl(c, TX3912_UARTA_BASE + TX3912_UART_DATA);
- IntEnable2 = int2;
+ /* Wait for UARTA_TX register to empty */
+ i = 10000;
+ while(!(inl(TX3912_INT2_STATUS) & TX3912_INT2_UARTATXINT) && i--);
+ outl(TX3912_INT2_UARTA_TX_BITS, TX3912_INT2_CLEAR);
+
+ /* Enable UARTA_TX interrupts */
+ outl(int2, TX3912_INT2_ENABLE);
}
static int serial_console_wait_key(struct console *co)
{
unsigned int int2, res;
- int2 = IntEnable2;
- IntEnable2 = 0;
+ int2 = inl(TX3912_INT2_ENABLE);
+ outl(0, TX3912_INT2_ENABLE);
- while (!(UartA_Ctrl1 & UART_RX_HOLD_FULL));
- res = UartA_Data;
+ while (!(inl(TX3912_UARTA_CTRL1) & TX3912_UART_CTRL1_RXHOLDFULL));
+ res = inl(TX3912_UARTA_BASE + TX3912_UART_DATA);
udelay(10);
- IntEnable2 = int2;
+ outl(int2, TX3912_INT2_ENABLE);
return res;
}
static void serial_console_write(struct console *co, const char *s,
- unsigned count)
+ unsigned count)
{
- unsigned int i;
+ unsigned int i;
for (i = 0; i < count; i++) {
if (*s == '\n')
@@ -1030,22 +1033,22 @@
unsigned int scratch = 0;
/* Setup master clock for UART */
- scratch = inl(TX3912_CLK_CTRL_BASE);
+ scratch = inl(TX3912_CLK_CTRL);
scratch &= ~TX3912_CLK_CTRL_SIBMCLKDIV_MASK;
scratch |= ((0x2 << TX3912_CLK_CTRL_SIBMCLKDIV_SHIFT) &
TX3912_CLK_CTRL_SIBMCLKDIV_MASK)
| TX3912_CLK_CTRL_SIBMCLKDIR
| TX3912_CLK_CTRL_ENSIBMCLK
| TX3912_CLK_CTRL_CSERSEL;
- outl(scratch, TX3912_CLK_CTRL_BASE);
+ outl(scratch, TX3912_CLK_CTRL);
/* Configure UARTA clock */
- scratch = inl(TX3912_CLK_CTRL_BASE);
+ scratch = inl(TX3912_CLK_CTRL);
scratch |= ((0x3 << TX3912_CLK_CTRL_CSERDIV_SHIFT) &
TX3912_CLK_CTRL_CSERDIV_MASK)
| TX3912_CLK_CTRL_ENCSERCLK
| TX3912_CLK_CTRL_ENUARTACLK;
- outl(scratch, TX3912_CLK_CTRL_BASE);
+ outl(scratch, TX3912_CLK_CTRL);
/* Setup UARTA for 115200,8N1 */
outl(0, TX3912_UARTA_BASE + TX3912_UART_CTRL1);
|
|
From: James S. <jsi...@us...> - 2001-11-13 17:10:11
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv26774/arch/mips
Modified Files:
config.in
Log Message:
Nino updates.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.49
retrieving revision 1.50
diff -u -d -r1.49 -r1.50
--- config.in 2001/11/10 03:52:48 1.49
+++ config.in 2001/11/13 17:10:09 1.50
@@ -306,6 +306,7 @@
if [ "$CONFIG_NINO" = "y" ]; then
define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_NEW_TIME_C y
define_bool CONFIG_PC_KEYB y
fi
if [ "$CONFIG_PS2" = "y" ]; then
|
|
From: James S. <jsi...@us...> - 2001-11-13 17:10:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino
In directory usw-pr-cvs1:/tmp/cvs-serv26774/arch/mips/philips/nino
Modified Files:
Makefile prom.c setup.c
Added Files:
TODO power.c
Removed Files:
time.c
Log Message:
Nino updates.
--- NEW FILE: TODO ---
This is a basic TODO list for the Philips Nino porting effort. Things
will be added and removed from time to time. Pick an item and help
me out! Thanks!
- COMPACTFLASH
* get IDE/PCMCIA chip interface working to read flash cards and the
ethernet card
- FRAMEBUFFER
* complete rewrite to match new framebuffer API
* get 2bpp and 4bpp working (use Microwindows driver examples)
- GPIO
* go through all the interrupt sources in status registers 1-5
and see what all the different IO pins are hooked to
- KGDB
* get stub working
- SERIAL
* complete rewrite and use only one interrupt instead of two
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/Makefile,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- Makefile 2001/11/04 19:20:38 1.7
+++ Makefile 2001/11/13 17:10:09 1.8
@@ -15,12 +15,9 @@
all: nino.o
-obj-y := int-handler.o irq.o setup.o \
- prom.o power.o time.o
+obj-y := int-handler.o irq.o setup.o prom.o power.o
int-handler.o: int-handler.S
-
-obj-$(CONFIG_REMOTE_DEBUG) += kgdb.o
clean:
rm -f *.o
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/prom.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- prom.c 2001/11/06 20:23:54 1.5
+++ prom.c 2001/11/13 17:10:09 1.6
@@ -30,7 +30,6 @@
unsigned long magic, int *prom_vec)
{
unsigned long mem_size;
- unsigned int i;
strcpy(arcs_cmdline, "console=tty0 console=ttyS0,115200");
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/setup.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- setup.c 2001/11/06 20:23:54 1.6
+++ setup.c 2001/11/13 17:10:09 1.7
@@ -9,6 +9,7 @@
*
* Interrupt and exception initialization for Philips Nino
*/
+#include <linux/console.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
@@ -46,15 +47,17 @@
static __init void nino_time_init(void)
{
- unsigned int scratch = 0;
+ /* Load the counter and enable the timer */
+ outl(TX3912_SYS_TIMER_VALUE, TX3912_TIMER_PERIOD);
+ outl(TX3912_TIMER_CTRL_ENPERTIMER, TX3912_TIMER_CTRL);
- RTCperiodTimer = PER_TIMER_COUNT;
- RTCtimerControl = TIM_ENPERTIMER;
- IntEnable5 |= INT5_PERIODICINT;
+ /* Enable the timer clock line */
+ outl(inl(TX3912_CLK_CTRL) | TX3912_CLK_CTRL_ENTIMERCLK,
+ TX3912_CLK_CTRL);
- scratch = inl(TX3912_CLK_CTRL_BASE);
- scratch |= TX3912_CLK_CTRL_ENTIMERCLK;
- outl(scratch, TX3912_CLK_CTRL_BASE);
+ /* Enable the interrupt */
+ outl(inl(TX3912_INT5_ENABLE) | TX3912_INT5_PERINT,
+ TX3912_INT5_ENABLE);
}
static __init void nino_timer_setup(struct irqaction *irq)
@@ -79,6 +82,10 @@
board_timer_setup = nino_timer_setup;
cpu_wait = nino_wait;
+
+#ifdef CONFIG_FB
+ conswitchp = &dummy_con;
+#endif
nino_board_init();
}
--- time.c DELETED ---
|
|
From: Pete P. <pp...@us...> - 2001-11-12 22:58:52
|
Update of /cvsroot/linux-mips/linux/arch/mips/ite-boards/qed-4n-s01b
In directory usw-pr-cvs1:/tmp/cvs-serv4756/arch/mips/ite-boards/qed-4n-s01b
Modified Files:
pci_fixup.c
Log Message:
* updated defconfig file
* pci_fixup bug fix (irq fixup was not doing the pci write)
* added it8172 sound support in the config.in and sound Makefile
Index: pci_fixup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ite-boards/qed-4n-s01b/pci_fixup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pci_fixup.c 2001/07/07 19:41:39 1.2
+++ pci_fixup.c 2001/11/12 22:58:48 1.3
@@ -64,8 +64,9 @@
};
pci_for_each_dev(dev) {
- if (dev->bus->number != 0)
+ if (dev->bus->number != 0) {
return;
+ }
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
slot = PCI_SLOT(dev->devfn);
@@ -74,8 +75,9 @@
switch (slot) {
case 0x01:
/*
- * Internal device 1 is actually 7 different internal
- * devices on the IT8172G (a multi-function device).
+ * Internal device 1 is actually 7 different
+ * internal devices on the IT8172G (a multi-
+ * function device).
*/
if (func < 7)
dev->irq = internal_func_irqs[func];
@@ -181,15 +183,13 @@
}
break;
default:
- return;
+ continue; /* do nothing */
}
- }
-
#ifdef DEBUG
- printk("irq fixup: slot %d, vendor %x, int line %d, int number %d\n",
- slot, vendor, pin, dev->irq);
+ printk("irq fixup: slot %d, int line %d, int number %d\n",
+ slot, pin, dev->irq);
#endif
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+ }
}
#endif
|
|
From: Pete P. <pp...@us...> - 2001-11-12 22:58:52
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv4756/arch/mips/configs Modified Files: defconfig-it8172 Log Message: * updated defconfig file * pci_fixup bug fix (irq fixup was not doing the pci write) * added it8172 sound support in the config.in and sound Makefile Index: defconfig-it8172 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-it8172,v retrieving revision 1.13 retrieving revision 1.14 diff -u -d -r1.13 -r1.14 --- defconfig-it8172 2001/11/07 20:50:10 1.13 +++ defconfig-it8172 2001/11/12 22:58:48 1.14 @@ -1,8 +1,7 @@ # -# Automatically generated make config: don't edit +# Automatically generated by make menuconfig: don't edit # CONFIG_MIPS=y -# CONFIG_SMP is not set # # Code maturity level options @@ -18,19 +17,22 @@ # CONFIG_COBALT_MICRO_SERVER is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_NEC_KORVA is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_NINO is not set +# CONFIG_SIBYTE_SB1250 is not set # CONFIG_PS2 is not set +# CONFIG_CASIO_BE300 is not set +# CONFIG_VADEM_CLIO_1000 is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_NEC_OSPREY is not set -# CONFIG_NEC_EAGLE is not set -# CONFIG_NEC_KORVA is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set @@ -38,6 +40,7 @@ # CONFIG_IT8172_REVC is not set # CONFIG_MIPS_IVR is not set # CONFIG_MIPS_PB1000 is not set +# CONFIG_TOSHIBA_JMR3927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set # CONFIG_MCA is not set @@ -57,7 +60,7 @@ # CONFIG_MODULES=y # CONFIG_MODVERSIONS is not set -# CONFIG_KMOD is not set +CONFIG_KMOD=y # # CPU selection @@ -107,11 +110,6 @@ # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_PARTITIONS is not set # CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_BOOTLDR_PARTS is not set - -# -# User Modules And Translation Layers -# CONFIG_MTD_CHAR=y # CONFIG_MTD_BLOCK is not set # CONFIG_MTD_BLOCK_RO is not set @@ -122,14 +120,17 @@ # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=y -# CONFIG_MTD_CFI_VIRTUAL_ER is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_AMDSTD is not set -# CONFIG_MTD_SHARP is not set # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set +# CONFIG_MTD_AMDSTD is not set +# CONFIG_MTD_SHARP is not set # CONFIG_MTD_JEDEC is not set # @@ -139,25 +140,7 @@ CONFIG_MTD_PHYSMAP_START=8000000 CONFIG_MTD_PHYSMAP_LEN=2000000 CONFIG_MTD_PHYSMAP_BUSWIDTH=4 -# CONFIG_MTD_SUN_UFLASH is not set -# CONFIG_MTD_NORA is not set -# CONFIG_MTD_PNC2000 is not set -# CONFIG_MTD_RPXLITE is not set -# CONFIG_MTD_SC520CDP is not set -# CONFIG_MTD_NETSC520 is not set -# CONFIG_MTD_SBC_GXX is not set -# CONFIG_MTD_ELAN_104NC is not set -# CONFIG_MTD_SA1100 is not set -# CONFIG_MTD_SA1100_REDBOOT_PARTITIONS is not set -# CONFIG_MTD_SA1100_BOOTLDR_PARTITIONS is not set -# CONFIG_MTD_DC21285 is not set -# CONFIG_MTD_IQ80310 is not set -# CONFIG_MTD_DBOX2 is not set # CONFIG_MTD_CSTM_MIPS_IXX is not set -# CONFIG_MTD_CFI_FLAGADM is not set -# CONFIG_MTD_MIXMEM is not set -# CONFIG_MTD_OCTAGON is not set -# CONFIG_MTD_VMAX is not set # CONFIG_MTD_OCELOT is not set # @@ -166,10 +149,7 @@ # CONFIG_MTD_PMC551 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_MTDRAM is not set - -# -# Disk-On-Chip Device Drivers -# +# CONFIG_MTD_BLKMTD is not set # CONFIG_MTD_DOC1000 is not set # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set @@ -214,11 +194,12 @@ # # Networking options # -# CONFIG_PACKET is not set +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y # CONFIG_NETLINK is not set # CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set -# CONFIG_UNIX is not set +CONFIG_FILTER=y +CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set @@ -234,10 +215,6 @@ # CONFIG_KHTTPD is not set # CONFIG_ATM is not set # CONFIG_VLAN_8021Q is not set - -# -# -# # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_DECNET is not set @@ -272,10 +249,6 @@ # IDE, ATA and ATAPI Block devices # CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# # CONFIG_BLK_DEV_HD_IDE is not set # CONFIG_BLK_DEV_HD is not set CONFIG_BLK_DEV_IDEDISK=y @@ -294,10 +267,6 @@ # CONFIG_BLK_DEV_IDETAPE is not set # CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# # CONFIG_BLK_DEV_CMD640 is not set # CONFIG_BLK_DEV_CMD640_ENHANCED is not set # CONFIG_BLK_DEV_ISAPNP is not set @@ -333,16 +302,11 @@ # CONFIG_PDC202XX_BURST is not set # CONFIG_PDC202XX_FORCE is not set # CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_OSB4 is not set # CONFIG_BLK_DEV_SIS5513 is not set # CONFIG_BLK_DEV_SLC90E66 is not set # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set CONFIG_IDE_CHIPSETS=y - -# -# Note: most of these also require special kernel boot parameters -# # CONFIG_BLK_DEV_4DRIVES is not set # CONFIG_BLK_DEV_ALI14XX is not set # CONFIG_BLK_DEV_DTC2278 is not set @@ -391,7 +355,6 @@ # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_ARM_AM79C961A is not set # CONFIG_SUNLANCE is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNBMAC is not set @@ -414,6 +377,7 @@ # CONFIG_TULIP_MMIO is not set # CONFIG_DE4X5 is not set # CONFIG_DGRS is not set +# CONFIG_TC35815 is not set # CONFIG_DM9102 is not set # CONFIG_EEPRO100 is not set # CONFIG_LNE390 is not set @@ -422,6 +386,7 @@ # CONFIG_NE2K_PCI is not set # CONFIG_NE3210 is not set # CONFIG_ES3210 is not set +# CONFIG_8139CP is not set CONFIG_8139TOO=y # CONFIG_8139TOO_PIO is not set # CONFIG_8139TOO_TUNE_TWISTER is not set @@ -439,7 +404,6 @@ # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set -# CONFIG_ACENIC_OMIT_TIGON_I is not set # CONFIG_DL2K is not set # CONFIG_MYRI_SBUS is not set # CONFIG_NS83820 is not set @@ -498,8 +462,8 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_QTRONIX_KEYBOARD=y -CONFIG_IT8172_CIR=y +# CONFIG_QTRONIX_KEYBOARD is not set +CONFIG_PC_KEYB=y # CONFIG_IT8172_SCR0 is not set # CONFIG_IT8172_SCR1 is not set CONFIG_UNIX98_PTYS=y @@ -520,14 +484,6 @@ # Joysticks # # CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# # CONFIG_QIC02_TAPE is not set # @@ -536,11 +492,10 @@ # CONFIG_WATCHDOG is not set # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set -# CONFIG_RTC is not set +CONFIG_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -636,23 +591,37 @@ # # Sound # -# CONFIG_SOUND is not set +CONFIG_SOUND=y +# CONFIG_SOUND_BT878 is not set +# CONFIG_SOUND_CMPCI is not set +# CONFIG_SOUND_EMU10K1 is not set +# CONFIG_MIDI_EMU10K1 is not set +# CONFIG_SOUND_FUSION is not set +# CONFIG_SOUND_CS4281 is not set +# CONFIG_SOUND_ES1370 is not set +# CONFIG_SOUND_ES1371 is not set +# CONFIG_SOUND_ESSSOLO1 is not set +# CONFIG_SOUND_MAESTRO is not set +# CONFIG_SOUND_MAESTRO3 is not set +# CONFIG_SOUND_ICH is not set +# CONFIG_SOUND_RME96XX is not set +# CONFIG_SOUND_SONICVIBES is not set +CONFIG_SOUND_IT8172=y +# CONFIG_SOUND_TRIDENT is not set +# CONFIG_SOUND_MSNDCLAS is not set +# CONFIG_SOUND_MSNDPIN is not set +# CONFIG_SOUND_VIA82CXXX is not set +# CONFIG_MIDI_VIA82CXXX is not set +# CONFIG_SOUND_OSS is not set +# CONFIG_SOUND_TVMIXER is not set # # USB support # # CONFIG_USB is not set - -# -# USB Controllers -# # CONFIG_USB_UHCI is not set # CONFIG_USB_UHCI_ALT is not set # CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# # CONFIG_USB_AUDIO is not set # CONFIG_USB_BLUETOOTH is not set # CONFIG_USB_STORAGE is not set @@ -666,44 +635,16 @@ # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# # CONFIG_USB_DC2XX is not set # CONFIG_USB_MDC800 is not set # CONFIG_USB_SCANNER is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# # CONFIG_USB_PEGASUS is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_CATC is not set # CONFIG_USB_CDCETHER is not set # CONFIG_USB_USBNET is not set - -# -# USB port drivers -# # CONFIG_USB_USS720 is not set # @@ -734,10 +675,6 @@ # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# # CONFIG_USB_RIO500 is not set # |
|
From: Pete P. <pp...@us...> - 2001-11-12 22:58:52
|
Update of /cvsroot/linux-mips/linux/drivers/sound
In directory usw-pr-cvs1:/tmp/cvs-serv4756/drivers/sound
Modified Files:
Config.in Makefile
Log Message:
* updated defconfig file
* pci_fixup bug fix (irq fixup was not doing the pci write)
* added it8172 sound support in the config.in and sound Makefile
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/Config.in,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- Config.in 2001/11/08 17:09:41 1.9
+++ Config.in 2001/11/12 22:58:48 1.10
@@ -49,6 +49,9 @@
dep_tristate ' SGI Visual Workstation Sound' CONFIG_SOUND_VWSND $CONFIG_SOUND
fi
+if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then
+ dep_tristate ' IT8172G Sound' CONFIG_SOUND_IT8172 $CONFIG_SOUND
+fi
if [ "$CONFIG_DDB5477" = "y" ]; then
dep_tristate ' NEC Vrc5477 AC97 sound' CONFIG_SOUND_VRC5477 $CONFIG_SOUND
fi
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/Makefile,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- Makefile 2001/11/08 17:09:41 1.9
+++ Makefile 2001/11/12 22:58:48 1.10
@@ -64,6 +64,7 @@
obj-$(CONFIG_SOUND_ES1370) += es1370.o
obj-$(CONFIG_SOUND_ES1371) += es1371.o ac97_codec.o
obj-$(CONFIG_SOUND_VRC5477) += nec_vrc5477.o ac97_codec.o
+obj-$(CONFIG_SOUND_IT8172) += ite8172.o ac97_codec.o
obj-$(CONFIG_SOUND_AU1000) += au1000.o ac97_codec.o
obj-$(CONFIG_SOUND_ESSSOLO1) += esssolo1.o
obj-$(CONFIG_SOUND_FUSION) += cs46xx.o ac97_codec.o
|
|
From: Pete P. <pp...@us...> - 2001-11-12 19:11:35
|
Update of /cvsroot/linux-mips/linux/arch/mips/ramdisk
In directory usw-pr-cvs1:/tmp/cvs-serv15281/arch/mips/ramdisk
Modified Files:
Makefile
Added Files:
ld.script
Removed Files:
ld.script.in
Log Message:
The generic ramdisk support was broken. One of the problems was
that different toolchains have different default output targets -- the
elf32-trad{little/big}mips vs elf32-{little/big}mips. The updated
Makefile uses objdump to figure out the proper output format.
--- NEW FILE: ld.script ---
OUTPUT_ARCH(mips)
SECTIONS
{
.initrd :
{
*(.data)
}
}
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ramdisk/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile 2001/10/05 21:04:46 1.1
+++ Makefile 2001/11/12 19:11:33 1.2
@@ -6,8 +6,10 @@
# unless it's something special (ie not a .c file).
#
+O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
ramdisk.o: ramdisk.gz ld.script
- $(LD) -T ld.script -b binary -o $@ ramdisk.gz
+ echo "O_FORMAT: " $(O_FORMAT)
+ $(LD) -T ld.script -b binary --oformat $(O_FORMAT) -o $@ ramdisk.gz
include $(TOPDIR)/Rules.make
--- ld.script.in DELETED ---
|
|
From: James S. <jsi...@us...> - 2001-11-12 18:41:39
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv7735 Modified Files: pci.h Log Message: pci_map_page fixes. Index: pci.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pci.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- pci.h 2001/11/06 09:10:22 1.6 +++ pci.h 2001/11/12 18:41:36 1.7 @@ -130,6 +130,7 @@ BUG(); addr = (unsigned long) page_address(page); + addr += offset; #ifndef CONFIG_COHERENT_IO dma_cache_wback_inv(addr, size); #endif |
582 messages has been excluded from this view by a project administrator.
