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From: James S. <jsi...@us...> - 2001-11-10 03:52:51
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv20843/arch/mips/kernel Modified Files: setup.c Log Message: Imported support for JMR-TX3927 by Alice Hennessy. Thank you. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v retrieving revision 1.27 retrieving revision 1.28 diff -u -d -r1.27 -r1.28 --- setup.c 2001/11/08 17:12:25 1.27 +++ setup.c 2001/11/10 03:52:49 1.28 @@ -644,6 +644,7 @@ void nec_korva_setup(void); void ps2_setup(void); void clio_1000_setup(void); + void jmr3927_setup(void); unsigned long bootmap_size; unsigned long start_pfn, max_pfn, first_usable_pfn; @@ -774,6 +775,11 @@ #ifdef CONFIG_MIPS_PB1000 case MACH_GROUP_ALCHEMY: au1000_setup(); + break; +#endif +#ifdef CONFIG_TOSHIBA_JMR3927 + case MACH_GROUP_TOSHIBA: + jmr3927_setup(); break; #endif #ifdef CONFIG_PS2 |
|
From: James S. <jsi...@us...> - 2001-11-10 03:52:51
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv20843/arch/mips/configs Added Files: defconfig-jmr3927 Log Message: Imported support for JMR-TX3927 by Alice Hennessy. Thank you. --- NEW FILE: defconfig-jmr3927 --- # # Automatically generated by make menuconfig: don't edit # CONFIG_MIPS=y # # Code maturity level options # CONFIG_EXPERIMENTAL=y # # Machine selection # # CONFIG_ACER_PICA_61 is not set # CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set # CONFIG_COBALT_MICRO_SERVER is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_NINO is not set # CONFIG_PS2 is not set # CONFIG_SIBYTE_SB1250 is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_NEC_OSPREY is not set # CONFIG_NEC_EAGLE is not set # CONFIG_NEC_KORVA is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_IVR is not set # CONFIG_MIPS_PB1000 is not set CONFIG_TOSHIBA_JMR3927=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set # CONFIG_MCA is not set # CONFIG_SBUS is not set CONFIG_TOSHIBA_BOARDS=y CONFIG_PCI=y CONFIG_NEW_PCI=y CONFIG_PCI_AUTO=y CONFIG_NEW_IRQ=y CONFIG_NEW_TIME_C=y CONFIG_SWAP_IO_SPACE=y CONFIG_PC_KEYB=y # CONFIG_ISA is not set # CONFIG_EISA is not set # CONFIG_I8259 is not set # # Loadable module support # # CONFIG_MODULES is not set # # CPU selection # # CONFIG_CPU_R3000 is not set CONFIG_CPU_TX39XX=y # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_SB1 is not set # CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_ADVANCED is not set # CONFIG_CPU_HAS_LLSC is not set # CONFIG_CPU_HAS_LLDSCD is not set # CONFIG_CPU_HAS_WB is not set # # General setup # # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_RTC_DS1742=y CONFIG_KCORE_ELF=y CONFIG_ELF_KERNEL=y # CONFIG_BINFMT_IRIX is not set # CONFIG_FORWARD_KEYBOARD is not set # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_NET=y # CONFIG_PCI_NAMES is not set # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # # Memory Technology Devices (MTD) # # CONFIG_MTD is not set # # Parallel port support # # CONFIG_PARPORT is not set # # Block devices # # CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_XD is not set # CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # # Multi-device support (RAID and LVM) # # CONFIG_MD is not set # CONFIG_BLK_DEV_MD is not set # CONFIG_MD_LINEAR is not set # CONFIG_MD_RAID0 is not set # CONFIG_MD_RAID1 is not set # CONFIG_MD_RAID5 is not set # CONFIG_MD_MULTIPATH is not set # CONFIG_BLK_DEV_LVM is not set # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set # CONFIG_NETLINK is not set # CONFIG_NETFILTER is not set # CONFIG_FILTER is not set CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set # CONFIG_IPV6 is not set # CONFIG_KHTTPD is not set # CONFIG_ATM is not set # CONFIG_VLAN_8021Q is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_FASTROUTE is not set # CONFIG_NET_HW_FLOWCONTROL is not set # # QoS and/or fair queueing # # CONFIG_NET_SCHED is not set # # Telephony Support # # CONFIG_PHONE is not set # CONFIG_PHONE_IXJ is not set # CONFIG_PHONE_IXJ_PCMCIA is not set # # ATA/IDE/MFM/RLL support # # CONFIG_IDE is not set # CONFIG_BLK_DEV_IDE_MODES is not set # CONFIG_BLK_DEV_HD is not set # # SCSI support # # CONFIG_SCSI is not set # # I2O device support # # CONFIG_I2O is not set # CONFIG_I2O_PCI is not set # CONFIG_I2O_BLOCK is not set # CONFIG_I2O_LAN is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set # # Network device support # CONFIG_NETDEVICES=y # # ARCnet devices # # CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y # CONFIG_SUNLANCE is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNBMAC is not set # CONFIG_SUNQE is not set # CONFIG_SUNLANCE is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_HP100 is not set # CONFIG_NET_ISA is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_ADAPTEC_STARFIRE is not set # CONFIG_APRICOT is not set # CONFIG_CS89x0 is not set # CONFIG_TULIP is not set CONFIG_TC35815=y # CONFIG_DE4X5 is not set # CONFIG_DGRS is not set # CONFIG_DM9102 is not set # CONFIG_EEPRO100 is not set # CONFIG_LNE390 is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set # CONFIG_NE2K_PCI is not set # CONFIG_NE3210 is not set # CONFIG_ES3210 is not set # CONFIG_8139CP is not set # CONFIG_8139TOO is not set # CONFIG_8139TOO_PIO is not set # CONFIG_8139TOO_TUNE_TWISTER is not set # CONFIG_8139TOO_8129 is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_WINBOND_840 is not set # CONFIG_LAN_SAA9730 is not set # CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_MYRI_SBUS is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_SK98LIN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set # # Token Ring devices # # CONFIG_TR is not set # CONFIG_NET_FC is not set # CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # # Wan interfaces # # CONFIG_WAN is not set # # Amateur Radio support # # CONFIG_HAMRADIO is not set # # IrDA (infrared) support # # CONFIG_IRDA is not set # # ISDN subsystem # # CONFIG_ISDN is not set # # Old CD-ROM drivers (not SCSI, not IDE) # # CONFIG_CD_NO_IDESCSI is not set # # Character devices # CONFIG_VT=y # CONFIG_VT_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_SERIAL_EXTENDED is not set CONFIG_SERIAL_NONSTANDARD=y # CONFIG_COMPUTONE is not set # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set # CONFIG_DIGIEPCA is not set # CONFIG_DIGI is not set # CONFIG_ESPSERIAL is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_ISI is not set # CONFIG_SYNCLINK is not set # CONFIG_N_HDLC is not set # CONFIG_RISCOM8 is not set # CONFIG_SPECIALIX is not set # CONFIG_SX is not set # CONFIG_RIO is not set # CONFIG_STALDRV is not set # CONFIG_SERIAL_TX3912 is not set # CONFIG_SERIAL_TX3912_CONSOLE is not set # CONFIG_AU1000_UART is not set CONFIG_TXX927_SERIAL=y CONFIG_TXX927_SERIAL_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 # # I2C support # # CONFIG_I2C is not set # # Mice # # CONFIG_BUSMOUSE is not set # CONFIG_MOUSE is not set # # Joysticks # # CONFIG_INPUT_GAMEPORT is not set # CONFIG_QIC02_TAPE is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # # Ftape, the floppy tape device driver # # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set # # Multimedia devices # # CONFIG_VIDEO_DEV is not set # # File systems # # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_REISERFS_CHECK is not set # CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_FAT_FS is not set # CONFIG_MSDOS_FS is not set # CONFIG_UMSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set # CONFIG_TMPFS is not set # CONFIG_RAMFS is not set # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_ZISOFS is not set # CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set # CONFIG_NTFS_FS is not set # CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set CONFIG_PROC_FS=y # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set # CONFIG_EXT2_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set # CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set # CONFIG_UFS_FS_WRITE is not set # # Network File Systems # # CONFIG_CODA_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set # CONFIG_NFSD_V3 is not set CONFIG_SUNRPC=y CONFIG_LOCKD=y # CONFIG_SMB_FS is not set # CONFIG_NCP_FS is not set # CONFIG_NCPFS_PACKET_SIGNING is not set # CONFIG_NCPFS_IOCTL_LOCKING is not set # CONFIG_NCPFS_STRONG is not set # CONFIG_NCPFS_NFS_NS is not set # CONFIG_NCPFS_OS2_NS is not set # CONFIG_NCPFS_SMALLDOS is not set # CONFIG_NCPFS_NLS is not set # CONFIG_NCPFS_EXTRAS is not set # CONFIG_ZISOFS_FS is not set # CONFIG_ZLIB_FS_INFLATE is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y # CONFIG_SMB_NLS is not set # CONFIG_NLS is not set # # Console drivers # # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set # # Frame-buffer support # CONFIG_FB=y CONFIG_DUMMY_CONSOLE=y # CONFIG_FB_RIVA is not set # CONFIG_FB_CLGEN is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_ATY is not set # CONFIG_FB_RADEON is not set # CONFIG_FB_ATY128 is not set # CONFIG_FB_SIS is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set # CONFIG_FB_VIRTUAL is not set CONFIG_FBCON_ADVANCED=y CONFIG_FBCON_MFB=y # CONFIG_FBCON_CFB2 is not set # CONFIG_FBCON_CFB4 is not set CONFIG_FBCON_CFB8=y CONFIG_FBCON_CFB16=y # CONFIG_FBCON_CFB24 is not set # CONFIG_FBCON_CFB32 is not set # CONFIG_FBCON_AFB is not set # CONFIG_FBCON_ILBM is not set # CONFIG_FBCON_IPLAN2P2 is not set # CONFIG_FBCON_IPLAN2P4 is not set # CONFIG_FBCON_IPLAN2P8 is not set # CONFIG_FBCON_MAC is not set # CONFIG_FBCON_VGA_PLANES is not set # CONFIG_FBCON_VGA is not set # CONFIG_FBCON_HGA is not set # CONFIG_FBCON_FONTWIDTH8_ONLY is not set # CONFIG_FBCON_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y # # Sound # # CONFIG_SOUND is not set # # USB support # # CONFIG_USB is not set # CONFIG_USB_UHCI is not set # CONFIG_USB_UHCI_ALT is not set # CONFIG_USB_OHCI is not set # CONFIG_USB_AUDIO is not set # CONFIG_USB_BLUETOOTH is not set # CONFIG_USB_STORAGE is not set # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_HP8200e is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_DC2XX is not set # CONFIG_USB_MDC800 is not set # CONFIG_USB_SCANNER is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USB_HPUSBSCSI is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_CATC is not set # CONFIG_USB_CDCETHER is not set # CONFIG_USB_USBNET is not set # CONFIG_USB_USS720 is not set # # USB Serial Converter support # # CONFIG_USB_SERIAL is not set # CONFIG_USB_SERIAL_GENERIC is not set # CONFIG_USB_SERIAL_BELKIN is not set # CONFIG_USB_SERIAL_WHITEHEAT is not set # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set # CONFIG_USB_SERIAL_EMPEG is not set # CONFIG_USB_SERIAL_FTDI_SIO is not set # CONFIG_USB_SERIAL_VISOR is not set # CONFIG_USB_SERIAL_IR is not set # CONFIG_USB_SERIAL_EDGEPORT is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set # CONFIG_USB_SERIAL_KEYSPAN is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set # CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set # CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set # CONFIG_USB_SERIAL_MCT_U232 is not set # CONFIG_USB_SERIAL_PL2303 is not set # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_RIO500 is not set # # Input core support # # CONFIG_INPUT is not set # CONFIG_INPUT_KEYBDEV is not set # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set # # Kernel hacking # CONFIG_CROSSCOMPILE=y # CONFIG_DEBUG is not set # CONFIG_MAGIC_SYSRQ is not set # CONFIG_MIPS_UNCACHED is not set |
|
From: James S. <jsi...@us...> - 2001-11-10 03:52:51
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv20843/arch/mips
Modified Files:
Makefile config.in
Log Message:
Imported support for JMR-TX3927 by Alice Hennessy. Thank you.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.27
retrieving revision 1.28
diff -u -d -r1.27 -r1.28
--- Makefile 2001/11/08 17:42:07 1.27
+++ Makefile 2001/11/10 03:52:48 1.28
@@ -369,6 +369,12 @@
LOADADDR += 0x80001000
endif
+ifdef CONFIG_TOSHIBA_JMR3927
+CORE_FILES += arch/mips/jmr3927/rbhma3100/jmr3927.o arch/mips/jmr3927/common/tx3927.o
+SUBDIRS += arch/mips/jmr3927/rbhma3100 arch/mips/jmr3927/common
+LOADADDR += 0x80050000
+endif
+
#
# Choosing incompatible machines durings configuration will result in
# error messages during linking. Select a default linkscript if
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.48
retrieving revision 1.49
diff -u -d -r1.48 -r1.49
--- config.in 2001/11/08 17:42:07 1.48
+++ config.in 2001/11/10 03:52:48 1.49
@@ -95,6 +95,7 @@
if [ "$CONFIG_MIPS_PB1000" = "y" ]; then
bool ' Support for PCI AUTO Config' CONFIG_PCI_AUTO
fi
+bool 'Support for Toshiba JMR-TX3927 board' CONFIG_TOSHIBA_JMR3927
define_bool CONFIG_RWSEM_GENERIC_SPINLOCK y
@@ -328,6 +329,17 @@
define_bool CONFIG_PCI y
fi
+if [ "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
+ define_bool CONFIG_TOSHIBA_BOARDS y
+ define_bool CONFIG_PCI y
+ define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_PCI_AUTO y
+ define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_SWAP_IO_SPACE y
+ define_bool CONFIG_PC_KEYB y
+fi
+
if [ "$CONFIG_ISA" != "y" ]; then
define_bool CONFIG_ISA n
define_bool CONFIG_EISA n
@@ -385,7 +397,9 @@
bool ' lld/scd Instructions available' CONFIG_CPU_HAS_LLDSCD
bool ' Writeback Buffer available' CONFIG_CPU_HAS_WB
else
- if [ "$CONFIG_CPU_R3000" = "y" -o "$CONFIG_CPU_VR41XX" = "y" ]; then
+ if [ "$CONFIG_CPU_R3000" = "y" -o \
+ "$CONFIG_CPU_VR41XX" = "y" -o \
+ "$CONFIG_CPU_TX39XX" = "y" ]; then
if [ "$CONFIG_DECSTATION" = "y" ]; then
define_bool CONFIG_CPU_HAS_LLSC n
define_bool CONFIG_CPU_HAS_LLDSCD n
@@ -420,6 +434,10 @@
else
bool 'Generate little endian code' CONFIG_CPU_LITTLE_ENDIAN
fi
+
+if [ "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
+ bool 'DS1742 BRAM/RTC support' CONFIG_RTC_DS1742
+fi
if [ "$CONFIG_PROC_FS" = "y" ]; then
define_bool CONFIG_KCORE_ELF y
|
|
From: James S. <jsi...@us...> - 2001-11-09 22:52:19
|
Update of /cvsroot/linux-mips/linux/arch/mips/cobalt In directory usw-pr-cvs1:/tmp/cvs-serv30008 Modified Files: setup.c Log Message: Having problems with the ioport and iomem regions. Added old values back in and it works again. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/setup.c,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- setup.c 2001/11/01 19:30:43 1.11 +++ setup.c 2001/11/09 22:52:17 1.12 @@ -145,11 +145,16 @@ * IO/MEM resources. */ mips_io_port_base = COBALT_LOCAL_IO_SPACE; - ioport_resource.start = 0x10000000; - ioport_resource.end = 0x11FFFFFF; - iomem_resource.start = 0x12000000; - iomem_resource.end = 0x13FFFFFF; +#ifdef CONFIG_NEW_PCI + ioport_resource.start = 0x10000000; + ioport_resource.end = 0x11FFFFFF; + iomem_resource.start = 0x12000000; + iomem_resource.end = 0x13FFFFFF; +#else + ioport_resource.start = 0x00000000; + ioport_resource.end = 0xFFFFFFFF; +#endif _machine_restart = cobalt_machine_restart; _machine_halt = cobalt_machine_halt; _machine_power_off = cobalt_machine_power_off; |
|
From: Jun S. <ju...@us...> - 2001-11-09 19:57:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/korva In directory usw-pr-cvs1:/tmp/cvs-serv29166/arch/mips/korva Modified Files: setup.c Log Message: Always use external clock for UART. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/setup.c,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- setup.c 2001/10/30 21:43:37 1.5 +++ setup.c 2001/11/09 19:57:33 1.6 @@ -108,7 +108,10 @@ // korva_out32(KORVA_S_WRCR, 0x1f); korva_out32(KORVA_S_WRCR, 0x0f); - /* enable IBUS arbitration for peripherals */ - korva_set_bits(KORVA_S_GMR, 0x2); + /* + * enable IBUS arbitration for peripherals and use extern clock + * for serial port + */ + korva_set_bits(KORVA_S_GMR, 0x2 | 0x8); } |
|
From: Steve L. <slo...@us...> - 2001-11-08 18:03:21
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv16661/arch/mips/au1000/common
Modified Files:
usbdev.c
Log Message:
Au1000 sound updates.
Index: usbdev.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/usbdev.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- usbdev.c 2001/11/06 20:23:53 1.5
+++ usbdev.c 2001/11/08 18:03:18 1.6
@@ -100,8 +100,7 @@
static void serial_unthrottle(struct tty_struct *tty);
static int serial_ioctl(struct tty_struct *tty, struct file *file,
unsigned int cmd, unsigned long arg);
-static void serial_set_termios(struct tty_struct *tty,
- struct termios *old);
+static void serial_set_termios (struct tty_struct *tty, struct termios * old);
typedef struct {
int read_fifo;
@@ -150,7 +149,7 @@
/* task queue for line discipline waking up on send packet complete */
struct tq_struct send_complete_tq;
- /* task queue for line discipline waking up on receive packet complete */
+ /* task queue for line discipline wakeup on receive packet complete */
struct tq_struct receive_complete_tq;
int open_count; /* number of times this port has been opened */
@@ -283,19 +282,15 @@
{USB_DEV_EP0_READ_FIFO, USB_DEV_EP0_WRITE_FIFO,
USB_DEV_EP0_CS, USB_DEV_FIFO0_STATUS, USB_DEV_FIFO1_STATUS},
// FIFO 2 is EP2, Port 0, bulk IN
-
- {-1, USB_DEV_EP2_WRITE_FIFO, USB_DEV_EP2_CS, -1,
- USB_DEV_FIFO2_STATUS},
+ { -1, USB_DEV_EP2_WRITE_FIFO, USB_DEV_EP2_CS,
+ -1, USB_DEV_FIFO2_STATUS },
// FIFO 4 is EP4, Port 0, bulk OUT
-
{USB_DEV_EP4_READ_FIFO, -1, USB_DEV_EP4_CS,
USB_DEV_FIFO4_STATUS, -1},
// FIFO 3 is EP3, Port 1, bulk IN
-
- {-1, USB_DEV_EP3_WRITE_FIFO, USB_DEV_EP3_CS, -1,
- USB_DEV_FIFO3_STATUS},
+ { -1, USB_DEV_EP3_WRITE_FIFO, USB_DEV_EP3_CS,
+ -1, USB_DEV_FIFO3_STATUS },
// FIFO 5 is EP5, Port 1, bulk OUT
-
{USB_DEV_EP5_READ_FIFO, -1, USB_DEV_EP5_CS,
USB_DEV_FIFO5_STATUS, -1}
};
@@ -304,13 +299,12 @@
unsigned int id;
const char *str;
} ep_dma_id[] = {
- {
- DMA_ID_USBDEV_EP0_TX, "USBDev EP0 IN"}, {
- DMA_ID_USBDEV_EP0_RX, "USBDev EP0 OUT"}, {
- DMA_ID_USBDEV_EP2_TX, "USBDev EP2 IN"}, {
- DMA_ID_USBDEV_EP4_RX, "USBDev EP4 OUT"}, {
- DMA_ID_USBDEV_EP3_TX, "USBDev EP3 IN"}, {
- DMA_ID_USBDEV_EP5_RX, "USBDev EP5 OUT"}
+ { DMA_ID_USBDEV_EP0_TX, "USBDev EP0 IN" },
+ { DMA_ID_USBDEV_EP0_RX, "USBDev EP0 OUT" },
+ { DMA_ID_USBDEV_EP2_TX, "USBDev EP2 IN" },
+ { DMA_ID_USBDEV_EP4_RX, "USBDev EP4 OUT" },
+ { DMA_ID_USBDEV_EP3_TX, "USBDev EP3 IN" },
+ { DMA_ID_USBDEV_EP5_RX, "USBDev EP5 OUT" }
};
static int serial_refcount;
@@ -323,9 +317,8 @@
#define DIR_OUT 0
#define DIR_IN (1<<3)
-static const u32 au1000_config_table[25] = {
+static const u32 au1000_config_table[25] __devinitdata = {
0x00,
-
((EP0_MAX_PACKET_SIZE & 0x380) >> 7) |
(USB_ENDPOINT_XFER_CONTROL << 4),
(EP0_MAX_PACKET_SIZE & 0x7f) << 1,
@@ -333,7 +326,6 @@
0x01,
0x10,
-
((EP2_MAX_PACKET_SIZE & 0x380) >> 7) | DIR_IN |
(USB_ENDPOINT_XFER_BULK << 4),
(EP2_MAX_PACKET_SIZE & 0x7f) << 1,
@@ -341,7 +333,6 @@
0x02,
0x20,
-
((EP3_MAX_PACKET_SIZE & 0x380) >> 7) | DIR_IN |
(USB_ENDPOINT_XFER_BULK << 4),
(EP3_MAX_PACKET_SIZE & 0x7f) << 1,
@@ -349,7 +340,6 @@
0x03,
0x30,
-
((EP4_MAX_PACKET_SIZE & 0x380) >> 7) | DIR_OUT |
(USB_ENDPOINT_XFER_BULK << 4),
(EP4_MAX_PACKET_SIZE & 0x7f) << 1,
@@ -357,7 +347,6 @@
0x04,
0x40,
-
((EP5_MAX_PACKET_SIZE & 0x380) >> 7) | DIR_OUT |
(USB_ENDPOINT_XFER_BULK << 4),
(EP5_MAX_PACKET_SIZE & 0x7f) << 1,
@@ -365,8 +354,8 @@
0x05
};
-static inline endpoint_t *fifonum_to_ep(struct usb_serial *serial,
- int fifo_num)
+static inline endpoint_t *
+fifonum_to_ep(struct usb_serial* serial, int fifo_num)
{
switch (fifo_num) {
case 0:
@@ -385,9 +374,8 @@
return NULL;
}
-static inline struct usb_serial_port *fifonum_to_port(struct usb_serial
- *serial,
- int fifo_num)
+static inline struct usb_serial_port *
+fifonum_to_port(struct usb_serial* serial, int fifo_num)
{
switch (fifo_num) {
case 2:
@@ -401,8 +389,8 @@
return NULL;
}
-static inline endpoint_t *epnum_to_ep(struct usb_serial *serial,
- int ep_num)
+static inline endpoint_t *
+epnum_to_ep(struct usb_serial* serial, int ep_num)
{
switch (ep_num) {
case 0:
@@ -440,14 +428,13 @@
return 0;
}
-static inline struct usb_serial *get_usb_serial(struct usb_serial_port
- *port,
- const char *function)
+static inline struct usb_serial*
+get_usb_serial (struct usb_serial_port *port, const char *function)
{
/* if no port was specified, or it fails a paranoia check */
if (!port || port_paranoia_check(port, function)) {
- /* then say that we dont have a valid usb_serial thing, which will
- * end up genrating -ENODEV return values */
+ /* then say that we dont have a valid usb_serial thing,
+ * which will end up genrating -ENODEV return values */
return NULL;
}
@@ -455,10 +442,10 @@
}
-static inline pkt_t *alloc_packet(int data_size)
+static inline pkt_t *
+alloc_packet(int data_size)
{
- pkt_t *pkt =
- (pkt_t *) kmalloc(sizeof(pkt_t) + data_size, ALLOC_FLAGS);
+ pkt_t* pkt = (pkt_t *)kmalloc(sizeof(pkt_t) + data_size, ALLOC_FLAGS);
if (!pkt)
return NULL;
pkt->size = data_size;
@@ -474,7 +461,8 @@
/*
* Link a packet to the tail of the enpoint's packet list.
*/
-static void link_packet(endpoint_t * ep, pkt_list_t * list, pkt_t * pkt)
+static void
+link_packet(endpoint_t * ep, pkt_list_t * list, pkt_t * pkt)
{
unsigned long flags;
@@ -495,7 +483,8 @@
/*
* Unlink and return a packet from the head of the enpoint's packet list.
*/
-static pkt_t *unlink_packet(endpoint_t * ep, pkt_list_t * list)
+static pkt_t *
+unlink_packet(endpoint_t * ep, pkt_list_t * list)
{
unsigned long flags;
pkt_t *pkt;
@@ -524,7 +513,8 @@
* Create and attach a new packet to the tail of the enpoint's
* packet list.
*/
-static pkt_t *add_packet(endpoint_t * ep, pkt_list_t * list, int size)
+static pkt_t *
+add_packet(endpoint_t * ep, pkt_list_t * list, int size)
{
pkt_t *pkt = alloc_packet(size);
if (!pkt)
@@ -539,19 +529,22 @@
* Unlink and free a packet from the head of the enpoint's
* packet list.
*/
-static inline void free_packet(endpoint_t * ep, pkt_list_t * list)
+static inline void
+free_packet(endpoint_t * ep, pkt_list_t * list)
{
kfree(unlink_packet(ep, list));
}
-static inline void flush_pkt_list(endpoint_t * ep, pkt_list_t * list)
+static inline void
+flush_pkt_list(endpoint_t * ep, pkt_list_t * list)
{
while (list->count)
free_packet(ep, list);
}
-static inline void flush_write_fifo(endpoint_t * ep)
+static inline void
+flush_write_fifo(endpoint_t * ep)
{
if (ep->reg->write_fifo_status >= 0) {
outl_sync(USBDEV_FSTAT_FLUSH, ep->reg->write_fifo_status);
@@ -562,7 +555,8 @@
}
-static inline void flush_read_fifo(endpoint_t * ep)
+static inline void
+flush_read_fifo(endpoint_t * ep)
{
if (ep->reg->read_fifo_status >= 0) {
outl_sync(USBDEV_FSTAT_FLUSH, ep->reg->read_fifo_status);
@@ -573,7 +567,8 @@
}
-static void endpoint_flush(endpoint_t * ep)
+static void
+endpoint_flush(endpoint_t * ep)
{
unsigned long flags;
@@ -591,7 +586,8 @@
}
-static void endpoint_stall(endpoint_t * ep)
+static void
+endpoint_stall(endpoint_t * ep)
{
unsigned long flags;
u32 cs;
@@ -606,7 +602,8 @@
spin_unlock_irqrestore(&ep->lock, flags);
}
-static void endpoint_unstall(endpoint_t * ep)
+static void
+endpoint_unstall(endpoint_t * ep)
{
unsigned long flags;
u32 cs;
@@ -621,14 +618,16 @@
spin_unlock_irqrestore(&ep->lock, flags);
}
-static void endpoint_reset_datatoggle(endpoint_t * ep)
+static void
+endpoint_reset_datatoggle(endpoint_t * ep)
{
// FIXME: is this possible?
}
#ifdef USBDEV_PIO
-static int endpoint_fifo_read(endpoint_t * ep)
+static int
+endpoint_fifo_read(endpoint_t * ep)
{
unsigned long flags;
int read_count = 0;
@@ -653,7 +652,8 @@
}
-static int endpoint_fifo_write(endpoint_t * ep)
+static int
+endpoint_fifo_write(endpoint_t * ep)
{
unsigned long flags;
int write_count = 0;
@@ -687,7 +687,8 @@
* The endpoint's TSIZE must be set to the new packet's size,
* and DMA to the write FIFO needs to be restarted.
*/
-static void kickstart_send_packet(endpoint_t * ep)
+static void
+kickstart_send_packet(endpoint_t * ep)
{
u32 cs;
pkt_t *pkt = ep->inlist.head;
@@ -728,7 +729,8 @@
* completed. Frees the completed packet and starts sending the
* next.
*/
-static void send_packet_complete(endpoint_t * ep)
+static void
+send_packet_complete(endpoint_t * ep)
{
if (ep->inlist.head)
dbg(__FUNCTION__ ": pkt=%p, ab=%d",
@@ -749,7 +751,8 @@
* outlist. It is the responsibility of the caller to free the packet.
* The receive complete interrupt adds packets to the tail of this list.
*/
-static pkt_t *receive_packet(endpoint_t * ep)
+static pkt_t *
+receive_packet(endpoint_t * ep)
{
pkt_t *pkt = unlink_packet(ep, &ep->outlist);
//dma_cache_inv((unsigned long)pkt->buf, pkt->size);
@@ -759,7 +762,8 @@
/*
* This routine is called to restart reception of a packet.
*/
-static void kickstart_receive_packet(endpoint_t * ep)
+static void
+kickstart_receive_packet(endpoint_t * ep)
{
pkt_t *pkt;
@@ -797,7 +801,8 @@
* and restarts DMA. FIXME: what if another packet comes in
* on top of the completed packet? Counter would be wrong.
*/
-static void receive_packet_complete(endpoint_t * ep)
+static void
+receive_packet_complete(endpoint_t * ep)
{
pkt_t *pkt = ep->outlist.tail;
@@ -848,8 +853,7 @@
spin_lock_irqsave(&ep->lock, flags);
- dbg(__FUNCTION__ ": size=%d, list count=%d", pkt->size,
- list->count);
+ dbg(__FUNCTION__ ": size=%d, list count=%d", pkt->size, list->count);
if (list->count == 1) {
/*
@@ -866,7 +870,8 @@
// SETUP packet request parser
-static void process_setup(struct usb_serial *serial, devrequest * setup)
+static void
+process_setup (struct usb_serial* serial, devrequest* setup)
{
int desc_len, strnum;
@@ -894,22 +899,21 @@
desc_len = desc_len > serial->dev_desc->bLength ?
serial->dev_desc->bLength : desc_len;
dbg("sending device desc, size=%d", desc_len);
- send_packet(&serial->ep_ctrl,
- (u8 *) serial->dev_desc, desc_len, 0);
+ send_packet(&serial->ep_ctrl, (u8*)serial->dev_desc,
+ desc_len, 0);
break;
case USB_DT_CONFIG:
- // If the config descr index in low-byte of setup->value
- // is valid, send config descr, otherwise stall ep0.
+ // If the config descr index in low-byte of
+ // setup->value is valid, send config descr,
+ // otherwise stall ep0.
if ((le16_to_cpu(setup->value) & 0xff) == 0) {
// send config descriptor!
if (desc_len <= USB_DT_CONFIG_SIZE) {
- dbg
- ("sending partial config desc, size=%d",
+ dbg("sending partial config desc, size=%d",
desc_len);
send_packet(&serial->ep_ctrl,
- (u8 *) serial->
- conf_desc, desc_len,
- 0);
+ (u8*)serial->conf_desc,
+ desc_len, 0);
} else {
u8 full_conf_desc[CONFIG_DESC_LEN];
int i, index = 0;
@@ -922,34 +926,24 @@
USB_DT_INTERFACE_SIZE);
index += USB_DT_INTERFACE_SIZE;
for (i = 0; i < NUM_PORTS; i++) {
- memcpy(&full_conf_desc
- [index],
- serial->port[i].
- ep_bulkin.desc,
+ memcpy(&full_conf_desc[index],
+ serial->port[i].ep_bulkin.desc,
USB_DT_ENDPOINT_SIZE);
- index +=
- USB_DT_ENDPOINT_SIZE;
- memcpy(&full_conf_desc
- [index],
- serial->port[i].
- ep_bulkout.desc,
+ index += USB_DT_ENDPOINT_SIZE;
+ memcpy(&full_conf_desc[index],
+ serial->port[i].ep_bulkout.desc,
USB_DT_ENDPOINT_SIZE);
- index +=
- USB_DT_ENDPOINT_SIZE;
+ index += USB_DT_ENDPOINT_SIZE;
}
- dbg
- ("sending whole config desc, size=%d, our size=%d",
+ dbg("sending whole config desc, size=%d, our size=%d",
desc_len, CONFIG_DESC_LEN);
- desc_len =
- desc_len >
- CONFIG_DESC_LEN ?
+ desc_len = desc_len > CONFIG_DESC_LEN ?
CONFIG_DESC_LEN : desc_len;
send_packet(&serial->ep_ctrl,
- full_conf_desc,
- desc_len, 0);
+ full_conf_desc, desc_len, 0);
}
} else
- endpoint_stall(&serial->ep_ctrl); // Stall endpoint 0
+ endpoint_stall(&serial->ep_ctrl);
break;
case USB_DT_STRING:
// If the string descr index in low-byte of setup->value
@@ -958,15 +952,13 @@
if (strnum >= 0 && strnum < 6) {
struct usb_string_descriptor *desc =
serial->str_desc[strnum];
- desc_len =
- desc_len >
- desc->bLength ? desc->
- bLength : desc_len;
+ desc_len = desc_len > desc->bLength ?
+ desc->bLength : desc_len;
dbg("sending string desc %d", strnum);
send_packet(&serial->ep_ctrl, (u8 *) desc,
desc_len, 0);
} else
- endpoint_stall(&serial->ep_ctrl); // Stall endpoint 0
+ endpoint_stall(&serial->ep_ctrl);
break;
default: // Invalid request
dbg("invalid get desc=%d, stalled",
@@ -980,8 +972,8 @@
break;
case USB_REQ_GET_INTERFACE:
// interface must be zero.
- if ((le16_to_cpu(setup->index) & 0xff)
- || serial->state == ADDRESS) {
+ if ((le16_to_cpu(setup->index) & 0xff) ||
+ serial->state == ADDRESS) {
// FIXME: respond with "request error". how?
} else if (serial->state == CONFIGURED) {
// send serial->alternate_setting
@@ -994,8 +986,7 @@
if (serial->state == ADDRESS) {
// FIXME: respond with "request error". how?
} else if (serial->state == CONFIGURED) {
- serial->interface =
- le16_to_cpu(setup->index) & 0xff;
+ serial->interface = le16_to_cpu(setup->index) & 0xff;
serial->alternate_setting =
le16_to_cpu(setup->value) & 0xff;
// interface and alternate_setting must be zero
@@ -1019,8 +1010,7 @@
case USB_REQ_GET_CONFIGURATION:
// send serial->configuration
dbg("sending config");
- send_packet(&serial->ep_ctrl, &serial->configuration, 1,
- 0);
+ send_packet(&serial->ep_ctrl, &serial->configuration, 1, 0);
break;
case USB_REQ_GET_STATUS:
// FIXME: looks like the h/w handles this one
@@ -1043,21 +1033,20 @@
switch (setup->requesttype) {
case 0x00: // Device
if ((le16_to_cpu(setup->value) & 0xff) == 1)
- serial->remote_wakeup_en = 0; // Disable Remote Wakeup
+ serial->remote_wakeup_en = 0;
else
- endpoint_stall(&serial->ep_ctrl); // Stall End Point 0
+ endpoint_stall(&serial->ep_ctrl);
break;
case 0x02: // End Point
if ((le16_to_cpu(setup->value) & 0xff) == 0) {
endpoint_t *ep =
epnum_to_ep(serial,
- le16_to_cpu(setup->
- index) & 0xff);
+ le16_to_cpu(setup->index) & 0xff);
endpoint_unstall(ep);
endpoint_reset_datatoggle(ep);
} else
- endpoint_stall(&serial->ep_ctrl); // Stall End Point 0
+ endpoint_stall(&serial->ep_ctrl);
break;
}
break;
@@ -1065,20 +1054,19 @@
switch (setup->requesttype) {
case 0x00: // Device
if ((le16_to_cpu(setup->value) & 0xff) == 1)
- serial->remote_wakeup_en = 1; // Enable Remote Wakeup
+ serial->remote_wakeup_en = 1;
else
- endpoint_stall(&serial->ep_ctrl); // Stall End Point 0
+ endpoint_stall(&serial->ep_ctrl);
break;
case 0x02: // End Point
if ((le16_to_cpu(setup->value) & 0xff) == 0) {
endpoint_t *ep =
epnum_to_ep(serial,
- le16_to_cpu(setup->
- index) & 0xff);
+ le16_to_cpu(setup->index) & 0xff);
endpoint_stall(ep);
} else
- endpoint_stall(&serial->ep_ctrl); // Stall End Point 0
+ endpoint_stall(&serial->ep_ctrl);
break;
}
break;
@@ -1093,7 +1081,8 @@
* A complete packet (SETUP, DATA0, or DATA1) has been received
* on the given endpoint's fifo.
*/
-static void process_complete(struct usb_serial *serial, int fifo_num)
+static void
+process_complete (struct usb_serial* serial, int fifo_num)
{
endpoint_t *ep = fifonum_to_ep(serial, fifo_num);
struct usb_serial_port *port = NULL;
@@ -1113,24 +1102,24 @@
spin_unlock(&ep->lock);
return;
}
+
// SETUP packet received ?
- if (cs & USBDEV_CS_SU) {
+ //if (cs & USBDEV_CS_SU) { FIXME: uncomment!
if (pkt->size == sizeof(devrequest)) {
devrequest setup;
- if ((cs & (USBDEV_CS_NAK | USBDEV_CS_ACK))
- == USBDEV_CS_ACK)
+ if ((cs & (USBDEV_CS_NAK | USBDEV_CS_ACK)) ==
+ USBDEV_CS_ACK)
dbg("got SETUP");
else
dbg("got NAK SETUP, cs=%08x", cs);
- memcpy(&setup, pkt->bufptr,
- sizeof(devrequest));
+ memcpy(&setup, pkt->bufptr, sizeof(devrequest));
process_setup(serial, &setup);
- } else
- dbg(__FUNCTION__
- ": wrong size SETUP received");
+ //} else FIXME: uncomment!
+ //dbg(__FUNCTION__ ": wrong size SETUP received");
} else {
// DATAx packet received on endpoint 0
- // FIXME: will need a state machine for control OUT transactions
+ // FIXME: will need a state machine for control
+ // OUT transactions
dbg("got DATAx on EP0, size=%d, cs=%08x",
pkt->size, cs);
}
@@ -1160,7 +1149,8 @@
// This ISR needs to ack both the complete and suspend events
-static void req_sus_intr(int irq, void *dev_id, struct pt_regs *regs)
+static void
+req_sus_intr (int irq, void *dev_id, struct pt_regs *regs)
{
struct usb_serial *serial = (struct usb_serial *) dev_id;
int i;
@@ -1189,20 +1179,20 @@
}
-static void dma_done_ctrl(struct usb_serial *serial)
+static void
+dma_done_ctrl(struct usb_serial* serial)
{
endpoint_t *ep = &serial->ep_ctrl;
- int buff_done;
- u32 cs0;
+ u32 cs0, buff_done;
spin_lock(&ep->lock);
cs0 = inl(ep->reg->ctrl_stat);
// first check packet transmit done
- if ((buff_done = get_dma_buffer_done(ep->indma)) >= 0) {
+ if ((buff_done = get_dma_buffer_done(ep->indma)) != 0) {
// transmitted a DATAx packet on control endpoint 0
// clear DMA done bit
- if (buff_done == 0)
+ if (buff_done == DMA_D0)
clear_dma_done0(ep->indma);
else
clear_dma_done1(ep->indma);
@@ -1215,9 +1205,9 @@
* the receive packet complete intr should happen
* before the DMA done intr occurs.
*/
- if ((buff_done = get_dma_buffer_done(ep->outdma)) >= 0) {
+ if ((buff_done = get_dma_buffer_done(ep->outdma)) != 0) {
// clear DMA done bit
- if (buff_done == 0)
+ if (buff_done == DMA_D0)
clear_dma_done0(ep->outdma);
else
clear_dma_done1(ep->outdma);
@@ -1226,18 +1216,19 @@
spin_unlock(&ep->lock);
}
-static void dma_done_port(struct usb_serial_port *port)
+static void
+dma_done_port(struct usb_serial_port * port)
{
endpoint_t *ep;
- int buff_done;
+ u32 buff_done;
// first check packet transmit done (bulk IN ep)
ep = &port->ep_bulkin;
spin_lock(&ep->lock);
- if ((buff_done = get_dma_buffer_done(ep->indma)) >= 0) {
+ if ((buff_done = get_dma_buffer_done(ep->indma)) != 0) {
// transmitted a DATAx packet on the port's bulk IN endpoint
// clear DMA done bit
- if (buff_done == 0)
+ if (buff_done == DMA_D0)
clear_dma_done0(ep->indma);
else
clear_dma_done1(ep->indma);
@@ -1256,10 +1247,10 @@
*/
ep = &port->ep_bulkout;
spin_lock(&ep->lock);
- if ((buff_done = get_dma_buffer_done(ep->outdma)) >= 0) {
+ if ((buff_done = get_dma_buffer_done(ep->outdma)) != 0) {
// received a DATAx packet on the port's bulk OUT endpoint
// clear DMA done bit
- if (buff_done == 0)
+ if (buff_done == DMA_D0)
clear_dma_done0(ep->outdma);
else
clear_dma_done1(ep->outdma);
@@ -1269,7 +1260,8 @@
// This ISR needs to handle dma done events for ALL endpoints!
-static void dma_done_intr(int irq, void *dev_id, struct pt_regs *regs)
+static void
+dma_done_intr (int irq, void *dev_id, struct pt_regs *regs)
{
struct usb_serial *serial = (struct usb_serial *) dev_id;
int i;
@@ -1316,9 +1308,10 @@
if (!port->active) {
port->active = 1;
- /* force low_latency on so that our tty_push actually forces the
- * data through, otherwise it is scheduled, and with high data
- * rates (like with OHCI) data can get lost.
+ /*
+ * force low_latency on so that our tty_push actually forces
+ * the data through, otherwise it is scheduled, and with high
+ * data rates (like with OHCI) data can get lost.
*/
port->tty->low_latency = 1;
@@ -1537,8 +1530,8 @@
}
tty = port->tty;
- if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP))
- && tty->ldisc.write_wakeup) {
+ if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
+ tty->ldisc.write_wakeup) {
dbg(__FUNCTION__ " - write wakeup call.");
(tty->ldisc.write_wakeup) (tty);
}
@@ -1623,8 +1616,8 @@
free_irq(AU1000_USB_DEV_SUS_INT, &usbserial);
free_irq(ep->inirq, &usbserial);
//free_irq(ep->outirq, &usbserial);
- free_dma(ep->indma);
- free_dma(ep->outdma);
+ free_au1000_dma(ep->indma);
+ free_au1000_dma(ep->outdma);
endpoint_flush(ep);
// now free all port resources
@@ -1632,18 +1625,17 @@
// free port's bulk IN endpoint resources
ep = &usbserial.port[i].ep_bulkin;
free_irq(ep->inirq, &usbserial);
- free_dma(ep->indma);
+ free_au1000_dma(ep->indma);
endpoint_flush(ep);
// free port's bulk OUT endpoint resources
ep = &usbserial.port[i].ep_bulkout;
//free_irq(ep->outirq, &usbserial);
- free_dma(ep->outdma);
+ free_au1000_dma(ep->outdma);
endpoint_flush(ep);
tty_unregister_devfs(&serial_tty_driver, i);
- info
- ("usbdev serial converter now disconnected from ttyUSBdev%d",
+ info("usbdev serial converter now disconnected from ttyUSBdev%d",
i);
}
@@ -1692,8 +1684,7 @@
return -1;
}
- usbserial.str_desc[0] =
- (struct usb_string_descriptor *) str_desc_buf;
+ usbserial.str_desc[0] = (struct usb_string_descriptor *)str_desc_buf;
memcpy(usbserial.str_desc[0], &string_desc0, string_desc0.bLength);
usbserial.str_desc[1] = (struct usb_string_descriptor *)
(str_desc_buf + string_desc0.bLength);
@@ -1733,13 +1724,13 @@
ep->reg = &ep_reg[0];
ep->max_pkt_size = usbserial.dev_desc->bMaxPacketSize0;
ep->indma = ep->outdma = -1;
- if ((ep->indma = request_dma(ep_dma_id[0].id, ep_dma_id[0].str)) <
- 0) {
+ if ((ep->indma = request_au1000_dma(ep_dma_id[0].id,
+ ep_dma_id[0].str)) < 0) {
err("Can't get %s DMA\n", ep_dma_id[0].str);
goto err_out;
}
- if ((ep->outdma = request_dma(ep_dma_id[1].id, ep_dma_id[1].str)) <
- 0) {
+ if ((ep->outdma = request_au1000_dma(ep_dma_id[1].id,
+ ep_dma_id[1].str)) < 0) {
err("Can't get %s DMA\n", ep_dma_id[1].str);
goto err_out;
}
@@ -1763,8 +1754,7 @@
know what ports we are bound to */
for (i = 0; i < NUM_PORTS; ++i) {
tty_register_devfs(&serial_tty_driver, 0, i);
- info
- ("usbdev serial attached to ttyUSBdev%d (or devfs usb/ttsdev/%d)",
+ info("usbdev serial attached to ttyUSBdev%d (or devfs usb/ttsdev/%d)",
i, i);
port = &usbserial.port[i];
port->serial = &usbserial;
@@ -1782,9 +1772,8 @@
ep->reg = &ep_reg[1 + NUM_PORTS * i];
ep->max_pkt_size = ep->desc->wMaxPacketSize;
ep->indma = ep->outdma = -1;
- if (
- (ep->indma =
- request_dma(ep_dma_id[2 + NUM_PORTS * i].id,
+ if ((ep->indma =
+ request_au1000_dma(ep_dma_id[2+NUM_PORTS*i].id,
ep_dma_id[2 + NUM_PORTS * i].str)) < 0) {
err("Can't get %s DMA\n",
ep_dma_id[2 + NUM_PORTS * i].str);
@@ -1803,11 +1792,9 @@
ep->reg = &ep_reg[1 + NUM_PORTS * i + 1];
ep->max_pkt_size = ep->desc->wMaxPacketSize;
ep->indma = ep->outdma = -1;
- if (
- (ep->outdma =
- request_dma(ep_dma_id[2 + NUM_PORTS * i + 1].id,
- ep_dma_id[2 + NUM_PORTS * i + 1].str)) <
- 0) {
+ if ((ep->outdma =
+ request_au1000_dma(ep_dma_id[2+NUM_PORTS*i + 1].id,
+ ep_dma_id[2+NUM_PORTS*i + 1].str)) < 0) {
err("Can't get %s DMA\n",
ep_dma_id[2 + NUM_PORTS * i + 1].str);
goto err_out;
@@ -1816,8 +1803,7 @@
#if 0
if (request_irq(ep->outirq, dma_done_intr, SA_INTERRUPT,
"USBdev bulk OUT", &usbserial)) {
- err("Can't get port %d bulk OUT dma done irq\n",
- i);
+ err("Can't get port %d bulk OUT dma done irq\n", i);
goto err_out;
}
#endif
|
|
From: Steve L. <slo...@us...> - 2001-11-08 18:03:21
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv16661/include/asm-mips
Modified Files:
au1000_dma.h
Log Message:
Au1000 sound updates.
Index: au1000_dma.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000_dma.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- au1000_dma.h 2001/11/06 20:23:55 1.5
+++ au1000_dma.h 2001/11/08 18:03:18 1.6
@@ -337,22 +337,15 @@
}
/*
- * Returns which buffer has its done bit set in the mode register.
- * Returns -1 if neither or both done bits set.
+ * Returns the buffer done bits.
*/
-static __inline__ int get_dma_buffer_done(unsigned int dmanr)
+static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)
{
- unsigned int mode;
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
- mode = inl(chan->io + DMA_MODE_SET);
- if (!(mode & (DMA_D0 | DMA_D1)) ||
- (mode & (DMA_D0 | DMA_D1)) == (DMA_D0 | DMA_D1))
- return -1;
-
- return (mode & DMA_D0) ? 0 : 1;
+ return inl(chan->io + DMA_MODE_SET) & (DMA_D0 | DMA_D1);
}
|
|
From: Steve L. <slo...@us...> - 2001-11-08 18:03:20
|
Update of /cvsroot/linux-mips/linux/drivers/sound
In directory usw-pr-cvs1:/tmp/cvs-serv16661/drivers/sound
Modified Files:
au1000.c
Log Message:
Au1000 sound updates.
Index: au1000.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/au1000.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- au1000.c 2001/10/22 22:39:58 1.5
+++ au1000.c 2001/11/08 18:03:18 1.6
@@ -92,7 +92,7 @@
#define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
/* Boot options */
-static int vra = 0; // 0 = no VRA, 1 = use VRA if codec supports it
+static int vra = 0; // 0 = no VRA, 1 = use VRA if codec supports it
MODULE_PARM(vra, "i");
MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
@@ -100,47 +100,46 @@
/* --------------------------------------------------------------------- */
[...1816 lines suppressed...]
{
info("st...@mv..., built " __TIME__ " on " __DATE__);
@@ -2113,7 +2122,7 @@
static int __init au1000_setup(char *options)
{
- char* this_opt;
+ char *this_opt;
if (!options || !*options)
return 0;
@@ -2124,7 +2133,7 @@
vra = 1;
}
}
-
+
return 1;
}
|
|
From: James S. <jsi...@us...> - 2001-11-08 17:42:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm
In directory usw-pr-cvs1:/tmp/cvs-serv7520/sibyte/swarm
Added Files:
Makefile cfe_api.c cfe_api.h cfe_error.h cfe_xiocb.h cmdline.c
memory.c rtc.c setup.c smp.c time.c
Log Message:
Cleanup Makefile crap and add support for Sibyte SB1250 / SWARM.
--- NEW FILE: Makefile ---
.S.s:
$(CPP) $(AFLAGS) $< -o $@
.S.o:
$(CC) $(AFLAGS) -c $< -o $@
EXTRA_AFLAGS = -mips3 -mcpu=r4000
all: sbswarm.a
OBJS-y = setup.o cmdline.o rtc.o time.o memory.o cfe_api.o
OBJS-$(CONFIG_SMP) += smp.o
OBJS-$(CONFIG_L3DEMO) += procl3switch.o l3procbootstrap.o l3proc.o
OBJS-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
#XMITTER=1
ifdef XMITTER
l3proc.bin: xmitter
ln xmitter l3proc.bin
else
l3proc.bin: l3proc
ln l3proc l3proc.bin
endif
l3proc.o: l3proc.bin
mips-linux-ld -Tl3proc.lds -bbinary -o l3proc.o l3proc.bin
sbswarm.a: $(OBJS-y)
$(AR) rcs sbswarm.a $^
rm -f l3proc.o l3proc.bin
include $(TOPDIR)/Rules.make
--- NEW FILE: cfe_api.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* *********************************************************************
* Broadcom Common Firmware Environment (CFE)
*
* Device Function stubs File: cfe_api.c
*
* This module contains device function stubs (small routines to
* call the standard "iocb" interface entry point to CFE).
* There should be one routine here per iocb function call.
*
* Author: Mitch Lichtenberg (mp...@br...)
*
********************************************************************* */
#include "cfe_xiocb.h"
#include "cfe_api.h"
#include <linux/string.h>
static long cfe_console_handle = -1;
static int (*cfe_dispfunc)(long handle,cfe_xiocb_t *xiocb) = 0;
static cfe_xuint_t cfe_handle = 0;
/*
* This macro makes a "signed 64-bit pointer" - basically extending a regular
* pointer to its 64-bit compatibility space equivalent.
*/
#define BIGPTR(x) (long long) (long) (x)
typedef unsigned long intptr_t;
int cfe_init(cfe_xuint_t handle)
{
unsigned int *sealloc = (unsigned int *) (intptr_t) (int) CFE_APISEAL;
if (*sealloc != CFE_EPTSEAL) return -1;
cfe_dispfunc = (void *) (cfe_xptr_t) (int) CFE_APIENTRY;
if (handle) cfe_handle = handle;
return 0;
}
int cfe_iocb_dispatch(cfe_xiocb_t *xiocb);
int cfe_iocb_dispatch(cfe_xiocb_t *xiocb)
{
if (!cfe_dispfunc) return -1;
return (*cfe_dispfunc)(cfe_handle,xiocb);
}
static int cfe_strlen(char *name)
{
int count = 0;
while (*name) {
count++;
name++;
}
return count;
}
int cfe_open(char *name)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.plist.xiocb_buffer.buf_offset = 0;
xiocb.plist.xiocb_buffer.buf_ptr = BIGPTR(name);
xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name);
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status < 0) ? xiocb.xiocb_status : xiocb.xiocb_handle;
}
int cfe_close(int handle)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = 0;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status);
}
int cfe_readblk(int handle,cfe_xint_t offset,unsigned char *buffer,int length)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_READ;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.plist.xiocb_buffer.buf_offset = offset;
xiocb.plist.xiocb_buffer.buf_ptr = BIGPTR(buffer);
xiocb.plist.xiocb_buffer.buf_length = length;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status < 0) ? xiocb.xiocb_status : xiocb.plist.xiocb_buffer.buf_retlen;
}
int cfe_read(int handle,unsigned char *buffer,int length)
{
return cfe_readblk(handle,0,buffer,length);
}
int cfe_writeblk(int handle,cfe_xint_t offset,unsigned char *buffer,int length)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.plist.xiocb_buffer.buf_offset = offset;
xiocb.plist.xiocb_buffer.buf_ptr = BIGPTR(buffer);
xiocb.plist.xiocb_buffer.buf_length = length;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status < 0) ? xiocb.xiocb_status : xiocb.plist.xiocb_buffer.buf_retlen;
}
int cfe_write(int handle,unsigned char *buffer,int length)
{
return cfe_writeblk(handle,0,buffer,length);
}
int cfe_ioctl(int handle,unsigned int ioctlnum,unsigned char *buffer,int length,int *retlen)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.plist.xiocb_buffer.buf_ioctlcmd = (cfe_xint_t) ioctlnum;
xiocb.plist.xiocb_buffer.buf_ptr = BIGPTR(buffer);
xiocb.plist.xiocb_buffer.buf_length = length;
cfe_iocb_dispatch(&xiocb);
if (retlen) *retlen = xiocb.plist.xiocb_buffer.buf_retlen;
return xiocb.xiocb_status;
}
int cfe_inpstat(int handle)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_inpstat_t);
xiocb.plist.xiocb_inpstat.inp_status = 0;
cfe_iocb_dispatch(&xiocb);
if (xiocb.xiocb_status < 0) return xiocb.xiocb_status;
return xiocb.plist.xiocb_inpstat.inp_status;
}
long long cfe_getticks(void)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_time_t);
xiocb.plist.xiocb_time.ticks = 0;
cfe_iocb_dispatch(&xiocb);
return xiocb.plist.xiocb_time.ticks;
}
int cfe_getenv(char *name,char *dest,int destlen)
{
cfe_xiocb_t xiocb;
*dest = 0;
xiocb.xiocb_fcode = CFE_CMD_ENV_GET;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
xiocb.plist.xiocb_envbuf.enum_idx = 0;
xiocb.plist.xiocb_envbuf.name_ptr = BIGPTR(name);
xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
xiocb.plist.xiocb_envbuf.val_ptr = BIGPTR(dest);
xiocb.plist.xiocb_envbuf.val_length = destlen;
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
int cfe_setenv(char *name,char *val)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
xiocb.plist.xiocb_envbuf.enum_idx = 0;
xiocb.plist.xiocb_envbuf.name_ptr = BIGPTR(name);
xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
xiocb.plist.xiocb_envbuf.val_ptr = BIGPTR(val);
xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val);
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
int cfe_enummem(long idx, unsigned long *addr, unsigned long *size, long *type)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_meminfo_t);
xiocb.plist.xiocb_meminfo.mi_idx = idx;
cfe_iocb_dispatch(&xiocb);
(*addr) = xiocb.plist.xiocb_meminfo.mi_addr;
(*size) = xiocb.plist.xiocb_meminfo.mi_size;
(*type) = xiocb.plist.xiocb_meminfo.mi_type;
return xiocb.xiocb_status;
}
int cfe_enumenv(int idx,char *name,int namelen,char *val,int vallen)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
xiocb.plist.xiocb_envbuf.enum_idx = idx;
xiocb.plist.xiocb_envbuf.name_ptr = BIGPTR(name);
xiocb.plist.xiocb_envbuf.name_length = namelen;
xiocb.plist.xiocb_envbuf.val_ptr = BIGPTR(val);
xiocb.plist.xiocb_envbuf.val_length = vallen;
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
int cfe_exit(int warm, int status)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_RESTART;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0;
xiocb.xiocb_psize = sizeof(xiocb_exitstat_t);
xiocb.plist.xiocb_exitstat.status = (cfe_xint_t) status;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status);
}
int cfe_flushcache(int flg)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = flg;
xiocb.xiocb_psize = 0;
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
int cfe_getstdhandle(int flg)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = flg;
xiocb.xiocb_psize = 0;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status < 0) ? xiocb.xiocb_status : xiocb.xiocb_handle;
}
int cfe_start_cpu(int cpu, void (*fn)(void), long sp, long gp, long a1)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t);
xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START;
xiocb.plist.xiocb_cpuctl.gp_val = gp;
xiocb.plist.xiocb_cpuctl.sp_val = sp;
xiocb.plist.xiocb_cpuctl.a1_val = a1;
xiocb.plist.xiocb_cpuctl.start_addr = (long)fn;
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
void cfe_open_console()
{
cfe_console_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
}
void cfe_console_print(char *str)
{
if (cfe_console_handle != -1) {
cfe_write(cfe_console_handle, str, strlen(str));
}
}
--- NEW FILE: cfe_api.h ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* *********************************************************************
* Broadcom Common Firmware Environment (CFE)
*
* Device function prototypes File: cfe_api.h
*
* This module contains prototypes for cfe_devfuncs.c, a set
* of wrapper routines to the IOCB interface. This file,
* along with cfe_api.c, can be incorporated into programs
* that need to call CFE.
*
* Author: Mitch Lichtenberg (mp...@br...)
*
********************************************************************* */
#define CFE_EPTSEAL 0x43464531
#define CFE_APIENTRY 0x9FC00500
#define CFE_APISEAL 0x9FC00508
#ifndef __ASSEMBLER__
int cfe_init(cfe_xuint_t handle);
int cfe_open(char *name);
int cfe_close(int handle);
int cfe_readblk(int handle,cfe_xint_t offset,unsigned char *buffer,int length);
int cfe_read(int handle,unsigned char *buffer,int length);
int cfe_writeblk(int handle,cfe_xint_t offset,unsigned char *buffer,int length);
int cfe_write(int handle,unsigned char *buffer,int length);
int cfe_ioctl(int handle,unsigned int ioctlnum,unsigned char *buffer,int length,int *retlen);
int cfe_inpstat(int handle);
int cfe_enumenv(int idx,char *name,int namelen,char *val,int vallen);
int cfe_enummem(long idx, unsigned long *addr, unsigned long *size, long *type);
int cfe_setenv(char *name,char *val);
int cfe_getenv(char *name,char *dest,int destlen);
long long cfe_getticks(void);
int cfe_exit(int warm, int status);
int cfe_flushcache(int flg);
int cfe_getstdhandle(int flg);
int cfe_start_cpu(int cpu, void (*fn)(void), long sp, long gp, long a1);
void cfe_open_console(void);
void cfe_console_print(char *);
#endif
--- NEW FILE: cfe_error.h ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* *********************************************************************
* Broadcom Common Firmware Environment (CFE)
*
* Error codes File: cfe_error.h
*
* CFE's global error code list is here.
*
* Author: Mitch Lichtenberg (mp...@br...)
*
********************************************************************* */
#define CFE_OK 0
#define CFE_ERR -1 /* generic error */
#define CFE_ERR_INV_COMMAND -2
#define CFE_ERR_EOF -3
#define CFE_ERR_IOERR -4
#define CFE_ERR_NOMEM -5
#define CFE_ERR_DEVNOTFOUND -6
#define CFE_ERR_DEVOPEN -7
#define CFE_ERR_INV_PARAM -8
#define CFE_ERR_ENVNOTFOUND -9
#define CFE_ERR_ENVREADONLY -10
#define CFE_ERR_NOTELF -11
#define CFE_ERR_NOT32BIT -12
#define CFE_ERR_WRONGENDIAN -13
#define CFE_ERR_BADELFVERS -14
#define CFE_ERR_NOTMIPS -15
#define CFE_ERR_BADELFFMT -16
#define CFE_ERR_BADADDR -17
#define CFE_ERR_FILENOTFOUND -18
#define CFE_ERR_UNSUPPORTED -19
#define CFE_ERR_HOSTUNKNOWN -20
#define CFE_ERR_TIMEOUT -21
#define CFE_ERR_PROTOCOLERR -22
#define CFE_ERR_NETDOWN -23
#define CFE_ERR_NONAMESERVER -24
#define CFE_ERR_NOHANDLES -25
#define CFE_ERR_ALREADYBOUND -26
#define CFE_ERR_CANNOTSET -27
#define CFE_ERR_NOMORE -28
#define CFE_ERR_BADFILESYS -29
#define CFE_ERR_FSNOTAVAIL -30
#define CFE_ERR_INVBOOTBLOCK -31
#define CFE_ERR_WRONGDEVTYPE -32
#define CFE_ERR_BBCHECKSUM -33
#define CFE_ERR_BOOTPROGCHKSUM -34
--- NEW FILE: cfe_xiocb.h ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* *********************************************************************
* Broadcom Common Firmware Environment (CFE)
*
* IOCB definitions File: cfe_iocb.h
*
* This module describes CFE's IOCB structure, the main
* data structure used to communicate API requests with CFE.
*
* Author: Mitch Lichtenberg (mp...@br...)
*
********************************************************************* */
/* *********************************************************************
* Constants
********************************************************************* */
#define CFE_CMD_FW_GETINFO 0
#define CFE_CMD_FW_RESTART 1
#define CFE_CMD_FW_BOOT 2
#define CFE_CMD_FW_CPUCTL 3
#define CFE_CMD_FW_GETTIME 4
#define CFE_CMD_FW_MEMENUM 5
#define CFE_CMD_FW_FLUSHCACHE 6
#define CFE_CMD_DEV_GETHANDLE 9
#define CFE_CMD_DEV_ENUM 10
#define CFE_CMD_DEV_OPEN 11
#define CFE_CMD_DEV_INPSTAT 12
#define CFE_CMD_DEV_READ 13
#define CFE_CMD_DEV_WRITE 14
#define CFE_CMD_DEV_IOCTL 15
#define CFE_CMD_DEV_CLOSE 16
#define CFE_CMD_DEV_GETINFO 17
#define CFE_CMD_ENV_ENUM 20
#define CFE_CMD_ENV_GET 22
#define CFE_CMD_ENV_SET 23
#define CFE_CMD_ENV_DEL 24
#define CFE_CMD_MAX 32
#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */
#define CFE_MI_AVAILABLE 1 /* memory is available */
#define CFE_FLG_WARMSTART 0x00000001
#define CFE_FLG_ENV_PERMANENT 0x00000001
#define CFE_CPU_CMD_START 1
#define CFE_CPU_CMD_STOP 0
#define CFE_STDHANDLE_CONSOLE 0
#define CFE_DEV_NETWORK 1
#define CFE_DEV_DISK 2
#define CFE_DEV_FLASH 3
#define CFE_DEV_SERIAL 4
#define CFE_DEV_CPU 5
#define CFE_DEV_NVRAM 6
#define CFE_DEV_OTHER 7
#define CFE_DEV_MASK 0x0F
#define CFE_CACHE_FLUSH_D 1
#define CFE_CACHE_INVAL_I 2
#define CFE_CACHE_INVAL_D 4
#define CFE_CACHE_INVAL_L2 8
/* *********************************************************************
* Structures
********************************************************************* */
typedef unsigned long long cfe_xuint_t;
typedef long long cfe_xint_t;
typedef long long cfe_xptr_t;
typedef struct xiocb_buffer_s {
cfe_xuint_t buf_offset; /* offset on device (bytes) */
cfe_xptr_t buf_ptr; /* pointer to a buffer */
cfe_xuint_t buf_length; /* length of this buffer */
cfe_xuint_t buf_retlen; /* returned length (for read ops) */
cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */
} xiocb_buffer_t;
#define buf_devflags buf_ioctlcmd /* returned device info flags */
typedef struct xiocb_inpstat_s {
cfe_xuint_t inp_status; /* 1 means input available */
} xiocb_inpstat_t;
typedef struct xiocb_envbuf_s {
cfe_xint_t enum_idx; /* 0-based enumeration index */
cfe_xptr_t name_ptr; /* name string buffer */
cfe_xint_t name_length; /* size of name buffer */
cfe_xptr_t val_ptr; /* value string buffer */
cfe_xint_t val_length; /* size of value string buffer */
} xiocb_envbuf_t;
typedef struct xiocb_cpuctl_s {
cfe_xuint_t cpu_number; /* cpu number to control */
cfe_xuint_t cpu_command; /* command to issue to CPU */
cfe_xuint_t start_addr; /* CPU start address */
cfe_xuint_t gp_val; /* starting GP value */
cfe_xuint_t sp_val; /* starting SP value */
cfe_xuint_t a1_val; /* starting A1 value */
} xiocb_cpuctl_t;
typedef struct xiocb_time_s {
cfe_xint_t ticks; /* current time in ticks */
} xiocb_time_t;
typedef struct xiocb_exitstat_s {
cfe_xint_t status;
} xiocb_exitstat_t;
typedef struct xiocb_meminfo_s {
cfe_xint_t mi_idx; /* 0-based enumeration index */
cfe_xint_t mi_type; /* type of memory block */
cfe_xuint_t mi_addr; /* physical start address */
cfe_xuint_t mi_size; /* block size */
} xiocb_meminfo_t;
#define CFE_FWI_64BIT 0x00000001
#define CFE_FWI_32BIT 0x00000002
#define CFE_FWI_RELOC 0x00000004
#define CFE_FWI_UNCACHED 0x00000008
#define CFE_FWI_MULTICPU 0x00000010
#define CFE_FWI_FUNCSIM 0x00000020
#define CFE_FWI_RTLSIM 0x00000040
typedef struct xiocb_fwinfo_s {
cfe_xint_t fwi_version; /* major, minor, eco version */
cfe_xint_t fwi_totalmem; /* total installed mem */
cfe_xint_t fwi_flags; /* various flags */
cfe_xint_t fwi_boardid; /* board ID */
cfe_xint_t fwi_bootarea_va; /* VA of boot area */
cfe_xint_t fwi_bootarea_pa; /* PA of boot area */
cfe_xint_t fwi_bootarea_size; /* size of boot area */
cfe_xint_t fwi_reserved1;
cfe_xint_t fwi_reserved2;
cfe_xint_t fwi_reserved3;
} xiocb_fwinfo_t,cfe_fwinfo_t;
typedef struct cfe_xiocb_s {
cfe_xuint_t xiocb_fcode; /* IOCB function code */
cfe_xint_t xiocb_status; /* return status */
cfe_xint_t xiocb_handle; /* file/device handle */
cfe_xuint_t xiocb_flags; /* flags for this IOCB */
cfe_xuint_t xiocb_psize; /* size of parameter list */
union {
xiocb_buffer_t xiocb_buffer; /* buffer parameters */
xiocb_inpstat_t xiocb_inpstat; /* input status parameters */
xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */
xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */
xiocb_time_t xiocb_time; /* timer parameters */
xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */
xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */
xiocb_exitstat_t xiocb_exitstat; /* Exit status */
} plist;
} cfe_xiocb_t;
--- NEW FILE: cmdline.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <asm/bootinfo.h>
/*
* The naming of this variable is a remnant of the initial mips port to ARC-firmware
* based SGI consoles. We don't really need to do anything for the variable other
* than provide an instantiation. Everything about arcs_cmdline seems more than a
* little bit hackish...
*/
char arcs_cmdline[COMMAND_LINE_SIZE];
--- NEW FILE: memory.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Memory related routines
*/
#include <asm/page.h>
#include <linux/autoconf.h>
extern long swarm_mem_region_addrs[];
extern long swarm_mem_region_sizes[];
extern unsigned int swarm_mem_region_count;
int page_is_ram(unsigned long pagenr)
{
unsigned long addr = pagenr << PAGE_SHIFT;
#ifdef CONFIG_SWARM_STANDALONE
if (addr < (CONFIG_SIBYTE_SWARM_RAM_SIZE * 1024 * 1024)) {
return 1;
}
#else
int i;
for (i = 0; i < swarm_mem_region_count; i++) {
if ((addr >= swarm_mem_region_addrs[i])
&& (addr < (swarm_mem_region_addrs[i] + swarm_mem_region_sizes[i]))) {
return 1;
}
}
#endif
return 0;
}
--- NEW FILE: rtc.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Not really sure what is supposed to be here, yet
*/
#include <linux/spinlock.h>
#include <linux/mc146818rtc.h>
static unsigned char swarm_rtc_read_data(unsigned long addr)
{
return 0;
}
static void swarm_rtc_write_data(unsigned char data, unsigned long addr)
{
}
static int swarm_rtc_bcd_mode(void)
{
return 0;
}
struct rtc_ops swarm_rtc_ops = {
&swarm_rtc_read_data,
&swarm_rtc_write_data,
&swarm_rtc_bcd_mode
};
--- NEW FILE: setup.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Setup code for the SWARM board
*/
#include <linux/spinlock.h>
#include <linux/mc146818rtc.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/blk.h>
#include <asm/irq.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/sibyte/swarm.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_defs.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/reboot.h>
#include <linux/ide.h>
#include "cfe_xiocb.h"
#include "cfe_api.h"
#include "cfe_error.h"
extern struct rtc_ops swarm_rtc_ops;
extern int cfe_console_handle;
#ifdef CONFIG_BLK_DEV_IDE_SWARM
struct ide_ops *ide_ops;
#endif
#ifdef CONFIG_L3DEMO
extern void *l3info;
#endif
/* Max ram addressable in 32-bit segments */
#define MAX_RAM_SIZE (1024*1024*256)
#ifndef CONFIG_SWARM_STANDALONE
long swarm_mem_region_addrs[CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS];
long swarm_mem_region_sizes[CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS];
unsigned int swarm_mem_region_count;
#endif
#ifdef CONFIG_BLK_DEV_IDE_SWARM
static int swarm_ide_default_irq(ide_ioreg_t base)
{
return 0;
}
static ide_ioreg_t swarm_ide_default_io_base(int index)
{
return 0;
}
static void swarm_ide_init_hwif_ports (hw_regs_t *hw, ide_ioreg_t data_port,
ide_ioreg_t ctrl_port, int *irq)
{
ide_ioreg_t reg = data_port;
int i;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port) {
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
} else {
hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206;
}
if (irq != NULL)
*irq = 0;
hw->io_ports[IDE_IRQ_OFFSET] = 0;
}
static int swarm_ide_request_irq(unsigned int irq,
void (*handler)(int,void *, struct pt_regs *),
unsigned long flags, const char *device,
void *dev_id)
{
return request_irq(irq, handler, flags, device, dev_id);
}
static void swarm_ide_free_irq(unsigned int irq, void *dev_id)
{
free_irq(irq, dev_id);
}
static int swarm_ide_check_region(ide_ioreg_t from, unsigned int extent)
{
/* Note: "check_region" and friends do conflict management on ISA I/O
space. Our disk is not in that space, so this check won't work */
/* return check_region(from, extent); */
return 0;
}
static void swarm_ide_request_region(ide_ioreg_t from, unsigned int extent,
const char *name)
{
/* request_region(from, extent, name); */
}
static void swarm_ide_release_region(ide_ioreg_t from, unsigned int extent)
{
/* release_region(from, extent); */
}
struct ide_ops swarm_ide_ops = {
&swarm_ide_default_irq,
&swarm_ide_default_io_base,
&swarm_ide_init_hwif_ports,
&swarm_ide_request_irq,
&swarm_ide_free_irq,
&swarm_ide_check_region,
&swarm_ide_request_region,
&swarm_ide_release_region
};
#endif
static void stop_this_cpu(void *dummy)
{
printk("Cpu %d stopping\n", smp_processor_id());
for (;;);
}
static void smp_cpu0_exit(void)
{
printk("cpu %d poked\n", smp_processor_id());
/* XXXKW we are in the mailbox handler... */
__asm__(".set push\n\t"
".set mips32\n\t"
"la $2, swarm_linux_exit\n\t"
"mtc0 $2, $24\n\t"
"eret\n\t"
".set pop"
::: "$2");
}
extern void (*smp_cpu0_finalize)(void);
static void swarm_linux_exit(void)
{
if (smp_processor_id()) {
/* Make cpu 0 do the swarm_linux_exit */
/* XXXKW this isn't quite there yet */
smp_cpu0_finalize = smp_cpu0_exit;
stop_this_cpu(NULL);
} else {
printk("swarm_linux_exit called...passing control back to CFE\n");
cfe_exit(1, 0);
printk("cfe_exit returned??\n");
while(1);
}
}
extern unsigned long mips_io_port_base;
void __init swarm_setup(void)
{
extern int panic_timeout;
rtc_ops = &swarm_rtc_ops;
panic_timeout = 5; /* For debug. This should probably be raised later */
_machine_restart = (void (*)(char *))swarm_linux_exit;
_machine_halt = swarm_linux_exit;
_machine_power_off = swarm_linux_exit;
#ifdef CONFIG_L3DEMO
if (l3info != NULL) {
printk("\n");
}
#endif
printk("This kernel optimized for "
#ifdef CONFIG_SIMULATION
"simulation"
#else
"board"
#endif
" runs\n");
#ifdef CONFIG_BLK_DEV_IDE_SWARM
ide_ops = &swarm_ide_ops;
#endif
}
/* This is the kernel command line. Actually, it's
copied, eventually, to command_line, and looks to be
quite redundant. But not something to fix just now */
extern char arcs_cmdline[];
#ifdef CONFIG_EMBEDDED_RAMDISK
/* These are symbols defined by the ramdisk linker script */
extern unsigned char __rd_start;
extern unsigned char __rd_end;
#endif
static void prom_meminit(void)
{
#ifndef CONFIG_SWARM_STANDALONE
unsigned long addr, size;
long type;
unsigned int idx;
int rd_flag;
#endif
#ifdef CONFIG_BLK_DEV_INITRD
unsigned long initrd_pstart;
unsigned long initrd_pend;
#ifdef CONFIG_EMBEDDED_RAMDISK
/* If we're using an embedded ramdisk, then __rd_start and __rd_end
are defined by the linker to be on either side of the ramdisk
area. Otherwise, initrd_start should be defined by kernel command
line arguments */
if (initrd_start == 0) {
initrd_start = (unsigned long)&__rd_start;
initrd_end = (unsigned long)&__rd_end;
}
#endif
initrd_pstart = __pa(initrd_start);
initrd_pend = __pa(initrd_end);
if (initrd_start &&
((initrd_pstart > MAX_RAM_SIZE)
|| (initrd_pend > MAX_RAM_SIZE))) {
setleds("INRD");
panic("initrd out of addressable memory\n");
}
#endif /* INITRD */
#ifdef CONFIG_SWARM_STANDALONE
/* Standalone compile, memory is hardcoded */
if (initrd_start) {
add_memory_region(0, initrd_pstart, BOOT_MEM_RAM);
add_memory_region(initrd_pstart, initrd_pend-initrd_pstart, BOOT_MEM_RESERVED);
add_memory_region(initrd_pend, (CONFIG_SIBYTE_SWARM_RAM_SIZE * 1024 * 1024)-initrd_pend, BOOT_MEM_RAM);
} else {
add_memory_region(0, CONFIG_SIBYTE_SWARM_RAM_SIZE * 1024 * 1024, BOOT_MEM_RAM);
}
#else /* Run with the firmware */
for (idx = 0; cfe_enummem(idx, &addr, &size, &type) != CFE_ERR_NOMORE; idx++) {
rd_flag = 0;
if (type == CFE_MI_AVAILABLE) {
/* See if this block contains (any portion of) the ramdisk */
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start) {
if ((initrd_pstart > addr) && (initrd_pstart < (addr + size))) {
add_memory_region(addr, initrd_pstart-addr, BOOT_MEM_RAM);
rd_flag = 1;
}
if ((initrd_pend > addr) && (initrd_pend < (addr + size))) {
add_memory_region(initrd_pend, (addr + size)-initrd_pend, BOOT_MEM_RAM);
rd_flag = 1;
}
}
#endif
if (!rd_flag) {
if (addr < MAX_RAM_SIZE) {
if (size > MAX_RAM_SIZE) {
size = MAX_RAM_SIZE - addr;
}
add_memory_region(addr, size, BOOT_MEM_RAM);
}
}
swarm_mem_region_addrs[swarm_mem_region_count] = addr;
swarm_mem_region_sizes[swarm_mem_region_count] = size;
swarm_mem_region_count++;
if (swarm_mem_region_count == CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS) {
while(1); /* Too many regions. Need to configure more */
}
}
}
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start) {
add_memory_region(initrd_pstart, initrd_pend-initrd_pstart, BOOT_MEM_RESERVED);
}
#endif
#endif /* CONFIG_SWARM_STANDALONE */
}
#ifdef CONFIG_BLK_DEV_INITRD
static int __init initrd_setup(char *str)
{
/*
*Initrd location comes in the form "<hex size of ramdisk in bytes>@<location in memory>"
* e.g. initrd=3abfd@80010000. This is set up by the loader.
*/
char *tmp, *endptr;
unsigned long initrd_size;
for (tmp = str; *tmp != '@'; tmp++) {
if (!*tmp) {
goto fail;
}
}
*tmp = 0;
tmp++;
if (!*tmp) {
goto fail;
}
initrd_size = simple_strtol(str, &endptr, 16);
if (*endptr) {
goto fail;
}
initrd_start = simple_strtol(tmp, &endptr, 16);
if (*endptr) {
goto fail;
}
initrd_end = initrd_start + initrd_size;
printk("Found initrd of %lx@%lx\n", initrd_size, initrd_start);
return 1;
fail:
printk("Bad initrd argument. Disabling initrd\n");
initrd_start = 0;
initrd_end = 0;
return 1;
}
#endif
/* prom_init is called just after the cpu type is determined, from
init_arch() */
int prom_init(int argc, char **argv, char **envp, int *prom_vec)
{
#ifdef CONFIG_SWARM_STANDALONE
strcpy(arcs_cmdline, "root=/dev/ram0 ");
#else
/*
* This should go away. Detect if we're booting
* straight from cfe without a loader. If we
* are, then we've got a prom vector in a0. Otherwise,
* argc (and argv and envp, for that matter) will be 0)
*/
if (argc < 0) {
prom_vec = (int *)argc;
}
cfe_init((long)prom_vec);
cfe_open_console();
if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, COMMAND_LINE_SIZE) < 0) {
if (argc < 0) {
/* It's OK for direct boot to not provide a
command line */
strcpy(arcs_cmdline, "root=/dev/ram0 ");
} else {
/* The loader should have set the command
line */
setleds("CMDL");
panic("LINUX_CMDLINE not defined in cfe.");
}
}
#ifdef CONFIG_BLK_DEV_INITRD
{
char *ptr;
/* Need to find out early whether we've got an initrd. So scan
the list looking now */
for (ptr = arcs_cmdline; *ptr; ptr++) {
while (*ptr == ' ') {
ptr++;
}
if (!strncmp(ptr, "initrd=", 7)) {
initrd_setup(ptr+7);
break;
} else {
while (*ptr && (*ptr != ' ')) {
ptr++;
}
}
}
}
#endif /* CONFIG_BLK_DEV_INITRD */
#endif /* CONFIG_SWARM_STANDALONE */
/* Not sure this is needed, but it's the safe way. */
arcs_cmdline[COMMAND_LINE_SIZE-1] = 0;
mips_machgroup = MACH_GROUP_SIBYTE;
#if 0
#ifndef CONFIG_SWARM_STANDALONE
for (i = 0; (i < argc) && (cmdline_idx < COMMAND_LINE_SIZE); i++) {
if (!strncmp(argv[i], "initrd=", 7)) {
/* Handle initrd argument early; we need to know
about them for the memory map */
unsigned char *size_str = argv[i] + 7;
unsigned char *loc_str = size_str;
unsigned long size, loc;
while (*loc_str && (*loc_str != '@')) {
loc_str++;
}
if (!*loc_str) {
printk("Ignoring malformed initrd argument: %s\n", argv[i]);
continue;
}
*loc_str = '\0';
loc_str++;
size = simple_strtoul(size_str, NULL, 16);
loc = simple_strtoul(loc_str, NULL, 16);
if (size && loc) {
printk("Found initrd argument: 0x%lx@0x%lx\n", size, loc);
initrd_start = loc;
initrd_end = (loc + size + PAGE_SIZE - 1) & PAGE_MASK;
}
} else {
if ((strlen(argv[i]) + cmdline_idx + 1) > COMMAND_LINE_SIZE) {
printk("Command line too long. Cut these:\n");
for (; i < argc; i++) {
printk(" %s\n", argv[i]);
}
} else {
strcpy(arcs_cmdline + cmdline_idx, argv[i]);
}
}
}
#endif
#endif
prom_meminit();
return 0;
}
/* Not sure what I'm supposed to do here. Nothing, I think */
void prom_free_prom_memory(void)
{
}
static void setled(unsigned int index, char c)
{
volatile unsigned char *led_ptr = (unsigned char *)(IO_SPACE_BASE | LED_BASE_ADDR);
if (index < 4) {
led_ptr[(3-index)<<3] = c;
}
}
void setleds(char *str)
{
int i;
for (i = 0; i < 4; i++) {
if (!str[i]) {
for (; i < 4; i++) {
setled(' ', str[i]);
}
} else {
setled(i, str[i]);
}
}
}
#include <linux/timer.h>
static struct timer_list led_timer;
/*
#ifdef CONFIG_SMP
static unsigned char led_msg[] = "CSWARM...now in glorious SMP! ";
#else
static unsigned char led_msg[] = "CSWARM Lives!!! ";
#endif
*/
static unsigned char default_led_msg[] = "Today: the CSWARM. Tomorrow: the WORLD!!!! ";
static unsigned char *led_msg = default_led_msg;
static unsigned char *led_msg_ptr = default_led_msg;
void set_led_msg(char *new_msg)
{
led_msg = new_msg;
led_msg_ptr = new_msg;
setleds(" ");
}
static void move_leds(unsigned long arg)
{
int i;
unsigned char *tmp = led_msg_ptr;
for (i = 0; i < 4; i++) {
setled(i, *tmp);
tmp++;
if (!*tmp) {
tmp = led_msg;
}
}
led_msg_ptr++;
if (!*led_msg_ptr) {
led_msg_ptr = led_msg;
}
del_timer(&led_timer);
led_timer.expires = jiffies + (HZ/8);
add_timer(&led_timer);
}
void hack_leds(void)
{
init_timer(&led_timer);
led_timer.expires = jiffies + (HZ/8);
led_timer.data = 0;
led_timer.function = move_leds;
add_timer(&led_timer);
}
--- NEW FILE: smp.c ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/mipsregs.h>
#include "cfe_xiocb.h"
#include "cfe_api.h"
extern void asmlinkage smp_bootstrap(void);
/* Boot all other cpus in the system, initialize them, and
bring them into the boot fn */
int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
{
int retval;
if ((retval = cfe_start_cpu(1, &smp_bootstrap, sp, gp, 0)) != 0) {
printk("cfe_start_cpu returned %i\n" , retval);
panic ("secondary bootstrap failed\n");
}
return 1;
}
void prom_init_secondary(void)
{
/* Set up kseg0 to be cachable coherent */
clear_cp0_config(CONF_CM_CMASK);
set_cp0_config(0x5);
/* Enable interrupts for lines 0-4 */
clear_cp0_status(0xe000);
set_cp0_status(0x1f01);
}
/*
* Set up state, return the total number of cpus in the system, including
* the master
*/
int prom_setup_smp(void)
{
/* Nothing to do here */
return 2;
}
void prom_smp_finish(void)
{
sb1250_smp_finish();
}
--- NEW FILE: time.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Time routines for the swarm board. We pass all the hard stuff
* through to the sb1250 handling code. Only thing we really keep
* track of here is what time of day we think it is. And we don't
* really even do a good job of that...
*/
#include <linux/init.h>
#include <linux/time.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <asm/system.h>
#include <asm/addrspace.h>
#include <asm/sibyte/64bit.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_smbus.h>
static unsigned long long sec_bias = 0;
static unsigned int usec_bias = 0;
extern rwlock_t xtime_lock;
/* Xicor 1241 definitions */
/*
* Register bits
*/
#define X1241REG_SR_BAT 0x80 /* currently on battery power */
#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */
#define X1241REG_SR_RTCF 0x01 /* clock failed */
#define X1241REG_BL_BP2 0x80 /* block protect 2 */
#define X1241REG_BL_BP1 0x40 /* block protect 1 */
#define X1241REG_BL_BP0 0x20 /* block protect 0 */
#define X1241REG_BL_WD1 0x10
#define X1241REG_BL_WD0 0x08
#define X1241REG_HR_MIL 0x80 /* military time format */
/*
* Register numbers
*/
#define X1241REG_BL 0x10 /* block protect bits */
#define X1241REG_INT 0x11 /* */
#define X1241REG_SC 0x30 /* Seconds */
#define X1241REG_MN 0x31 /* Minutes */
#define X1241REG_HR 0x32 /* Hours */
#define X1241REG_DT 0x33 /* Day of month */
#define X1241REG_MO 0x34 /* Month */
#define X1241REG_YR 0x35 /* Year */
#define X1241REG_DW 0x36 /* Day of Week */
#define X1241REG_Y2K 0x37 /* Year 2K */
#define X1241REG_SR 0x3F /* Status register */
#define X1241_CCR_ADDRESS 0x6F
#define SMB_CSR(reg) (KSEG1 | A_SMB_REGISTER(1, reg))
static int xicor_read(uint8_t addr)
{
while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
out64((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
out64((addr & 0xff), SMB_CSR(R_SMB_DATA));
out64((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), SMB_CSR(R_SMB_START));
while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
out64((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), SMB_CSR(R_SMB_START));
while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
out64(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
}
return (in64(SMB_CSR(R_SMB_DATA)) & 0xff);
}
static int xicor_write(uint8_t addr, int b)
{
while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
out64(addr, SMB_CSR(R_SMB_CMD));
out64((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
out64(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
SMB_CSR(R_SMB_START));
while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
;
if (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
/* Clear error bit by writing a 1 */
out64(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
return -1;
} else {
return 0;
}
}
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
/*
* In order to set the CMOS clock precisely, set_rtc_mmss has to be
* called 500 ms after the second nowtime has started, because when
* nowtime is written into the registers of the CMOS clock, it will
* jump to the next second precisely 500 ms later. Check the Motorola
* MC146818A or Dallas DS12887 data sheet for details.
*
* BUG: This routine does not handle hour overflow properly; it just
* sets the minutes. Usually you'll only notice that after reboot!
*/
int set_rtc_mmss(unsigned long nowtime)
{
int retval = 0;
int real_seconds, real_minutes, cmos_minutes;
cmos_minutes = xicor_read(X1241REG_MN);
BCD_TO_BIN(cmos_minutes);
/*
* since we're only adjusting minutes and seconds,
* don't interfere with hour overflow. This avoids
* messing with unknown time zones but requires your
* RTC not to be off by more than 15 minutes
*/
real_seconds = nowtime % 60;
real_minutes = nowtime / 60;
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
real_minutes += 30; /* correct for half hour time zone */
real_minutes %= 60;
/* unlock writes to the CCR */
xicor_write(X1241REG_SR, X1241REG_SR_WEL);
xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
if (abs(real_minutes - cmos_minutes) < 30) {
BIN_TO_BCD(real_seconds);
BIN_TO_BCD(real_minutes);
xicor_write(X1241REG_SC, real_seconds);
xicor_write(X1241REG_MN, real_minutes);
} else {
printk(KERN_WARNING
"set_rtc_mmss: can't update from %d to %d\n",
cmos_minutes, real_minutes);
retval = -1;
}
xicor_write(X1241REG_SR, 0);
printk("set_rtc_mmss: %02d:%02d\n", real_minutes, real_seconds);
return retval;
}
static unsigned long __init get_swarm_time(void)
{
unsigned int year, mon, day, hour, min, sec, y2k;
sec = xicor_read(X1241REG_SC);
min = xicor_read(X1241REG_MN);
hour = xicor_read(X1241REG_HR);
if (hour & X1241REG_HR_MIL) {
hour &= 0x3f;
} else {
if (hour & 0x20)
hour = (hour & 0xf) + 0x12;
}
BCD_TO_BIN(sec);
BCD_TO_BIN(min);
BCD_TO_BIN(hour);
day = xicor_read(X1241REG_DT);
mon = xicor_read(X1241REG_MO);
year = xicor_read(X1241REG_YR);
y2k = xicor_read(X1241REG_Y2K);
BCD_TO_BIN(day);
BCD_TO_BIN(mon);
BCD_TO_BIN(year);
BCD_TO_BIN(y2k);
year += (y2k * 100);
return mktime(year, mon, day, hour, min, sec);
}
/*
* Bring up the timer at 100 Hz.
*/
void __init time_init(void)
{
unsigned int flags;
int status;
/* Set up the scd general purpose timer 0 to cpu 0 */
sb1250_time_init();
/* Establish communication with the Xicor 1241 RTC */
/* XXXKW how do I share the SMBus with the I2C subsystem? */
out64(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
out64(0, SMB_CSR(R_SMB_CONTROL));
if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) {
printk("x1241: couldn't detect on SWARM SMBus 1\n");
} else {
if (status & X1241REG_SR_RTCF)
printk("x1241: battery failed -- time is probably wrong\n");
write_lock_irqsave (&xtime_lock, flags);
xtime.tv_sec = get_swarm_time();
xtime.tv_usec = 0;
write_unlock_irqrestore(&xtime_lock, flags);
}
}
void do_settimeofday(struct timeval *tv)
{
unsigned long saved_jiffies;
unsigned long flags;
saved_jiffies = jiffies;
write_lock_irqsave(&xtime_lock, flags);
sec_bias = (saved_jiffies/HZ) - tv->tv_sec;
usec_bias = ((saved_jiffies%HZ)*(1000000/HZ)) - tv->tv_usec;
write_unlock_irqrestore(&xtime_lock, flags);
}
void do_gettimeofday(struct timeval *tv)
{
unsigned long saved_jiffies;
unsigned long flags;
saved_jiffies = jiffies;
read_lock_irqsave(&xtime_lock, flags);
tv->tv_sec = sec_bias + (saved_jiffies/HZ);
tv->tv_usec = usec_bias + ((saved_jiffies%HZ) * (1000000/HZ));
read_unlock_irqrestore(&xtime_lock, flags);
}
|
|
From: James S. <jsi...@us...> - 2001-11-08 17:42:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250
In directory usw-pr-cvs1:/tmp/cvs-serv7520/sibyte/sb1250
Added Files:
Makefile bcm1250_tbprof.c bcm1250_tbprof.h irq.c irq_handler.S
lib_hssubr.S lib_hssubr.h pci.c setup.c smp.c time.c
Log Message:
Cleanup Makefile crap and add support for Sibyte SB1250 / SWARM.
--- NEW FILE: Makefile ---
#all: sb1250.a
O_TARGET := sb1250.o
obj-y := setup.o irq.o irq_handler.o time.o pci.o lib_hssubr.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_BCM1250_TBPROF) += bcm1250_tbprof.o
include $(TOPDIR)/Rules.make
--- NEW FILE: bcm1250_tbprof.c ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#define SBPROF_TB_DEBUG 0
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/devfs_fs_kernel.h>
#include <asm/uaccess.h>
#include <asm/smplock.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sbmips.h>
#include <asm/sibyte/64bit.h>
#include "bcm1250_tbprof.h"
#define DEVNAME "sb1250_tbprof"
static struct sbprof_tb *sbp;
/************************************************************************
* Support for ZBbus sampling using the trace buffer
*
* We use the SCD performance counter interrupt, caused by a Zclk counter
* overflow, to trigger the start of tracing.
*
* We set the trace buffer to sample everything and freeze on
* overflow.
*
* We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
*
************************************************************************/
/* Once per second on a 500 Mhz 1250 */
#define TB_PERIOD 250000000ULL
static void arm_tb(void)
{
unsigned long long next = (1ULL << 40) - TB_PERIOD;
/* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
trigger start of trace. XXX vary sampling period */
out64(0, KSEG1 + A_SCD_PERF_CNT_1);
out64(in64(KSEG1 + A_SCD_PERF_CNT_CFG) | // keep counters 0,2,3 as is
M_SPC_CFG_ENABLE | // enable counting
V_SPC_CFG_SRC1(1), // counter 1 counts cycles
KSEG1 + A_SCD_PERF_CNT_CFG);
out64(next, KSEG1 + A_SCD_PERF_CNT_1);
/* Reset the trace buffer */
out64(M_SCD_TRACE_CFG_RESET, KSEG1 + A_SCD_TRACE_CFG);
out64(M_SCD_TRACE_CFG_FREEZE_FULL, KSEG1 + A_SCD_TRACE_CFG);
sbp->tb_armed = 1;
}
static void sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
{
int i;
DBG(printk(DEVNAME ": tb_intr\n"));
if (sbp->next_tb_sample < MAX_TB_SAMPLES) {
/* XXX should use XKPHYS to make writes bypass L2 */
unsigned long long *p = sbp->sbprof_tbbuf[sbp->next_tb_sample++];
/* Read out trace */
out64(M_SCD_TRACE_CFG_START_READ, KSEG1 + A_SCD_TRACE_CFG);
__asm__ __volatile__ ("sync" : : : "memory");
/* Loop runs backwards because bundles are read out in reverse order */
for (i = 256 * 6; i > 0; i -= 6) {
// Subscripts decrease to put bundle in the order
// t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
p[i-1] = in64(KSEG1 + A_SCD_TRACE_READ); // read t2 hi
p[i-2] = in64(KSEG1 + A_SCD_TRACE_READ); // read t2 lo
p[i-3] = in64(KSEG1 + A_SCD_TRACE_READ); // read t1 hi
p[i-4] = in64(KSEG1 + A_SCD_TRACE_READ); // read t1 lo
p[i-5] = in64(KSEG1 + A_SCD_TRACE_READ); // read t0 hi
p[i-6] = in64(KSEG1 + A_SCD_TRACE_READ); // read t0 lo
}
if (!sbp->tb_enable) {
DBG(printk(DEVNAME ": tb_intr shutdown\n"));
out64(M_SCD_TRACE_CFG_RESET, KSEG1 + A_SCD_TRACE_CFG);
sbp->tb_armed = 0;
wake_up(&sbp->tb_sync);
} else {
arm_tb(); // knock down current interrupt and get another one later
}
} else {
/* No more trace buffer samples */
DBG(printk(DEVNAME ": tb_intr full\n"));
out64(M_SCD_TRACE_CFG_RESET, KSEG1 + A_SCD_TRACE_CFG);
sbp->tb_armed = 0;
if (!sbp->tb_enable) {
wake_up(&sbp->tb_sync);
}
}
}
static void sbprof_pc_intr(int irq, void *dev_id, struct pt_regs *regs)
{
panic(DEVNAME ": pc_intr");
}
static int sbprof_zbprof_start(struct file *filp)
{
if (sbp->tb_enable)
return -EBUSY;
DBG(printk(DEVNAME ": starting\n"));
sbp->tb_enable = 1;
sbp->next_tb_sample = 0;
filp->f_pos = 0;
if (request_irq
(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, "sbprof_tb trace freeze", sbp)) {
return -EBUSY;
}
if (request_irq
(K_INT_PERF_CNT, sbprof_pc_intr, 0, "sbprof_tb scd perfcnt", sbp)) {
free_irq(K_INT_TRACE_FREEZE, sbp);
return -EBUSY;
}
/* I need the core to mask these, but the interrupt mapper to
pass them through. I am exploiting my knowledge that
cp0_status masks out IP[5]. krw */
out64(K_INT_MAP_I3,
KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (K_INT_PERF_CNT<<3));
/* Initialize address traps */
out64(0, KSEG1 + A_ADDR_TRAP_UP_0);
out64(0, KSEG1 + A_ADDR_TRAP_UP_1);
out64(0, KSEG1 + A_ADDR_TRAP_UP_2);
out64(0, KSEG1 + A_ADDR_TRAP_UP_3);
out64(0, KSEG1 + A_ADDR_TRAP_DOWN_0);
out64(0, KSEG1 + A_ADDR_TRAP_DOWN_1);
out64(0, KSEG1 + A_ADDR_TRAP_DOWN_2);
out64(0, KSEG1 + A_ADDR_TRAP_DOWN_3);
out64(0, KSEG1 + A_ADDR_TRAP_CFG_0);
out64(0, KSEG1 + A_ADDR_TRAP_CFG_1);
out64(0, KSEG1 + A_ADDR_TRAP_CFG_2);
out64(0, KSEG1 + A_ADDR_TRAP_CFG_3);
/* Initialize Trace Event 0-7 */
// when interrupt
out64(M_SCD_TREVT_INTERRUPT, KSEG1 + A_SCD_TRACE_EVENT_0);
out64(0, KSEG1 + A_SCD_TRACE_EVENT_1);
out64(0, KSEG1 + A_SCD_TRACE_EVENT_2);
out64(0, KSEG1 + A_SCD_TRACE_EVENT_3);
out64(0, KSEG1 + A_SCD_TRACE_EVENT_4);
out64(0, KSEG1 + A_SCD_TRACE_EVENT_5);
out64(0, KSEG1 + A_SCD_TRACE_EVENT_6);
out64(0, KSEG1 + A_SCD_TRACE_EVENT_7);
/* Initialize Trace Sequence 0-7 */
// Start on event 0 (interrupt)
out64(V_SCD_TRSEQ_FUNC_START|0x0fff,
KSEG1 + A_SCD_TRACE_SEQUENCE_0);
// dsamp when d used | asamp when a used
out64(M_SCD_TRSEQ_ASAMPLE|M_SCD_TRSEQ_DSAMPLE|K_SCD_TRSEQ_TRIGGER_ALL,
KSEG1 + A_SCD_TRACE_SEQUENCE_1);
out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_2);
out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_3);
out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_4);
out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_5);
out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_6);
out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_7);
/* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
out64((1ULL << K_INT_PERF_CNT), KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE));
arm_tb();
DBG(printk(DEVNAME ": done starting\n"));
return 0;
}
static int sbprof_zbprof_stop(void)
{
DBG(printk(DEVNAME ": stopping\n"));
if (sbp->tb_enable) {
sbp->tb_enable = 0;
/* XXXKW there is a window here where the intr handler
may run, see the disable, and do the wake_up before
this sleep happens. */
if (sbp->tb_armed) {
DBG(printk(DEVNAME ": wait for disarm\n"));
interruptible_sleep_on(&sbp->tb_sync);
DBG(printk(DEVNAME ": disarm complete\n"));
}
free_irq(K_INT_TRACE_FREEZE, sbp);
free_irq(K_INT_PERF_CNT, sbp);
}
DBG(printk(DEVNAME ": done stopping\n"));
return 0;
}
static int sbprof_tb_open(struct inode *inode, struct file *filp)
{
int minor;
minor = MINOR(inode->i_rdev);
if (minor != 0) {
return -ENODEV;
}
if (sbp != NULL) {
return -EBUSY;
}
/* XXXKW spinlock? */
sbp = kmalloc(sizeof(struct sbprof_tb), GFP_KERNEL);
if (!sbp) {
return -ENOMEM;
}
memset(sbp, 0, sizeof(struct sbprof_tb));
sbp->sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
if (!sbp->sbprof_tbbuf) {
kfree(sbp);
sbp = NULL;
return -ENOMEM;
}
memset(sbp->sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
init_waitqueue_head(&sbp->tb_sync);
return 0;
}
static int sbprof_tb_release(struct inode *inode, struct file *filp)
{
int minor;
minor = MINOR(inode->i_rdev);
if (minor != 0 || sbp == NULL) {
return -ENODEV;
}
if (sbp->tb_armed || sbp->tb_enable) {
sbprof_zbprof_stop();
}
vfree(sbp->sbprof_tbbuf);
kfree(sbp);
sbp = NULL;
return 0;
}
static ssize_t sbprof_tb_read(struct file *filp, char *buf,
size_t size, loff_t *offp)
{
int cur_sample, sample_off, cur_count, sample_left;
char *src;
int count = 0;
char *dest = buf;
long cur_off = *offp;
count = 0;
cur_sample = cur_off / TB_SAMPLE_SIZE;
sample_off = cur_off % TB_SAMPLE_SIZE;
sample_left = TB_SAMPLE_SIZE - sample_off;
while (size && (cur_sample < sbp->next_tb_sample)) {
cur_count = size < sample_left ? size : sample_left;
src = (char *)(((long)sbp->sbprof_tbbuf[cur_sample])+sample_off);
copy_to_user(dest, src, cur_count);
DBG(printk(DEVNAME ": read from sample %d, %d bytes\n", cur_sample, cur_count));
size -= cur_count;
sample_left -= cur_count;
if (!sample_left) {
cur_sample++;
sample_off = 0;
sample_left = TB_SAMPLE_SIZE;
} else {
sample_off += cur_count;
}
cur_off += cur_count;
dest += cur_count;
count += cur_count;
}
*offp = cur_off;
return count;
}
#define SBPROF_ZBSTART _IOW('s', 0, int)
#define SBPROF_ZBSTOP _IOW('s', 1, int)
#define SBPROF_ZBFULL _IOW('s', 2, int)
static int sbprof_tb_ioctl(struct inode *inode,
struct file *filp,
unsigned int command,
unsigned long arg)
{
int error = 0;
int full;
switch (command) {
case SBPROF_ZBSTART:
error = sbprof_zbprof_start(filp);
break;
case SBPROF_ZBSTOP:
error = sbprof_zbprof_stop();
break;
case SBPROF_ZBFULL:
full = (sbp->next_tb_sample == MAX_TB_SAMPLES);
return put_user(full, (int *) arg);
default:
error = -EINVAL;
break;
}
return error;
}
static struct file_operations sbprof_tb_fops = {
owner: THIS_MODULE,
open: sbprof_tb_open,
release: sbprof_tb_release,
read: sbprof_tb_read,
ioctl: sbprof_tb_ioctl,
mmap: NULL,
};
static devfs_handle_t devfs_handle;
static int __init sbprof_tb_init(void)
{
if (devfs_register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
SBPROF_TB_MAJOR);
return -EIO;
}
devfs_handle = devfs_register(NULL, DEVNAME,
DEVFS_FL_DEFAULT, SBPROF_TB_MAJOR, 0,
S_IFCHR | S_IRUGO | S_IWUGO,
&sbprof_tb_fops, NULL);
sbp = NULL;
printk(KERN_INFO DEVNAME ": initialized\n");
return 0;
}
static void __exit sbprof_tb_cleanup(void)
{
devfs_unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
devfs_unregister(devfs_handle);
}
module_init(sbprof_tb_init);
module_exit(sbprof_tb_cleanup);
--- NEW FILE: bcm1250_tbprof.h ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef BCM1250_TBPROF_H
#if SBPROF_TB_DEBUG
#define DBG(a) a
#else
#define DBG(a)
#endif
#define SBPROF_TB_MAJOR 240
typedef u_int64_t tb_sample_t[6*256];
struct sbprof_tb {
tb_sample_t *sbprof_tbbuf;
int next_tb_sample;
volatile int tb_enable;
volatile int tb_armed;
wait_queue_head_t tb_sync;
};
#define MAX_SAMPLE_BYTES (24*1024*1024)
#define MAX_TBSAMPLE_BYTES (12*1024*1024)
#define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
#define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
#define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
/***************************************************************************
* Routines for gathering ZBbus profiles using trace buffer
***************************************************************************/
/* Requires: Already called zclk_timer_init with a value that won't
saturate 40 bits. No subsequent use of SCD performance counters
or trace buffer.
Effect: Starts gathering random ZBbus profiles using trace buffer. */
static int sbprof_zbprof_start(struct file *filp);
/* Effect: Stops collection of ZBbus profiles */
static int sbprof_zbprof_stop(void);
/***************************************************************************
* Routines for using 40-bit SCD cycle counter
*
* Client responsible for either handling interrupts or making sure
* the cycles counter never saturates, e.g., by doing
* zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
***************************************************************************/
/* Configures SCD counter 0 to count ZCLKs starting from val;
Configures SCD counters1,2,3 to count nothing.
Must not be called while gathering ZBbus profiles.
unsigned long long val; */
#define zclk_timer_init(val) \
__asm__ __volatile__ (".set push;" \
".set mips64;" \
"la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
"sd %0, 0x10($8);" /* write val to counter0 */ \
"sd %1, 0($8);" /* config counter0 for zclks*/ \
".set pop" \
: /* no outputs */ \
/* enable, counter0 */ \
: /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
: /* modifies */ "$8" )
/* Reads SCD counter 0 and puts result in value
unsigned long long val; */
#define zclk_get(val) \
__asm__ __volatile__ (".set push;" \
".set mips64;" \
"la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
"ld %0, 0x10($8);" /* write val to counter0 */ \
".set pop" \
: /* outputs */ "=r"(val) \
: /* inputs */ \
: /* modifies */ "$8" )
#endif
--- NEW FILE: irq.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/irq.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/irq_cpustat.h>
#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/64bit.h>
/* Sanity check. We're an sb1250, with 2 SB1 cores on die; we'd better have configured for
an sb1 cpu */
#ifndef CONFIG_CPU_SB1
#error "SB1250 requires configuration of SB1 cpu"
#endif
/*
* These are the routines that handle all the low level interrupt stuff.
* Actions handled here are: initialization of the interrupt map,
* requesting of interrupt lines by handlers, dispatching if interrupts
* to handlers, probing for interrupt lines
*/
#define shutdown_sb1250_irq disable_sb1250_irq
static void end_sb1250_irq(unsigned int irq);
static void enable_sb1250_irq(unsigned int irq);
static void disable_sb1250_irq(unsigned int irq);
static unsigned int startup_sb1250_irq(unsigned int irq);
static void ack_sb1250_irq(unsigned int irq);
#ifdef CONFIG_REMOTE_DEBUG
extern void breakpoint(void);
#endif
#define NR_IRQS 64
static struct hw_interrupt_type sb1250_irq_type = {
"SB1250-IMR",
startup_sb1250_irq,
shutdown_sb1250_irq,
enable_sb1250_irq,
disable_sb1250_irq,
ack_sb1250_irq,
end_sb1250_irq,
NULL
};
spinlock_t global_irq_lock = SPIN_LOCK_UNLOCKED;
spinlock_t sb1250_imr_lock = SPIN_LOCK_UNLOCKED;
void sb1250_mask_irq(int cpu, int irq)
{
unsigned long flags;
u64 cur_ints;
spin_lock_irqsave(&sb1250_imr_lock, flags);
cur_ints = in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
cur_ints |= (((u64) 1) << irq);
out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}
void sb1250_unmask_irq(int cpu, int irq)
{
unsigned long flags;
u64 cur_ints;
spin_lock_irqsave(&sb1250_imr_lock, flags);
cur_ints = in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
cur_ints &= ~(((u64) 1) << irq);
out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}
/* Defined in arch/mips/sibyte/sb1250/irq_handler.S */
extern void sb1250_irq_handler(void);
/* ********************************************************************************************* */
static unsigned int startup_sb1250_irq(unsigned int irq)
{
sb1250_unmask_irq(0, irq);
return 0; /* never anything pending */
}
static void disable_sb1250_irq(unsigned int irq)
{
sb1250_mask_irq(0, irq);
}
static void enable_sb1250_irq(unsigned int irq)
{
sb1250_unmask_irq(0, irq);
}
static void ack_sb1250_irq(unsigned int irq)
{
sb1250_mask_irq(0, irq);
}
static void end_sb1250_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
sb1250_unmask_irq(0, irq);
}
}
void __init init_sb1250_irqs(void)
{
int i;
for (i = 0; i < NR_IRQS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &sb1250_irq_type;
}
}
/*
* init_IRQ is called early in the boot sequence from init/main.c. It
* is responsible for setting up the interrupt mapper and installing the
* handler that will be responsible for dispatching interrupts to the
* "right" place.
*/
/*
* For now, map all interrupts to IP[2]. We could save
* some cycles by parceling out system interrupts to different
* IP lines, but keep it simple for bringup. We'll also direct
* all interrupts to a single CPU; we should probably route
* PCI and LDT to one cpu and everything else to the other
* to balance the load a bit.
*
* On the second cpu, everything is set to IP5, which is
* ignored, EXCEPT the mailbox interrupt. That one is
* set to IP[2] so it is handled. This is needed so we
* can do cross-cpu function calls, as requred by SMP
*/
#define IMR_IP2_VAL K_INT_MAP_I0
#define IMR_IP3_VAL K_INT_MAP_I1
#define IMR_IP4_VAL K_INT_MAP_I2
void __init init_IRQ(void)
{
unsigned int i;
u64 tmp;
/* Default everything to IP2 */
for (i = 0; i < NR_IRQS; i++) { /* was I0 */
out64(IMR_IP2_VAL,
KSEG1 + A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3));
out64(IMR_IP2_VAL,
KSEG1 + A_IMR_REGISTER(1,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3));
}
init_sb1250_irqs();
/* Map the high 16 bits of the mailbox registers to IP[3], for inter-cpu messages */
/* Was I1 */
out64(IMR_IP3_VAL,
KSEG1 + A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3));
out64(IMR_IP3_VAL,
KSEG1 + A_IMR_REGISTER(1,
R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3));
/* Clear the mailboxes. The firmware may leave them dirty */
out64(0xffffffffffffffff,
KSEG1 + A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU));
out64(0xffffffffffffffff,
KSEG1 + A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU));
/* Mask everything except the mailbox registers for both cpus */
tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
out64(tmp, KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK));
out64(tmp, KSEG1 + A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK));
/* Note that the timer interrupts are also mapped, but this is
done in sb1250_time_init() */
#ifdef CONFIG_SIBYTE_SB1250_PROF
/* Enable IP[7,4:0], disable the rest */
clear_cp0_status(0x6000);
set_cp0_status(0x9f00);
#else
/* Enable IP[4:0], disable the rest */
clear_cp0_status(0xe000);
set_cp0_status(0x1f00);
#endif
set_except_vector(0, sb1250_irq_handler);
#ifdef CONFIG_REMOTE_DEBUG
/* If local serial I/O used for debug port, enter kgdb at once */
// puts("Waiting for kgdb to connect...");
set_debug_traps();
breakpoint();
#endif
}
--- NEW FILE: irq_handler.S ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* sb1250_handle_int() is the routine that is actually called when an interrupt
* occurs. It is installed as the exception vector handler in init_IRQ()
* in arch/mips/sibyte/sb1250/irq.c
*
* In the handle we figure out which interrupts need handling, and use that to call
* the dispatcher, which will take care of actually calling registered handlers
*
* Note that we take care of all raised interrupts in one go at the handler. This
* is more BSDish than the Indy code, and also, IMHO, more sane.
*/
#include <asm/addrspace.h>
#include <asm/processor.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/sibyte/sb1250_defs.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include "asm/sibyte/sbmips.h"
/*
* What a pain. We have to be really careful saving
* the upper 32 bits of any register across function
* calls if we don't want them trashed--since were
* running in -o32, the calling routing never saves
* the full 64 bits of a register across a function
* call. Being the interrupt handler, we're guaranteed
* that interrupts are disabled during this code so we
* don't have to worry about random interrupts blasting
* the high 32 bits.
*/
.text
.set push
.set noreorder
.set noat
.set mips64
.align 5
NESTED(sb1250_irq_handler, PT_SIZE, sp)
SAVE_ALL
/* Indicate kernel mode (set CU0, clear KSU,ERL,EXL, leave IE off) */
CLI
li s1, 0xb00a0020
lw t1, 0(s1)
#ifdef CONFIG_SIBYTE_SB1250_PROF
/* Set compare to count to silence count/compare timer interrupts */
mfc0 t1, C0_COUNT
mtc0 t1, C0_COMPARE /* pause to clear IP[7] bit of cause ? */
#endif
/* Read cause */
mfc0 s0, C0_CAUSE
#ifdef CONFIG_SIBYTE_SB1250_PROF
/* Cpu performance counter interrupt is routed to IP[7] */
andi t1, s0, CAUSEF_IP7
beqz t1, 0f
srl t1, s0, (CAUSEB_BD-2) /* Shift BD bit to bit 2 */
and t1, t1, 0x4 /* mask to get just BD bit */
mfc0 a0, C0_EPC
jal sbprof_cpu_intr
addu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
j ret_from_irq
nop # delay slot
0:
#endif
/* Timer interrupt is routed to IP[4] */
andi t1, s0, CAUSEF_IP4
beqz t1, 1f
nop
jal sb1250_timer_interrupt
move a0, sp /* Pass the registers along */
lw t1, 4(s1)
j ret_from_irq
nop # delay slot
1:
lw t1, 8(s1)
#ifdef CONFIG_SMP
/* Mailbox interrupt is routed to IP[3] */
andi t1, s0, CAUSEF_IP3
beqz t1, 2f
nop
jal sb1250_mailbox_interrupt
move a0, sp
lw t1, 12(s1)
j ret_from_irq
nop # delay slot
2:
lw t1, 16(s1)
#endif
and t1, s0, CAUSEF_IP2
beqz t1, 4f
nop
/* Default...we've hit an IP[2] interrupt, which means we've got to check the
1250 interrupt registers to figure out what to do */
la v0, KSEG1 + A_IMR_CPU0_BASE
ld s1, R_IMR_INTERRUPT_MASK(v0)
ld s0, R_IMR_INTERRUPT_SOURCE_STATUS(v0)
ld t0, R_IMR_LDT_INTERRUPT(v0)
nor s1, s1, zero /* Negate mask to turn it into an and mask */
or s0, s0, t0 /* Merge pending system and LDT IRQS */
and s0, s0, s1 /* Now s0 has a bitfield of unmasked pending IRQs */
/*
* Don't let timer interrupts or mailbox interrupts get dispatched
* through this mechanism - they get handled specially above
*/
#ifdef CONFIG_SMP
li t0, (_SB_MAKEMASK1(K_INT_TIMER_0) | _SB_MAKEMASK1(K_INT_TIMER_1) \
| _SB_MAKEMASK1(K_INT_MBOX_0)) /* remove timer bits from mask */
#else
li t0, _SB_MAKEMASK1(K_INT_TIMER_0) /* remove timer bits from mask */
#endif
not t0
and s0, s0, t0 /* timer interrupts don't count here */
/* Now the timer and mailbox interrupts have been removed from the pending mask */
and t0, t0, s1 /* LDT interrupts we will service */
beqz s0, 4f /* No interrupts. Return */
daddiu a1, sp, 0 /* registers get passed along as the second argument */
sd t0, R_IMR_LDT_INTERRUPT_CLR(v0) /* Clear what we'll service */
3: dclz s1, s0 /* Find the next interrupt */
dsubu a0, zero, s1
daddiu a0, a0, 63
jal do_IRQ
nop
4:
j ret_from_irq /* defined in arch/mips/kernel/entry.S */
nop
.set pop
END(sb1250_irq_handler)
--- NEW FILE: lib_hssubr.S ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "asm/sibyte/sb1250_defs.h"
#include "asm/sibyte/sbmips.h"
.set mips64
#define HAZARD ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop
/* *********************************************************************
* hs_read8 - read 8-bit bytes
********************************************************************* */
LEAF(hs_read8)
mfc0 t2,C0_SR
or t1,t2,M_SR_KX
mtc0 t1,C0_SR
HAZARD
dli v0,PHYS_TO_XKSEG_UNCACHED(0)
dsll a0,a0,32
dsrl a0,a0,32
or a0,a0,v0
lb v0,(a0)
and v0,0xFF
mtc0 t2,C0_SR
HAZARD
j ra
END(hs_read8)
/* *********************************************************************
* hs_read16 - read 16-bit shorts
********************************************************************* */
LEAF(hs_read16)
mfc0 t2,C0_SR
or t1,t2,M_SR_KX
mtc0 t1,C0_SR
HAZARD
dli v0,PHYS_TO_XKSEG_UNCACHED(0)
dsll a0,a0,32
dsrl a0,a0,32
or a0,a0,v0
lh v0,(a0)
and v0,0xFFFF
mtc0 t2,C0_SR
HAZARD
j ra
END(hs_read16)
/* *********************************************************************
* hs_read32 - read 32-bit ints
********************************************************************* */
LEAF(hs_read32)
mfc0 t2,C0_SR
or t1,t2,M_SR_KX
mtc0 t1,C0_SR
HAZARD
dli v0,PHYS_TO_XKSEG_UNCACHED(0)
dsll a0,a0,32
dsrl a0,a0,32
or a0,a0,v0
lw v0,(a0)
and v0,0xFFFFFFFF
mtc0 t2,C0_SR
HAZARD
j ra
END(hs_read32)
/* *********************************************************************
* hs_read64 - read 64-bit longs
********************************************************************* */
LEAF(hs_read64)
mfc0 t2,C0_SR
or t1,t2,M_SR_KX
mtc0 t1,C0_SR
HAZARD
dli v0,PHYS_TO_XKSEG_UNCACHED(0)
dsll a0,a0,32
dsrl a0,a0,32
or a0,a0,v0
ld v0,(a0)
mtc0 t2,C0_SR
HAZARD
j ra
END(hs_read64)
/* *********************************************************************
* hs_write8 - write 8-bit bytes
********************************************************************* */
LEAF(hs_write8)
mfc0 t2,C0_SR
or t1,t2,M_SR_KX
mtc0 t1,C0_SR
HAZARD
dli v0,PHYS_TO_XKSEG_UNCACHED(0)
dsll a0,a0,32
dsrl a0,a0,32
or a0,a0,v0
sb a1,(a0)
mtc0 t2,C0_SR
HAZARD
j ra
END(hs_write8)
/* *********************************************************************
* hs_write16 - write 16-bit shorts
********************************************************************* */
LEAF(hs_write16)
mfc0 t2,C0_SR
or t1,t2,M_SR_KX
mtc0 t1,C0_SR
HAZARD
dli v0,PHYS_TO_XKSEG_UNCACHED(0)
dsll a0,a0,32
dsrl a0,a0,32
or a0,a0,v0
sh a1,(a0)
mtc0 t2,C0_SR
HAZARD
j ra
END(hs_write16)
/* *********************************************************************
* hs_write32 - write 32-bit longs
********************************************************************* */
LEAF(hs_write32)
mfc0 t2,C0_SR
or t1,t2,M_SR_KX
mtc0 t1,C0_SR
HAZARD
dli v0,PHYS_TO_XKSEG_UNCACHED(0)
dsll a0,a0,32
dsrl a0,a0,32
or a0,a0,v0
sw a1,(a0)
mtc0 t2,C0_SR
HAZARD
j ra
END(hs_write32)
/* *********************************************************************
* hs_write64 - write 64-bit longs
********************************************************************* */
LEAF(hs_write64)
mfc0 t2,C0_SR
or t1,t2,M_SR_KX
mtc0 t1,C0_SR
HAZARD
dli v0,PHYS_TO_XKSEG_UNCACHED(0)
dsll a0,a0,32
dsrl a0,a0,32
or a0,a0,v0
sd a1,(a0)
mtc0 t2,C0_SR
HAZARD
j ra
END(hs_write64)
/* *********************************************************************
* End
********************************************************************* */
--- NEW FILE: lib_hssubr.h ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _LIB_HSSUBR_H
#define _LIB_HSSUBR_H
/*
* If __long64 we can do this via macros. Otherwise, call
* the magic functions.
*/
#if __long64
typedef long hsaddr_t;
#define hs_write8(a,b) *((volatile uint8_t *) (a)) = (b)
#define hs_write16(a,b) *((volatile uint16_t *) (a)) = (b)
#define hs_write32(a,b) *((volatile uint32_t *) (a)) = (b)
#define hs_write64(a,b) *((volatile uint32_t *) (a)) = (b)
#define hs_read8(a) *((volatile uint8_t *) (a))
#define hs_read16(a) *((volatile uint16_t *) (a))
#define hs_read32(a) *((volatile uint32_t *) (a))
#define hs_read64(a) *((volatile uint64_t *) (a))
#else /* not __long64 */
typedef long hsaddr_t;
extern void hs_write8(hsaddr_t a,uint8_t b);
extern void hs_write16(hsaddr_t a,uint16_t b);
extern void hs_write32(hsaddr_t a,uint32_t b);
extern void hs_write64(hsaddr_t a,uint64_t b);
extern uint8_t hs_read8(hsaddr_t a);
extern uint16_t hs_read16(hsaddr_t a);
extern uint32_t hs_read32(hsaddr_t a);
extern uint64_t hs_read64(hsaddr_t a);
#endif
#endif
--- NEW FILE: pci.c ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* SB1250-specific PCI support
*
* This module provides the glue between Linux's PCI subsystem
* and the hardware. We basically provide glue for accessing
* configuration space, and set up the translation for I/O
* space accesses.
*
* To access configuration space, we call some assembly-level
* stubs that flip the KX bit on and off in the status
* register, and do XKSEG addressed memory accesses there.
* It's slow (7 SSNOPs to guarantee that KX is set!) but
* fortunately, config space accesses are rare.
*
* We could use the ioremap functionality for the confguration
* space as well as I/O space, but I'm not sure of the
* implications of setting aside 16MB of KSEG2 for something
* that is used so rarely (how much space in the page tables?)
*
*/
#include <linux/config.h>
#ifdef CONFIG_PCI
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <asm/sibyte/sb1250_defs.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_pci.h>
#include "lib_hssubr.h"
/*
* This macro calculates the offset into config space where
* a given bus, device/function, and offset live on the sb1250
*/
#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
/*
* Using the above offset, this macro calcuates the actual
* address. Note that the physical address is not accessible
* without remapping or setting KX. We use 'match bits'
* as our endian policy to guarantee that 32-bit accesses
* look the same from either endianness.
*/
#define CFGADDR(dev,where) (A_PHYS_LDTPCI_CFG_MATCH_BITS + \
CFGOFFSET(dev->bus->number,dev->devfn,where))
/*
* Read/write 32-bit values in config space.
*/
#define READCFG32(addr) hs_read32((addr)&~3)
#define WRITECFG32(addr,data) hs_write32(((addr)&~3),(data))
/*
* This variable is the KSEG2 (kernel virtual) mapping
* of the ISA/PCI I/O space area. We map 64K here and
* the offsets from this address get treated with "match bytes"
* policy to make everything look little-endian. So,
* you need to also set CONFIG_SWAP_IO_SPACE, but this is the
* combination that works correctly with most of Linux's drivers.
*/
extern unsigned long mips_io_port_base;
#define PCI_BUS_ENABLED 1
#define LDT_BUS_ENABLED 2
static int sb1250_bus_status = 0;
#define MATCH_BITS 0x20000000 /* really belongs in an include file */
#define LDT_BRIDGE_START ((A_PCI_TYPE01_HEADER|MATCH_BITS)+0x00)
#define LDT_BRIDGE_END ((A_PCI_TYPE01_HEADER|MATCH_BITS)+0x20)
/*
* Read/write access functions for various sizes of values
* in config space.
*/
static int
sb1250_pci_read_config_byte(struct pci_dev *dev, int where, u8 * val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev, where);
data = READCFG32(cfgaddr);
/*
* If the LDT was not configured, make it look like the bridge
* header is not there.
*/
if (!(sb1250_bus_status & LDT_BUS_ENABLED) &&
(cfgaddr >= LDT_BRIDGE_START) && (cfgaddr < LDT_BRIDGE_END)) {
data = 0xFFFFFFFF;
}
*val = (data >> ((where & 3) << 3)) & 0xff;
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_read_config_word(struct pci_dev *dev, int where, u16 * val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev, where);
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
data = READCFG32(cfgaddr);
/*
* If the LDT was not configured, make it look like the bridge
* header is not there.
*/
if (!(sb1250_bus_status & LDT_BUS_ENABLED) &&
(cfgaddr >= LDT_BRIDGE_START) && (cfgaddr < LDT_BRIDGE_END)) {
data = 0xFFFFFFFF;
}
*val = (data >> ((where & 3) << 3)) & 0xffff;
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_read_config_dword(struct pci_dev *dev, int where, u32 * val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev, where);
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
data = READCFG32(cfgaddr);
/*
* If the LDT was not configured, make it look like the bridge
* header is not there.
*/
if (!(sb1250_bus_status & LDT_BUS_ENABLED) &&
(cfgaddr >= LDT_BRIDGE_START) && (cfgaddr < LDT_BRIDGE_END)) {
data = 0xFFFFFFFF;
}
*val = data;
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev, where);
data = READCFG32(cfgaddr);
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
WRITECFG32(cfgaddr, data);
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_write_config_word(struct pci_dev *dev, int where, u16 val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev, where);
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
data = READCFG32(cfgaddr);
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
WRITECFG32(cfgaddr, data);
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
{
u32 cfgaddr = CFGADDR(dev, where);
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
WRITECFG32(cfgaddr, val);
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops sb1250_pci_ops = {
sb1250_pci_read_config_byte,
sb1250_pci_read_config_word,
sb1250_pci_read_config_dword,
sb1250_pci_write_config_byte,
sb1250_pci_write_config_word,
sb1250_pci_write_config_dword
};
void __init pcibios_init(void)
{
uint32_t cmdreg;
/*
* See if the PCI bus has been configured by the firmware.
*/
cmdreg = READCFG32((A_PCI_TYPE00_HEADER | MATCH_BITS) +
R_PCI_TYPE0_CMDSTATUS);
if (!(cmdreg & M_PCI_CMD_MASTER_EN)) {
printk
("PCI: Skipping PCI probe. Bus is not initialized.\n");
return;
}
sb1250_bus_status |= PCI_BUS_ENABLED;
/*
* Establish a mapping from KSEG2 (kernel virtual) to PCI I/O space
* Use "match bytes", even though this exposes endianness.
* big-endian Linuxes will have CONFIG_SWAP_IO_SPACE set.
*/
mips_io_port_base =
(unsigned long) ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536);
/*
* Also check the LDT bridge's enable, just in case we didn't
* initialize that one.
*/
cmdreg = READCFG32((A_PCI_TYPE01_HEADER | MATCH_BITS) +
R_PCI_TYPE0_CMDSTATUS);
if (cmdreg & M_PCI_CMD_MASTER_EN) {
sb1250_bus_status |= LDT_BUS_ENABLED;
}
/* Probe for PCI hardware */
printk("PCI: Probing PCI hardware on host bus 0.\n");
pci_scan_bus(0, &sb1250_pci_ops, NULL);
}
int __init pcibios_enable_device(struct pci_dev *dev)
{
/* Not needed, since we enable all devices at startup. */
return 0;
}
void __init
pcibios_align_resource(void *data, struct resource *res,
unsigned long size)
{
}
char *__init pcibios_setup(char *str)
{
/* Nothing to do for now. */
return str;
}
struct pci_fixup pcibios_fixups[] = {
{0}
};
void __init
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
unsigned long where, size;
u32 reg;
where = PCI_BASE_ADDRESS_0 + (resource * 4);
size = res->end - res->start;
pci_read_config_dword(dev, where, ®);
reg = (reg & size) | (((u32) (res->start - root->start)) & ~size);
pci_write_config_dword(dev, where, reg);
}
/*
* Called after each bus is probed, but before its children
* are examined.
*/
void __init pcibios_fixup_bus(struct pci_bus *b)
{
pci_read_bridge_bases(b);
}
unsigned __init int pcibios_assign_all_busses(void)
{
return 1;
}
#endif /* CONFIG_PCI */
--- NEW FILE: setup.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* Setup code likely to be common to all SB1250 platforms */
#include <linux/config.h>
#include <linux/errno.h>
#include <linux/hdreg.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/string.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
#include <linux/utsname.h>
#include <linux/a.out.h>
#include <linux/tty.h>
#include <linux/bootmem.h>
#ifdef CONFIG_BLK_DEV_RAM
#include <linux/blk.h>
#endif
#include <linux/ide.h>
#ifdef CONFIG_RTC
#include <linux/timex.h>
#endif
#include <asm/asm.h>
#include <asm/bootinfo.h>
#include <asm/cachectl.h>
#include <asm/cpu.h>
#include <asm/io.h>
#include <asm/stackframe.h>
#include <asm/system.h>
#include <asm/cpu.h>
#include <asm/mmu_context.h>
#include <asm/sibyte/swarm.h>
#include <asm/sibyte/sb1250_defs.h>
#include <asm/sibyte/sb1250_regs.h>
/*
*
*/
void sb1250_setup(void)
{
}
--- NEW FILE: smp.c ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <asm/sibyte/64bit.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/addrspace.h>
#include <asm/smp.h>
#include <linux/sched.h>
/*
* These are routines for dealing with the sb1250 smp capabilities
* independent of board/firmware
*/
static u64 mailbox_set_regs[] =
{ KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU,
KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU };
static u64 mailbox_clear_regs[] =
{ KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU,
KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU };
static u64 mailbox_regs[] =
{ KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU,
KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU };
/* Simple enough; everything is set up, so just poke the appropriate mailbox
register, and we should be set */
void core_send_ipi(int cpu, unsigned int action)
{
out64((((u64)action)<< 48), mailbox_set_regs[cpu]);
}
void sb1250_smp_finish(void)
{
extern void sb1_sanitize_tlb(void);
sb1_sanitize_tlb();
sb1250_time_init();
}
static void sb1250_smp_reschedule(void)
{
current->need_resched = 1;
}
static void sb1250_smp_call_function(void)
{
void (*func) (void *info) = smp_fn_call.fn;
void *data = smp_fn_call.data;
int wait = smp_fn_call.wait;
/* Notify initiating CPU that I've grabbed the data
* and am about to execute the function */
atomic_inc(&smp_fn_call.started);
(*func)(data);
if (wait)
atomic_inc(&smp_fn_call.finished);
}
void sb1250_mailbox_interrupt(struct pt_regs *regs)
{
int cpu = smp_processor_id();
unsigned int action;
/* Load the mailbox register to figure out what we're supposed to do */
action = (in64(mailbox_regs[cpu]) >> 48) & 0xffff;
/* Clear the mailbox to clear the interrupt */
out64(((u64)action)<<48, mailbox_clear_regs[cpu]);
if (action & SMP_RESCHEDULE_YOURSELF) {
sb1250_smp_reschedule();
}
if (action & SMP_CALL_FUNCTION) {
sb1250_smp_call_function();
}
}
--- NEW FILE: time.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* These are routines to set up and handle interrupts from the
* sb1250 general purpose timer 0. We're using the timer as a
* system clock, so we set it up to run at 100 Hz. On every
* interrupt, we update our idea of what the time of day is,
* then call do_timer() in the architecture-independent kernel
* code to do general bookkeeping (e.g. update jiffies, run
* bottom halves, etc.)
*/
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <asm/irq.h>
#include <asm/ptrace.h>
#include <asm/addrspace.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/64bit.h>
void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs);
#define IMR_IP2_VAL K_INT_MAP_I0
#define IMR_IP3_VAL K_INT_MAP_I1
#define IMR_IP4_VAL K_INT_MAP_I2
void sb1250_time_init(void)
{
int cpu = smp_processor_id();
/* Only have 4 general purpose timers */
if (cpu > 3) {
BUG();
}
sb1250_mask_irq(cpu, K_INT_TIMER_0 + cpu);
/* Map the timer interrupt to ip[4] of this cpu */
out64(IMR_IP4_VAL, KSEG1 + A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE)
+ ((K_INT_TIMER_0 + cpu)<<3));
/* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
/* Disable the timer and set up the count */
out64(0, KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
out64(
#ifndef CONFIG_SIMULATION
1000000/HZ
#else
50000/HZ
#endif
, KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
/* Set the timer running */
out64(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
sb1250_unmask_irq(cpu, K_INT_TIMER_0 + cpu);
/* This interrupt is "special" in that it doesn't use the request_irq way
to hook the irq line. The timer interrupt is initialized early enough
to make this a major pain, and it's also firing enough to warrant a
bit of special case code. sb1250_timer_interrupt is called directly
from irq_handler.S when IP[4] is set during an interrupt */
}
extern int set_rtc_mmss(unsigned long nowtime);
extern rwlock_t xtime_lock;
static long last_rtc_update = 0;
void sb1250_timer_interrupt(struct pt_regs *regs)
{
int cpu = smp_processor_id();
/* Reset the timer */
out64(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
/* Need to do some stuff here with xtime, too, but that looks like
it should be architecture independent...does it really belong here? */
if (!cpu) {
do_timer(regs);
read_lock(&xtime_lock);
if ((time_status & STA_UNSYNC) == 0
&& xtime.tv_sec > last_rtc_update + 660
&& xtime.tv_usec >= 500000 - (tick >> 1)
&& xtime.tv_usec <= 500000 + (tick >> 1))
if (set_rtc_mmss(xtime.tv_sec) == 0)
last_rtc_update = xtime.tv_sec;
else
/* do it again in 60 s */
last_rtc_update = xtime.tv_sec - 600;
read_unlock(&xtime_lock);
}
#ifdef CONFIG_SMP
{
int user = user_mode(regs);
/* We need to make like a normal interrupt -- otherwise
timer interrupts ignore the global interrupt lock,
which would be a Bad Thing. */
irq_enter(cpu, 0);
update_process_times(user);
irq_exit(cpu, 0);
if (softirq_pending(cpu))
do_softirq();
}
#endif /* CONFIG_SMP */
}
|
|
From: James S. <jsi...@us...> - 2001-11-08 17:42:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/ite-boards/qed-4n-s01b In directory usw-pr-cvs1:/tmp/cvs-serv7520/ite-boards/qed-4n-s01b Modified Files: Makefile Log Message: Cleanup Makefile crap and add support for Sibyte SB1250 / SWARM. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/ite-boards/qed-4n-s01b/Makefile,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- Makefile 2001/10/05 21:25:32 1.2 +++ Makefile 2001/11/08 17:42:08 1.3 @@ -16,17 +16,10 @@ .S.o: $(CC) $(CFLAGS) -c $< -o $*.o -all: ite.o - O_TARGET := ite.o obj-y := init.o -ifdef CONFIG_PCI -obj-y += pci_fixup.o -endif - -dep: - $(CPP) -M *.c > .depend +obj-$(CONFIG_PCI) += pci_fixup.o include $(TOPDIR)/Rules.make |
|
From: James S. <jsi...@us...> - 2001-11-08 17:42:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1
In directory usw-pr-cvs1:/tmp/cvs-serv7520/sibyte/sb1
Added Files:
Makefile cache_err_handler.S
Log Message:
Cleanup Makefile crap and add support for Sibyte SB1250 / SWARM.
--- NEW FILE: Makefile ---
L_TARGET = sb1kern.a
OBJS-$(CONFIG_SB1_CACHE_ERROR) += cache_err_handler.o
include $(TOPDIR)/Rules.make
--- NEW FILE: cache_err_handler.S ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/config.h>
#include <linux/threads.h>
#include <asm/asm.h>
#include <asm/cacheops.h>
#include <asm/current.h>
#include <asm/offset.h>
#include <asm/processor.h>
#include <asm/regdef.h>
#include <asm/cachectl.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#define __ASSEMBLY__
#include <asm/bootinfo.h>
.text
/* Special Cache Error handler for SB1 for now*/
LEAF(except_vec2_sb1)
.set noat
.set mips0
/*
* This is a very bad place to be. Our cache error
* detection has triggered. If we have write-back data
* in the cache, we may not be able to recover. As a
* first-order desperate measure, turn off KSEG0 cacheing.
*/
.set push
.set mips64
.set reorder
# look for signature of spurious CErr
mfc0 k1,$26,0
lui k0,0x4000
bne k0,k1,real_cerr
mfc0 k1,$27,1
lui k0,0xffe0
and k1,k0,k1
lui k0,0x0200
bne k0,k1,real_cerr
# clear/unlock the registers
mtc0 zero,$26,0
mtc0 zero,$27,1
eret
# XXXXPK - this is a real error. set the LEDs and spin for now
real_cerr:
lui k0,0xb00A
li k1,'C'
sb k1,56(k0)
li k1,'E'
sb k1,48(k0)
li k1,'R'
sb k1,40(k0)
li k1,'R'
sb k1,32(k0)
2:
b 2b
.set pop
END(except_vec2_sb1)
|
|
From: James S. <jsi...@us...> - 2001-11-08 17:42:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/dec/prom In directory usw-pr-cvs1:/tmp/cvs-serv7520/dec/prom Added Files: Makefile Log Message: Cleanup Makefile crap and add support for Sibyte SB1250 / SWARM. --- NEW FILE: Makefile --- # # Makefile for the DECstation prom monitor library routines # under Linux. # # Note! Dependencies are done automagically by 'make dep', which also # removes any old dependencies. DON'T put your own dependencies here # unless it's something special (ie not a .c file). # # Note 2! The CFLAGS definitions are now in the main makefile... .S.s: $(CPP) $(CFLAGS) $< -o $*.s .S.o: $(CC) $(CFLAGS) -c $< -o $*.o L_TARGET = rexlib.a obj-y += init.o memory.o cmdline.o identify.o locore.o include $(TOPDIR)/Rules.make |
|
From: James S. <jsi...@us...> - 2001-11-08 17:42:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv7520/configs Modified Files: defconfig-sb1250-swarm Log Message: Cleanup Makefile crap and add support for Sibyte SB1250 / SWARM. Index: defconfig-sb1250-swarm =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-sb1250-swarm,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- defconfig-sb1250-swarm 2001/11/07 19:58:02 1.1 +++ defconfig-sb1250-swarm 2001/11/08 17:42:08 1.2 @@ -33,7 +33,6 @@ CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS=16 CONFIG_SMP=y CONFIG_EMBEDDED_RAMDISK=y -# CONFIG_SIBYTE_RAMDISK_IKOS is not set # CONFIG_SIBYTE_RAMDISK_SIMPLE_INIT is not set CONFIG_SIBYTE_RAMDISK_GENERAL=y # CONFIG_SIBYTE_RAMDISK_PROMICE_CONSOLE is not set |
|
From: James S. <jsi...@us...> - 2001-11-08 17:42:10
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv7520
Modified Files:
Makefile config.in
Log Message:
Cleanup Makefile crap and add support for Sibyte SB1250 / SWARM.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -d -r1.26 -r1.27
--- Makefile 2001/11/01 21:58:13 1.26
+++ Makefile 2001/11/08 17:42:07 1.27
@@ -94,7 +94,10 @@
endif
ifdef CONFIG_CPU_SB1
GCCFLAGS += -mcpu=sb1 -mips2 -Wa,--trap
+ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+MODFLAGS += -msb1-pass1-workarounds
endif
+endif
GCCFLAGS += -pipe
@@ -313,8 +316,34 @@
# Au1000 eval board
#
ifdef CONFIG_MIPS_PB1000
-LIBS += arch/mips/au1000/pb1000/pb1000.o arch/mips/au1000/common/au1000.o
+LIBS += arch/mips/au1000/pb1000/pb1000.o \
+ arch/mips/au1000/common/au1000.o
SUBDIRS += arch/mips/au1000/pb1000 arch/mips/au1000/common
+LOADADDR += 0x80100000
+endif
+
+#
+# Sibyte SB1250 SOC
+#
+ifdef CONFIG_SIBYTE_SB1250
+# This is a LIB so that it links at the end, and initcalls are later
+# the sequence; but it is built as an object so that modules don't get
+# removed (as happens, even if they have __initcall/module_init)
+LIBS += arch/mips/sibyte/sb1250/sb1250.o
+SUBDIRS += arch/mips/sibyte/sb1250
+endif
+
+#
+# Sibyte SWARM board
+#
+ifdef CONFIG_SB1_CACHE_ERROR
+LIBS += arch/mips/sibyte/sb1/sb1kern.a
+SUBDIRS += arch/mips/sibyte/sb1
+endif
+
+ifdef CONFIG_SIBYTE_SWARM
+LIBS += arch/mips/sibyte/swarm/sbswarm.a
+SUBDIRS += arch/mips/sibyte/swarm
LOADADDR += 0x80100000
endif
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.47
retrieving revision 1.48
diff -u -d -r1.47 -r1.48
--- config.in 2001/11/06 02:57:37 1.47
+++ config.in 2001/11/08 17:42:07 1.48
@@ -3,7 +3,6 @@
# see Documentation/kbuild/config-language.txt.
#
define_bool CONFIG_MIPS y
-define_bool CONFIG_SMP n
mainmenu_name "Linux Kernel Configuration"
@@ -44,6 +43,37 @@
Model-200/210/312/320/325/350/390 CONFIG_NINO_8MB \
Model-500/510 CONFIG_NINO_16MB" CONFIG_NINO_8MB
fi
+ bool 'Support for SiByte SB1250 SOC' CONFIG_SIBYTE_SB1250
+ if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; then
+ bool ' Support for SB1250 onchip PCI controller' CONFIG_PCI
+ bool ' Support for SB1250 profiling - SB1/SCD perf counters' CONFIG_SIBYTE_SB1250_PROF
+ bool ' Support for BCM1250 profiling using trace buffer' CONFIG_BCM1250_TBPROF
+ bool ' Remote debugging (kgdb over UART 1)' CONFIG_REMOTE_DEBUG
+ bool ' Support for SiByte SWARM board' CONFIG_SIBYTE_SWARM
+ if [ "$CONFIG_SIBYTE_SWARM" = "y" ]; then
+ bool ' Running under simulation' CONFIG_SIMULATION
+ bool ' Configure for L3proc Demo' CONFIG_L3DEMO
+ bool ' Standalone compile (for simulation without firmware)' CONFIG_SWARM_STANDALONE
+ if [ "$CONFIG_SWARM_STANDALONE" = "y" ]; then
+ int ' Memory size (in megabytes)' CONFIG_SIBYTE_SWARM_RAM_SIZE 32
+ fi
+ if [ "$CONFIG_SWARM_STANDALONE" = "n" ]; then
+ int ' Maximum memory chunks' CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS 16
+ bool ' Multi-Processing support' CONFIG_SMP
+ fi
+ if [ "$CONFIG_BLK_DEV_INITRD" = "y" ]; then
+ bool ' Embed root filesystem ramdisk into the kernel' CONFIG_EMBEDDED_RAMDISK
+ if [ "$CONFIG_EMBEDDED_RAMDISK" = "y" ]; then
+ choice ' Ramdisk Image to use for root filesystem' \
+ "Simple-init CONFIG_SIBYTE_RAMDISK_SIMPLE_INIT \
+ General CONFIG_SIBYTE_RAMDISK_GENERAL \
+ Promice-console CONFIG_SIBYTE_RAMDISK_PROMICE_CONSOLE\
+ N+I-demo CONFIG_SIBYTE_RAMDISK_NIDEMO\
+ Screening CONFIG_SIBYTE_RAMDISK_SCREENING" General
+ fi
+ fi
+ fi
+ fi
bool 'Support for Sony PlayStation 2' CONFIG_PS2
bool 'Support for Casio Cassiopeia BE-300 (EXPERIMENTAL)' CONFIG_CASIO_BE300
bool 'Support for Vadem Clio 1000 (EXPERIMENTAL)' CONFIG_VADEM_CLIO_1000
@@ -88,6 +118,13 @@
define_bool CONFIG_MCA n
define_bool CONFIG_SBUS n
+if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; then
+ define_bool CONFIG_COHERENT_IO y
+ define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_PCI n
+ define_bool CONFIG_SWAP_IO_SPACE y
+fi
+
if [ "$CONFIG_MIPS_EV96100" = "y" ]; then
define_bool CONFIG_PCI y
define_bool CONFIG_MIPS_GT96100 y
@@ -337,8 +374,12 @@
MIPS32 CONFIG_CPU_MIPS32 \
MIPS64 CONFIG_CPU_MIPS64" R4x00
-bool 'Override CPU Options' CONFIG_CPU_ADVANCED
+if [ "$CONFIG_CPU_SB1" = "y" ]; then
+ bool ' Workarounds for pass 1 sb1 bugs' CONFIG_SB1_PASS_1_WORKAROUNDS
+ bool ' Support for SB1 Cache Error handler' CONFIG_SB1_CACHE_ERROR
+fi
+bool 'Override CPU Options' CONFIG_CPU_ADVANCED
if [ "$CONFIG_CPU_ADVANCED" = "y" ]; then
bool ' ll/sc Instructions available' CONFIG_CPU_HAS_LLSC
bool ' lld/scd Instructions available' CONFIG_CPU_HAS_LLDSCD
|
|
From: James S. <jsi...@us...> - 2001-11-08 17:42:10
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000 In directory usw-pr-cvs1:/tmp/cvs-serv7520/au1000/pb1000 Modified Files: Makefile Log Message: Cleanup Makefile crap and add support for Sibyte SB1250 / SWARM. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/Makefile,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- Makefile 2001/08/17 22:53:26 1.3 +++ Makefile 2001/11/08 17:42:08 1.4 @@ -15,15 +15,10 @@ .S.o: $(CC) $(CFLAGS) -c $< -o $*.o -all: pb1000.o - O_TARGET := pb1000.o obj-y := init.o setup.o obj-$(CONFIG_PCI) += pci_fixup.o pci_ops.o - -dep: - $(CPP) -M *.c > .depend include $(TOPDIR)/Rules.make |
|
From: James S. <jsi...@us...> - 2001-11-08 17:31:20
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sibyte/swarm
In directory usw-pr-cvs1:/tmp/cvs-serv4654/swarm
Added Files:
Makefile cmdline.c memory.c rtc.c setup.c smp.c time.c
Log Message:
64-bit support for SB1250 / SWARM.
--- NEW FILE: Makefile ---
all: sbswarm.a
OBJS-y = setup.o cmdline.o rtc.o time.o memory.o
OBJS-$(CONFIG_SMP) += smp.o
sbswarm.a: $(OBJS-y)
$(AR) rcs sbswarm.a $^
dep:
$(CPP) $(CPPFLAGS) -M *.c > .depend
include $(TOPDIR)/Rules.make
--- NEW FILE: cmdline.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <asm/bootinfo.h>
/*
* The naming of this variable is a remnant of the initial mips port to ARC-firmware
* based SGI consoles. We don't really need to do anything for the variable other
* than provide an instantiation. Everything about arcs_cmdline seems more than a
* little bit hackish...
*/
char arcs_cmdline[CL_SIZE];
--- NEW FILE: memory.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Memory related routines
*/
#include <asm/page.h>
#include <linux/autoconf.h>
extern long swarm_mem_region_addrs[];
extern long swarm_mem_region_sizes[];
extern unsigned int swarm_mem_region_count;
int page_is_ram(unsigned long pagenr)
{
unsigned long addr = pagenr << PAGE_SHIFT;
#ifdef CONFIG_SWARM_STANDALONE
if (addr < (CONFIG_SIBYTE_SWARM_RAM_SIZE * 1024 * 1024)) {
return 1;
}
#else
int i;
for (i = 0; i < swarm_mem_region_count; i++) {
if ((addr >= swarm_mem_region_addrs[i])
&& (addr < (swarm_mem_region_addrs[i] + swarm_mem_region_sizes[i]))) {
return 1;
}
}
#endif
return 0;
}
--- NEW FILE: rtc.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Not really sure what is supposed to be here, yet
*/
#include <linux/spinlock.h>
#include <linux/mc146818rtc.h>
static unsigned char swarm_rtc_read_data(unsigned long addr)
{
return 0;
}
static void swarm_rtc_write_data(unsigned char data, unsigned long addr)
{
}
static int swarm_rtc_bcd_mode(void)
{
return 0;
}
struct rtc_ops swarm_rtc_ops = {
&swarm_rtc_read_data,
&swarm_rtc_write_data,
&swarm_rtc_bcd_mode
};
--- NEW FILE: setup.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Setup code for the SWARM board
*/
#include <linux/spinlock.h>
#include <linux/mc146818rtc.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/blk.h>
#include <asm/irq.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/sibyte/swarm.h>
#include <asm/cfe/cfe_api.h>
#include <asm/cfe/cfe_error.h>
#include <asm/cfe/cfe_xiocb.h>
extern struct rtc_ops swarm_rtc_ops;
extern int cfe_console_handle;
#ifndef CONFIG_SWARM_STANDALONE
long swarm_mem_region_addrs[CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS];
long swarm_mem_region_sizes[CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS];
unsigned int swarm_mem_region_count;
#endif
void swarm_setup(void)
{
rtc_ops = &swarm_rtc_ops;
}
/* This is the kernel command line. Actually, it's
copied, eventually, to command_line, and looks to be
quite redundant. But not something to fix just now */
extern char arcs_cmdline[];
#ifdef CONFIG_EMBEDDED_RAMDISK
/* These are symbols defined by the ramdisk linker script */
extern unsigned char __rd_start;
extern unsigned char __rd_end;
#endif
static void prom_meminit(void)
{
#ifndef CONFIG_SWARM_STANDALONE
unsigned long addr, size;
long type;
unsigned int idx;
int rd_flag;
#endif
unsigned long initrd_pstart;
unsigned long initrd_pend;
#ifdef CONFIG_EMBEDDED_RAMDISK
/* If we're using an embedded ramdisk, then __rd_start and __rd_end
are defined by the linker to be on either side of the ramdisk
area. Otherwise, initrd_start should be defined by kernel command
line arguments */
if (initrd_start == 0) {
initrd_start = (unsigned long)&__rd_start;
initrd_end = (unsigned long)&__rd_end;
}
#endif
initrd_pstart = __pa(initrd_start);
initrd_pend = __pa(initrd_end);
#ifdef CONFIG_SWARM_STANDALONE
/* Standalone compile, memory is hardcoded */
if (initrd_start) {
add_memory_region(0, initrd_pstart, BOOT_MEM_RAM);
add_memory_region(initrd_pstart, initrd_pend-initrd_pstart, BOOT_MEM_RESERVED);
add_memory_region(initrd_pend, (CONFIG_SIBYTE_SWARM_RAM_SIZE * 1024 * 1024)-initrd_pend, BOOT_MEM_RAM);
} else {
add_memory_region(0, CONFIG_SIBYTE_SWARM_RAM_SIZE * 1024 * 1024, BOOT_MEM_RAM);
}
#else /* Run with the firmware */
for (idx = 0; cfe_enummem(idx, &addr, &size, &type) != CFE_ERR_NOMORE; idx++) {
rd_flag = 0;
if (type == CFE_MI_AVAILABLE) {
/* See if this block contains (any portion of) the ramdisk */
if (initrd_start) {
if ((initrd_pstart > addr) && (initrd_pstart < (addr + size))) {
add_memory_region(addr, initrd_pstart-addr, BOOT_MEM_RAM);
rd_flag = 1;
}
if ((initrd_pend > addr) && (initrd_pend < (addr + size))) {
add_memory_region(initrd_pend, (addr + size)-initrd_pend, BOOT_MEM_RAM);
rd_flag = 1;
}
}
if (!rd_flag) {
add_memory_region(addr, size, BOOT_MEM_RAM);
}
swarm_mem_region_addrs[swarm_mem_region_count] = addr;
swarm_mem_region_sizes[swarm_mem_region_count] = size;
swarm_mem_region_count++;
if (swarm_mem_region_count == CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS) {
while(1); /* Too many regions. Need to configure more */
}
}
}
if (initrd_start) {
add_memory_region(initrd_pstart, initrd_pend-initrd_pstart, BOOT_MEM_RESERVED);
}
#endif /* CONFIG_SWARM_STANDALONE */
}
#if 1
static int __init initrd_setup(char *str)
{
/*
*Initrd location comes in the form "<hex size of ramdisk in bytes>@<location in memory>"
* e.g. initrd=3abfd@80010000. This is set up by the loader.
*/
char *tmp, *endptr;
unsigned long initrd_size;
for (tmp = str; *tmp != '@'; tmp++) {
if (!*tmp) {
goto fail;
}
}
*tmp = 0;
tmp++;
if (!*tmp) {
goto fail;
}
initrd_size = simple_strtol(str, &endptr, 16);
if (*endptr) {
goto fail;
}
initrd_start = simple_strtol(tmp, &endptr, 16);
if (*endptr) {
goto fail;
}
initrd_end = initrd_start + initrd_size;
printk("Found initrd of %lx@%lx\n", initrd_size, initrd_start);
return 1;
fail:
printk("Bad initrd argument. Disabling initrd\n");
initrd_start = 0;
initrd_end = 0;
return 1;
}
#endif
//__setup("initrd=", initrd_setup);
/* prom_init is called just after the cpu type is determined, from
init_arch() */
int prom_init(long argc, char **argv, char **envp, int *prom_vec)
{
#ifndef CONFIG_SWARM_STANDALONE
// int i;
// int cmdline_idx = 0;
char *ptr;
/*
* This should go away. Detect if we're booting
* straight from cfe without a loader. If we
* are, then we've got a prom vector in a0. Otherwise,
* argc (and argv and envp, for that matter) will be 0)
*/
if (argc < 0) {
prom_vec = (int *)argc;
strcpy(arcs_cmdline, "root=/dev/ram0 ");
} else {
}
cfe_init((unsigned long)prom_vec);
cfe_open_console();
if (argc >= 0) {
if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) {
panic("LINUX_CMDLINE not defined in cfe.");
}
}
/* Not sure this is needed, but it's the safe way. */
arcs_cmdline[CL_SIZE-1] = 0;
/* Need to find out early whether we've got an initrd. So scan
the list looking now */
for (ptr = arcs_cmdline; *ptr; ptr++) {
while (*ptr == ' ') {
ptr++;
}
if (!strncmp(ptr, "initrd=", 7)) {
initrd_setup(ptr+7);
break;
} else {
while (*ptr && (*ptr != ' ')) {
ptr++;
}
}
}
if (!*ptr) {
printk("No initrd found\n");
}
#else
strcpy(arcs_cmdline, "root=/dev/ram0 ");
#endif
mips_machgroup = MACH_GROUP_SIBYTE;
#if 0
#ifndef CONFIG_SWARM_STANDALONE
for (i = 0; (i < argc) && (cmdline_idx < CL_SIZE); i++) {
if (!strncmp(argv[i], "initrd=", 7)) {
/* Handle initrd argument early; we need to know
about them for the memory map */
unsigned char *size_str = argv[i] + 7;
unsigned char *loc_str = size_str;
unsigned long size, loc;
while (*loc_str && (*loc_str != '@')) {
loc_str++;
}
if (!*loc_str) {
printk("Ignoring malformed initrd argument: %s\n", argv[i]);
continue;
}
*loc_str = '\0';
loc_str++;
size = simple_strtoul(size_str, NULL, 16);
loc = simple_strtoul(loc_str, NULL, 16);
if (size && loc) {
printk("Found initrd argument: 0x%lx@0x%lx\n", size, loc);
initrd_start = loc;
initrd_end = (loc + size + PAGE_SIZE - 1) & PAGE_MASK;
}
} else {
if ((strlen(argv[i]) + cmdline_idx + 1) > CL_SIZE) {
printk("Command line too long. Cut these:\n");
for (; i < argc; i++) {
printk(" %s\n", argv[i]);
}
} else {
strcpy(arcs_cmdline + cmdline_idx, argv[i]);
}
}
}
#endif
#endif
prom_meminit();
return 0;
}
/* Not sure what I'm supposed to do here. Nothing, I think */
void prom_free_prom_memory(void)
{
}
void do_ibe(struct pt_regs *regs)
{
printk("do_ibe called\n");
while(1);
}
void do_dbe(struct pt_regs *regs)
{
printk("Got dbe at 0x%lx\n", regs->cp0_epc);
while(1);
}
extern asmlinkage void handle_ibe(void);
extern asmlinkage void handle_dbe(void);
void __init
bus_error_init(void)
{
set_except_vector(6, handle_ibe);
set_except_vector(7, handle_dbe);
/* At this time nothing uses the DBE protection mechanism on the
Indy, so this here is needed to make the kernel link. */
// get_dbe(dummy, (int *)KSEG0);
}
void machine_restart(char *command)
{
printk("machine_restart called\n");
while(1);
}
void machine_halt(void)
{
printk("machine_halt called\n");
while(1);
}
void machine_power_off(void)
{
printk("machine_power_off called\n");
while(1);
}
static void setled(unsigned int index, char c)
{
volatile unsigned char *led_ptr = (unsigned char *)(IO_SPACE_BASE | LED_BASE_ADDR);
if (index < 4) {
led_ptr[(3-index)<<3] = c;
}
}
void setleds(char *str)
{
int i;
for (i = 0; i < 4; i++) {
if (!str[i]) {
for (; i < 4; i++) {
setled(' ', str[i]);
}
} else {
setled(i, str[i]);
}
}
}
#include <linux/timer.h>
static struct timer_list led_timer;
/*
#ifdef CONFIG_SMP
static unsigned char led_msg[] = "CSWARM...now in glorious SMP! ";
#else
static unsigned char led_msg[] = "CSWARM Lives!!! ";
#endif
*/
static unsigned char default_led_msg[] = "And Justin said...LET THERE BE 64-BIT LINUX! And he saw that it was mediocre. But improving! ";
static unsigned char *led_msg = default_led_msg;
static unsigned char *led_msg_ptr = default_led_msg;
void set_led_msg(char *new_msg)
{
led_msg = new_msg;
led_msg_ptr = new_msg;
setleds(" ");
}
static void move_leds(unsigned long arg)
{
int i;
unsigned char *tmp = led_msg_ptr;
for (i = 0; i < 4; i++) {
setled(i, *tmp);
tmp++;
if (!*tmp) {
tmp = led_msg;
}
}
led_msg_ptr++;
if (!*led_msg_ptr) {
led_msg_ptr = led_msg;
}
del_timer(&led_timer);
led_timer.expires = jiffies + (HZ/8);
add_timer(&led_timer);
}
void hack_leds(void)
{
init_timer(&led_timer);
led_timer.expires = jiffies + (HZ/8);
led_timer.data = 0;
led_timer.function = move_leds;
add_timer(&led_timer);
}
void __add_wait_queue(wait_queue_head_t *head, wait_queue_t *new)
{
#if WAITQUEUE_DEBUG
if (!head || !new)
WQ_BUG();
CHECK_MAGIC_WQHEAD(head);
CHECK_MAGIC(new->__magic);
if (!head->task_list.next || !head->task_list.prev)
WQ_BUG();
#endif
// printk("%i (%s) adding %i (%s) added to wait queue @ %p (%p %p %p %p)\n", new->task->pid, new->task->comm,
// current->pid, current->comm, head, new->task_list.next, new->task_list.prev, head->task_list.next, head->task_list.next->prev);
list_add(&new->task_list, &head->task_list);
}
void __remove_wait_queue(wait_queue_head_t *head, wait_queue_t *old)
{
#if WAITQUEUE_DEBUG
if (!old)
WQ_BUG();
CHECK_MAGIC(old->__magic);
#endif
// printk("%i (%s) removing %i (%s) added to wait queue @ %p\n", old->task->pid, old->task->comm,
// current->pid, current->comm, head);
list_del(&old->task_list);
}
--- NEW FILE: smp.c ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/mipsregs.h>
#include <asm/cfe/cfe_xiocb.h>
#include <asm/cfe/cfe_api.h>
extern void asmlinkage smp_bootstrap(void);
/* Boot all other cpus in the system, initialize them, and
bring them into the boot fn */
int sys_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
{
int retval;
if ((retval = cfe_start_cpu(1, &smp_bootstrap, sp, gp, 0)) != 0) {
printk("cfe_start_cpu returned %i\n" , retval);
panic ("secondary bootstrap failed\n");
}
return 1;
}
void sys_init_secondary(void)
{
/* Set up kseg0 to be cachable coherent */
set_cp0_config(CONF_CM_CMASK, 0x5);
/* Enable interrupts for lines 0-4 */
set_cp0_status(0xff01, 0x1f01);
}
/*
* Set up state, return the total number of cpus in the system, including
* the master
*/
int sys_setup_smp(void)
{
/* Nothing to do here */
return 2;
}
void sys_smp_finish(void)
{
sb1250_smp_finish();
}
--- NEW FILE: time.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Time routines for the swarm board. We pass all the hard stuff
* through to the sb1250 handling code. Only thing we really keep
* track of here is what time of day we think it is. And we don't
* really even do a good job of that...
*/
#include <linux/time.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <asm/system.h>
#include <asm/sibyte/sb1250.h>
static unsigned long long sec_bias = 0;
static unsigned int usec_bias = 0;
static rwlock_t time_lock = RW_LOCK_UNLOCKED;
void do_settimeofday(struct timeval *tv)
{
unsigned long saved_jiffies;
unsigned long flags;
saved_jiffies = jiffies;
write_lock_irqsave(&time_lock, flags);
sec_bias = (saved_jiffies/HZ) - tv->tv_sec;
usec_bias = ((saved_jiffies%HZ)*(1000000/HZ)) - tv->tv_usec;
write_unlock_irqrestore(&time_lock, flags);
}
void do_gettimeofday(struct timeval *tv)
{
unsigned long saved_jiffies;
unsigned long flags;
saved_jiffies = jiffies;
read_lock_irqsave(&time_lock, flags);
tv->tv_sec = sec_bias + (saved_jiffies/HZ);
tv->tv_usec = usec_bias + ((saved_jiffies%HZ) * (1000000/HZ));
read_unlock_irqrestore(&time_lock, flags);
}
/*
* Bring up the timer at 100 Hz.
*/
void time_init(void)
{
/* Just use the sb1250 scd timer. This is a pass through because other
boards may want to use a different timer... */
sb1250_time_init();
}
|
|
From: James S. <jsi...@us...> - 2001-11-08 17:31:20
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sibyte/sb1250
In directory usw-pr-cvs1:/tmp/cvs-serv4654/sb1250
Added Files:
Makefile irq.c irq_handler.S pci-dma.c pci.c setup.c smp.c
time.c
Log Message:
64-bit support for SB1250 / SWARM.
--- NEW FILE: Makefile ---
all: sb1250.a
OBJS-y := setup.o irq.o irq_handler.o time.o
OBJS-$(CONFIG_SMP) += smp.o
OBJS-$(CONFIG_PCI) += pci.o pci-dma.o
sb1250.a: $(OBJS-y)
$(AR) rcs sb1250.a $^
dep:
$(CPP) $(CPPFLAGS) -M *.c > .depend
include $(TOPDIR)/Rules.make
--- NEW FILE: irq.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/irq.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/irq_cpustat.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/sibyte/64bit.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/sb1250.h>
/* Sanity check. We're an sb1250, with 2 SB1 cores on die; we'd better have configured for
an sb1 cpu */
#ifndef CONFIG_CPU_SB1
#error "Sb1250 requires configuration of SB1 cpu"
#endif
/*
* These are the routines that handle all the low level interrupt stuff.
* Actions handled here are: initialization of the interrupt map,
* requesting of interrupt lines by handlers, dispatching if interrupts
* to handlers, probing for interrupt lines */
static spinlock_t irq_mask_lock = SPIN_LOCK_UNLOCKED;
#define IMR_MASK(cpu) (*(volatile unsigned long *)(IO_SPACE_BASE | A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MASK)))
#define IMR_REG(cpu, ofs) (*(volatile unsigned long *)((IO_SPACE_BASE | A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE)) + (ofs<<3)))
#define IMR_MAILBOX(cpu) (*(volatile unsigned long *)(IO_SPACE_BASE | A_IMR_REGISTER(cpu, R_IMR_MAILBOX_CPU)))
/*
* These functions (sb1250_mask_irq and sb1250_unmask_irq) provide
* a safe, locked way to enable and disable interrupts at the
* hardware level. Note they only operate on cpu0; all irq's
* are routed to cpu0 except the mailbox interrupt needed
* for inter-processor-interrupts, so these are usable for
* any other kind of irq.
*/
void sb1250_mask_irq(int cpu, int irq)
{
unsigned long flags;
u64 cur_ints;
spin_lock_irqsave(&irq_mask_lock, flags);
cur_ints = in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
cur_ints |= (((u64)1)<<irq);
out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
spin_unlock_irqrestore(&irq_mask_lock, flags);
}
void sb1250_unmask_irq(int cpu, int irq)
{
unsigned long flags;
u64 cur_ints;
spin_lock_irqsave(&irq_mask_lock, flags);
cur_ints = in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
cur_ints &= ~(((u64)1)<<irq);
out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK);
spin_unlock_irqrestore(&irq_mask_lock, flags);
}
static unsigned int startup_none(unsigned int irq)
{
/* Do nothing */
return 0;
}
static void shutdown_none(unsigned int irq)
{
/* Do nothing */
}
#define enable_none shutdown_none
#define disable_none shutdown_none
#define ack_none shutdown_none
#define end_none shutdown_none
static void affinity_none(unsigned int irq, unsigned long mask)
{
/* Do nothing */
}
/*
* If depth is 0, then unmask the interrupt. Increment depth
*/
void enable_irq(unsigned int irq)
{
unsigned long flags;
irq_desc_t *desc = irq_desc + irq;
spin_lock_irqsave(&desc->lock, flags);
if (!desc->depth) {
u64 cur_ints;
spin_lock(&irq_mask_lock);
cur_ints = in64(KSEG1 + A_IMR_MAPPER(0) + R_IMR_INTERRUPT_MASK);
cur_ints &= ~(((u64)1)<<irq);
out64(cur_ints, KSEG1 + A_IMR_MAPPER(0) + R_IMR_INTERRUPT_MASK);
spin_unlock(&irq_mask_lock);
desc->status &= ~IRQ_DISABLED;
}
desc->depth++;
spin_unlock_irqrestore(&desc->lock, flags);
}
/*
* If depth hits 0, disable the interrupt. By grabbing desc->lock, we
* implicitly sync because a dispatched interrupt will grab that lock
* before calling handlers. IRQ_DISABLED is checked by the dispatcher
* under desc->lock, so we set that in case we're racing with a dispatch.
*/
void disable_irq(unsigned int irq)
{
unsigned long flags;
irq_desc_t *desc = irq_desc + irq;
spin_lock_irqsave(&desc->lock, flags);
if (!desc->depth) {
BUG();
}
desc->depth--;
if (!desc->depth) {
u64 cur_ints;
spin_lock(&irq_mask_lock);
cur_ints = in64(KSEG1 + A_IMR_MAPPER(0) + R_IMR_INTERRUPT_MASK);
cur_ints |= (((u64)1)<<irq);
out64(cur_ints, KSEG1 + A_IMR_MAPPER(0) + R_IMR_INTERRUPT_MASK);
spin_unlock(&irq_mask_lock);
desc->status |= IRQ_DISABLED;
}
spin_unlock_irqrestore(&desc->lock, flags);
}
static struct hw_interrupt_type no_irq_type = {
"none",
startup_none,
shutdown_none,
enable_none,
disable_none,
ack_none,
end_none,
affinity_none
};
/*
* irq_desc is the structure that keeps track of the state
* and handlers for each of the IRQ lines
*/
static irq_desc_t irq_desc[NR_IRQS] =
{ [0 ... NR_IRQS-1] = { 0, &no_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
/* Defined in arch/mips/sibyte/sb1250/irq_handler.S */
extern void sb1250_irq_handler(void);
/*
* spurious_count is used in arch/mips/kernel/entry.S to record the
* number of spurious interrupts we see before the handler is installed.
* It doesn't provide any particularly relevant information for us, so
* we basically ignore it.
*/
unsigned long spurious_count = 0;
/*
* The interrupt handler calls this once for every unmasked interrupt
* that is pending. vector is the IRQ number that was raised
*/
void sb1250_dispatch_irq(unsigned int vector, struct pt_regs *regs)
{
struct irqaction *action;
irq_desc_t *desc = irq_desc + vector;
/* XXX This race nipping stuff seems to be incorrect. Revisit this later. */
/*spin_lock(&desc->lock);*/
/* Nip a race. If we had a disable_irq() call that happened after we
started the interrupt but before we got here, it set the DISABLED
flag. Check that flag under the lock before doing anything */
if (!(desc->status & IRQ_DISABLED)) {
for (action = desc->action; action != NULL; action = action->next) {
if (action->handler != NULL) {
(*(action->handler))(vector, action->dev_id, regs);
}
}
}
/*spin_unlock(&desc->lock);*/
}
/*
* Stolen, pretty much intact, from arch/i386/kernel/irq.c
*/
int setup_irq(unsigned int irq, struct irqaction * new)
{
int shared = 0;
unsigned long flags;
struct irqaction *old, **p;
irq_desc_t *desc = irq_desc + irq;
/*
* The following block of code has to be executed atomically
*/
spin_lock_irqsave(&desc->lock,flags);
p = &desc->action;
if ((old = *p) != NULL) {
/* Can't share interrupts unless both agree to */
if (!(old->flags & new->flags & SA_SHIRQ)) {
spin_unlock_irqrestore(&desc->lock,flags);
return -EBUSY;
}
/* add new interrupt at end of irq queue */
do {
p = &old->next;
old = *p;
} while (old);
shared = 1;
}
*p = new;
if (!shared) {
desc->depth = 0;
desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING);
desc->handler->startup(irq);
}
spin_unlock_irqrestore(&desc->lock,flags);
return 0;
}
/*
* init_IRQ is called early in the boot sequence from init/main.c. It
* is responsible for setting up the interrupt mapper and installing the
* handler that will be responsible for dispatching interrupts to the
* "right" place.
*/
/*
* For now, map all interrupts to IP[2]. We could save
* some cycles by parceling out system interrupts to different
* IP lines, but keep it simple for bringup. We'll also direct
* all interrupts to a single CPU; we should probably route
* PCI and LDT to one cpu and everything else to the other
* to balance the load a bit.
*
* On the second cpu, everything is set to IP5, which is
* ignored, EXCEPT the mailbox interrupt. That one is
* set to IP2 so it is handled. This is needed so we
* can do cross-cpu function calls, as requred by SMP
*/
void __init init_IRQ(void)
{
unsigned int i;
u64 tmp;
/* Default everything to IP2 */
for (i = 0; i < 64; i++) {
IMR_REG(0, i) = K_INT_MAP_I0;
IMR_REG(1, i) = K_INT_MAP_I0;
}
/* Map general purpose timer 0 to IP[4] on cpu 0. This is the system timer */
IMR_REG(0, K_INT_TIMER_0) = K_INT_MAP_I2;
/* Map the high 16 bits of the mailbox registers to IP[3], for inter-cpu messages */
IMR_REG(0, K_INT_MBOX_0) = K_INT_MAP_I1;
IMR_REG(1, K_INT_MBOX_0) = K_INT_MAP_I1;
/* Clear the mailboxes. The firmware may leave them dirty */
IMR_MAILBOX(0) = 0;
IMR_MAILBOX(1) = 0;
/* Mask everything except the mailbox registers for both cpus */
tmp = ~((u64)0) ^ (((u64)1) << K_INT_MBOX_0);
IMR_MASK(0) = tmp;
IMR_MASK(1) = tmp;
/* Enable IP[4:0], disable the rest */
set_cp0_status(0xff00, 0x1f00);
set_except_vector(0, sb1250_irq_handler);
}
/*
* request_irq() is called by drivers to request addition to the chain
* of handlers called for a given interrupt.
*
* arch/i386/kernel/irq.c says this is going to become generic code in 2.5
* Makes sense, considering it's already architecture independent. As such,
* I've tried to match the i386 style as much as possible to make the
* transition simple
*/
int request_irq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long irqflags, const char * devname, void *dev_id)
{
int retval;
struct irqaction * action;
/*
* Sanity-check: shared interrupts should REALLY pass in
* a real dev-ID, otherwise we'll have trouble later trying
* to figure out which interrupt is which (messes up the
* interrupt freeing logic etc).
*/
if (irqflags & SA_SHIRQ) {
if (!dev_id)
printk("Bad boy: %s (at 0x%x) called us without a dev_id!\n", devname, (&irq)[-1]);
}
if (irq >= NR_IRQS) {
return -EINVAL;
}
if (!handler) {
return -EINVAL;
}
action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL);
if (!action) {
return -ENOMEM;
}
action->handler = handler;
action->flags = irqflags;
action->mask = 0;
action->name = devname;
action->next = NULL;
action->dev_id = dev_id;
retval = setup_irq(irq, action);
if (retval) {
kfree(action);
}
else {
if ((irq >= 56) && (irq <= 59)) {
sb1250_unmask_irq(0,irq);
}
}
return retval;
}
/*
* free_irq() releases a handler set up by request_irq()
*/
void free_irq(unsigned int irq, void *dev_id)
{
irq_desc_t *desc;
struct irqaction **p;
unsigned long flags;
if (irq >= NR_IRQS)
return;
desc = irq_desc + irq;
spin_lock_irqsave(&desc->lock,flags);
p = &desc->action;
for (;;) {
struct irqaction * action = *p;
if (action) {
struct irqaction **pp = p;
p = &action->next;
if (action->dev_id != dev_id)
continue;
/* Found it - now remove it from the list of entries */
*pp = action->next;
if (!desc->action) {
desc->status |= IRQ_DISABLED;
desc->handler->shutdown(irq);
}
spin_unlock_irqrestore(&desc->lock,flags);
#ifdef CONFIG_SMP
/* Wait to make sure it's not being used on another CPU */
while (desc->status & IRQ_INPROGRESS)
barrier();
#endif
kfree(action);
return;
}
spin_unlock_irqrestore(&desc->lock,flags);
return;
}
}
/*
* get_irq_list() pretty prints a list of who has requested which
* irqs. This function is activated by a read of a file in /proc/
* Returns the length of the string generated
*
*/
int get_irq_list(char *buf)
{
return 0;
}
/*
* probe_irq_on() and probe_irq_off() are a pair of functions used for
* determining which interrupt a device is using. I *think* this is
* pretty much legacy for [E]ISA applications, thus the stubbing out.
*/
unsigned long probe_irq_on (void)
{
panic("probe_irq_on called");
}
int probe_irq_off (unsigned long irqs)
{
panic("probe_irq_off called");
}
/*
* I don't see a good way to do this without syncing, given the
* way desc->lock works, so just sync anyways.
*/
void disable_irq_nosync(unsigned int irq)
{
disable_irq(irq);
}
--- NEW FILE: irq_handler.S ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* sb1250_handle_int() is the routine that is actually called when an interrupt
* occurs. It is installed as the exception vector handler in init_IRQ()
* in arch/mips/sibyte/sb1250/irq.c
*
* In the handle we figure out which interrupts need handling, and use that to call
* the dispatcher, which will take care of actually calling registered handlers
*
* Note that we take care of all raised interrupts in one go at the handler. This
* is more BSDish than the Indy code, and also, IMHO, more sane.
*/
#include <asm/addrspace.h>
#include <asm/processor.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/sibyte/sb1250_regs.h>
.text
.set push
.set noreorder
.set noat
.align 5
NESTED(sb1250_irq_handler, PT_SIZE, sp)
SAVE_ALL
/* Is the CLI really needed? If it is, this looks suspiciously
like a place that would need a spinlock instead of a CLI.
*/
CLI
mfc0 s0, $13
/* Timer interrupt is routed to IP[4] */
andi t1, s0, 0x1000
beqz t1, 1f
nop
jal sb1250_timer_interrupt
move a0, sp /* Pass the registers along */
1:
#ifdef CONFIG_SMP
/* Mailbox interrupt is routed to IP[3] */
andi t1, s0, 0x800
beqz t1, 2f
nop
jal sb1250_mailbox_interrupt
move a0, sp
2:
#endif
and t1, s0, 0x400
beqz t1, 4f
nop
/* Default...we've hit an IP[2] interrupt, which means we've got to check the
1250 interrupt registers to figure out what to do */
la v0, KSEG1 + A_IMR_CPU0_BASE
ld s1, R_IMR_INTERRUPT_MASK(v0)
ld s0, R_IMR_INTERRUPT_SOURCE_STATUS(v0)
ld t0, R_IMR_LDT_INTERRUPT(v0)
nor s1, s1, zero /* Negate mask to turn it into an and mask */
or s0, s0, t0 /* Merge pending system and LDT IRQS */
and s0, s0, s1 /* Now s0 has a bitfield of unmasked pending IRQs */
and t0, t0, s1 /* LDT interrupts we will service */
beqz s0, 4f /* No interrupts. Return */
daddiu a1, sp, 0 /* registers get passed along as the second argument */
sd t0, R_IMR_LDT_INTERRUPT_CLR(v0) /* Clear what we'll service */
3:
.word 0x72118824 /* find next interrupt, actually a dclz s1,s0 */
dsubu a0, zero, s1
jal sb1250_dispatch_irq /* Handle the interrupt */
daddiu a0, a0, 63
daddiu s1, s1, 1 /* Get shift amount for clearing of top interrupt */
dsllv s0, s0, s1 /* Clear the top interrupt */
bnez s0, 3b /* More interrupts to service? */
dsrlv s0, s0, s1 /* realign pending interrupts */
4:
j ret_from_irq /* defined in arch/mips/kernel/entry.S */
nop
.set pop
END(sb1250_irq_handler)
--- NEW FILE: pci-dma.c ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* from: ip27-pci-dma.c
*
* Dynamic DMA mapping support.
*
* On the Origin there is dynamic DMA address translation for all PCI DMA.
* However we don't use this facility yet but rely on the 2gb direct
* mapped DMA window for PCI64. So consistent alloc/free are merely page
* allocation/freeing. The rest of the dynamic DMA mapping interface is
* implemented in <asm/pci.h>. So this code will fail with more than
* 2gb of memory.
*/
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <asm/io.h>
/* Pure 2^n version of get_order */
extern __inline__ int __get_order(unsigned long size)
{
int order;
size = (size-1) >> (PAGE_SHIFT-1);
order = -1;
do {
size >>= 1;
order++;
} while (size);
return order;
}
void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t *dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC;
int order = __get_order(size);
if (hwdev == NULL || hwdev->dma_mask != 0xffffffff)
gfp |= GFP_DMA;
ret = (void *)__get_free_pages(gfp, order);
if (ret != NULL) {
memset(ret, 0, size);
*dma_handle = (bus_to_baddr[hwdev->bus->number] | __pa(ret));
}
return ret;
}
void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
free_pages((unsigned long)vaddr, __get_order(size));
}
--- NEW FILE: pci.c ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* SB1250-specific PCI support
*
* This module provides the glue between Linux's PCI subsystem
* and the hardware. We basically provide glue for accessing
* configuration space, and set up the translation for I/O
* space accesses.
*
* To access configuration space, we call some assembly-level
* stubs that flip the KX bit on and off in the status
* register, and do XKSEG addressed memory accesses there.
* It's slow (7 SSNOPs to guarantee that KX is set!) but
* fortunately, config space accesses are rare.
*
* We could use the ioremap functionality for the confguration
* space as well as I/O space, but I'm not sure of the
* implications of setting aside 16MB of KSEG2 for something
* that is used so rarely (how much space in the page tables?)
*
*/
#include <linux/config.h>
#ifdef CONFIG_PCI
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <asm/sibyte/sb1250_defs.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_pci.h>
#define PCI_BUS_ENABLED 1
#define LDT_BUS_ENABLED 2
static int sb1250_bus_status = 0;
#define MATCH_BITS 0x20000000 /* really belongs in an include file */
#define LDT_BRIDGE_START ((A_PCI_TYPE01_HEADER|MATCH_BITS)+0x00)
#define LDT_BRIDGE_END ((A_PCI_TYPE01_HEADER|MATCH_BITS)+0x20)
/*
* This macro calculates the offset into config space where
* a given bus, device/function, and offset live on the sb1250
*/
#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
/*
* Using the above offset, this macro calcuates the actual
* address. Note that the physical address is not accessible
* without remapping or setting KX. We use 'match bits'
* as our endian policy to guarantee that 32-bit accesses
* look the same from either endianness.
*/
#define CFGADDR(dev,where) (A_PHYS_LDTPCI_CFG_MATCH_BITS + \
CFGOFFSET(dev->bus->number,dev->devfn,where))
/*
* Read/write 32-bit values in config space.
*/
#define READCFG32(addr) *((volatile uint32_t *) (K1BASE+((addr)&~3)))
#define WRITECFG32(addr,data) *((volatile uint32_t *) (K1BASE+((addr)&~3))) = (data)
/*
* This variable is the mapping
* of the ISA/PCI I/O space area. We map 64K here and
* the offsets from this address get treated with "match bytes"
* policy to make everything look little-endian. So,
* you need to also set CONFIG_SWAP_IO_SPACE, but this is the
* combination that works correctly with most of Linux's drivers.
*/
unsigned long mips_io_port_base;
/*
* Read/write access functions for various sizes of values
* in config space.
*/
static int
sb1250_pci_read_config_byte (struct pci_dev *dev, int where, u8 *val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev,where);
data = READCFG32(cfgaddr);
/*
* If the LDT was not configured, make it look like the bridge
* header is not there.
*/
if (!(sb1250_bus_status & LDT_BUS_ENABLED) &&
(cfgaddr >= LDT_BRIDGE_START) &&
(cfgaddr < LDT_BRIDGE_END)) {
data = 0xFFFFFFFF;
}
*val = (data >> ((where & 3) << 3)) & 0xff;
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_read_config_word (struct pci_dev *dev, int where, u16 *val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev,where);
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
data = READCFG32(cfgaddr);
/*
* If the LDT was not configured, make it look like the bridge
* header is not there.
*/
if (!(sb1250_bus_status & LDT_BUS_ENABLED) &&
(cfgaddr >= LDT_BRIDGE_START) &&
(cfgaddr < LDT_BRIDGE_END)) {
data = 0xFFFFFFFF;
}
*val = (data >> ((where & 3) << 3)) & 0xffff;
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_read_config_dword (struct pci_dev *dev, int where, u32 *val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev,where);
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
data = READCFG32(cfgaddr);
/*
* If the LDT was not configured, make it look like the bridge
* header is not there.
*/
if (!(sb1250_bus_status & LDT_BUS_ENABLED) &&
(cfgaddr >= LDT_BRIDGE_START) &&
(cfgaddr < LDT_BRIDGE_END)) {
data = 0xFFFFFFFF;
}
*val = data;
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_write_config_byte (struct pci_dev *dev, int where, u8 val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev,where);
data = READCFG32(cfgaddr);
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
WRITECFG32(cfgaddr,data);
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_write_config_word (struct pci_dev *dev, int where, u16 val)
{
u32 data = 0;
u32 cfgaddr = CFGADDR(dev,where);
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
data = READCFG32(cfgaddr);
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
WRITECFG32(cfgaddr,data);
return PCIBIOS_SUCCESSFUL;
}
static int
sb1250_pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
{
u32 cfgaddr = CFGADDR(dev,where);
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
WRITECFG32(cfgaddr,val);
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops sb1250_pci_ops = {
sb1250_pci_read_config_byte,
sb1250_pci_read_config_word,
sb1250_pci_read_config_dword,
sb1250_pci_write_config_byte,
sb1250_pci_write_config_word,
sb1250_pci_write_config_dword
};
void __init pcibios_init(void)
{
uint32_t cmdreg;
/*
* See if the PCI bus has been configured by the firmware.
*/
cmdreg = READCFG32((A_PCI_TYPE00_HEADER|MATCH_BITS) + R_PCI_TYPE0_CMDSTATUS);
if (!(cmdreg & M_PCI_CMD_MASTER_EN)) {
printk("PCI: Skipping PCI probe. Bus is not initialized.\n");
return;
}
sb1250_bus_status |= PCI_BUS_ENABLED;
/*
* Also check the LDT bridge's enable, just in case we didn't
* initialize that one.
*/
cmdreg = READCFG32((A_PCI_TYPE01_HEADER|MATCH_BITS) + R_PCI_TYPE0_CMDSTATUS);
if (cmdreg & M_PCI_CMD_MASTER_EN) {
sb1250_bus_status |= LDT_BUS_ENABLED;
}
/*
* Establish a mapping from kernel uncached space to ISA-style I/O space.
* Use "match bytes", even though this exposes endianness.
* big-endian Linuxes will have CONFIG_SWAP_IO_SPACE set.
*/
#if defined(CONFIG_SWAP_IO_SPACE)
mips_io_port_base = K1BASE | (A_PHYS_LDTPCI_IO_MATCH_BYTES);
#else
mips_io_port_base = K1BASE | (A_PHYS_LDTPCI_IO_MATCH_BITS);
#endif
/* Probe for PCI hardware */
printk("PCI: Probing PCI hardware on host bus 0.\n");
pci_scan_bus(0, &sb1250_pci_ops, NULL);
}
int __init
pcibios_enable_device(struct pci_dev *dev)
{
/* Not needed, since we enable all devices at startup. */
return 0;
}
void __init
pcibios_align_resource(void *data, struct resource *res, unsigned long size)
{
}
char * __init
pcibios_setup(char *str)
{
/* Nothing to do for now. */
return str;
}
struct pci_fixup pcibios_fixups[] = {
{ 0 }
};
void __init
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
unsigned long where, size;
u32 reg;
where = PCI_BASE_ADDRESS_0 + (resource * 4);
size = res->end - res->start;
pci_read_config_dword(dev, where, ®);
reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
pci_write_config_dword(dev, where, reg);
}
/*
* Called after each bus is probed, but before its children
* are examined.
*/
void __init pcibios_fixup_bus(struct pci_bus *b)
{
pci_read_bridge_bases(b);
}
#endif /* CONFIG_PCI */
--- NEW FILE: setup.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* Setup code likely to be common to all SB1250 platforms */
#include <linux/spinlock.h>
#include <linux/mc146818rtc.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/blk.h>
#include <asm/irq.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
unsigned long bus_to_baddr[256];
void sb1250_setup(void)
{
printk("sb1250_setup was called.\n");
}
--- NEW FILE: smp.c ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <asm/sibyte/64bit.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/addrspace.h>
#include <asm/smp.h>
#include <asm/processor.h>
#include <asm/delay.h>
#include <linux/sched.h>
extern struct cpuinfo_mips cpu_data[NR_CPUS];
/*
* These are routines for dealing with the sb1250 smp capabilities
* independent of board/firmware
*/
static u64 mailbox_set_regs[] =
{ KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU,
KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU };
static u64 mailbox_clear_regs[] =
{ KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU,
KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU };
static u64 mailbox_regs[] =
{ KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU,
KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU };
/* Simple enough; everything is set up, so just poke the appropriate mailbox
register, and we should be set */
void sys_send_intercpu_int(int cpu, unsigned int action)
{
#ifdef PARANOID
if (action & ~0xff) {
BUG();
}
#endif
out64((((u64)action)<< 48), mailbox_set_regs[cpu]);
}
void sb1250_smp_finish(void)
{
void sb1_sanitize_tlb(void);
cpu_data[0].udelay_val = loops_per_jiffy;
cpu_data[1].udelay_val = loops_per_jiffy;
sb1250_time_init();
sb1_sanitize_tlb();
}
void sb1250_mailbox_interrupt(struct pt_regs *regs)
{
/* Function pointer to latch the value before we say we're started */
unsigned int action;
/* Load the mailbox register to figure out what we're supposed to do */
action = (in64(mailbox_regs[smp_processor_id()]) >> 48) & 0xffff;
/* Clear the mailbox to clear the interrupt */
out64(((u64)0xffff)<<48, mailbox_clear_regs[smp_processor_id()]);
if (action & SMP_INT_RESCHEDULE) {
current->need_resched = 1;
}
if (action & SMP_INT_CALL_FUNC) {
smp_call_function_interrupt();
}
}
--- NEW FILE: time.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* These are routines to set up and handle interrupts from the
* sb1250 general purpose timer 0. We're using the timer as a
* system clock, so we set it up to run at 100 Hz. On every
* interrupt, we update our idea of what the time of day is,
* then call do_timer() in the architecture-independent kernel
* code to do general bookkeeping (e.g. update jiffies, run
* bottom halves, etc.)
*/
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <asm/irq.h>
#include <asm/ptrace.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/64bit.h>
#include <asm/pgtable.h>
void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs);
void sb1250_time_init(void)
{
int cpu;
cpu = smp_processor_id();
/* Only have 4 general purpose timers */
if (cpu > 3) {
BUG();
}
sb1250_mask_irq(cpu, 2 + cpu);
/* Map the timer interrupt to ip[4] of this cpu */
out64(K_INT_MAP_I2, KSEG1 + A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE)
+ ((K_INT_TIMER_0 + cpu)<<3));
/* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
/* Disable the timer and set up the count */
out64(0, KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
out64(1000000/HZ, KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
/* Set the timer running */
out64(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
sb1250_unmask_irq(cpu, 2 + cpu);
/* This interrupt is "special" in that it doesn't use the request_irq way
to hook the irq line. The timer interrupt is initialized early enough
to make this a major pain, and it's also firing enough to warrant a
bit of special case code. sb1250_timer_interrupt is called directly
from irq_handler.S when IP[4] is set during an interrupt */
}
void sb1250_timer_interrupt(struct pt_regs *regs)
{
int cpu = smp_processor_id();
/* Reset the timer */
out64(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
/* Need to do some stuff here with xtime, too, but that looks like
it should be architecture independent...does it really belong here? */
if (!cpu) {
do_timer(regs);
}
#ifdef CONFIG_SMP
{
int user = user_mode(regs);
/*
* update_process_times() expects us to have done irq_enter().
* Besides, if we don't timer interrupts ignore the global
* interrupt lock, which is the WrongThing (tm) to do.
* Picked from i386 code.
*/
irq_enter(cpu, 0);
update_process_times(user);
irq_exit(cpu, 0);
}
#endif /* CONFIG_SMP */
}
|
|
From: James S. <jsi...@us...> - 2001-11-08 17:31:20
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sibyte/sb1 In directory usw-pr-cvs1:/tmp/cvs-serv4654/sb1 Added Files: Makefile cache.c tlb.c Log Message: 64-bit support for SB1250 / SWARM. --- NEW FILE: Makefile --- L_TARGET = sb1kern.a obj-y += tlb.o cache.o include $(TOPDIR)/Rules.make --- NEW FILE: cache.c --- --- NEW FILE: tlb.c --- |
|
From: James S. <jsi...@us...> - 2001-11-08 17:31:20
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sibyte/cfe
In directory usw-pr-cvs1:/tmp/cvs-serv4654/cfe
Added Files:
Makefile cfe_api.c
Log Message:
64-bit support for SB1250 / SWARM.
--- NEW FILE: Makefile ---
all: cfe_api.o
dep:
$(CPP) $(CPPFLAGS) -M *.c > .depend
include $(TOPDIR)/Rules.make
--- NEW FILE: cfe_api.c ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* **********************************************************************
* Broadcom Common Firmware Environment (CFE)
*
* Device Function stubs File: cfe_api.c
*
* This module contains device function stubs (small routines to
* call the standard "iocb" interface entry point to CFE).
* There should be one routine here per iocb function call.
*
* Author: Mitch Lichtenberg (mp...@br...)
*
********************************************************************** */
#include <asm/cfe/cfe_xiocb.h>
#include <asm/cfe/cfe_api.h>
#include <linux/string.h>
static long cfe_console_handle = -1;
static int (*cfe_dispfunc)(long handle,cfe_xiocb_t *xiocb) = 0;
static cfe_xuint_t cfe_handle = 0;
typedef unsigned long intptr_t;
int cfe_init(cfe_xuint_t handle)
{
unsigned int *sealloc = (unsigned int *) (intptr_t) (int) CFE_APISEAL;
if (*sealloc != CFE_EPTSEAL) return -1;
cfe_dispfunc = (void *) (cfe_xptr_t) (int) CFE_APIENTRY;
if (handle) cfe_handle = handle;
return 0;
}
int cfe_iocb_dispatch(cfe_xiocb_t *xiocb);
int cfe_iocb_dispatch(cfe_xiocb_t *xiocb)
{
if (!cfe_dispfunc) return -1;
return (*cfe_dispfunc)(cfe_handle,xiocb);
}
static int cfe_strlen(char *name)
{
int count = 0;
while (*name) {
count++;
name++;
}
return count;
}
int cfe_open(char *name)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.plist.xiocb_buffer.buf_offset = 0;
xiocb.plist.xiocb_buffer.buf_ptr = (cfe_xptr_t) (intptr_t) name;
xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name);
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status < 0) ? xiocb.xiocb_status : xiocb.xiocb_handle;
}
int cfe_close(int handle)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = 0;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status);
}
int cfe_readblk(int handle,cfe_xint_t offset,unsigned char *buffer,int length)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_READ;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.plist.xiocb_buffer.buf_offset = offset;
xiocb.plist.xiocb_buffer.buf_ptr = (cfe_xptr_t) (intptr_t) buffer;
xiocb.plist.xiocb_buffer.buf_length = length;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status < 0) ? xiocb.xiocb_status : xiocb.plist.xiocb_buffer.buf_retlen;
}
int cfe_read(int handle,unsigned char *buffer,int length)
{
return cfe_readblk(handle,0,buffer,length);
}
int cfe_writeblk(int handle,cfe_xint_t offset,unsigned char *buffer,int length)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.plist.xiocb_buffer.buf_offset = offset;
xiocb.plist.xiocb_buffer.buf_ptr = (cfe_xptr_t) (intptr_t) buffer;
xiocb.plist.xiocb_buffer.buf_length = length;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status < 0) ? xiocb.xiocb_status : xiocb.plist.xiocb_buffer.buf_retlen;
}
int cfe_write(int handle,unsigned char *buffer,int length)
{
return cfe_writeblk(handle,0,buffer,length);
}
int cfe_ioctl(int handle,unsigned int ioctlnum,unsigned char *buffer,int length,int *retlen)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
xiocb.plist.xiocb_buffer.buf_ioctlcmd = (cfe_xint_t) ioctlnum;
xiocb.plist.xiocb_buffer.buf_ptr = (cfe_xptr_t) (intptr_t) buffer;
xiocb.plist.xiocb_buffer.buf_length = length;
cfe_iocb_dispatch(&xiocb);
if (retlen) *retlen = xiocb.plist.xiocb_buffer.buf_retlen;
return xiocb.xiocb_status;
}
int cfe_inpstat(int handle)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = handle;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_inpstat_t);
xiocb.plist.xiocb_inpstat.inp_status = 0;
cfe_iocb_dispatch(&xiocb);
if (xiocb.xiocb_status < 0) return xiocb.xiocb_status;
return xiocb.plist.xiocb_inpstat.inp_status;
}
long long cfe_getticks(void)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_time_t);
xiocb.plist.xiocb_time.ticks = 0;
cfe_iocb_dispatch(&xiocb);
return xiocb.plist.xiocb_time.ticks;
}
int cfe_getenv(char *name,char *dest,int destlen)
{
cfe_xiocb_t xiocb;
*dest = 0;
xiocb.xiocb_fcode = CFE_CMD_ENV_GET;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
xiocb.plist.xiocb_envbuf.enum_idx = 0;
xiocb.plist.xiocb_envbuf.name_ptr = (cfe_xptr_t) (intptr_t) name;
xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
xiocb.plist.xiocb_envbuf.val_ptr = (cfe_xptr_t) (intptr_t) dest;
xiocb.plist.xiocb_envbuf.val_length = destlen;
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
int cfe_setenv(char *name,char *val)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
xiocb.plist.xiocb_envbuf.enum_idx = 0;
xiocb.plist.xiocb_envbuf.name_ptr = (cfe_xptr_t) (intptr_t) name;
xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
xiocb.plist.xiocb_envbuf.val_ptr = (cfe_xptr_t) (intptr_t) val;
xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val);
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
int cfe_enummem(long idx, unsigned long *addr, unsigned long *size, long *type)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_meminfo_t);
xiocb.plist.xiocb_meminfo.mi_idx = idx;
cfe_iocb_dispatch(&xiocb);
(*addr) = xiocb.plist.xiocb_meminfo.mi_addr;
(*size) = xiocb.plist.xiocb_meminfo.mi_size;
(*type) = xiocb.plist.xiocb_meminfo.mi_type;
return xiocb.xiocb_status;
}
int cfe_enumenv(int idx,char *name,int namelen,char *val,int vallen)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
xiocb.plist.xiocb_envbuf.enum_idx = idx;
xiocb.plist.xiocb_envbuf.name_ptr = (cfe_xptr_t) (intptr_t) name;
xiocb.plist.xiocb_envbuf.name_length = namelen;
xiocb.plist.xiocb_envbuf.val_ptr = (cfe_xptr_t) (intptr_t) val;
xiocb.plist.xiocb_envbuf.val_length = vallen;
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
int cfe_exit(int warm)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_RESTART;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0;
xiocb.xiocb_psize = 0;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status);
}
int cfe_flushcache(int flg)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = flg;
xiocb.xiocb_psize = 0;
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
int cfe_getstdhandle(int flg)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = flg;
xiocb.xiocb_psize = 0;
cfe_iocb_dispatch(&xiocb);
return (xiocb.xiocb_status < 0) ? xiocb.xiocb_status : xiocb.xiocb_handle;
}
int cfe_start_cpu(int cpu, void (*fn)(void), long sp, long gp, long a1)
{
cfe_xiocb_t xiocb;
xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
xiocb.xiocb_flags = 0;
xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t);
xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START;
xiocb.plist.xiocb_cpuctl.gp_val = gp;
xiocb.plist.xiocb_cpuctl.sp_val = sp;
xiocb.plist.xiocb_cpuctl.a1_val = a1;
xiocb.plist.xiocb_cpuctl.start_addr = (long)fn;
cfe_iocb_dispatch(&xiocb);
return xiocb.xiocb_status;
}
void cfe_open_console()
{
cfe_console_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
}
void cfe_console_print(char *str)
{
if (cfe_console_handle != -1) {
cfe_write(cfe_console_handle, str, strlen(str));
}
}
|
|
From: James S. <jsi...@us...> - 2001-11-08 17:28:28
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv4111/asm-mips64/sibyte
Added Files:
64bit.h sb1250.h sb1250_defs.h sb1250_dma.h sb1250_genbus.h
sb1250_int.h sb1250_l2c.h sb1250_ldt.h sb1250_mac.h
sb1250_mc.h sb1250_pci.h sb1250_regs.h sb1250_scd.h
sb1250_smbus.h sb1250_syncser.h sb1250_uart.h sb1250regs.h
sbmips.h swarm.h
Log Message:
More Sibyte bulk merging.
--- NEW FILE: 64bit.h ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _ASM_SIBYTE_64BIT_H
#define _ASM_SIBYTE_64BIT_H
#include <asm/types.h>
/* These are provided so as to be able to use common
driver code for the 32-bit and 64-bit trees */
extern inline void out64(u64 val, unsigned long addr)
{
*(volatile unsigned long *)addr = val;
}
extern inline u64 in64(unsigned long addr)
{
return *(volatile unsigned long *)addr;
}
#endif
--- NEW FILE: sb1250.h ---
/*
* Copyright (C) 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
extern void sb1250_mask_irq(int cpu, int irq);
extern void sb1250_unmask_irq(int cpu, int irq);
extern void sb1250_time_init(void);
--- NEW FILE: sb1250_defs.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* Global constants and macros File: sb1250_defs.h
*
* This file contains macros and definitions used by the other
* include files.
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
/* *********************************************************************
* Naming schemes for constants in these files:
*
* M_xxx MASK constant (identifies bits in a register).
* For multi-bit fields, all bits in the field will
* be set.
*
* K_xxx "Code" constant (value for data in a multi-bit
* field). The value is right justified.
*
* V_xxx "Value" constant. This is the same as the
* corresponding "K_xxx" constant, except it is
* shifted to the correct position in the register.
*
* S_xxx SHIFT constant. This is the number of bits that
* a field value (code) needs to be shifted
* (towards the left) to put the value in the right
* position for the register.
*
* A_xxx ADDRESS constant. This will be a physical
* address. Use the PHYS_TO_K1 macro to generate
* a K1SEG address.
*
* R_xxx RELATIVE offset constant. This is an offset from
* an A_xxx constant (usually the first register in
* a group).
*
* G_xxx(X) GET value. This macro obtains a multi-bit field
* from a register, masks it, and shifts it to
* the bottom of the register (retrieving a K_xxx
* value, for example).
*
* V_xxx(X) VALUE. This macro computes the value of a
* K_xxx constant shifted to the correct position
* in the register.
********************************************************************* */
#ifndef _SB1250_DEFS_H
#define _SB1250_DEFS_H
/*
* Cast to 64-bit number. Presumably the syntax is different in
* assembly language.
*
* Note: you'll need to define uint32_t and uint64_t in your headers.
*/
#if !defined(__ASSEMBLER__)
#define _SB_MAKE64(x) ((uint64_t)(x))
#define _SB_MAKE32(x) ((uint32_t)(x))
#else
#define _SB_MAKE64(x) (x)
#define _SB_MAKE32(x) (x)
#endif
/*
* Make a mask for 1 bit at position 'n'
*/
#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
/*
* Make a mask for 'v' bits at position 'n'
*/
#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
/*
* Make a value at 'v' at bit position 'n'
*/
#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n))
#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n))
#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
/*
* Macros to read/write on-chip registers
* XXX should we do the PHYS_TO_K1 here?
*/
#if !defined(__ASSEMBLER__)
#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
#endif /* __ASSEMBLER__ */
#endif
--- NEW FILE: sb1250_dma.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* DMA definitions File: sb1250_dma.h
*
* This module contains constants and macros useful for
* programming the SB1250's DMA controllers, both the data mover
* and the Ethernet DMA.
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_DMA_H
#define _SB1250_DMA_H
#include "sb1250_defs.h"
/* *********************************************************************
* DMA Registers
********************************************************************* */
/*
* Ethernet and Serial DMA Configuration Register 0 (Table 7-4)
* Registers: DMA_CONFIG0_MAC_x_RX_CH_0
* Registers: DMA_CONFIG0_MAC_x_TX_CH_0
* Registers: DMA_CONFIG0_SER_x_RX
* Registers: DMA_CONFIG0_SER_x_TX
*/
#define M_DMA_DROP _SB_MAKEMASK1(0)
#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1)
#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5)
#define M_DMA_TBX_EN _SB_MAKEMASK1(6)
#define M_DMA_TDX_EN _SB_MAKEMASK1(7)
#define S_DMA_INT_PKTCNT _SB_MAKE64(8)
#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT)
#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT)
#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT)
#define S_DMA_RINGSZ _SB_MAKE64(16)
#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ)
#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ)
#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ)
#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK)
#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK)
#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK)
#define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK)
#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK)
#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK)
/*
* Ethernet and Serial DMA Configuration Register 2 (Table 7-5)
* Registers: DMA_CONFIG1_MAC_x_RX_CH_0
* Registers: DMA_CONFIG1_DMA_x_TX_CH_0
* Registers: DMA_CONFIG1_SER_x_RX
* Registers: DMA_CONFIG1_SER_x_TX
*/
#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0)
#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1)
#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2)
#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3)
#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
#define M_DMA_L2CA _SB_MAKEMASK1(5)
#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
#define S_DMA_HDR_SIZE _SB_MAKE64(21)
#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE)
#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE)
#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE)
#define M_DMA_MBZ2 _SB_MAKEMASK(5,32)
#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE)
#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE)
#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE)
#define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT)
#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT)
#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT)
/*
* Ethernet and Serial DMA Descriptor base address (Table 7-6)
*/
#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0)
/*
* ASIC Mode Base Address (Table 7-7)
*/
#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0)
/*
* DMA Descriptor Count Registers (Table 7-8)
*/
/* No bitfields */
/*
* Current Descriptor Address Register (Table 7-11)
*/
#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR)
#define S_DMA_CURDSCR_COUNT _SB_MAKE64(48)
#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
/* *********************************************************************
* DMA Descriptors
********************************************************************* */
/*
* Descriptor doubleword "A" (Table 7-12)
*/
#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET)
/* Note: Don't shift the address over, just mask it with the mask below */
#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR)
#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
#define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS)
#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS)
#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS)
/*
* Descriptor doubleword "B" (Table 7-13)
*/
#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS)
#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
/* Note: Don't shift the address over, just mask it with the mask below */
#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR)
#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE)
#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE)
#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE)
#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE)
#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE)
/*
* Ethernet Descriptor Status Bits (Table 7-15)
*/
#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
#define S_DMA_ETHRX_RXCH 53
#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH)
#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH)
#define S_DMA_ETHRX_PKTTYPE 55
#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE)
#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE)
#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE)
#define K_DMA_ETHRX_PKTTYPE_IPV4 0
#define K_DMA_ETHRX_PKTTYPE_ARPV4 1
#define K_DMA_ETHRX_PKTTYPE_802 2
#define K_DMA_ETHRX_PKTTYPE_OTHER 3
#define K_DMA_ETHRX_PKTTYPE_USER0 4
#define K_DMA_ETHRX_PKTTYPE_USER1 5
#define K_DMA_ETHRX_PKTTYPE_USER2 6
#define K_DMA_ETHRX_PKTTYPE_USER3 7
#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(58)
#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(59)
#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60)
#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61)
#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62)
#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63)
/*
* Ethernet Transmit Status Bits (Table 7-16)
*/
#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63)
/*
* Ethernet Transmit Options (Table 7-17)
*/
#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00)
#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01)
#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02)
#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07)
#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F)
/*
* Serial Receive Options (Table 7-18)
*/
#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56)
#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57)
#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58)
#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
#define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61)
#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62)
#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63)
/*
* Serial Transmit Status Bits (Table 7-20)
*/
#define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63)
/*
* Serial Transmit Options (Table 7-21)
*/
#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0)
#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1)
#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2)
#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3)
/* *********************************************************************
* Data Mover Registers
********************************************************************* */
/*
* Data Mover Descriptor Base Address Register (Table 7-22)
* Register: DM_DSCR_BASE_0
* Register: DM_DSCR_BASE_1
* Register: DM_DSCR_BASE_2
* Register: DM_DSCR_BASE_3
*/
#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(3,0)
/* Note: Just mask the base address and then OR it in. */
#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(3)
#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR)
#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ)
#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ)
#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ)
#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY)
#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY)
#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY)
#define K_DM_DSCR_BASE_PRIORITY_1 0
#define K_DM_DSCR_BASE_PRIORITY_2 1
#define K_DM_DSCR_BASE_PRIORITY_4 2
#define K_DM_DSCR_BASE_PRIORITY_8 3
#define K_DM_DSCR_BASE_PRIORITY_16 4
#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59)
#define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60)
#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */
#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */
#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62)
#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63)
/*
* Data Mover Descriptor Count Register (Table 7-25)
*/
/* no bitfields */
/*
* Data Mover Current Descriptor Address (Table 7-24)
* Register: DM_CUR_DSCR_ADDR_0
* Register: DM_CUR_DSCR_ADDR_1
* Register: DM_CUR_DSCR_ADDR_2
* Register: DM_CUR_DSCR_ADDR_3
*/
#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR)
#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT)
#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT)
#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\
M_DM_CUR_DSCR_DSCR_COUNT)
/*
* Data Mover Descriptor Doubleword "A" (Table 7-26)
*/
#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR)
#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42)
#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43)
#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST)
#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST)
#define K_DM_DSCRA_DIR_DEST_INCR 0
#define K_DM_DSCRA_DIR_DEST_DECR 1
#define K_DM_DSCRA_DIR_DEST_CONST 2
#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST)
#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC)
#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC)
#define K_DM_DSCRA_DIR_SRC_INCR 0
#define K_DM_DSCRA_DIR_SRC_DECR 1
#define K_DM_DSCRA_DIR_SRC_CONST 2
#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC)
#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48)
#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49)
#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(12,52)
/*
* Data Mover Descriptor Doubleword "B" (Table 7-25)
*/
#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR)
#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)
#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH)
#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH)
#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH)
#endif
--- NEW FILE: sb1250_genbus.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* Generic Bus Constants File: sb1250_genbus.h
*
* This module contains constants and macros useful for
* manipulating the SB1250's Generic Bus interface
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_GENBUS_H
#define _SB1250_GENBUS_H
#include "sb1250_defs.h"
/*
* Generic Bus Region Configuration Registers (Table 11-4)
*/
#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(0)
#define M_IO_ENA_RDY _SB_MAKEMASK1(1)
#define S_IO_WIDTH_SEL 2
#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
#define K_IO_WIDTH_SEL_1 0
#define K_IO_WIDTH_SEL_2 1
#define K_IO_WIDTH_SEL_4 3
#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
#define M_IO_PARITY_ENA _SB_MAKEMASK1(4)
#define M_IO_PARITY_ODD _SB_MAKEMASK1(6)
#define M_IO_NONMUX _SB_MAKEMASK1(7)
#define S_IO_TIMEOUT 8
#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT)
#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT)
#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT)
/*
* Generic Bus Region Size register (Table 11-5)
*/
#define S_IO_MULT_SIZE 0
#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE)
#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE)
#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE)
#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */
/*
* Generic Bus Region Address (Table 11-6)
*/
#define S_IO_START_ADDR 0
#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR)
#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR)
#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR)
#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
/*
* Generic Bus Region 0 Timing Registers (Table 11-7)
*/
#define S_IO_ALE_WIDTH 0
#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH)
#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
#define S_IO_ALE_TO_CS 4
#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
#define S_IO_CS_WIDTH 8
#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH)
#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH)
#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH)
#define S_IO_RDY_SMPLE 13
#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE)
#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE)
#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE)
/*
* Generic Bus Timing 1 Registers (Table 11-8)
*/
#define S_IO_ALE_TO_WRITE 0
#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE)
#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
#define S_IO_WRITE_WIDTH 4
#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH)
#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH)
#define S_IO_IDLE_CYCLE 8
#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE)
#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE)
#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE)
#define S_IO_CS_TO_OE 12
#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE)
#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE)
#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
#define S_IO_OE_TO_CS 14
#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS)
#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS)
#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS)
/*
* Generic Bus Interrupt Status Register (Table 11-9)
*/
#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8)
#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3)
#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4)
#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5)
#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6)
#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7)
#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9)
#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
/*
* PCMCIA configuration register (Table 12-6)
*/
#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0)
#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1)
#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2)
#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3)
#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4)
#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5)
#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6)
#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7)
#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
/*
* PCMCIA status register (Table 12-7)
*/
#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0)
#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1)
#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2)
#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3)
#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4)
#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5)
#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6)
#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7)
#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8)
#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9)
#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10)
/*
* GPIO Interrupt Type Register (table 13-3)
*/
#define K_GPIO_INTR_DISABLE 0
#define K_GPIO_INTR_EDGE 1
#define K_GPIO_INTR_LEVEL 2
#define K_GPIO_INTR_SPLIT 3
#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2)
#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n))
#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n))
#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n))
#define S_GPIO_INTR_TYPE0 0
#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0)
#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0)
#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0)
#define S_GPIO_INTR_TYPE2 2
#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2)
#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2)
#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2)
#define S_GPIO_INTR_TYPE4 4
#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4)
#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4)
#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4)
#define S_GPIO_INTR_TYPE6 6
#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6)
#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6)
#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6)
#define S_GPIO_INTR_TYPE8 8
#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8)
#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8)
#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8)
#define S_GPIO_INTR_TYPE10 10
#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10)
#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10)
#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10)
#define S_GPIO_INTR_TYPE12 12
#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12)
#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12)
#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12)
#define S_GPIO_INTR_TYPE14 14
#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14)
#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
#endif
--- NEW FILE: sb1250_int.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* Interrupt Mapper definitions File: sb1250_int.h
*
* This module contains constants for manipulating the SB1250's
* interrupt mapper and definitions for the interrupt sources.
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_INT_H
#define _SB1250_INT_H
#include "sb1250_defs.h"
/* *********************************************************************
* Interrupt Mapper Constants
********************************************************************* */
/*
* Interrupt sources (Table 4-8, UM 0.2)
*
* First, the interrupt numbers.
*/
#define K_INT_WATCHDOG_TIMER_0 0
#define K_INT_WATCHDOG_TIMER_1 1
#define K_INT_TIMER_0 2
#define K_INT_TIMER_1 3
#define K_INT_TIMER_2 4
#define K_INT_TIMER_3 5
#define K_INT_SMB_0 6
#define K_INT_SMB_1 7
#define K_INT_UART_0 8
#define K_INT_UART_1 9
#define K_INT_SER_0 10
#define K_INT_SER_1 11
#define K_INT_PCMCIA 12
#define K_INT_ADDR_TRAP 13
#define K_INT_PERF_CNT 14
#define K_INT_TRACE_FREEZE 15
#define K_INT_BAD_ECC 16
#define K_INT_COR_ECC 17
#define K_INT_IO_BUS 18
#define K_INT_MAC_0 19
#define K_INT_MAC_1 20
#define K_INT_MAC_2 21
#define K_INT_DM_CH_0 22
#define K_INT_DM_CH_1 23
#define K_INT_DM_CH_2 24
#define K_INT_DM_CH_3 25
#define K_INT_MBOX_0 26
#define K_INT_MBOX_1 27
#define K_INT_MBOX_2 28
#define K_INT_MBOX_3 29
#define K_INT_SPARE_0 30
#define K_INT_SPARE_1 31
#define K_INT_GPIO_0 32
#define K_INT_GPIO_1 33
#define K_INT_GPIO_2 34
#define K_INT_GPIO_3 35
#define K_INT_GPIO_4 36
#define K_INT_GPIO_5 37
#define K_INT_GPIO_6 38
#define K_INT_GPIO_7 39
#define K_INT_GPIO_8 40
#define K_INT_GPIO_9 41
#define K_INT_GPIO_10 42
#define K_INT_GPIO_11 43
#define K_INT_GPIO_12 44
#define K_INT_GPIO_13 45
#define K_INT_GPIO_14 46
#define K_INT_GPIO_15 47
#define K_INT_LDT_FATAL 48
#define K_INT_LDT_NONFATAL 49
#define K_INT_LDT_SMI 50
#define K_INT_LDT_NMI 51
#define K_INT_LDT_INIT 52
#define K_INT_LDT_STARTUP 53
#define K_INT_LDT_EXT 54
#define K_INT_PCI_ERROR 55
#define K_INT_PCI_INTA 56
#define K_INT_PCI_INTB 57
#define K_INT_PCI_INTC 58
#define K_INT_PCI_INTD 59
#define K_INT_SPARE_2 60
#define K_INT_SPARE_3 61
#define K_INT_SPARE_4 62
#define K_INT_SPARE_5 63
/*
* Mask values for each interrupt
*/
#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
#define M_INT_SPARE_0 _SB_MAKEMASK1(K_INT_SPARE_0)
#define M_INT_SPARE_1 _SB_MAKEMASK1(K_INT_SPARE_1)
#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
#define M_INT_SPARE_3 _SB_MAKEMASK1(K_INT_SPARE_3)
#define M_INT_SPARE_4 _SB_MAKEMASK1(K_INT_SPARE_4)
#define M_INT_SPARE_5 _SB_MAKEMASK1(K_INT_SPARE_5)
/*
* Interrupt mappings
*/
#define K_INT_MAP_I0 0 /* interrupt pins on processor */
#define K_INT_MAP_I1 1
#define K_INT_MAP_I2 2
#define K_INT_MAP_I3 3
#define K_INT_MAP_I4 4
#define K_INT_MAP_I5 5
#define K_INT_MAP_NMI 6 /* nonmaskable */
#define K_INT_MAP_DINT 7 /* debug interrupt */
/*
* LDT Interrupt Set Register (table 4-5)
*/
#define S_INT_LDT_INTMSG 0
#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
#define K_INT_LDT_INTMSG_FIXED 0
#define K_INT_LDT_INTMSG_ARBITRATED 1
#define K_INT_LDT_INTMSG_SMI 2
#define K_INT_LDT_INTMSG_NMI 3
#define K_INT_LDT_INTMSG_INIT 4
#define K_INT_LDT_INTMSG_STARTUP 5
#define K_INT_LDT_INTMSG_EXTINT 6
#define K_INT_LDT_INTMSG_RESERVED 7
#define M_INT_LDT_EDGETRIGGER 0
#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
#define M_INT_LDT_PHYSICALDEST 0
#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
#define S_INT_LDT_INTDEST 5
#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
#define S_INT_LDT_VECTOR 13
#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
/*
* Vector format (Table 4-6)
*/
#define M_LDTVECT_RAISEINT 0x00
#define M_LDTVECT_RAISEMBOX 0x40
#endif
--- NEW FILE: sb1250_l2c.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* L2 Cache constants and macros File: sb1250_l2c.h
*
* This module contains constants useful for manipulating the
* level 2 cache.
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_L2C_H
#define _SB1250_L2C_H
#include "sb1250_defs.h"
/*
* Level 2 Cache Tag register (Table 5-3)
*/
#define S_L2C_TAG_MBZ 0
#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ)
#define S_L2C_TAG_INDEX 5
#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX)
#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX)
#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX)
#define S_L2C_TAG_TAG 17
#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG)
#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG)
#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG)
#define S_L2C_TAG_ECC 40
#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC)
#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC)
#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC)
#define S_L2C_TAG_WAY 46
#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY)
#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY)
#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY)
#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
/*
* Format of level 2 cache management address (table 5-2)
*/
#define S_L2C_MGMT_INDEX 5
#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX)
#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX)
#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX)
#define S_L2C_MGMT_WAY 17
#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY)
#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY)
#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY)
#define S_L2C_MGMT_TAG 21
#define M_L2C_MGMT_TAG _SB_MAKEMASK(6,S_L2C_MGMT_TAG)
#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG)
#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG)
#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
#define A_L2C_MGMT_TAG_BASE 0x00D0000000
#define L2C_ENTRIES_PER_WAY 4096
#define L2C_NUM_WAYS 4
#endif
--- NEW FILE: sb1250_ldt.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* LDT constants File: sb1250_ldt.h
*
* This module contains constants and macros to describe
* the LDT interface on the SB1250.
*
* SB1250 specification level: 0.2 plus errata
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_LDT_H
#define _SB1250_LDT_H
#include "sb1250_defs.h"
#define K_LDT_VENDOR_SIBYTE 0x166D
#define K_LDT_DEVICE_SB1250 0x0002
/*
* LDT Interface Type 1 (bridge) configuration header
*/
#define R_LDT_TYPE1_DEVICEID 0x0000
#define R_LDT_TYPE1_CMDSTATUS 0x0004
#define R_LDT_TYPE1_CLASSREV 0x0008
#define R_LDT_TYPE1_DEVHDR 0x000C
#define R_LDT_TYPE1_BAR0 0x0010 /* not used */
#define R_LDT_TYPE1_BAR1 0x0014 /* not used */
#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */
#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */
#define R_LDT_TYPE1_MEMLIMIT 0x0020
#define R_LDT_TYPE1_PREFETCH 0x0024
#define R_LDT_TYPE1_PREF_BASE 0x0028
#define R_LDT_TYPE1_PREF_LIMIT 0x002C
#define R_LDT_TYPE1_IOLIMIT 0x0030
#define R_LDT_TYPE1_CAPPTR 0x0034
#define R_LDT_TYPE1_ROMADDR 0x0038
#define R_LDT_TYPE1_BRCTL 0x003C
#define R_LDT_TYPE1_CMD 0x0040
#define R_LDT_TYPE1_LINKCTRL 0x0044
#define R_LDT_TYPE1_LINKFREQ 0x0048
#define R_LDT_TYPE1_RESERVED1 0x004C
#define R_LDT_TYPE1_SRICMD 0x0050
#define R_LDT_TYPE1_SRITXNUM 0x0054
#define R_LDT_TYPE1_SRIRXNUM 0x0058
#define R_LDT_TYPE1_ERRSTATUS 0x0068
#define R_LDT_TYPE1_SRICTRL 0x006C
#define R_LDT_TYPE1_TXBUFCNT 0x00C8
#define R_LDT_TYPE1_EXPCRC 0x00DC
#define R_LDT_TYPE1_RXCRC 0x00F0
/*
* LDT Device ID register
*/
#define S_LDT_DEVICEID_VENDOR 0
#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR)
#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR)
#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR)
#define S_LDT_DEVICEID_DEVICEID 16
#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID)
#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID)
#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID)
/*
* LDT Command Register (Table 8-13)
*/
#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0)
#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1)
#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2)
#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3)
#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5)
#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6)
#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7)
#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8)
#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9)
/*
* LDT class and revision registers
*/
#define S_LDT_CLASSREV_REV 0
#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV)
#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV)
#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV)
#define S_LDT_CLASSREV_CLASS 8
#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS)
#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS)
#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS)
#define K_LDT_REV 0x01
#define K_LDT_CLASS 0x060000
/*
* Device Header (offset 0x0C)
*/
#define S_LDT_DEVHDR_CLINESZ 0
#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ)
#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ)
#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ)
#define S_LDT_DEVHDR_LATTMR 8
#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR)
#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR)
#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR)
#define S_LDT_DEVHDR_HDRTYPE 16
#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE)
#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE)
#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE)
#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
#define S_LDT_DEVHDR_BIST 24
#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST)
#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST)
#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST)
/*
* LDT Status Register (Table 8-14). Note that these constants
* assume you've read the command and status register
* together (32-bit read at offset 0x04)
*
* These bits also apply to the secondary status
* register (Table 8-15), offset 0x1C
*/
#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23)
#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
#define S_LDT_STATUS_DEVSELTIMING 25
#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING)
#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING)
#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING)
#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29)
#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30)
#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
/*
* Bridge Control Register (Table 8-16). Note that these
* constants assume you've read the register as a 32-bit
* read (offset 0x3C)
*/
#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16)
#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17)
#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18)
#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19)
#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21)
#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22)
#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23)
#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24)
#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25)
#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26)
#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27)
/*
* LDT Command Register (Table 8-17). Note that these constants
* assume you've read the command and status register together
* 32-bit read at offset 0x40
*/
#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16)
#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
#define S_LDT_CMD_CAPTYPE 29
#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE)
#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE)
#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE)
/*
* LDT link control register (Table 8-18), and (Table 8-19)
*/
#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1)
#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2)
#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3)
#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4)
#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5)
#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6)
#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
#define S_LDT_LINKCTRL_CRCERR 8
#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR)
#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR)
#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR)
#define S_LDT_LINKCTRL_MAXIN 16
#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN)
#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN)
#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN)
#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
#define S_LDT_LINKCTRL_MAXOUT 20
#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT)
#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT)
#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT)
#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
#define S_LDT_LINKCTRL_WIDTHIN 24
#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN)
#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN)
#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN)
#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
#define S_LDT_LINKCTRL_WIDTHOUT 28
#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT)
#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT)
#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT)
#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
/*
* LDT Link frequency register (Table 8-20) offset 0x48
*/
#define S_LDT_LINKFREQ_FREQ 8
#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ)
#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ)
#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ)
#define K_LDT_LINKFREQ_200MHZ 0
#define K_LDT_LINKFREQ_300MHZ 1
#define K_LDT_LINKFREQ_400MHZ 2
#define K_LDT_LINKFREQ_500MHZ 3
#define K_LDT_LINKFREQ_600MHZ 4
#define K_LDT_LINKFREQ_800MHZ 5
#define K_LDT_LINKFREQ_1000MHZ 6
/*
* LDT SRI Command Register (Table 8-21). Note that these constants
* assume you've read the command and status register together
* 32-bit read at offset 0x50
*/
#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16)
#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17)
#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18)
#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19)
#define S_LDT_SRICMD_RXMARGIN 20
#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN)
#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN)
#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN)
#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
#define S_LDT_SRICMD_TXINITIALOFFSET 28
#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET)
#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET)
#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET)
#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
/*
* LDT Error control and status register (Table 8-22) (Table 8-23)
*/
#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0)
#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1)
#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2)
#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3)
#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4)
#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5)
#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6)
#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)
#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9)
#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10)
#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11)
#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12)
#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)
#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15)
#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)
#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
#define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24)
#define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25)
#define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26)
#define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27)
#define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28)
/*
* SRI Control register (Table 8-24, 8-25) Offset 0x6C
*/
#define S_LDT_SRICTRL_NEEDRESP 0
#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP)
#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP)
#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP)
#define S_LDT_SRICTRL_NEEDNPREQ 2
#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ)
#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ)
#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ)
#define S_LDT_SRICTRL_NEEDPREQ 4
#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEM...
[truncated message content] |
|
From: James S. <jsi...@us...> - 2001-11-08 17:28:28
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv4111/asm-mips/sibyte
Added Files:
64bit.h sb1250.h sb1250_defs.h sb1250_dma.h sb1250_genbus.h
sb1250_int.h sb1250_l2c.h sb1250_ldt.h sb1250_mac.h
sb1250_mc.h sb1250_pci.h sb1250_prof.h sb1250_regs.h
sb1250_scd.h sb1250_smbus.h sb1250_syncser.h sb1250_uart.h
sbmips.h swarm.h
Log Message:
More Sibyte bulk merging.
--- NEW FILE: 64bit.h ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _SB1_64BIT_H
#define _SB1_64BIT_H
#include <asm/system.h>
/* This is annoying...we can't actually write the 64-bit IO
register properly without having access to 64-bit registers...
which doesn't work by default in o32 format...grrr...*/
extern inline void out64(u64 val, unsigned long addr)
{
u32 low, high;
unsigned long flags;
high = val >> 32;
low = val & 0xffffffff;
// save_flags(flags);
__save_and_cli(flags);
__asm__ __volatile__ (
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n"
" dsll32 $2, %1, 0 \n"
" dsll32 $1, %0, 0 \n"
" dsrl32 $2, $2, 0 \n"
" or $1, $1, $2 \n"
" sd $1, (%2)\n"
".set pop\n"
::"r" (high), "r" (low), "r" (addr)
:"$1", "$2");
__restore_flags(flags);
}
extern inline u64 in64(unsigned long addr)
{
u32 low, high;
unsigned long flags;
__save_and_cli(flags);
__asm__ __volatile__ (
".set push\n"
".set noreorder\n"
".set noat \n"
".set mips4 \n"
" ld %1, (%2)\n"
" dsra32 %0, %1, 0\n"
" sll %1, %1, 0\n"
".set pop\n"
:"=r" (high), "=r" (low): "r" (addr));
__restore_flags(flags);
return (((u64)high) << 32) | low;
}
#endif
--- NEW FILE: sb1250.h ---
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _ASM_SIBYTE_SB1250_H
#define _ASM_SIBYTE_SB1250_H
extern void sb1250_time_init(void);
extern void sb1250_mask_irq(int cpu, int irq);
extern void sb1250_unmask_irq(int cpu, int irq);
extern void sb1250_smp_finish(void);
#define IO_SPACE_BASE 0xa0000000UL
#endif
--- NEW FILE: sb1250_defs.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* Global constants and macros File: sb1250_defs.h
*
* This file contains macros and definitions used by the other
* include files.
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
/* *********************************************************************
* Naming schemes for constants in these files:
*
* M_xxx MASK constant (identifies bits in a register).
* For multi-bit fields, all bits in the field will
* be set.
*
* K_xxx "Code" constant (value for data in a multi-bit
* field). The value is right justified.
*
* V_xxx "Value" constant. This is the same as the
* corresponding "K_xxx" constant, except it is
* shifted to the correct position in the register.
*
* S_xxx SHIFT constant. This is the number of bits that
* a field value (code) needs to be shifted
* (towards the left) to put the value in the right
* position for the register.
*
* A_xxx ADDRESS constant. This will be a physical
* address. Use the PHYS_TO_K1 macro to generate
* a K1SEG address.
*
* R_xxx RELATIVE offset constant. This is an offset from
* an A_xxx constant (usually the first register in
* a group).
*
* G_xxx(X) GET value. This macro obtains a multi-bit field
* from a register, masks it, and shifts it to
* the bottom of the register (retrieving a K_xxx
* value, for example).
*
* V_xxx(X) VALUE. This macro computes the value of a
* K_xxx constant shifted to the correct position
* in the register.
********************************************************************* */
#ifndef _SB1250_DEFS_H
#define _SB1250_DEFS_H
/*
* Cast to 64-bit number. Presumably the syntax is different in
* assembly language.
*
* Note: you'll need to define uint32_t and uint64_t in your headers.
*/
#if !defined(__ASSEMBLER__)
#define _SB_MAKE64(x) ((uint64_t)(x))
#define _SB_MAKE32(x) ((uint32_t)(x))
#else
#define _SB_MAKE64(x) (x)
#define _SB_MAKE32(x) (x)
#endif
/*
* Make a mask for 1 bit at position 'n'
*/
#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
/*
* Make a mask for 'v' bits at position 'n'
*/
#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
/*
* Make a value at 'v' at bit position 'n'
*/
#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n))
#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n))
#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
/*
* Macros to read/write on-chip registers
* XXX should we do the PHYS_TO_K1 here?
*/
#if !defined(__ASSEMBLER__)
#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
#endif /* __ASSEMBLER__ */
#endif
--- NEW FILE: sb1250_dma.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* DMA definitions File: sb1250_dma.h
*
* This module contains constants and macros useful for
* programming the SB1250's DMA controllers, both the data mover
* and the Ethernet DMA.
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_DMA_H
#define _SB1250_DMA_H
#include "sb1250_defs.h"
/* *********************************************************************
* DMA Registers
********************************************************************* */
/*
* Ethernet and Serial DMA Configuration Register 0 (Table 7-4)
* Registers: DMA_CONFIG0_MAC_x_RX_CH_0
* Registers: DMA_CONFIG0_MAC_x_TX_CH_0
* Registers: DMA_CONFIG0_SER_x_RX
* Registers: DMA_CONFIG0_SER_x_TX
*/
#define M_DMA_DROP _SB_MAKEMASK1(0)
#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1)
#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5)
#define M_DMA_TBX_EN _SB_MAKEMASK1(6)
#define M_DMA_TDX_EN _SB_MAKEMASK1(7)
#define S_DMA_INT_PKTCNT _SB_MAKE64(8)
#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT)
#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT)
#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT)
#define S_DMA_RINGSZ _SB_MAKE64(16)
#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ)
#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ)
#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ)
#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK)
#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK)
#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK)
#define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK)
#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK)
#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK)
/*
* Ethernet and Serial DMA Configuration Register 2 (Table 7-5)
* Registers: DMA_CONFIG1_MAC_x_RX_CH_0
* Registers: DMA_CONFIG1_DMA_x_TX_CH_0
* Registers: DMA_CONFIG1_SER_x_RX
* Registers: DMA_CONFIG1_SER_x_TX
*/
#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0)
#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1)
#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2)
#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3)
#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
#define M_DMA_L2CA _SB_MAKEMASK1(5)
#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
#define S_DMA_HDR_SIZE _SB_MAKE64(21)
#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE)
#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE)
#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE)
#define M_DMA_MBZ2 _SB_MAKEMASK(5,32)
#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE)
#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE)
#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE)
#define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT)
#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT)
#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT)
/*
* Ethernet and Serial DMA Descriptor base address (Table 7-6)
*/
#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0)
/*
* ASIC Mode Base Address (Table 7-7)
*/
#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0)
/*
* DMA Descriptor Count Registers (Table 7-8)
*/
/* No bitfields */
/*
* Current Descriptor Address Register (Table 7-11)
*/
#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR)
#define S_DMA_CURDSCR_COUNT _SB_MAKE64(48)
#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
/* *********************************************************************
* DMA Descriptors
********************************************************************* */
/*
* Descriptor doubleword "A" (Table 7-12)
*/
#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET)
/* Note: Don't shift the address over, just mask it with the mask below */
#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR)
#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
#define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS)
#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS)
#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS)
/*
* Descriptor doubleword "B" (Table 7-13)
*/
#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS)
#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
/* Note: Don't shift the address over, just mask it with the mask below */
#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR)
#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE)
#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE)
#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE)
#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE)
#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE)
/*
* Ethernet Descriptor Status Bits (Table 7-15)
*/
#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
#define S_DMA_ETHRX_RXCH 53
#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH)
#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH)
#define S_DMA_ETHRX_PKTTYPE 55
#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE)
#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE)
#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE)
#define K_DMA_ETHRX_PKTTYPE_IPV4 0
#define K_DMA_ETHRX_PKTTYPE_ARPV4 1
#define K_DMA_ETHRX_PKTTYPE_802 2
#define K_DMA_ETHRX_PKTTYPE_OTHER 3
#define K_DMA_ETHRX_PKTTYPE_USER0 4
#define K_DMA_ETHRX_PKTTYPE_USER1 5
#define K_DMA_ETHRX_PKTTYPE_USER2 6
#define K_DMA_ETHRX_PKTTYPE_USER3 7
#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(58)
#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(59)
#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60)
#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61)
#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62)
#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63)
/*
* Ethernet Transmit Status Bits (Table 7-16)
*/
#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63)
/*
* Ethernet Transmit Options (Table 7-17)
*/
#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00)
#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01)
#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02)
#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07)
#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F)
/*
* Serial Receive Options (Table 7-18)
*/
#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56)
#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57)
#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58)
#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
#define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61)
#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62)
#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63)
/*
* Serial Transmit Status Bits (Table 7-20)
*/
#define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63)
/*
* Serial Transmit Options (Table 7-21)
*/
#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0)
#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1)
#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2)
#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3)
/* *********************************************************************
* Data Mover Registers
********************************************************************* */
/*
* Data Mover Descriptor Base Address Register (Table 7-22)
* Register: DM_DSCR_BASE_0
* Register: DM_DSCR_BASE_1
* Register: DM_DSCR_BASE_2
* Register: DM_DSCR_BASE_3
*/
#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(3,0)
/* Note: Just mask the base address and then OR it in. */
#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(3)
#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR)
#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ)
#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ)
#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ)
#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY)
#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY)
#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY)
#define K_DM_DSCR_BASE_PRIORITY_1 0
#define K_DM_DSCR_BASE_PRIORITY_2 1
#define K_DM_DSCR_BASE_PRIORITY_4 2
#define K_DM_DSCR_BASE_PRIORITY_8 3
#define K_DM_DSCR_BASE_PRIORITY_16 4
#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59)
#define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60)
#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */
#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */
#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62)
#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63)
/*
* Data Mover Descriptor Count Register (Table 7-25)
*/
/* no bitfields */
/*
* Data Mover Current Descriptor Address (Table 7-24)
* Register: DM_CUR_DSCR_ADDR_0
* Register: DM_CUR_DSCR_ADDR_1
* Register: DM_CUR_DSCR_ADDR_2
* Register: DM_CUR_DSCR_ADDR_3
*/
#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR)
#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT)
#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT)
#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\
M_DM_CUR_DSCR_DSCR_COUNT)
/*
* Data Mover Descriptor Doubleword "A" (Table 7-26)
*/
#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR)
#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42)
#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43)
#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST)
#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST)
#define K_DM_DSCRA_DIR_DEST_INCR 0
#define K_DM_DSCRA_DIR_DEST_DECR 1
#define K_DM_DSCRA_DIR_DEST_CONST 2
#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST)
#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC)
#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC)
#define K_DM_DSCRA_DIR_SRC_INCR 0
#define K_DM_DSCRA_DIR_SRC_DECR 1
#define K_DM_DSCRA_DIR_SRC_CONST 2
#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC)
#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48)
#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49)
#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(12,52)
/*
* Data Mover Descriptor Doubleword "B" (Table 7-25)
*/
#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR)
#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)
#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH)
#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH)
#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH)
#endif
--- NEW FILE: sb1250_genbus.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* Generic Bus Constants File: sb1250_genbus.h
*
* This module contains constants and macros useful for
* manipulating the SB1250's Generic Bus interface
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_GENBUS_H
#define _SB1250_GENBUS_H
#include "sb1250_defs.h"
/*
* Generic Bus Region Configuration Registers (Table 11-4)
*/
#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(0)
#define M_IO_ENA_RDY _SB_MAKEMASK1(1)
#define S_IO_WIDTH_SEL 2
#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
#define K_IO_WIDTH_SEL_1 0
#define K_IO_WIDTH_SEL_2 1
#define K_IO_WIDTH_SEL_4 3
#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
#define M_IO_PARITY_ENA _SB_MAKEMASK1(4)
#define M_IO_PARITY_ODD _SB_MAKEMASK1(6)
#define M_IO_NONMUX _SB_MAKEMASK1(7)
#define S_IO_TIMEOUT 8
#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT)
#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT)
#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT)
/*
* Generic Bus Region Size register (Table 11-5)
*/
#define S_IO_MULT_SIZE 0
#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE)
#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE)
#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE)
#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */
/*
* Generic Bus Region Address (Table 11-6)
*/
#define S_IO_START_ADDR 0
#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR)
#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR)
#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR)
#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
/*
* Generic Bus Region 0 Timing Registers (Table 11-7)
*/
#define S_IO_ALE_WIDTH 0
#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH)
#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
#define S_IO_ALE_TO_CS 4
#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
#define S_IO_CS_WIDTH 8
#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH)
#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH)
#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH)
#define S_IO_RDY_SMPLE 13
#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE)
#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE)
#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE)
/*
* Generic Bus Timing 1 Registers (Table 11-8)
*/
#define S_IO_ALE_TO_WRITE 0
#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE)
#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
#define S_IO_WRITE_WIDTH 4
#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH)
#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH)
#define S_IO_IDLE_CYCLE 8
#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE)
#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE)
#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE)
#define S_IO_CS_TO_OE 12
#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE)
#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE)
#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
#define S_IO_OE_TO_CS 14
#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS)
#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS)
#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS)
/*
* Generic Bus Interrupt Status Register (Table 11-9)
*/
#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8)
#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3)
#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4)
#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5)
#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6)
#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7)
#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9)
#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
/*
* PCMCIA configuration register (Table 12-6)
*/
#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0)
#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1)
#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2)
#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3)
#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4)
#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5)
#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6)
#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7)
#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
/*
* PCMCIA status register (Table 12-7)
*/
#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0)
#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1)
#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2)
#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3)
#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4)
#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5)
#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6)
#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7)
#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8)
#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9)
#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10)
/*
* GPIO Interrupt Type Register (table 13-3)
*/
#define K_GPIO_INTR_DISABLE 0
#define K_GPIO_INTR_EDGE 1
#define K_GPIO_INTR_LEVEL 2
#define K_GPIO_INTR_SPLIT 3
#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2)
#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n))
#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n))
#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n))
#define S_GPIO_INTR_TYPE0 0
#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0)
#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0)
#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0)
#define S_GPIO_INTR_TYPE2 2
#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2)
#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2)
#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2)
#define S_GPIO_INTR_TYPE4 4
#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4)
#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4)
#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4)
#define S_GPIO_INTR_TYPE6 6
#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6)
#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6)
#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6)
#define S_GPIO_INTR_TYPE8 8
#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8)
#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8)
#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8)
#define S_GPIO_INTR_TYPE10 10
#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10)
#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10)
#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10)
#define S_GPIO_INTR_TYPE12 12
#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12)
#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12)
#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12)
#define S_GPIO_INTR_TYPE14 14
#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14)
#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
#endif
--- NEW FILE: sb1250_int.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* Interrupt Mapper definitions File: sb1250_int.h
*
* This module contains constants for manipulating the SB1250's
* interrupt mapper and definitions for the interrupt sources.
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_INT_H
#define _SB1250_INT_H
#include "sb1250_defs.h"
/* *********************************************************************
* Interrupt Mapper Constants
********************************************************************* */
/*
* Interrupt sources (Table 4-8, UM 0.2)
*
* First, the interrupt numbers.
*/
#define K_INT_WATCHDOG_TIMER_0 0
#define K_INT_WATCHDOG_TIMER_1 1
#define K_INT_TIMER_0 2
#define K_INT_TIMER_1 3
#define K_INT_TIMER_2 4
#define K_INT_TIMER_3 5
#define K_INT_SMB_0 6
#define K_INT_SMB_1 7
#define K_INT_UART_0 8
#define K_INT_UART_1 9
#define K_INT_SER_0 10
#define K_INT_SER_1 11
#define K_INT_PCMCIA 12
#define K_INT_ADDR_TRAP 13
#define K_INT_PERF_CNT 14
#define K_INT_TRACE_FREEZE 15
#define K_INT_BAD_ECC 16
#define K_INT_COR_ECC 17
#define K_INT_IO_BUS 18
#define K_INT_MAC_0 19
#define K_INT_MAC_1 20
#define K_INT_MAC_2 21
#define K_INT_DM_CH_0 22
#define K_INT_DM_CH_1 23
#define K_INT_DM_CH_2 24
#define K_INT_DM_CH_3 25
#define K_INT_MBOX_0 26
#define K_INT_MBOX_1 27
#define K_INT_MBOX_2 28
#define K_INT_MBOX_3 29
#define K_INT_SPARE_0 30
#define K_INT_SPARE_1 31
#define K_INT_GPIO_0 32
#define K_INT_GPIO_1 33
#define K_INT_GPIO_2 34
#define K_INT_GPIO_3 35
#define K_INT_GPIO_4 36
#define K_INT_GPIO_5 37
#define K_INT_GPIO_6 38
#define K_INT_GPIO_7 39
#define K_INT_GPIO_8 40
#define K_INT_GPIO_9 41
#define K_INT_GPIO_10 42
#define K_INT_GPIO_11 43
#define K_INT_GPIO_12 44
#define K_INT_GPIO_13 45
#define K_INT_GPIO_14 46
#define K_INT_GPIO_15 47
#define K_INT_LDT_FATAL 48
#define K_INT_LDT_NONFATAL 49
#define K_INT_LDT_SMI 50
#define K_INT_LDT_NMI 51
#define K_INT_LDT_INIT 52
#define K_INT_LDT_STARTUP 53
#define K_INT_LDT_EXT 54
#define K_INT_PCI_ERROR 55
#define K_INT_PCI_INTA 56
#define K_INT_PCI_INTB 57
#define K_INT_PCI_INTC 58
#define K_INT_PCI_INTD 59
#define K_INT_SPARE_2 60
#define K_INT_SPARE_3 61
#define K_INT_SPARE_4 62
#define K_INT_SPARE_5 63
/*
* Mask values for each interrupt
*/
#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
#define M_INT_SPARE_0 _SB_MAKEMASK1(K_INT_SPARE_0)
#define M_INT_SPARE_1 _SB_MAKEMASK1(K_INT_SPARE_1)
#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
#define M_INT_SPARE_3 _SB_MAKEMASK1(K_INT_SPARE_3)
#define M_INT_SPARE_4 _SB_MAKEMASK1(K_INT_SPARE_4)
#define M_INT_SPARE_5 _SB_MAKEMASK1(K_INT_SPARE_5)
/*
* Interrupt mappings
*/
#define K_INT_MAP_I0 0 /* interrupt pins on processor */
#define K_INT_MAP_I1 1
#define K_INT_MAP_I2 2
#define K_INT_MAP_I3 3
#define K_INT_MAP_I4 4
#define K_INT_MAP_I5 5
#define K_INT_MAP_NMI 6 /* nonmaskable */
#define K_INT_MAP_DINT 7 /* debug interrupt */
/*
* LDT Interrupt Set Register (table 4-5)
*/
#define S_INT_LDT_INTMSG 0
#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
#define K_INT_LDT_INTMSG_FIXED 0
#define K_INT_LDT_INTMSG_ARBITRATED 1
#define K_INT_LDT_INTMSG_SMI 2
#define K_INT_LDT_INTMSG_NMI 3
#define K_INT_LDT_INTMSG_INIT 4
#define K_INT_LDT_INTMSG_STARTUP 5
#define K_INT_LDT_INTMSG_EXTINT 6
#define K_INT_LDT_INTMSG_RESERVED 7
#define M_INT_LDT_EDGETRIGGER 0
#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
#define M_INT_LDT_PHYSICALDEST 0
#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
#define S_INT_LDT_INTDEST 5
#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
#define S_INT_LDT_VECTOR 13
#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
/*
* Vector format (Table 4-6)
*/
#define M_LDTVECT_RAISEINT 0x00
#define M_LDTVECT_RAISEMBOX 0x40
#endif
--- NEW FILE: sb1250_l2c.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* L2 Cache constants and macros File: sb1250_l2c.h
*
* This module contains constants useful for manipulating the
* level 2 cache.
*
* SB1250 specification level: 0.2
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_L2C_H
#define _SB1250_L2C_H
#include "sb1250_defs.h"
/*
* Level 2 Cache Tag register (Table 5-3)
*/
#define S_L2C_TAG_MBZ 0
#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ)
#define S_L2C_TAG_INDEX 5
#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX)
#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX)
#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX)
#define S_L2C_TAG_TAG 17
#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG)
#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG)
#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG)
#define S_L2C_TAG_ECC 40
#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC)
#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC)
#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC)
#define S_L2C_TAG_WAY 46
#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY)
#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY)
#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY)
#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
/*
* Format of level 2 cache management address (table 5-2)
*/
#define S_L2C_MGMT_INDEX 5
#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX)
#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX)
#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX)
#define S_L2C_MGMT_WAY 17
#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY)
#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY)
#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY)
#define S_L2C_MGMT_TAG 21
#define M_L2C_MGMT_TAG _SB_MAKEMASK(6,S_L2C_MGMT_TAG)
#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG)
#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG)
#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
#define A_L2C_MGMT_TAG_BASE 0x00D0000000
#define L2C_ENTRIES_PER_WAY 4096
#define L2C_NUM_WAYS 4
#endif
--- NEW FILE: sb1250_ldt.h ---
/* *********************************************************************
* SB1250 Board Support Package
*
* LDT constants File: sb1250_ldt.h
*
* This module contains constants and macros to describe
* the LDT interface on the SB1250.
*
* SB1250 specification level: 0.2 plus errata
*
* Author: Mitch Lichtenberg (mi...@si...)
*
*********************************************************************
*
* Copyright 2000,2001
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_LDT_H
#define _SB1250_LDT_H
#include "sb1250_defs.h"
#define K_LDT_VENDOR_SIBYTE 0x166D
#define K_LDT_DEVICE_SB1250 0x0002
/*
* LDT Interface Type 1 (bridge) configuration header
*/
#define R_LDT_TYPE1_DEVICEID 0x0000
#define R_LDT_TYPE1_CMDSTATUS 0x0004
#define R_LDT_TYPE1_CLASSREV 0x0008
#define R_LDT_TYPE1_DEVHDR 0x000C
#define R_LDT_TYPE1_BAR0 0x0010 /* not used */
#define R_LDT_TYPE1_BAR1 0x0014 /* not used */
#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */
#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */
#define R_LDT_TYPE1_MEMLIMIT 0x0020
#define R_LDT_TYPE1_PREFETCH 0x0024
#define R_LDT_TYPE1_PREF_BASE 0x0028
#define R_LDT_TYPE1_PREF_LIMIT 0x002C
#define R_LDT_TYPE1_IOLIMIT 0x0030
#define R_LDT_TYPE1_CAPPTR 0x0034
#define R_LDT_TYPE1_ROMADDR 0x0038
#define R_LDT_TYPE1_BRCTL 0x003C
#define R_LDT_TYPE1_CMD 0x0040
#define R_LDT_TYPE1_LINKCTRL 0x0044
#define R_LDT_TYPE1_LINKFREQ 0x0048
#define R_LDT_TYPE1_RESERVED1 0x004C
#define R_LDT_TYPE1_SRICMD 0x0050
#define R_LDT_TYPE1_SRITXNUM 0x0054
#define R_LDT_TYPE1_SRIRXNUM 0x0058
#define R_LDT_TYPE1_ERRSTATUS 0x0068
#define R_LDT_TYPE1_SRICTRL 0x006C
#define R_LDT_TYPE1_TXBUFCNT 0x00C8
#define R_LDT_TYPE1_EXPCRC 0x00DC
#define R_LDT_TYPE1_RXCRC 0x00F0
/*
* LDT Device ID register
*/
#define S_LDT_DEVICEID_VENDOR 0
#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR)
#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR)
#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR)
#define S_LDT_DEVICEID_DEVICEID 16
#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID)
#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID)
#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID)
/*
* LDT Command Register (Table 8-13)
*/
#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0)
#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1)
#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2)
#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3)
#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5)
#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6)
#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7)
#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8)
#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9)
/*
* LDT class and revision registers
*/
#define S_LDT_CLASSREV_REV 0
#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV)
#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV)
#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV)
#define S_LDT_CLASSREV_CLASS 8
#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS)
#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS)
#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS)
#define K_LDT_REV 0x01
#define K_LDT_CLASS 0x060000
/*
* Device Header (offset 0x0C)
*/
#define S_LDT_DEVHDR_CLINESZ 0
#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ)
#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ)
#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ)
#define S_LDT_DEVHDR_LATTMR 8
#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR)
#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR)
#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR)
#define S_LDT_DEVHDR_HDRTYPE 16
#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE)
#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE)
#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE)
#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
#define S_LDT_DEVHDR_BIST 24
#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST)
#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST)
#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST)
/*
* LDT Status Register (Table 8-14). Note that these constants
* assume you've read the command and status register
* together (32-bit read at offset 0x04)
*
* These bits also apply to the secondary status
* register (Table 8-15), offset 0x1C
*/
#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23)
#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
#define S_LDT_STATUS_DEVSELTIMING 25
#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING)
#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING)
#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING)
#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29)
#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30)
#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
/*
* Bridge Control Register (Table 8-16). Note that these
* constants assume you've read the register as a 32-bit
* read (offset 0x3C)
*/
#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16)
#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17)
#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18)
#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19)
#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21)
#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22)
#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23)
#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24)
#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25)
#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26)
#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27)
/*
* LDT Command Register (Table 8-17). Note that these constants
* assume you've read the command and status register together
* 32-bit read at offset 0x40
*/
#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16)
#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
#define S_LDT_CMD_CAPTYPE 29
#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE)
#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE)
#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE)
/*
* LDT link control register (Table 8-18), and (Table 8-19)
*/
#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1)
#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2)
#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3)
#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4)
#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5)
#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6)
#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
#define S_LDT_LINKCTRL_CRCERR 8
#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR)
#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR)
#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR)
#define S_LDT_LINKCTRL_MAXIN 16
#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN)
#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN)
#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN)
#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
#define S_LDT_LINKCTRL_MAXOUT 20
#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT)
#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT)
#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT)
#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
#define S_LDT_LINKCTRL_WIDTHIN 24
#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN)
#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN)
#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN)
#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
#define S_LDT_LINKCTRL_WIDTHOUT 28
#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT)
#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT)
#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT)
#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
/*
* LDT Link frequency register (Table 8-20) offset 0x48
*/
#define S_LDT_LINKFREQ_FREQ 8
#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ)
#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ)
#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ)
#define K_LDT_LINKFREQ_200MHZ 0
#define K_LDT_LINKFREQ_300MHZ 1
#define K_LDT_LINKFREQ_400MHZ 2
#define K_LDT_LINKFREQ_500MHZ 3
#define K_LDT_LINKFREQ_600MHZ 4
#define K_LDT_LINKFREQ_800MHZ 5
#define K_LDT_LINKFREQ_1000MHZ 6
/*
* LDT SRI Command Register (Table 8-21). Note that these constants
* assume you've read the command and status register together
* 32-bit read at offset 0x50
*/
#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16)
#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17)
#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18)
#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19)
#define S_LDT_SRICMD_RXMARGIN 20
#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN)
#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN)
#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN)
#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
#define S_LDT_SRICMD_TXINITIALOFFSET 28
#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET)
#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET)
#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET)
#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
/*
* LDT Error control and status register (Table 8-22) (Table 8-23)
*/
#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0)
#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1)
#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2)
#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3)
#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4)
#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5)
#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6)
#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)
#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9)
#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10)
#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11)
#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12)
#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)
#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15)
#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)
#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
#define M_LDT_ERRCTL_PROTOERR _...
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From: James S. <jsi...@us...> - 2001-11-08 17:17:10
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv1151 Modified Files: entry.S Log Message: Reformat comment. Index: entry.S =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/entry.S,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- entry.S 2001/10/24 21:43:33 1.8 +++ entry.S 2001/11/08 17:17:07 1.9 @@ -1,5 +1,4 @@ /* -/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. |
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From: James S. <jsi...@us...> - 2001-11-08 17:15:39
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv492/mips/kernel Added Files: branch.c Log Message: Handle non-fpu case properly. |
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From: James S. <jsi...@us...> - 2001-11-08 17:15:39
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel In directory usw-pr-cvs1:/tmp/cvs-serv492/mips64/kernel Added Files: branch.c Log Message: Handle non-fpu case properly. |
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