iverilog-devel — Conversations on matters of Icarus Verilog development

Re: [Iverilog-devel] FOSDEM

[Ouabache D. <z3q...@gm...>]

> Dear all,
>
> The FOSDEM 2016 EDA devroom Call for Participation is out:
>
> http://www.ohwr.org/projects/ohr-meta/wiki/FOSDEM2016
>
> This event is a great opportunity to catch up with the latest
> developments in FOSS EDA. Please consider submitting a contribution or
> just attending. Last year's was great fun, and we hope to come up with
> at least as interesting a program this year.
>
> Cheers,
>
> Javier
>
>
>
>
Be nice to have something like this without the 14 hr plane ride.

John Eaton

Re: [Iverilog-devel] transport delay

[Cary R. <cy...@ya...>]

Thanks for the double check and correction Martin. I had forgotten that the assignment in the declaration changes that statement into just a regular continuous assignment. I by default only do a continuous assignments with an assign statement so had forgotten that exception.
 


     On Sunday, November 8, 2015 2:59 AM, Martin Whitaker <mai...@ma...> wrote:
   

 Cary R. wrote:
> I agree with Martin. I believe a non-blocking delay is the only normal RTL
> construct that does not filter pulses smaller than the delay. Specify
> blocks can also tweak this a bit using the path pulse control, but Icarus
> only supports full pulse filtering.

Yes, I should have mentioned that. If you set the pulse reject limit and error 
limit both to zero, that effectively models a transport delay. But as Cary 
says, Icarus doesn't support this.

> The other comment is that I think the
> code shown is describing wire delays and Icarus does not currently support
> these type of delays and if I'm reading the standard correctly they should
> filter pulses smaller than the delay so it seems like the original
> assumption is incorrect. I believe the original code shown should have
> generated a not supported message.

Icarus doesn't support net delays, so would generate a "not supported" message for

  wire #delay dout;

But if the declaration includes a continuous assignment, e.g.

  wire #delay dout = d;

the delay is associated with the assignment, not the net, and Icarus does 
support this.

Martin


  

Re: [Iverilog-devel] transport delay

[Martin W. <mai...@ma...>]

Cary R. wrote:
> I agree with Martin. I believe a non-blocking delay is the only normal RTL
> construct that does not filter pulses smaller than the delay. Specify
> blocks can also tweak this a bit using the path pulse control, but Icarus
> only supports full pulse filtering.

Yes, I should have mentioned that. If you set the pulse reject limit and error 
limit both to zero, that effectively models a transport delay. But as Cary 
says, Icarus doesn't support this.

> The other comment is that I think the
> code shown is describing wire delays and Icarus does not currently support
> these type of delays and if I'm reading the standard correctly they should
> filter pulses smaller than the delay so it seems like the original
> assumption is incorrect. I believe the original code shown should have
> generated a not supported message.

Icarus doesn't support net delays, so would generate a "not supported" message for

   wire #delay dout;

But if the declaration includes a continuous assignment, e.g.

   wire #delay dout = d;

the delay is associated with the assignment, not the net, and Icarus does 
support this.

Martin

Re: [Iverilog-devel] transport delay

[Cary R. <cy...@ya...>]

I agree with Martin. I believe a non-blocking delay is the only normal RTL construct that does not filter pulses smaller than the delay. Specify blocks can also tweak this a bit using the path pulse control, but Icarus only supports full pulse filtering. The other comment is that I think the code shown is describing wire delays and Icarus does not currently support these type of delays and if I'm reading the standard correctly they should filter pulses smaller than the delay so it seems like the original assumption is incorrect.
I believe the original code shown should have generated a not supported message.

Cary 


     On Saturday, November 7, 2015 4:17 PM, Martin Whitaker <mai...@ma...> wrote:
   

 Hi Larry,

Larry Doolittle wrote:
> Friends -
>
> I want to model "transport delay" instead of "inertial delay".
> Some Verilog documents suggest that a simple
>
> reg [4:0] delay=15;
> wire #(delay * 78) dout = d;
>
> should work.  But iverilog-10 seemed to behave according to the
> inertial delay model.
>
I believe Icarus is doing the right thing. The IEEE standard doesn't use the 
terms "transport" and "inertial", but the behaviour it specifies matches the 
descriptions here:

  http://bawankule.com/verilogfaq/techqa.html

As far as I know, the only way to model a transport delay in Verilog is to use 
a non-blocking assignment.

Martin

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https://lists.sourceforge.net/lists/listinfo/iverilog-devel


  

Re: [Iverilog-devel] transport delay

[Martin W. <mai...@ma...>]

Hi Larry,

Larry Doolittle wrote:
> Friends -
>
> I want to model "transport delay" instead of "inertial delay".
> Some Verilog documents suggest that a simple
>
> reg [4:0] delay=15;
> wire #(delay * 78) dout = d;
>
> should work.  But iverilog-10 seemed to behave according to the
> inertial delay model.
>
I believe Icarus is doing the right thing. The IEEE standard doesn't use the 
terms "transport" and "inertial", but the behaviour it specifies matches the 
descriptions here:

   http://bawankule.com/verilogfaq/techqa.html

As far as I know, the only way to model a transport delay in Verilog is to use 
a non-blocking assignment.

Martin

[Iverilog-devel] transport delay

[Larry D. <ldo...@re...>]

Friends -

I want to model "transport delay" instead of "inertial delay".
Some Verilog documents suggest that a simple

reg [4:0] delay=15;
wire #(delay * 78) dout = d;

should work.  But iverilog-10 seemed to behave according to the
inertial delay model.

I found a workaround with a shift register,
Is there a built-in transport delay mechanism in iverilog?

In case my description here was too succinct, I posted the
code at http://recycle.lbl.gov/~ldoolitt/serdes.tar.gz

  - Larry

[Iverilog-devel] FOSDEM 2016 EDA devroom Call for Participation

[Javier S. <jav...@gm...>]

Dear all,

The FOSDEM 2016 EDA devroom Call for Participation is out:

http://www.ohwr.org/projects/ohr-meta/wiki/FOSDEM2016

This event is a great opportunity to catch up with the latest
developments in FOSS EDA. Please consider submitting a contribution or
just attending. Last year's was great fun, and we hope to come up with
at least as interesting a program this year.

Cheers,

Javier

Re: [Iverilog-devel] FOSS-EDA Pizza Wednesday

[Stephen W. <st...@ic...>]

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And of course I got the date wrong, I meant October 28th, which
is today.

On 10/26/2015 08:04 PM, Stephen Williams wrote:
> 
> On the 26'th of October, there will be another informal OSEDA pizza
> dinner. The generic announcement is here:
> 
> Open Source EDA Informal dinner is usually on the last Thursday of
> the month (unless that's a holiday involving dinner). It is ok to
> show up even if you forget to RSVP. Starts 7:15pm. The preferred
> location for this event is now - Round Table Pizza 860 Old San
> Francisco Road Sunnyvale CA 94086 (408) 245-9000
> http://www.roundtablepizza.com/ Note: RSVPs appreciated up to the
> last minute so we know how much table space to grab. see 
> http://tech.groups.yahoo.com/group/foss-eda-sv/cal for this and
> other events this month.
> 
> 
> ------------------------------------------------------------------------------
>
> 
_______________________________________________
> Iverilog-devel mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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[Iverilog-devel] FOSS-EDA Pizza Wednesday

[Stephen W. <st...@ic...>]

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On the 26'th of October, there will be another informal OSEDA
pizza dinner. The generic announcement is here:

Open Source EDA Informal dinner is usually on the last Thursday of the
month (unless that's a holiday involving dinner). It is ok to show up
even if you forget to RSVP. Starts 7:15pm. The preferred location for
this event is now - Round Table Pizza 860 Old San Francisco Road
Sunnyvale CA 94086 (408) 245-9000 http://www.roundtablepizza.com/
Note: RSVPs appreciated up to the last minute so we know how much
table space to grab. see
http://tech.groups.yahoo.com/group/foss-eda-sv/cal for this and other
events this month.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] FOSS-EDA Group get together

[Stephen W. <st...@ic...>]

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Hash: SHA1


This is tonight, folks. See ya there.

On 09/24/2015 02:58 PM, Stephen Williams wrote:
> 
> Once again, I'm going to try to make the FOSS-EDA group pizza. The
> yahoo group is here:
> 
> <https://groups.yahoo.com/neo/groups/foss-eda-sv/info>
> 
> The last announcement is copied below. Note that it seems to be 
> Tuesday this month, for some reason.
> 
> When: Tuesday, 29 September 2015 07:15 PM to 09:00 PM (GMT-08:00)
> Pacific Time (US & Canada) Where: Sunnyvale, CA
> 
> Open Source EDA Informal dinner is usually on the last Thursday of
> the month (unless that's a holiday involving dinner). It is ok to
> show up even if you forget to RSVP. Starts 7:15pm.The preferred
> location for this event is now -Round Table Pizza 860 Old San
> Francisco Road Sunnyvale CA 94086 (408) 245-9000
> http://www.roundtablepizza.com
> 
> Note: RSVPs appreciated up to the last minute so we know how much 
> table space to grab.see 
> http://tech.groups.yahoo.com/group/foss-eda-sv/cal for this and
> other events this month.
> 
> ------------------------------------------------------------------------------
>
> 
_______________________________________________
> Iverilog-devel mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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[Iverilog-devel] FOSS-EDA Group get together

[Stephen W. <st...@ic...>]

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Hash: SHA1


Once again, I'm going to try to make the FOSS-EDA group pizza.
The yahoo group is here:

<https://groups.yahoo.com/neo/groups/foss-eda-sv/info>

The last announcement is copied below. Note that it seems to be
Tuesday this month, for some reason.

When: Tuesday, 29 September 2015
07:15 PM to 09:00 PM (GMT-08:00) Pacific Time (US & Canada)
Where: Sunnyvale, CA

Open Source EDA Informal dinner is usually on the last Thursday of the
month (unless that's a holiday involving dinner). It is ok to show up
even if you forget to RSVP. Starts 7:15pm.The preferred location for
this event is now -Round Table Pizza 860 Old San Francisco Road
Sunnyvale CA 94086 (408) 245-9000 http://www.roundtablepizza.com

Note: RSVPs appreciated up to the last minute so we know how much
table space to grab.see
http://tech.groups.yahoo.com/group/foss-eda-sv/cal for this and other
events this month.
- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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[Iverilog-devel] FOSS-EDA Tonight

[Stephen W. <st...@ic...>]

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Hash: SHA1

I'm planning on going to the FOSS-EDA Dinner tonight. Anyone who
is interested may join in. Here's the details:


Open Source EDA Informal dinner is usually on the last Thursday of the
month (unless that's a holiday involving dinner). It is ok to show up
even if you forget to RSVP. Starts 7:15pm. The preferred location for
this event is now - Round Table Pizza 860 Old San Francisco Road
Sunnyvale CA 94086 (408) 245-9000 http://www.roundtablepizza.com/
Note: RSVPs appreciated up to the last minute so we know how much
table space to grab. see
http://tech.groups.yahoo.com/group/foss-eda-sv/cal for this and other
events this month.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Version 10.0 Release

[Stephen W. <st...@ic...>]

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I thought I got all the details needed in the wikia.com site.
If there are still some details needing update, let me know.

Or update it yourself, it is a wiki:-)

On 08/23/2015 07:22 PM, Larry Doolittle wrote:
> Steve -
> 
> On Sun, Aug 23, 2015 at 03:15:48PM -0700, Stephen Williams wrote:
>> I have uploaded to the ftp site the v10.0 release: 
>> <ftp://ftp.icarus.com/pub/eda/verilog/v10/>
> 
> This is good!  Thanks, and congratulations to you and the whole 
> team for putting together such useful software.
> 
> I see http://iverilog.wikia.com/wiki/Installation_Guide needs a
> bunch of details updated.
> 
> The next step will be to get the attention of any and all
> distribution packagers, so in their next releases v10 can be a
> simple apt or yum get away.  Sorry to say I don't think I can be of
> any help there.
> 
> - Larry
> 
> ------------------------------------------------------------------------------
>
> 
_______________________________________________
> Iverilog-devel mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Version 10.0 Release

[Larry D. <ldo...@re...>]

Steve -

On Sun, Aug 23, 2015 at 03:15:48PM -0700, Stephen Williams wrote:
> I have uploaded to the ftp site the v10.0 release:
> <ftp://ftp.icarus.com/pub/eda/verilog/v10/>

This is good!  Thanks, and congratulations to you and the whole
team for putting together such useful software.

I see http://iverilog.wikia.com/wiki/Installation_Guide
needs a bunch of details updated.

The next step will be to get the attention of any and all distribution
packagers, so in their next releases v10 can be a simple apt or yum
get away.  Sorry to say I don't think I can be of any help there.

  - Larry

[Iverilog-devel] Version 10.0 Release

[Stephen W. <st...@ic...>]

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I have uploaded to the ftp site the v10.0 release:

<ftp://ftp.icarus.com/pub/eda/verilog/v10/>

This includes a tarball of the source, and a src.rpm for those
who wish to use rpmbuild to compile for various rpm based platforms.
I've started that ball rolling with the openSUSE 13.2 x86_64 binary
rpm in the openSUSE-13.2 directory. Commence the build-fest.

And so a new era begins.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Synth option and v10

[Stephen W. <st...@ic...>]

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On 08/20/2015 02:43 PM, Larry Doolittle wrote:
> Steve, I guess you should update http://iverilog.icarus.com/ that 
> still points people to sourceforge.
> 

Done, thanks.


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Synth option and v10

[Larry D. <ldo...@re...>]

Steve -

On Thu, Aug 20, 2015 at 10:28:52PM +0100, Martin Whitaker wrote:
> Larry Doolittle wrote:
> > After five minutes of rummaging around on
> >    https://sourceforge.net/projects/ivtest/
> > I couldn't figure out the git access magic.
> We moved to GitHub a while back:
> https://github.com/steveicarus/ivtest

Ah.  Much better.
Steve, I guess you should update http://iverilog.icarus.com/ that
still points people to sourceforge.

  - Larry

Re: [Iverilog-devel] Synth option and v10

[Martin W. <mai...@ma...>]

Larry,

Larry Doolittle wrote:
> After five minutes of rummaging around on
>    https://sourceforge.net/projects/ivtest/
> I couldn't figure out the git access magic.
> Is sourceforge being deliberately opaque, or did something break?
> I got the six-month-old ivtest_v1.0.tar.gz, but of course
> there's no mention of v10 or v11 in there.
>
We moved to GitHub a while back:

https://github.com/steveicarus/ivtest

>> - so maybe a warning that synthesis support is
>> incomplete is still in order.
>
> Sure, I'm OK with that.  I agree with Steve that mentioning
> v0.8 is probably a mistake.
>
Likewise.

Martin

Re: [Iverilog-devel] Synth option and v10

[Larry D. <ldo...@re...>]

Martin -

On Thu, Aug 20, 2015 at 10:04:52PM +0100, Martin Whitaker wrote:
> There's still quite a long list of synthesis tests that no longer work though 
> - see regress-v11/list

After five minutes of rummaging around on
  https://sourceforge.net/projects/ivtest/
I couldn't figure out the git access magic.
Is sourceforge being deliberately opaque, or did something break?
I got the six-month-old ivtest_v1.0.tar.gz, but of course
there's no mention of v10 or v11 in there.

> - so maybe a warning that synthesis support is 
> incomplete is still in order.

Sure, I'm OK with that.  I agree with Steve that mentioning
v0.8 is probably a mistake.

  - Larry

Re: [Iverilog-devel] Synth option and v10

[Stephen W. <st...@ic...>]

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Sure. It remains true that high-level synthesis is a low
priority so some sort of message to communicate that makes
sense, but we certainly do NOT want to be sending users to
v0.8, or even v0.9.

There are some synthesis based targets, so we do want to
support limited synthesis, we just don't want to over-promise.

On 08/20/2015 02:04 PM, Martin Whitaker wrote:
> Stephen Williams wrote:
>> Well, the synthesis is not awesome in v10, but it may actually be
>> better than v0.8, so we may want to kill that warning. We have a
>> couple of targets now that actually use synthesis. (See the blif 
>> and sizer targets.)
> 
> Also one of our users has created a target for Atmel PLDs.
> 
> There's still quite a long list of synthesis tests that no longer
> work though - see regress-v11/list - so maybe a warning that
> synthesis support is incomplete is still in order.


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Synth option and v10

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
> Well, the synthesis is not awesome in v10, but it may actually
> be better than v0.8, so we may want to kill that warning. We have
> a couple of targets now that actually use synthesis. (See the blif
> and sizer targets.)

Also one of our users has created a target for Atmel PLDs.

There's still quite a long list of synthesis tests that no longer work though 
- see regress-v11/list - so maybe a warning that synthesis support is 
incomplete is still in order.

Martin

Re: [Iverilog-devel] Synth option and v10

[Larry D. <ldo...@re...>]

Steve -

On Thu, Aug 20, 2015 at 12:27:22PM -0700, Stephen Williams wrote:
> Well, the synthesis is not awesome in v10, but it may actually
> be better than v0.8, so we may want to kill that warning. We have
> a couple of targets now that actually use synthesis. (See the blif
> and sizer targets.)

OK then.  See bug #993: assertion in synth.
And I think I can come up with a couple more.

  - Larry

Re: [Iverilog-devel] Synth option and v10

[Stephen W. <st...@ic...>]

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Well, the synthesis is not awesome in v10, but it may actually
be better than v0.8, so we may want to kill that warning. We have
a couple of targets now that actually use synthesis. (See the blif
and sizer targets.)

On 08/20/2015 08:53 AM, Larry Doolittle wrote:
> Friends -
> 
> Open ended question -- what should a stable v10 say and do when 
> given the "-S" option?
> 
> Right now it starts with Warning: Synthesis is not currently being
> maintained and may not function correctly. V0.8 was the last
> release branch to have active synthesis development and support!
> 
> I venture to say that the synthesis pass in v10 is not useful for
> targeting real hardware, but the transformations can be interesting
> for understanding the abstract synthesizability of Verilog code.


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Synth option and v10

[Guy H. <ghu...@gm...>]

Hi Larry,

Have you looked at the sizer target?  This is something which does more
abstract analysis of the device without creating full results.

Guy

On Thursday, August 20, 2015, Larry Doolittle <ldo...@re...>
wrote:

> Friends -
>
> Open ended question -- what should a stable v10 say and do when
> given the "-S" option?
>
> Right now it starts with
> Warning: Synthesis is not currently being maintained and may not
>          function correctly. V0.8 was the last release branch to
>          have active synthesis development and support!
>
> I venture to say that the synthesis pass in v10 is not useful for targeting
> real hardware, but the transformations can be interesting for understanding
> the abstract synthesizability of Verilog code.
>
> I can trigger a handful of asserts in Icarus' synth pass by trying
> to synthesize my typical Verilog.  That doesn't seem like a show-stopper
> for v10, but it does suggest that a warning similar to what we have now
> is still called for.  Specifically:
> assert: /home/ldoolitt/git/iverilog/synth2.cc:182: failed assertion 0
> assert: /home/ldoolitt/git/iverilog/synth2.cc:232: failed assertion
> nex_out.pin_count()==1
> internal error: NetCondit::synth_async: Mux input sizes do not match. A
> size=32, B size=17
> Should I turn in bug reports?
>
> One change in the larger picture since v0.8 in 2004 is the
> emergence of yosys[1], which is open source and _can_ actually
> synthesize for real hardware.  I'd also observe that yosys
> would have a really hard time going public _without_ quality
> simulations from Icarus; it has an extensive self-test process
> based on using Icarus to compare the input Verilog with exported
> post-synthesis structural Verilog.
>
>    - Larry
>
> [1] http://www.clifford.at/yosys/
>
>
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[Iverilog-devel] Synth option and v10

[Larry D. <ldo...@re...>]

Friends -

Open ended question -- what should a stable v10 say and do when
given the "-S" option?

Right now it starts with
Warning: Synthesis is not currently being maintained and may not
         function correctly. V0.8 was the last release branch to
         have active synthesis development and support!

I venture to say that the synthesis pass in v10 is not useful for targeting
real hardware, but the transformations can be interesting for understanding
the abstract synthesizability of Verilog code.

I can trigger a handful of asserts in Icarus' synth pass by trying
to synthesize my typical Verilog.  That doesn't seem like a show-stopper
for v10, but it does suggest that a warning similar to what we have now
is still called for.  Specifically:
assert: /home/ldoolitt/git/iverilog/synth2.cc:182: failed assertion 0
assert: /home/ldoolitt/git/iverilog/synth2.cc:232: failed assertion nex_out.pin_count()==1
internal error: NetCondit::synth_async: Mux input sizes do not match. A size=32, B size=17
Should I turn in bug reports?

One change in the larger picture since v0.8 in 2004 is the
emergence of yosys[1], which is open source and _can_ actually
synthesize for real hardware.  I'd also observe that yosys
would have a really hard time going public _without_ quality
simulations from Icarus; it has an extensive self-test process
based on using Icarus to compare the input Verilog with exported
post-synthesis structural Verilog.

   - Larry

[1] http://www.clifford.at/yosys/