iverilog-devel — Conversations on matters of Icarus Verilog development

Re: [Iverilog-devel] A few more fixes

[Martin W. <mai...@ma...>]

This pull has also introduced a number of shadow warnings, e.g.

g++ -I. -I.. -I../../source/vhdlpp -I../../source/vhdlpp/.. -I../../source/vhdlpp/../libmisc 
-DHAVE_CONFIG_H -Wall -Wextra -Wshadow   -g -O2 -MD -c ../../source/vhdlpp/main.cc -o main.o
In file included from ../../source/vhdlpp/std_funcs.h:23:0,
                  from ../../source/vhdlpp/main.cc:79:
../../source/vhdlpp/subprogram.h: In constructor 
‘SubprogramStdHeader::SubprogramStdHeader(perm_string, std::list<InterfacePort*>*, const VType*)’:
../../source/vhdlpp/subprogram.h:150:40: warning: declaration of ‘name’ shadows a member of 'this' 
[-Wshadow]
                const VType*return_type) :

Re: [Iverilog-devel] A few more fixes

[Maciej S. <mac...@ce...>]

Yes, I had to change the tests. The reason is, now variables are emitted
in corresponding process scopes, so there is no direct access to them
from another module and these tests relied on that (i.e. I cannot check
'if(dut.variable == 42)' anymore). I will push the changes to the test
repository soon.

Regards,
Orson

On 03/07/2016 06:20 PM, Stephen Williams wrote:
> 
> 
> This pull seems to have created a few new regressoins in
> VHDL code. These fail now. Are there ivtest changes that
> you need to push?
> 
> 
> steve@icarus:~/icarus/eda/ivtest> diff regression_report-devel.txt
> regression_report.txt
> 2089c2089
> <             vhdl_string_lim: Passed.
> ---
>> vhdl_string_lim: ==> Failed - running iverilog.
> 2100c2100
> <            vhdl_textio_read: Passed.
> ---
>> vhdl_textio_read: ==> Failed - running iverilog.
> 2115c2115
> <                  vhdl_while: Passed.
> ---
>> vhdl_while: ==> Failed - running iverilog.
> 2192c2192
> <   Total=2187, Passed=2181, Failed=6, Not Implemented=0, Expected Fail=0
> ---
>> Total=2187, Passed=2178, Failed=9, Not Implemented=0, Expected
>> Fail=0
> 
> 
> On 03/07/2016 08:39 AM, Maciej Sumiński wrote:
>> Hi,
> 
>> There is a new branch [1] that contains a few fixes for vhdlpp and
>> one for ivl. There are also tests to support the introduced changes
>> [2].
> 
>> Again, it would be great if you could have a look at the ivl
>> related commit [3]. When I executed a certain test [4], it seemed
>> to me that slices were not correctly computed in a few cases. It
>> should be fixed now.
> 
>> The new pull request includes the previous one, so I have canceled
>> the old request.
> 
>> Regards, Orson
> 
>> 1. https://github.com/steveicarus/iverilog/pull/92 2.
>> https://github.com/orsonmmz/ivtest/tree/vhdlpp_fixes_test 3. 
>> https://github.com/orsonmmz/iverilog/commit/de775975e8d846c2a591a7889dd26c96b76acbc3
> 
> 
> 4.
>> https://github.com/orsonmmz/ivtest/blob/b926f97f9b1ece5d8a09a9be6fd4b33407c67d59/ivltests/array_packed_2d.v
> 
> 
> 

Re: [Iverilog-devel] A few more fixes

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1



This pull seems to have created a few new regressoins in
VHDL code. These fail now. Are there ivtest changes that
you need to push?


steve@icarus:~/icarus/eda/ivtest> diff regression_report-devel.txt
regression_report.txt
2089c2089
<             vhdl_string_lim: Passed.
- ---
> vhdl_string_lim: ==> Failed - running iverilog.
2100c2100
<            vhdl_textio_read: Passed.
- ---
> vhdl_textio_read: ==> Failed - running iverilog.
2115c2115
<                  vhdl_while: Passed.
- ---
> vhdl_while: ==> Failed - running iverilog.
2192c2192
<   Total=2187, Passed=2181, Failed=6, Not Implemented=0, Expected Fail=0
- ---
> Total=2187, Passed=2178, Failed=9, Not Implemented=0, Expected
> Fail=0


On 03/07/2016 08:39 AM, Maciej Sumiński wrote:
> Hi,
> 
> There is a new branch [1] that contains a few fixes for vhdlpp and
> one for ivl. There are also tests to support the introduced changes
> [2].
> 
> Again, it would be great if you could have a look at the ivl
> related commit [3]. When I executed a certain test [4], it seemed
> to me that slices were not correctly computed in a few cases. It
> should be fixed now.
> 
> The new pull request includes the previous one, so I have canceled
> the old request.
> 
> Regards, Orson
> 
> 1. https://github.com/steveicarus/iverilog/pull/92 2.
> https://github.com/orsonmmz/ivtest/tree/vhdlpp_fixes_test 3. 
> https://github.com/orsonmmz/iverilog/commit/de775975e8d846c2a591a7889dd26c96b76acbc3
>
> 
4.
> https://github.com/orsonmmz/ivtest/blob/b926f97f9b1ece5d8a09a9be6fd4b33407c67d59/ivltests/array_packed_2d.v
>
> 
- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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=igHT
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[Iverilog-devel] A few more fixes

[Maciej S. <mac...@ce...>]

Hi,

There is a new branch [1] that contains a few fixes for vhdlpp and one
for ivl. There are also tests to support the introduced changes [2].

Again, it would be great if you could have a look at the ivl related
commit [3]. When I executed a certain test [4], it seemed to me that
slices were not correctly computed in a few cases. It should be fixed now.

The new pull request includes the previous one, so I have canceled the
old request.

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/92
2. https://github.com/orsonmmz/ivtest/tree/vhdlpp_fixes_test
3.
https://github.com/orsonmmz/iverilog/commit/de775975e8d846c2a591a7889dd26c96b76acbc3
4.
https://github.com/orsonmmz/ivtest/blob/b926f97f9b1ece5d8a09a9be6fd4b33407c67d59/ivltests/array_packed_2d.v

[Iverilog-devel] Gnucap and Google summer of code

[al d. <ad...@fr...>]

Gnucap will again be participating in the Google Summer of Code, 
as part of the GNU project.

I am posting to the icarus list in hopes of some joint projects,
especially a wrapper to enable Icarus Verilog to generate device
plugins for gnucap.




Most Gnucap projects involve developing plugins or companion 
programs.  

Here are some links to find out more about it:

http://gnucap.org/dokuwiki/doku.php?id=gnucap:projects

http://www.gnu.org/software/soc-projects/guidelines.html

https://summerofcode.withgoogle.com/

The application window is March 14-25.

Accepted proposals will be announced April 22.

If your project is approved for funding, we expect nearly full-
time effort, as you would for a co-op job or internship, from 
May 23 to August 23.

Re: [Iverilog-devel] iverilog functions

[Dan M. <dan...@gm...>]

Awesome, thanks! I haven't had time for fun stuff lately but will
check it out when I get a chance.

On Tue, Feb 23, 2016 at 4:12 PM, Martin Whitaker
<mai...@ma...> wrote:
> Martin Whitaker wrote:
>> Martin Whitaker wrote:
>>> Yes, running with the -deval_tree debugging option shows that all the SV
>>> merged operator/assignments (++, --, >>=) don't work in a constant context.
>>>
>> I've pushed a fix for this to both the devel and v10 branches. I've tested
>> basic operation, but not explored mixing types, sizes, part selects, etc. Not
>> currently supported are:
>>
>>     - assignment to concatenations
>>     - increment/decrement operators inside expressions
>>
>> Operation on real operands is implemented but not tested, because tgt-vvp
>> doesn't currently support this either.
>
> I've now added the missing functionality to tgt-vvp and fixed a few other bugs
> in this area.
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel

Re: [Iverilog-devel] Pull request

[Stephen W. <st...@ic...>]

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Hash: SHA1


Thanks,

I'll take a look and merge it as soon as I can. (Busy day today.)

On 02/24/2016 07:46 AM, Maciej Sumiński wrote:
> On 02/20/2016 03:00 AM, Stephen Williams wrote:
>> On 02/15/2016 08:29 AM, Maciej Sumiński wrote:
>>> It would be great if the ivl & vvp changes were reviewed more 
>>> carefully. recv_vec4_pv() seemed suspiciously simple, and I am 
>>> afraid I might have missed something important there.
>> 
>> You did! What you missed is that those methods should be 
>> implemented in the derived classes, and not the vvp_net_fun_t 
>> class itself. The vvp_net_fun_t is used kinda like an abstract 
>> base class.
> 
> Thank you for the notice. I have already fixed it and rebased the
> branch.
> 
> I am still not sure about the semantics though. It works for me,
> and there is a test [1] that demonstrates what I was trying to
> achieve, but I do not know if it covers all possible cases.
> 
> Regards, Orson
> 
> 1. 
> https://github.com/orsonmmz/ivtest/commit/bf46c7d1eaddeec88a0c21a6208a2cd3a51b85d1
>
> 
- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Pull request

[Maciej S. <mac...@ce...>]

On 02/20/2016 03:00 AM, Stephen Williams wrote:
> On 02/15/2016 08:29 AM, Maciej Sumiński wrote:
>> It would be great if the ivl & vvp changes were reviewed more
>> carefully. recv_vec4_pv() seemed suspiciously simple, and I am
>> afraid I might have missed something important there.
> 
> You did! What you missed is that those methods should be
> implemented in the derived classes, and not the vvp_net_fun_t
> class itself. The vvp_net_fun_t is used kinda like an abstract
> base class.

Thank you for the notice. I have already fixed it and rebased the branch.

I am still not sure about the semantics though. It works for me, and
there is a test [1] that demonstrates what I was trying to achieve, but
I do not know if it covers all possible cases.

Regards,
Orson

1.
https://github.com/orsonmmz/ivtest/commit/bf46c7d1eaddeec88a0c21a6208a2cd3a51b85d1

Re: [Iverilog-devel] iverilog functions

[Martin W. <mai...@ma...>]

Martin Whitaker wrote:
> Martin Whitaker wrote:
>> Yes, running with the -deval_tree debugging option shows that all the SV
>> merged operator/assignments (++, --, >>=) don't work in a constant context.
>>
> I've pushed a fix for this to both the devel and v10 branches. I've tested
> basic operation, but not explored mixing types, sizes, part selects, etc. Not
> currently supported are:
>
>     - assignment to concatenations
>     - increment/decrement operators inside expressions
>
> Operation on real operands is implemented but not tested, because tgt-vvp
> doesn't currently support this either.

I've now added the missing functionality to tgt-vvp and fixed a few other bugs 
in this area.

Re: [Iverilog-devel] iverilog functions

[Martin W. <mai...@ma...>]

Martin Whitaker wrote:
> Cary R. wrote:
>> I can confirm that this does fail using both V10 and development.I'm
>> guessing it has something to do with the constant function code and the
>> SystemVerilog type or operators. I do not have time to look at this right
>> now. This looks like valid code and is likely a problem in Icarus so not
>> something that is easy for an end user to debug. If you feel adventurous
>> then look at the constant function code in the compiler (eval_tree.cc,
>> etc.) and add appropriate debug output to see what is going on. Cary
>
> Yes, running with the -deval_tree debugging option shows that all the SV
> merged operator/assignments (++, --, >>=) don't work in a constant context.
>
I've pushed a fix for this to both the devel and v10 branches. I've tested 
basic operation, but not explored mixing types, sizes, part selects, etc. Not 
currently supported are:

   - assignment to concatenations
   - increment/decrement operators inside expressions

Operation on real operands is implemented but not tested, because tgt-vvp 
doesn't currently support this either.

Martin

Re: [Iverilog-devel] Pull request

[Stephen W. <st...@ic...>]

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Hash: SHA1

On 02/15/2016 08:29 AM, Maciej Sumiński wrote:
> It would be great if the ivl & vvp changes were reviewed more
> carefully. recv_vec4_pv() seemed suspiciously simple, and I am
> afraid I might have missed something important there.

You did! What you missed is that those methods should be
implemented in the derived classes, and not the vvp_net_fun_t
class itself. The vvp_net_fun_t is used kinda like an abstract
base class.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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=evNv
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[Iverilog-devel] Pull request

[Maciej S. <mac...@ce...>]

Hi,

I have just created a new pull request [1] supported by unit tests [2].
Changes:

= vhdlpp
- support for basic loops (loop .. end loop)
- subtype declarations
- initial support for CHARACTER enums (LF & CR for now)
- system functions: now, shift_left, shift_right
- limited support for final wait statement
- concurrent assertion statements
- delayed assignment statements
- conditional assignments without the ending 'else' statement
- subprogram overloading (support for multiple functions with the same
name, but different parameters types)
- multidimensional arrays, only on the vhdlpp side (i.e. VHDL code is
translated but cannnot be executed yet)
- a bunch of fixes

= ivl
- part selection in multidimensional packed ports assignment

= vvp
- implemented vvp_net_fun_t::recv_vec4_pv()

It would be great if the ivl & vvp changes were reviewed more carefully.
recv_vec4_pv() seemed suspiciously simple, and I am afraid I might have
missed something important there.
Code responsible for part selection in multidimensional packed ports
assignment is based on the code I have seen in elab_expr.cc
(PEIdent::elaborate_expr_net_part_).

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/90
2. https://github.com/orsonmmz/ivtest/tree/subp_overload_test

Re: [Iverilog-devel] iverilog functions

[Martin W. <mai...@ma...>]

Cary R. wrote:
> I can confirm that this does fail using both V10 and development.I'm
> guessing it has something to do with the constant function code and the
> SystemVerilog type or operators. I do not have time to look at this right
> now. This looks like valid code and is likely a problem in Icarus so not
> something that is easy for an end user to debug. If you feel adventurous
> then look at the constant function code in the compiler (eval_tree.cc,
> etc.) and add appropriate debug output to see what is going on. Cary

Yes, running with the -deval_tree debugging option shows that all the SV 
merged operator/assignments (++, --, >>=) don't work in a constant context.

Martin

Re: [Iverilog-devel] iverilog functions

[Cary R. <cy...@ya...>]

And as a further note the Verilog equivalent of this code does work correctly. 

    On Monday, February 8, 2016 11:20 PM, Cary R. <cy...@ya...> wrote:
 

 I can confirm that this does fail using both V10 and development.I'm guessing it has something to do with the constant function code and the SystemVerilog type or operators. I do not have time to look at this right now. This looks like valid code and is likely a problem in Icarus so not something that is easy for an end user to debug. If you feel adventurous then look at the constant function code in the compiler (eval_tree.cc, etc.) and add appropriate debug output to see what is going on.
Cary
 

    On Monday, February 8, 2016 8:02 PM, Dan McLeran <dan...@gm...> wrote:
 

 Thanks. Here is a simple example. Using the function clog2 in the
declaration of the logic array causes the failure. Using clog2 in the
sequential logic appears to work.

iverilog -g2012 -Wall -o example example.sv

//example.sv
module example #(parameter N = 8) (output logic[3:0] result, input logic clk);
    //logic[clog2(N):0] temp; //comment this line back in to see the failure

    always@(posedge clk)
        result <= clog2(N);

    function int clog2(input int n);
        begin
            clog2 = 0;
            n--;
            while(n > 0)
                begin
                    clog2++;
                    n >>= 1;
                end
        end
    endfunction
endmodule

On Mon, Feb 8, 2016 at 5:13 PM, Stephen Williams <st...@ic...> wrote:
>
> If you make a small but complete example that we cal compile
> for ourselves, we can take a look at this.
>
> On 02/08/2016 12:50 PM, Dan McLeran wrote:
>> I am using iverilog to learn SystemVerilog. I am following along in a
>> digital system design book and am having trouble building one of the
>> examples. The code uses a function to calculate log2:
>>
>> module #(parameter AL = 8, BL = 8, QL = AL + BL) ...
>>
>>    logic[clog2(AL):0] count;
>>    ...
>>    function clog2(input int n);
>>        begin
>>            clog2 = 0;
>>            n--;
>>            while(n > 0)
>>                begin
>>                    clog2++;
>>                    n >>= 1;
>>                end
>>          end
>>    endfunction
>> endmodule
>>
>> I calling iverilog like this:
>>
>> iverilog -g2012 -Wall -o booth booth.sv
>>
>> It seems to get hung processing the loop or detecting n == 0 or
>> something. Is there an easy way
>> to debug this? I was thinking I'd run iverilog within gdb but maybe
>> there is a faster way to determine what is happening?
>>
>> Regards,
>>
>> Dan McLeran
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
>> _______________________________________________
>> Iverilog-devel mailing list
>> Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>
>
> --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com          But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel

------------------------------------------------------------------------------
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Monitor end-to-end web transactions and take corrective actions now
Troubleshoot faster and improve end-user experience. Signup Now!
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Re: [Iverilog-devel] iverilog functions

[Cary R. <cy...@ya...>]

I can confirm that this does fail using both V10 and development.I'm guessing it has something to do with the constant function code and the SystemVerilog type or operators. I do not have time to look at this right now. This looks like valid code and is likely a problem in Icarus so not something that is easy for an end user to debug. If you feel adventurous then look at the constant function code in the compiler (eval_tree.cc, etc.) and add appropriate debug output to see what is going on.
Cary
 

    On Monday, February 8, 2016 8:02 PM, Dan McLeran <dan...@gm...> wrote:
 

 Thanks. Here is a simple example. Using the function clog2 in the
declaration of the logic array causes the failure. Using clog2 in the
sequential logic appears to work.

iverilog -g2012 -Wall -o example example.sv

//example.sv
module example #(parameter N = 8) (output logic[3:0] result, input logic clk);
    //logic[clog2(N):0] temp; //comment this line back in to see the failure

    always@(posedge clk)
        result <= clog2(N);

    function int clog2(input int n);
        begin
            clog2 = 0;
            n--;
            while(n > 0)
                begin
                    clog2++;
                    n >>= 1;
                end
        end
    endfunction
endmodule

On Mon, Feb 8, 2016 at 5:13 PM, Stephen Williams <st...@ic...> wrote:
>
> If you make a small but complete example that we cal compile
> for ourselves, we can take a look at this.
>
> On 02/08/2016 12:50 PM, Dan McLeran wrote:
>> I am using iverilog to learn SystemVerilog. I am following along in a
>> digital system design book and am having trouble building one of the
>> examples. The code uses a function to calculate log2:
>>
>> module #(parameter AL = 8, BL = 8, QL = AL + BL) ...
>>
>>    logic[clog2(AL):0] count;
>>    ...
>>    function clog2(input int n);
>>        begin
>>            clog2 = 0;
>>            n--;
>>            while(n > 0)
>>                begin
>>                    clog2++;
>>                    n >>= 1;
>>                end
>>          end
>>    endfunction
>> endmodule
>>
>> I calling iverilog like this:
>>
>> iverilog -g2012 -Wall -o booth booth.sv
>>
>> It seems to get hung processing the loop or detecting n == 0 or
>> something. Is there an easy way
>> to debug this? I was thinking I'd run iverilog within gdb but maybe
>> there is a faster way to determine what is happening?
>>
>> Regards,
>>
>> Dan McLeran
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
>> _______________________________________________
>> Iverilog-devel mailing list
>> Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>
>
> --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com          But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
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Re: [Iverilog-devel] iverilog functions

[Dan M. <dan...@gm...>]

Thanks. Here is a simple example. Using the function clog2 in the
declaration of the logic array causes the failure. Using clog2 in the
sequential logic appears to work.

iverilog -g2012 -Wall -o example example.sv

//example.sv
module example #(parameter N = 8) (output logic[3:0] result, input logic clk);
    //logic[clog2(N):0] temp; //comment this line back in to see the failure

    always@(posedge clk)
        result <= clog2(N);

    function int clog2(input int n);
        begin
            clog2 = 0;
            n--;
            while(n > 0)
                begin
                    clog2++;
                    n >>= 1;
                end
        end
    endfunction
endmodule

On Mon, Feb 8, 2016 at 5:13 PM, Stephen Williams <st...@ic...> wrote:
>
> If you make a small but complete example that we cal compile
> for ourselves, we can take a look at this.
>
> On 02/08/2016 12:50 PM, Dan McLeran wrote:
>> I am using iverilog to learn SystemVerilog. I am following along in a
>> digital system design book and am having trouble building one of the
>> examples. The code uses a function to calculate log2:
>>
>> module #(parameter AL = 8, BL = 8, QL = AL + BL) ...
>>
>>     logic[clog2(AL):0] count;
>>     ...
>>     function clog2(input int n);
>>         begin
>>             clog2 = 0;
>>             n--;
>>             while(n > 0)
>>                 begin
>>                     clog2++;
>>                     n >>= 1;
>>                 end
>>          end
>>     endfunction
>> endmodule
>>
>> I calling iverilog like this:
>>
>> iverilog -g2012 -Wall -o booth booth.sv
>>
>> It seems to get hung processing the loop or detecting n == 0 or
>> something. Is there an easy way
>> to debug this? I was thinking I'd run iverilog within gdb but maybe
>> there is a faster way to determine what is happening?
>>
>> Regards,
>>
>> Dan McLeran
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
>> _______________________________________________
>> Iverilog-devel mailing list
>> Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>
>
> --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel

Re: [Iverilog-devel] iverilog functions

[Stephen W. <st...@ic...>]

If you make a small but complete example that we cal compile
for ourselves, we can take a look at this.

On 02/08/2016 12:50 PM, Dan McLeran wrote:
> I am using iverilog to learn SystemVerilog. I am following along in a
> digital system design book and am having trouble building one of the
> examples. The code uses a function to calculate log2:
> 
> module #(parameter AL = 8, BL = 8, QL = AL + BL) ...
> 
>     logic[clog2(AL):0] count;
>     ...
>     function clog2(input int n);
>         begin
>             clog2 = 0;
>             n--;
>             while(n > 0)
>                 begin
>                     clog2++;
>                     n >>= 1;
>                 end
>          end
>     endfunction
> endmodule
> 
> I calling iverilog like this:
> 
> iverilog -g2012 -Wall -o booth booth.sv
> 
> It seems to get hung processing the loop or detecting n == 0 or
> something. Is there an easy way
> to debug this? I was thinking I'd run iverilog within gdb but maybe
> there is a faster way to determine what is happening?
> 
> Regards,
> 
> Dan McLeran
> 
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

[Iverilog-devel] iverilog functions

[Dan M. <dan...@gm...>]

I am using iverilog to learn SystemVerilog. I am following along in a
digital system design book and am having trouble building one of the
examples. The code uses a function to calculate log2:

module #(parameter AL = 8, BL = 8, QL = AL + BL) ...

    logic[clog2(AL):0] count;
    ...
    function clog2(input int n);
        begin
            clog2 = 0;
            n--;
            while(n > 0)
                begin
                    clog2++;
                    n >>= 1;
                end
         end
    endfunction
endmodule

I calling iverilog like this:

iverilog -g2012 -Wall -o booth booth.sv

It seems to get hung processing the loop or detecting n == 0 or
something. Is there an easy way
to debug this? I was thinking I'd run iverilog within gdb but maybe
there is a faster way to determine what is happening?

Regards,

Dan McLeran

[Iverilog-devel] Release 10.1

[Stephen W. <st...@ic...>]

I added a new warning for my day job (they paid me;-) and they
are using the version 10 branch. I noticed that there have been
a bunch of minor updates to the v10 branch anyhow, so I went
ahead and made a release. So it is up to 10.1.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Re: [Iverilog-devel] stray patch

[Cary R. <cy...@ya...>]

I think I'm living in negative time right now.
Cary
 

    On Monday, January 25, 2016 1:53 PM, Larry Doolittle <ldo...@re...> wrote:
 

 Martin -

On Mon, Jan 25, 2016 at 07:59:15PM +0000, Martin Whitaker wrote:
> Larry Doolittle wrote:
> > I found the attached patch sitting in my iverilog tree, and
> > it doesn't show up in git master.  Should it?  I don't remember
> > anything about it.
> This looks to be bug #995.

Yes, I turned that in last August.  I guess this give you
an idea of depth of my brain's memory for details.  :-p

> We've been a bit remiss about handling this (and 
> its companions)! I'm a bit busy at present, but will try to look at it soon if 
> Steve or Cary don't have time.

OK, thanks.  This one is pretty simple and helpful, turning a crash
into a helpful error message.  Addressing the underlying missing feature
is surely a lot more work.

  - Larry

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Re: [Iverilog-devel] stray patch

[Larry D. <ldo...@re...>]

Martin -

On Mon, Jan 25, 2016 at 07:59:15PM +0000, Martin Whitaker wrote:
> Larry Doolittle wrote:
> > I found the attached patch sitting in my iverilog tree, and
> > it doesn't show up in git master.  Should it?  I don't remember
> > anything about it.
> This looks to be bug #995.

Yes, I turned that in last August.  I guess this give you
an idea of depth of my brain's memory for details.  :-p

> We've been a bit remiss about handling this (and 
> its companions)! I'm a bit busy at present, but will try to look at it soon if 
> Steve or Cary don't have time.

OK, thanks.  This one is pretty simple and helpful, turning a crash
into a helpful error message.  Addressing the underlying missing feature
is surely a lot more work.

  - Larry

Re: [Iverilog-devel] stray patch

[Martin W. <mai...@ma...>]

Hello Larry,

Larry Doolittle wrote:
> Friends -
>
> I found the attached patch sitting in my iverilog tree, and
> it doesn't show up in git master.  Should it?  I don't remember
> anything about it.

This looks to be bug #995. We've been a bit remiss about handling this (and 
its companions)! I'm a bit busy at present, but will try to look at it soon if 
Steve or Cary don't have time.

Martin

Re: [Iverilog-devel] input coerced messages

[Martin W. <mai...@ma...>]

Lonnie L Gliem wrote:
> Is there any way to suppress the input coerced messages? I know in vcs they
> just print 1 line unless you set -notice.

Only by modifying the compiler source code. Look around line 1420 in 
elaborate.cc. But do you really want to hide potential gotchas in your Verilog 
code?

It would be nice if Icarus had a more flexible system for enabling/disabling 
specific warning messages, but there are more important things to fix first.

Martin

[Iverilog-devel] stray patch

[Larry D. <ldo...@re...>]

Friends -

I found the attached patch sitting in my iverilog tree, and
it doesn't show up in git master.  Should it?  I don't remember
anything about it.

 - Larry

[Iverilog-devel] input coerced messages

[Lonnie L G. <lg...@sr...>]

Is there any way to suppress the input coerced messages? I know in vcs they
just print 1 line unless you set -notice.