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From: Martin W. <mai...@ma...> - 2016-01-19 19:21:42
|
Hi Larry, Larry Doolittle wrote: > The original Micron readme.txt file covers ModelSim, NC-Verilog, and VCS. > But most of my changes fix errors that would prevent correct execution > on _any_ simulator. What do other Icarus users do for DDR3 simulations? I've used the Micron DDR2 and DDR3 models with Icarus (and NC-Verilog) over many years now. I've generally had to make one or two minor changes to suppress unwanted warnings (and to fix the odd bug). I've never bothered to run their testbench, so my comments apply to the basic DDR model only. Looking at my testbench, I see I'm currently using ddr3.v v1.60, and have recorded the following changes: // MTW, 06-Nov-09, modified check of reserved MR bits to eliminate warning when the // address bus width is less than 14. Disabled power-up to RST_N // and RST_N to CKE checks. Fixed bug in tCL check. // MTW, 06-May-10, added option to suppress tWLS and tWLH timing checks. These // produce lots of spurious warnings during levelling. With these changes my tests run without any warnings. I have also used ddr3.v v1.69, but as it uses a few SystemVerilog constructs, only with NC_Verilog. I haven't checked to see if the SV support in Icarus has improved enough to run this now. The two big things you can do to speed up simulations, if your DRAM controller lets you, is to disable the power-up and reset delays, and to disable levelling. Even so, simulations run slowly in Icarus. HTH, Martin |
|
From: Larry D. <ldo...@re...> - 2016-01-19 16:57:46
|
Friends - I have a habit of _not_ using external RAM on my FPGA designs. It usually seems better to me to schlep data directly to commodity computer hardware instead. But I have a project now that may force me to finally get my feet wet. I downloaded a DDR3 model from Micron, and hacked it enough to get partial success according to this script: set -e if ! test -e micron_ddr3.zip; then curl -o micron_ddr3.zip https://www.micron.com/~/media/documents/products/sim-model/dram/ddr3/ddr3-sdram-verilog-model.zip; fi echo "e063c7c63e3453d04998a3a0af8f25c207bce0e72af33b572871d6df40d3d39d micron_ddr3.zip" | sha256sum -c DIR=`mktemp -d ddr_test_XXXXXX` cd $DIR unzip ../micron_ddr3.zip chmod a-x * chmod u+w * uudecode << EOT begin-base64 644 ddr3.patch.gz H4sIADjJnVYCA5VVbW/bNhD+HP2K+5BiFmQmpGwrsuR0TtphCNJkaWy0w4JM ky3a4aIXj6Kdot3++0hRkuWXpA0liMfjPUfe8eEpYrMZoCWga4gi3gkyzubH SjpaFYpSNhBCOwYHNiY9hPvyBdLzbMfrdY5w1QDhE4wNy7KajhTGQZgg4ioM 7nu2vYFxJWY4BEScTvsELN0NhwaoxtLFUsg+i4RvgNYdH8M0zqaP8DcTgnID KSWnYax6MX0MwtXcN6w92lPiYOxrL4IltJrKw2QRU7i7+eV2/O7y7NOviHj4 fsfwYddwn1n8jJkKsktw2wFLdc0gBZ1TDglNZtHdX+dn15ejagfysZo2zK8w TLAw1oMJnbMUPJixmAYsC7IFTfWMTsIc7s7PgvOL8QgQEGmI72ESpo/lnuy+ Sny309xT1Ux/PaZpJLeDquEs49Cq9wWngH3ZDUAH4BcqBhYQU4ewxrxou7G8 Tgm7l9MqqEDtOlBhtphZE6IkxQ2ncRZGkNOpYFlqRPuYfhU+UoXXFK1GW2yv 1Aek7/QRsVGHAHE8jOW7w92a7zWqwXibeAR7HbyX8biNJd/bBKusW2Ece3oP YmJYhlWKHohJeTXlrbQO2IpyFmdzQJ8lAtDcxriH8hWg9xFNbdx1ryZSzuek ByiDwyEc/qnc8WXacH+wWi0ApXA4UHPTmIapJ7U8ATSrrfYmMF9OBM3F0epB R70ebyVxPVGWDQcRWTZkNk484jxfNjZxdenoer2+1+vtTaTrKgIX3yZ/15Li RZBkES3HLdyGb6T70wQH8sE4IBv9f/AvJDx44oNBX4vTeDCwTV/R7Eq5uZU3 LpfFB56YeID3Hz5ITU5F83qk2WKDyq0k/NIaS9PL9viPjxfXF2PT9Nc34wXz POJhUiQWHzWgtaksjkFWlEndBqdAfHi+ySDEkqeQpQq69qO20CK4uFh7z75m YiFtnbdSve6kK0TzjF35h9j/e+i4bVdel6KrTvmJcboT3h1RtRPElwUvxqeg UjmlLG6Nf7+5PZYV32yDEgNZnatEvuwqh11Xo9rT6BWOojguHEmUPFxf8+VF zNd/prleXB7+u9GPQWS15CXkN/kbKon2g+tsEU6tab1izS24Xv+7uXniUCW5 JeRgAK4JP4MSveJrqe8b+3uu+vf67u66KmQEXVM7fPuWKKb/D6HaLiwRCQAA ==== EOT gunzip ddr3.patch.gz patch -p1 < ddr3.patch make A subsequent "make run" takes 3 minutes to run, spews 1409342 lines (mostly timing errors), but at least ends with tb.test_done at time 216066.7 ns: INFO: Simulation is Complete The original Micron readme.txt file covers ModelSim, NC-Verilog, and VCS. But most of my changes fix errors that would prevent correct execution on _any_ simulator. What do other Icarus users do for DDR3 simulations? - Larry |
|
From: Lonnie G. <lg...@sr...> - 2016-01-13 16:00:37
|
I have an example ready just have to get Managements approval to send it. On Wed, Jan 13, 2016 at 03:52:19PM +0000, Cary R. wrote: > I agree with the rest, this sure look like you are assigning to a register which is supported in SystemVerilog, but is not currently supported in Icarus. > > A working example would certainly help. > Cary > > On Tuesday, January 12, 2016 12:49 PM, Iztok Jeras <izt...@gm...> wrote: > > > you should further check if both 'ce' and 'wren' ports are inputs, and that the signals are not driven inside those modules > On Tue, Jan 12, 2016 at 9:18 PM, Lonnie Gliem <lg...@sr...> wrote: > > Not much on the grep I don't see any continuous assignments. > > $ grep wen > /temp/builds/150918-0934/carte/macros/carte/cntrlr_if/map_m/llvm_mapl_blockram_sync_8x93bit.v > input wen, > .ce (wen) > .wren (wen), > > Lonnie > > On Tue, Jan 12, 2016 at 08:54:29PM +0100, Iztok Jeras wrote: > > for now could jou just grep all lines containing wen > > inside llvm_mapl_blockram_sync_8x93bit > > > > $ grep wen llvm_mapl_blockram_sync_8x93bit.v > > > > On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...> > > wrote: > > > > > It is an input. > > > > > > module llvm_mapl_blockram_sync_8x93bit ( > > > output wire [92:0] out, > > > output reg almost_empty, > > > output reg empty, > > > output reg data_valid, > > > output reg almost_full, > > > input [92:0] inbit, > > > input ren, > > > input wen, > > > input ce, > > > input clk, > > > input rst > > > ); > > > > > > I will try and cut it down to s small testcase but it may take a bit it > > > is quite large. > > > > > > Lonnie > > > > > > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote: > > > > Hi, > > > > > > > > Could you check the direction of the 'wen' port inside the > > > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any > > > > asignments to the wen signal inside the module. > > > > > > > > Some simulators ignore signal directions, but check for multiple drivers. > > > > So although the direction is wrong, the design might be functionally > > > > correct. > > > > > > > > Regards, > > > > Iztok Jeras > > > > > > > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr... > > > > > > > > wrote: > > > > > > > > > I ran into some verilog code that iverilog is failing to compile but > > > vcs > > > > > > > > > > does. > > > > > > > > > > > > > > > > > > > > It appears the problem is having the reg on the right side of an > > > > > instantiation. > > > > > > > > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles. > > > > > > > > > > > > > > > > > > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it > > > > > compiles. > > > > > > > > > > > > > > > > > > > > I have several of these in one module and they all fail the same. > > > > > > > > > > > > > > > > > > > > Here are the iverilog errors: > > > > > > > > > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066: > > > > > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068: > > > > > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > > > > > > > > > Thanks > > > > > > > > > > Lonnie > > > > > > > > > > > > > > > > > > > > reg rmw_busy_fifo_wen; > > > > > > > > > > > > > > > > > > > > always @ (posedge sysclk or posedge user_reset) > > > > > > > > > > if (user_reset) > > > > > > > > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066 > > > > > > > > > > else > > > > > > > > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | > > > obm_busy)) > > > > > | <--- this is 2067 > > > > > > > > > > > > > > > (set_normal_wr_patha & (obm_read | obm_read_d1))); > > > > > > > > > > > > > > > > > > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo ( > > > > > > > > > > .out (rmw_busy_fifo_rd[92:00]), > > > > > > > > > > .almost_empty (rmw_busy_fifo_almost_empty), > > > > > > > > > > .empty (rmw_busy_fifo_empty), > > > > > > > > > > .data_valid (rmw_busy_fifo_valid), > > > > > > > > > > .almost_full (rmw_busy_fifo_full), > > > > > > > > > > .inbit > > > (rmw_busy_fifo_wrdata[92:0]), > > > > > > > > > > .ren (rmw_busy_fifo_ren), > > > > > > > > > > .wen (rmw_busy_fifo_wen), > > > > > > > > > > .ce (1'b1), > > > > > > > > > > .clk (sysclk), > > > > > > > > > > .rst (user_reset) > > > > > > > > > > ); > > > > > > > > > > > > > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > > > Monitor end-to-end web transactions and take corrective actions now > > > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > > > _______________________________________________ > > > > > Iverilog-devel mailing list > > > > > Ive...@li... > > > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > > Monitor end-to-end web transactions and take corrective actions now > > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > > _______________________________________________ > > > > Iverilog-devel mailing list > > > > Ive...@li... > > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > Monitor end-to-end web transactions and take corrective actions now > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > _______________________________________________ > > > Iverilog-devel mailing list > > > Ive...@li... > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > ------------------------------------------------------------------------------ > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > Monitor end-to-end web transactions and take corrective actions now > > Troubleshoot faster and improve end-user experience. Signup Now! > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > _______________________________________________ > > Iverilog-devel mailing list > > Ive...@li... > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel |
|
From: Cary R. <cy...@ya...> - 2016-01-13 15:55:11
|
ctrl-C and then typing $dumpflush() when needed and then resuming should make this work on your schedule.
Cary
On Tuesday, January 12, 2016 2:44 PM, "by...@nc..." <by...@nc...> wrote:
> Hello,
>
> I'm recently transitioned from .vcd to .fst output files and am happy with
> the saved disk space, but is there any way to get the .fst file written to
> disk more frequently? I'd like to be able to update my waveforms every
> minute or so to make sure the simulation is functioning properly.
> Sometimes the .fst file just never gets written to disk until the
> simulation ends, or I have to ctrl-C break it and $finish prematurely to
> force the .fst file to be written.
>
> Is there a better way?
>
> Thanks,
> -Brian
Brian,
Looking in sys_fst.c, it appears that $dumpflush called periodically in your testbench at the end of some timestep should do what you want. You'd have to make some timing measurements based on your cycles per second to update the waveforms as often as you want. Note that the filesize will get bigger the more often you force flushes.
-Tony
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APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
Monitor end-to-end web transactions and take corrective actions now
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|
From: Cary R. <cy...@ya...> - 2016-01-13 15:55:10
|
I agree with the rest, this sure look like you are assigning to a register which is supported in SystemVerilog, but is not currently supported in Icarus.
A working example would certainly help.
Cary
On Tuesday, January 12, 2016 12:49 PM, Iztok Jeras <izt...@gm...> wrote:
you should further check if both 'ce' and 'wren' ports are inputs, and that the signals are not driven inside those modules
On Tue, Jan 12, 2016 at 9:18 PM, Lonnie Gliem <lg...@sr...> wrote:
Not much on the grep I don't see any continuous assignments.
$ grep wen
/temp/builds/150918-0934/carte/macros/carte/cntrlr_if/map_m/llvm_mapl_blockram_sync_8x93bit.v
input wen,
.ce (wen)
.wren (wen),
Lonnie
On Tue, Jan 12, 2016 at 08:54:29PM +0100, Iztok Jeras wrote:
> for now could jou just grep all lines containing wen
> inside llvm_mapl_blockram_sync_8x93bit
>
> $ grep wen llvm_mapl_blockram_sync_8x93bit.v
>
> On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...>
> wrote:
>
> > It is an input.
> >
> > module llvm_mapl_blockram_sync_8x93bit (
> > output wire [92:0] out,
> > output reg almost_empty,
> > output reg empty,
> > output reg data_valid,
> > output reg almost_full,
> > input [92:0] inbit,
> > input ren,
> > input wen,
> > input ce,
> > input clk,
> > input rst
> > );
> >
> > I will try and cut it down to s small testcase but it may take a bit it
> > is quite large.
> >
> > Lonnie
> >
> > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote:
> > > Hi,
> > >
> > > Could you check the direction of the 'wen' port inside the
> > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any
> > > asignments to the wen signal inside the module.
> > >
> > > Some simulators ignore signal directions, but check for multiple drivers.
> > > So although the direction is wrong, the design might be functionally
> > > correct.
> > >
> > > Regards,
> > > Iztok Jeras
> > >
> > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr...
> > >
> > > wrote:
> > >
> > > > I ran into some verilog code that iverilog is failing to compile but
> > vcs
> > > >
> > > > does.
> > > >
> > > >
> > > >
> > > > It appears the problem is having the reg on the right side of an
> > > > instantiation.
> > > >
> > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles.
> > > >
> > > >
> > > >
> > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it
> > > > compiles.
> > > >
> > > >
> > > >
> > > > I have several of these in one module and they all fail the same.
> > > >
> > > >
> > > >
> > > > Here are the iverilog errors:
> > > >
> > > >
> > > >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066:
> > > >
> > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> > > >
> > > >
> > > >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068:
> > > >
> > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> > > >
> > > >
> > > >
> > > > Thanks
> > > >
> > > > Lonnie
> > > >
> > > >
> > > >
> > > > reg rmw_busy_fifo_wen;
> > > >
> > > >
> > > >
> > > > always @ (posedge sysclk or posedge user_reset)
> > > >
> > > > if (user_reset)
> > > >
> > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066
> > > >
> > > > else
> > > >
> > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy |
> > obm_busy))
> > > > | <--- this is 2067
> > > >
> > > >
> > > > (set_normal_wr_patha & (obm_read | obm_read_d1)));
> > > >
> > > >
> > > >
> > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo (
> > > >
> > > > .out (rmw_busy_fifo_rd[92:00]),
> > > >
> > > > .almost_empty (rmw_busy_fifo_almost_empty),
> > > >
> > > > .empty (rmw_busy_fifo_empty),
> > > >
> > > > .data_valid (rmw_busy_fifo_valid),
> > > >
> > > > .almost_full (rmw_busy_fifo_full),
> > > >
> > > > .inbit
> > (rmw_busy_fifo_wrdata[92:0]),
> > > >
> > > > .ren (rmw_busy_fifo_ren),
> > > >
> > > > .wen (rmw_busy_fifo_wen),
> > > >
> > > > .ce (1'b1),
> > > >
> > > > .clk (sysclk),
> > > >
> > > > .rst (user_reset)
> > > >
> > > > );
> > > >
> > > >
> > > >
> > > >
> > > >
> > ------------------------------------------------------------------------------
> > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > > > Monitor end-to-end web transactions and take corrective actions now
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> > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> > > >
> > > >
> >
> > >
> > ------------------------------------------------------------------------------
> > > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > > Monitor end-to-end web transactions and take corrective actions now
> > > Troubleshoot faster and improve end-user experience. Signup Now!
> > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > > _______________________________________________
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> > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> > ------------------------------------------------------------------------------
> > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > Monitor end-to-end web transactions and take corrective actions now
> > Troubleshoot faster and improve end-user experience. Signup Now!
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> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
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|
|
From: <by...@nc...> - 2016-01-12 22:43:46
|
> Hello, > > I'm recently transitioned from .vcd to .fst output files and am happy with > the saved disk space, but is there any way to get the .fst file written to > disk more frequently? I'd like to be able to update my waveforms every > minute or so to make sure the simulation is functioning properly. > Sometimes the .fst file just never gets written to disk until the > simulation ends, or I have to ctrl-C break it and $finish prematurely to > force the .fst file to be written. > > Is there a better way? > > Thanks, > -Brian Brian, Looking in sys_fst.c, it appears that $dumpflush called periodically in your testbench at the end of some timestep should do what you want. You'd have to make some timing measurements based on your cycles per second to update the waveforms as often as you want. Note that the filesize will get bigger the more often you force flushes. -Tony |
|
From: Iztok J. <izt...@gm...> - 2016-01-12 20:48:42
|
you should further check if both 'ce' and 'wren' ports are inputs, and that the signals are not driven inside those modules On Tue, Jan 12, 2016 at 9:18 PM, Lonnie Gliem <lg...@sr...> wrote: > Not much on the grep I don't see any continuous assignments. > > $ grep wen > > /temp/builds/150918-0934/carte/macros/carte/cntrlr_if/map_m/llvm_mapl_blockram_sync_8x93bit.v > input wen, > .ce (wen) > .wren (wen), > > Lonnie > > On Tue, Jan 12, 2016 at 08:54:29PM +0100, Iztok Jeras wrote: > > for now could jou just grep all lines containing wen > > inside llvm_mapl_blockram_sync_8x93bit > > > > $ grep wen llvm_mapl_blockram_sync_8x93bit.v > > > > On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...> > > wrote: > > > > > It is an input. > > > > > > module llvm_mapl_blockram_sync_8x93bit ( > > > output wire [92:0] out, > > > output reg almost_empty, > > > output reg empty, > > > output reg data_valid, > > > output reg almost_full, > > > input [92:0] inbit, > > > input ren, > > > input wen, > > > input ce, > > > input clk, > > > input rst > > > ); > > > > > > I will try and cut it down to s small testcase but it may take a bit it > > > is quite large. > > > > > > Lonnie > > > > > > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote: > > > > Hi, > > > > > > > > Could you check the direction of the 'wen' port inside the > > > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any > > > > asignments to the wen signal inside the module. > > > > > > > > Some simulators ignore signal directions, but check for multiple > drivers. > > > > So although the direction is wrong, the design might be functionally > > > > correct. > > > > > > > > Regards, > > > > Iztok Jeras > > > > > > > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem < > lg...@sr... > > > > > > > > wrote: > > > > > > > > > I ran into some verilog code that iverilog is failing to compile > but > > > vcs > > > > > > > > > > does. > > > > > > > > > > > > > > > > > > > > It appears the problem is having the reg on the right side of an > > > > > instantiation. > > > > > > > > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles. > > > > > > > > > > > > > > > > > > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the > wire it > > > > > compiles. > > > > > > > > > > > > > > > > > > > > I have several of these in one module and they all fail the same. > > > > > > > > > > > > > > > > > > > > Here are the iverilog errors: > > > > > > > > > > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066: > > > > > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068: > > > > > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > > > > > > > > > Thanks > > > > > > > > > > Lonnie > > > > > > > > > > > > > > > > > > > > reg rmw_busy_fifo_wen; > > > > > > > > > > > > > > > > > > > > always @ (posedge sysclk or posedge user_reset) > > > > > > > > > > if (user_reset) > > > > > > > > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066 > > > > > > > > > > else > > > > > > > > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | > > > obm_busy)) > > > > > | <--- this is 2067 > > > > > > > > > > > > > > > (set_normal_wr_patha & (obm_read | obm_read_d1))); > > > > > > > > > > > > > > > > > > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo ( > > > > > > > > > > .out (rmw_busy_fifo_rd[92:00]), > > > > > > > > > > .almost_empty > (rmw_busy_fifo_almost_empty), > > > > > > > > > > .empty (rmw_busy_fifo_empty), > > > > > > > > > > .data_valid (rmw_busy_fifo_valid), > > > > > > > > > > .almost_full (rmw_busy_fifo_full), > > > > > > > > > > .inbit > > > (rmw_busy_fifo_wrdata[92:0]), > > > > > > > > > > .ren (rmw_busy_fifo_ren), > > > > > > > > > > .wen (rmw_busy_fifo_wen), > > > > > > > > > > .ce (1'b1), > > > > > > > > > > .clk (sysclk), > > > > > > > > > > .rst (user_reset) > > > > > > > > > > ); > > > > > > > > > > > > > > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > > > Site24x7 APM Insight: Get Deep Visibility into Application > Performance > > > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > > > Monitor end-to-end web transactions and take corrective actions now > > > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > > > _______________________________________________ > > > > > Iverilog-devel mailing list > > > > > Ive...@li... > > > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > > Site24x7 APM Insight: Get Deep Visibility into Application > Performance > > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > > Monitor end-to-end web transactions and take corrective actions now > > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > > _______________________________________________ > > > > Iverilog-devel mailing list > > > > Ive...@li... > > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > Monitor end-to-end web transactions and take corrective actions now > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > _______________________________________________ > > > Iverilog-devel mailing list > > > Ive...@li... > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > ------------------------------------------------------------------------------ > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > Monitor end-to-end web transactions and take corrective actions now > > Troubleshoot faster and improve end-user experience. Signup Now! > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > _______________________________________________ > > Iverilog-devel mailing list > > Ive...@li... > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > |
|
From: Lonnie G. <lg...@sr...> - 2016-01-12 20:19:22
|
Not much on the grep I don't see any continuous assignments.
$ grep wen
/temp/builds/150918-0934/carte/macros/carte/cntrlr_if/map_m/llvm_mapl_blockram_sync_8x93bit.v
input wen,
.ce (wen)
.wren (wen),
Lonnie
On Tue, Jan 12, 2016 at 08:54:29PM +0100, Iztok Jeras wrote:
> for now could jou just grep all lines containing wen
> inside llvm_mapl_blockram_sync_8x93bit
>
> $ grep wen llvm_mapl_blockram_sync_8x93bit.v
>
> On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...>
> wrote:
>
> > It is an input.
> >
> > module llvm_mapl_blockram_sync_8x93bit (
> > output wire [92:0] out,
> > output reg almost_empty,
> > output reg empty,
> > output reg data_valid,
> > output reg almost_full,
> > input [92:0] inbit,
> > input ren,
> > input wen,
> > input ce,
> > input clk,
> > input rst
> > );
> >
> > I will try and cut it down to s small testcase but it may take a bit it
> > is quite large.
> >
> > Lonnie
> >
> > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote:
> > > Hi,
> > >
> > > Could you check the direction of the 'wen' port inside the
> > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any
> > > asignments to the wen signal inside the module.
> > >
> > > Some simulators ignore signal directions, but check for multiple drivers.
> > > So although the direction is wrong, the design might be functionally
> > > correct.
> > >
> > > Regards,
> > > Iztok Jeras
> > >
> > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr...
> > >
> > > wrote:
> > >
> > > > I ran into some verilog code that iverilog is failing to compile but
> > vcs
> > > >
> > > > does.
> > > >
> > > >
> > > >
> > > > It appears the problem is having the reg on the right side of an
> > > > instantiation.
> > > >
> > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles.
> > > >
> > > >
> > > >
> > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it
> > > > compiles.
> > > >
> > > >
> > > >
> > > > I have several of these in one module and they all fail the same.
> > > >
> > > >
> > > >
> > > > Here are the iverilog errors:
> > > >
> > > >
> > > >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066:
> > > >
> > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> > > >
> > > >
> > > >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068:
> > > >
> > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> > > >
> > > >
> > > >
> > > > Thanks
> > > >
> > > > Lonnie
> > > >
> > > >
> > > >
> > > > reg rmw_busy_fifo_wen;
> > > >
> > > >
> > > >
> > > > always @ (posedge sysclk or posedge user_reset)
> > > >
> > > > if (user_reset)
> > > >
> > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066
> > > >
> > > > else
> > > >
> > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy |
> > obm_busy))
> > > > | <--- this is 2067
> > > >
> > > >
> > > > (set_normal_wr_patha & (obm_read | obm_read_d1)));
> > > >
> > > >
> > > >
> > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo (
> > > >
> > > > .out (rmw_busy_fifo_rd[92:00]),
> > > >
> > > > .almost_empty (rmw_busy_fifo_almost_empty),
> > > >
> > > > .empty (rmw_busy_fifo_empty),
> > > >
> > > > .data_valid (rmw_busy_fifo_valid),
> > > >
> > > > .almost_full (rmw_busy_fifo_full),
> > > >
> > > > .inbit
> > (rmw_busy_fifo_wrdata[92:0]),
> > > >
> > > > .ren (rmw_busy_fifo_ren),
> > > >
> > > > .wen (rmw_busy_fifo_wen),
> > > >
> > > > .ce (1'b1),
> > > >
> > > > .clk (sysclk),
> > > >
> > > > .rst (user_reset)
> > > >
> > > > );
> > > >
> > > >
> > > >
> > > >
> > > >
> > ------------------------------------------------------------------------------
> > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > > > Monitor end-to-end web transactions and take corrective actions now
> > > > Troubleshoot faster and improve end-user experience. Signup Now!
> > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > > > _______________________________________________
> > > > Iverilog-devel mailing list
> > > > Ive...@li...
> > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> > > >
> > > >
> >
> > >
> > ------------------------------------------------------------------------------
> > > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > > Monitor end-to-end web transactions and take corrective actions now
> > > Troubleshoot faster and improve end-user experience. Signup Now!
> > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > > _______________________________________________
> > > Iverilog-devel mailing list
> > > Ive...@li...
> > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> > ------------------------------------------------------------------------------
> > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > Monitor end-to-end web transactions and take corrective actions now
> > Troubleshoot faster and improve end-user experience. Signup Now!
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> >
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
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|
|
From: Martin W. <mai...@ma...> - 2016-01-12 19:54:41
|
Lonnie L Gliem wrote: > I ran into some verilog code that iverilog is failing to compile but vcs > does. > The error message you are getting suggests: 1) There is a continuous assignment to rmw_busy_fifo_wen somewhere in your code. 2) You are instructing iverilog to compile SystemVerilog code. I can reproduce your error with the attached simple test case, which results in: % iverilog -g2012 bug.v bug.v:13: error: q Unable to assign to unresolved wires. bug.v:15: error: q Unable to assign to unresolved wires. 2 error(s) during elaboration. If the continuous assignment is inside the sub module, you should also get a warning like: bug.v:18: warning: input port w is coerced to inout. If compiled without the -g2012 option, you get a more helpful error: % iverilog bug.v bug.v:9: error: reg q; cannot be driven by primitives or continuous assignment. 1 error(s) during elaboration. If either of the above two conditions aren't true, it's likely a compiler bug, and we are going to need a failing test case to analyse. Martin |
|
From: Iztok J. <izt...@gm...> - 2016-01-12 19:54:37
|
for now could jou just grep all lines containing wen inside llvm_mapl_blockram_sync_8x93bit $ grep wen llvm_mapl_blockram_sync_8x93bit.v On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...> wrote: > It is an input. > > module llvm_mapl_blockram_sync_8x93bit ( > output wire [92:0] out, > output reg almost_empty, > output reg empty, > output reg data_valid, > output reg almost_full, > input [92:0] inbit, > input ren, > input wen, > input ce, > input clk, > input rst > ); > > I will try and cut it down to s small testcase but it may take a bit it > is quite large. > > Lonnie > > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote: > > Hi, > > > > Could you check the direction of the 'wen' port inside the > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any > > asignments to the wen signal inside the module. > > > > Some simulators ignore signal directions, but check for multiple drivers. > > So although the direction is wrong, the design might be functionally > > correct. > > > > Regards, > > Iztok Jeras > > > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr... > > > > wrote: > > > > > I ran into some verilog code that iverilog is failing to compile but > vcs > > > > > > does. > > > > > > > > > > > > It appears the problem is having the reg on the right side of an > > > instantiation. > > > > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles. > > > > > > > > > > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it > > > compiles. > > > > > > > > > > > > I have several of these in one module and they all fail the same. > > > > > > > > > > > > Here are the iverilog errors: > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066: > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068: > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > Thanks > > > > > > Lonnie > > > > > > > > > > > > reg rmw_busy_fifo_wen; > > > > > > > > > > > > always @ (posedge sysclk or posedge user_reset) > > > > > > if (user_reset) > > > > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066 > > > > > > else > > > > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | > obm_busy)) > > > | <--- this is 2067 > > > > > > > > > (set_normal_wr_patha & (obm_read | obm_read_d1))); > > > > > > > > > > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo ( > > > > > > .out (rmw_busy_fifo_rd[92:00]), > > > > > > .almost_empty (rmw_busy_fifo_almost_empty), > > > > > > .empty (rmw_busy_fifo_empty), > > > > > > .data_valid (rmw_busy_fifo_valid), > > > > > > .almost_full (rmw_busy_fifo_full), > > > > > > .inbit > (rmw_busy_fifo_wrdata[92:0]), > > > > > > .ren (rmw_busy_fifo_ren), > > > > > > .wen (rmw_busy_fifo_wen), > > > > > > .ce (1'b1), > > > > > > .clk (sysclk), > > > > > > .rst (user_reset) > > > > > > ); > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > Monitor end-to-end web transactions and take corrective actions now > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > _______________________________________________ > > > Iverilog-devel mailing list > > > Ive...@li... > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > ------------------------------------------------------------------------------ > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > Monitor end-to-end web transactions and take corrective actions now > > Troubleshoot faster and improve end-user experience. Signup Now! > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > _______________________________________________ > > Iverilog-devel mailing list > > Ive...@li... > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > |
|
From: Lonnie G. <lg...@sr...> - 2016-01-12 18:48:19
|
It is an input.
module llvm_mapl_blockram_sync_8x93bit (
output wire [92:0] out,
output reg almost_empty,
output reg empty,
output reg data_valid,
output reg almost_full,
input [92:0] inbit,
input ren,
input wen,
input ce,
input clk,
input rst
);
I will try and cut it down to s small testcase but it may take a bit it
is quite large.
Lonnie
On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote:
> Hi,
>
> Could you check the direction of the 'wen' port inside the
> module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any
> asignments to the wen signal inside the module.
>
> Some simulators ignore signal directions, but check for multiple drivers.
> So although the direction is wrong, the design might be functionally
> correct.
>
> Regards,
> Iztok Jeras
>
> On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr...>
> wrote:
>
> > I ran into some verilog code that iverilog is failing to compile but vcs
> >
> > does.
> >
> >
> >
> > It appears the problem is having the reg on the right side of an
> > instantiation.
> >
> > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles.
> >
> >
> >
> > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it
> > compiles.
> >
> >
> >
> > I have several of these in one module and they all fail the same.
> >
> >
> >
> > Here are the iverilog errors:
> >
> >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066:
> >
> > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> >
> >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068:
> >
> > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> >
> >
> >
> > Thanks
> >
> > Lonnie
> >
> >
> >
> > reg rmw_busy_fifo_wen;
> >
> >
> >
> > always @ (posedge sysclk or posedge user_reset)
> >
> > if (user_reset)
> >
> > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066
> >
> > else
> >
> > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | obm_busy))
> > | <--- this is 2067
> >
> >
> > (set_normal_wr_patha & (obm_read | obm_read_d1)));
> >
> >
> >
> > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo (
> >
> > .out (rmw_busy_fifo_rd[92:00]),
> >
> > .almost_empty (rmw_busy_fifo_almost_empty),
> >
> > .empty (rmw_busy_fifo_empty),
> >
> > .data_valid (rmw_busy_fifo_valid),
> >
> > .almost_full (rmw_busy_fifo_full),
> >
> > .inbit (rmw_busy_fifo_wrdata[92:0]),
> >
> > .ren (rmw_busy_fifo_ren),
> >
> > .wen (rmw_busy_fifo_wen),
> >
> > .ce (1'b1),
> >
> > .clk (sysclk),
> >
> > .rst (user_reset)
> >
> > );
> >
> >
> >
> >
> > ------------------------------------------------------------------------------
> > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > Monitor end-to-end web transactions and take corrective actions now
> > Troubleshoot faster and improve end-user experience. Signup Now!
> > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > _______________________________________________
> > Iverilog-devel mailing list
> > Ive...@li...
> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Larry D. <ldo...@re...> - 2016-01-12 18:43:34
|
Lonnie - On Tue, Jan 12, 2016 at 11:10:39AM -0600, Lonnie L Gliem wrote: > I ran into some verilog code that iverilog is failing to compile but vcs > does. The snippets you posted look good to me, iverilog should have no problem with that. Can you post a stand-alone test case that reproduces the error? - Larry |
|
From: Iztok J. <izt...@gm...> - 2016-01-12 18:21:06
|
Hi, Could you check the direction of the 'wen' port inside the module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any asignments to the wen signal inside the module. Some simulators ignore signal directions, but check for multiple drivers. So although the direction is wrong, the design might be functionally correct. Regards, Iztok Jeras On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr...> wrote: > I ran into some verilog code that iverilog is failing to compile but vcs > > does. > > > > It appears the problem is having the reg on the right side of an > instantiation. > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles. > > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it > compiles. > > > > I have several of these in one module and they all fail the same. > > > > Here are the iverilog errors: > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066: > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068: > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > Thanks > > Lonnie > > > > reg rmw_busy_fifo_wen; > > > > always @ (posedge sysclk or posedge user_reset) > > if (user_reset) > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066 > > else > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | obm_busy)) > | <--- this is 2067 > > > (set_normal_wr_patha & (obm_read | obm_read_d1))); > > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo ( > > .out (rmw_busy_fifo_rd[92:00]), > > .almost_empty (rmw_busy_fifo_almost_empty), > > .empty (rmw_busy_fifo_empty), > > .data_valid (rmw_busy_fifo_valid), > > .almost_full (rmw_busy_fifo_full), > > .inbit (rmw_busy_fifo_wrdata[92:0]), > > .ren (rmw_busy_fifo_ren), > > .wen (rmw_busy_fifo_wen), > > .ce (1'b1), > > .clk (sysclk), > > .rst (user_reset) > > ); > > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > |
|
From: Lonnie L G. <lg...@sr...> - 2016-01-12 17:27:13
|
I ran into some verilog code that iverilog is failing to compile but vcs
does.
It appears the problem is having the reg on the right side of an
instantiation.
If I comment out the line .wen (rmw_busy_fifo_wen) it compiles.
Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it
compiles.
I have several of these in one module and they all fail the same.
Here are the iverilog errors:
/home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066:
error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
/home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068:
error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
Thanks
Lonnie
reg rmw_busy_fifo_wen;
always @ (posedge sysclk or posedge user_reset)
if (user_reset)
rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066
else
rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | obm_busy)) |
<--- this is 2067
(set_normal_wr_patha & (obm_read | obm_read_d1)));
llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo (
.out (rmw_busy_fifo_rd[92:00]),
.almost_empty (rmw_busy_fifo_almost_empty),
.empty (rmw_busy_fifo_empty),
.data_valid (rmw_busy_fifo_valid),
.almost_full (rmw_busy_fifo_full),
.inbit (rmw_busy_fifo_wrdata[92:0]),
.ren (rmw_busy_fifo_ren),
.wen (rmw_busy_fifo_wen),
.ce (1'b1),
.clk (sysclk),
.rst (user_reset)
);
|
|
From: Stephen W. <st...@ic...> - 2016-01-11 00:56:56
|
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Merged into git master.
On 01/07/2016 05:19 AM, Maciej Sumiński wrote:
> Hi,
>
> I have just sent a new merge request [1] with tests [2]. Changes: -
> 'image attribute (VHDL) - VPI extension to allow functions return a
> string - $sformatf (SV) - improved report statements so they accept
> expressions instead of string literals (VHDL)
>
> I would be particularly thankful for reviewing the last commit from
> the pull request (32fab21e). I have done the change, so e.g. the
> following code could be run:
>
> $display({ $sformatf("%d",int_var), $sformatf("%d", int_var) });
>
> Without the change, I was getting a message:
>
> error: Concatenation/replication may not have zero width in this
> context.
>
> Regards, Orson
>
> 1. https://github.com/steveicarus/iverilog/pull/88 2.
> https://github.com/orsonmmz/ivtest/tree/image_attr_test
>
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iEYEARECAAYFAlaS78oACgkQrPt1Sc2b3imxgACg6hgll/mrSR7OqT1jqr4pjOOp
dxkAoOv5kHlkQRQLy9gbfh6AV8VLQlBJ
=qCSm
-----END PGP SIGNATURE-----
|
|
From: Brian K. <bri...@gm...> - 2016-01-10 00:47:29
|
Hello, I'm recently transitioned from .vcd to .fst output files and am happy with the saved disk space, but is there any way to get the .fst file written to disk more frequently? I'd like to be able to update my waveforms every minute or so to make sure the simulation is functioning properly. Sometimes the .fst file just never gets written to disk until the simulation ends, or I have to ctrl-C break it and $finish prematurely to force the .fst file to be written. Is there a better way? Thanks, -Brian |
|
From: Maciej S. <mac...@ce...> - 2016-01-07 13:19:35
|
Hi,
I have just sent a new merge request [1] with tests [2]. Changes:
- 'image attribute (VHDL)
- VPI extension to allow functions return a string
- $sformatf (SV)
- improved report statements so they accept expressions instead of
string literals (VHDL)
I would be particularly thankful for reviewing the last commit from the
pull request (32fab21e). I have done the change, so e.g. the following
code could be run:
$display({ $sformatf("%d",int_var), $sformatf("%d", int_var) });
Without the change, I was getting a message:
error: Concatenation/replication may not have zero width in this context.
Regards,
Orson
1. https://github.com/steveicarus/iverilog/pull/88
2. https://github.com/orsonmmz/ivtest/tree/image_attr_test
|
|
From: Cary R. <cy...@ya...> - 2015-12-08 06:23:23
|
It should probably be a private (Icarus specific define) like some of the ones in vpi_user.h and I agree it should be in the SV header file. The value should be way outside the range of the other return values to allow SV room to implement this, the two states variables, etc. that SV supports and not conflict.
Cary
On Monday, December 7, 2015 1:56 PM, Stephen Williams <st...@ic...> wrote:
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hmm... I think the proper answer is to define in the sv_vpi_user.h
a vpiStringFunc that is probably a value like 10 so that it is sure
to not intefere with other declaration. I'd put it in the sv_vpi_user.h
header file instead of the vpi_user.h header file so that it does not
pollute the vpi_user.h name space.
You are right that the SV standard doesn't have a code for string
return values, but I think we want such things, and absent any other
standard on the matter, we can define what we want.
It's either that, or start implementing DPI. Big job.
On 12/07/2015 12:48 PM, Maciej Sumiński wrote:
> True, I prefer to follow this way too. The thing is, $sformatf
> returns a string, which is seemingly impossible with the VPI
> interface. There are function types: vpiSysFuncInt, vpiSysFuncReal,
> vpiSysFuncTime and vpiSysFuncSized. I was wondering if adding
> vpiSysFuncString (in a separate header, so the original one is not
> polluted) is acceptable or is there any better method.
>
> Regards, Orson
>
> On 12/07/2015 07:11 PM, Stephen Williams wrote:
>>
>> First guess, I think the best would be to implement $sformatf. It
>> is something that we would need anyhow. On 12/07/2015 08:52 AM,
>> Maciej Sumi?ski wrote:
>>> Hi,
>>
>>> I am wondering what would be the right way to implement VHDL
>>> 'image attribute, which returns a string representation of a
>>> variable.
>>
>>> The first idea is to use SV $sformatf system function, which
>>> returns a string based on the formatting string (e.g. "%d" and
>>> input data, but it is currently not available in Icarus. I
>>> could add it, but as far as I know, the VPI standard does not
>>> allow to write functions that return strings.
>>
>>> What's your opinion? Should I extend VPI in Icarus to allow
>>> returning strings or is there another, more elegant solution to
>>> the problem?
>>
>>> Regards, Orson
>>
>>
>>
>>> ------------------------------------------------------------------------------
>>
>>
>>
>>>
Go from Idea to Many App Stores Faster with Intel(R) XDK
>>> Give your users amazing mobile app experiences with Intel(R)
>>> XDK. Use one codebase in this all-in-one HTML5 development
>>> environment. Design, debug & build mobile apps & 2D/3D
>>> high-impact games for multiple OSs.
>>> http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140
>>
>>
>>
>>>
>>>
_______________________________________________ Iverilog-devel
>>> mailing list Ive...@li...
>>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>>
>>
Go from Idea to Many App Stores Faster with Intel(R) XDK
>> Give your users amazing mobile app experiences with Intel(R)
>> XDK. Use one codebase in this all-in-one HTML5 development
>> environment. Design, debug & build mobile apps & 2D/3D
>> high-impact games for multiple OSs.
>> http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140
>> _______________________________________________ Iverilog-devel
>> mailing list Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>
>
>
> ------------------------------------------------------------------------------
>
>
Go from Idea to Many App Stores Faster with Intel(R) XDK
> Give your users amazing mobile app experiences with Intel(R) XDK.
> Use one codebase in this all-in-one HTML5 development environment.
> Design, debug & build mobile apps & 2D/3D high-impact games for
> multiple OSs.
> http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140
>
>
>
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iEYEARECAAYFAlZmAIUACgkQrPt1Sc2b3imLYQCgvbkuGBSbOBNIjnw++Yr+foRn
St0AnRWTrvLWJ9nHGkSngBI5xpm+MJuY
=eogv
-----END PGP SIGNATURE-----
------------------------------------------------------------------------------
Go from Idea to Many App Stores Faster with Intel(R) XDK
Give your users amazing mobile app experiences with Intel(R) XDK.
Use one codebase in this all-in-one HTML5 development environment.
Design, debug & build mobile apps & 2D/3D high-impact games for multiple OSs.
http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Stephen W. <st...@ic...> - 2015-12-07 21:56:30
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hmm... I think the proper answer is to define in the sv_vpi_user.h a vpiStringFunc that is probably a value like 10 so that it is sure to not intefere with other declaration. I'd put it in the sv_vpi_user.h header file instead of the vpi_user.h header file so that it does not pollute the vpi_user.h name space. You are right that the SV standard doesn't have a code for string return values, but I think we want such things, and absent any other standard on the matter, we can define what we want. It's either that, or start implementing DPI. Big job. On 12/07/2015 12:48 PM, Maciej Sumiński wrote: > True, I prefer to follow this way too. The thing is, $sformatf > returns a string, which is seemingly impossible with the VPI > interface. There are function types: vpiSysFuncInt, vpiSysFuncReal, > vpiSysFuncTime and vpiSysFuncSized. I was wondering if adding > vpiSysFuncString (in a separate header, so the original one is not > polluted) is acceptable or is there any better method. > > Regards, Orson > > On 12/07/2015 07:11 PM, Stephen Williams wrote: >> >> First guess, I think the best would be to implement $sformatf. It >> is something that we would need anyhow. On 12/07/2015 08:52 AM, >> Maciej Sumi?ski wrote: >>> Hi, >> >>> I am wondering what would be the right way to implement VHDL >>> 'image attribute, which returns a string representation of a >>> variable. >> >>> The first idea is to use SV $sformatf system function, which >>> returns a string based on the formatting string (e.g. "%d" and >>> input data, but it is currently not available in Icarus. I >>> could add it, but as far as I know, the VPI standard does not >>> allow to write functions that return strings. >> >>> What's your opinion? Should I extend VPI in Icarus to allow >>> returning strings or is there another, more elegant solution to >>> the problem? >> >>> Regards, Orson >> >> >> >>> ------------------------------------------------------------------------------ >> >> >> >>> Go from Idea to Many App Stores Faster with Intel(R) XDK >>> Give your users amazing mobile app experiences with Intel(R) >>> XDK. Use one codebase in this all-in-one HTML5 development >>> environment. Design, debug & build mobile apps & 2D/3D >>> high-impact games for multiple OSs. >>> http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140 >> >> >> >>> >>> _______________________________________________ Iverilog-devel >>> mailing list Ive...@li... >>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel >> >> >> >> >> ------------------------------------------------------------------------------ >> >> Go from Idea to Many App Stores Faster with Intel(R) XDK >> Give your users amazing mobile app experiences with Intel(R) >> XDK. Use one codebase in this all-in-one HTML5 development >> environment. Design, debug & build mobile apps & 2D/3D >> high-impact games for multiple OSs. >> http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140 >> _______________________________________________ Iverilog-devel >> mailing list Ive...@li... >> https://lists.sourceforge.net/lists/listinfo/iverilog-devel >> > > > > ------------------------------------------------------------------------------ > > Go from Idea to Many App Stores Faster with Intel(R) XDK > Give your users amazing mobile app experiences with Intel(R) XDK. > Use one codebase in this all-in-one HTML5 development environment. > Design, debug & build mobile apps & 2D/3D high-impact games for > multiple OSs. > http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140 > > > > _______________________________________________ Iverilog-devel > mailing list Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlZmAIUACgkQrPt1Sc2b3imLYQCgvbkuGBSbOBNIjnw++Yr+foRn St0AnRWTrvLWJ9nHGkSngBI5xpm+MJuY =eogv -----END PGP SIGNATURE----- |
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From: Maciej S. <mac...@ce...> - 2015-12-07 20:49:18
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True, I prefer to follow this way too. The thing is, $sformatf returns a string, which is seemingly impossible with the VPI interface. There are function types: vpiSysFuncInt, vpiSysFuncReal, vpiSysFuncTime and vpiSysFuncSized. I was wondering if adding vpiSysFuncString (in a separate header, so the original one is not polluted) is acceptable or is there any better method. Regards, Orson On 12/07/2015 07:11 PM, Stephen Williams wrote: > > First guess, I think the best would be to implement $sformatf. > It is something that we would need anyhow. > On 12/07/2015 08:52 AM, Maciej Sumi?ski wrote: >> Hi, > >> I am wondering what would be the right way to implement VHDL >> 'image attribute, which returns a string representation of a >> variable. > >> The first idea is to use SV $sformatf system function, which >> returns a string based on the formatting string (e.g. "%d" and >> input data, but it is currently not available in Icarus. I could >> add it, but as far as I know, the VPI standard does not allow to >> write functions that return strings. > >> What's your opinion? Should I extend VPI in Icarus to allow >> returning strings or is there another, more elegant solution to the >> problem? > >> Regards, Orson > > > >> ------------------------------------------------------------------------------ > > > Go from Idea to Many App Stores Faster with Intel(R) XDK >> Give your users amazing mobile app experiences with Intel(R) XDK. >> Use one codebase in this all-in-one HTML5 development environment. >> Design, debug & build mobile apps & 2D/3D high-impact games for >> multiple OSs. >> http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140 > > > >> _______________________________________________ Iverilog-devel >> mailing list Ive...@li... >> https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > ------------------------------------------------------------------------------ > Go from Idea to Many App Stores Faster with Intel(R) XDK > Give your users amazing mobile app experiences with Intel(R) XDK. > Use one codebase in this all-in-one HTML5 development environment. > Design, debug & build mobile apps & 2D/3D high-impact games for multiple OSs. > http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > |
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From: Stephen W. <st...@ic...> - 2015-12-07 18:12:06
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 First guess, I think the best would be to implement $sformatf. It is something that we would need anyhow. On 12/07/2015 08:52 AM, Maciej Sumi?ski wrote: > Hi, > > I am wondering what would be the right way to implement VHDL > 'image attribute, which returns a string representation of a > variable. > > The first idea is to use SV $sformatf system function, which > returns a string based on the formatting string (e.g. "%d" and > input data, but it is currently not available in Icarus. I could > add it, but as far as I know, the VPI standard does not allow to > write functions that return strings. > > What's your opinion? Should I extend VPI in Icarus to allow > returning strings or is there another, more elegant solution to the > problem? > > Regards, Orson > > > > ------------------------------------------------------------------------------ > > Go from Idea to Many App Stores Faster with Intel(R) XDK > Give your users amazing mobile app experiences with Intel(R) XDK. > Use one codebase in this all-in-one HTML5 development environment. > Design, debug & build mobile apps & 2D/3D high-impact games for > multiple OSs. > http://pubads.g.doubleclick.net/gampad/clk?id=254741911&iu=/4140 > > > > _______________________________________________ Iverilog-devel > mailing list Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlZly+4ACgkQrPt1Sc2b3im7sACgzRDRyA8tZkjZ0wIuVtLpqMr2 vXgAn0DOH3qd291wbhZq1fKtIZnLorOU =d2S0 -----END PGP SIGNATURE----- |
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From: Maciej S. <mac...@ce...> - 2015-12-07 16:53:03
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Hi, I am wondering what would be the right way to implement VHDL 'image attribute, which returns a string representation of a variable. The first idea is to use SV $sformatf system function, which returns a string based on the formatting string (e.g. "%d" and input data, but it is currently not available in Icarus. I could add it, but as far as I know, the VPI standard does not allow to write functions that return strings. What's your opinion? Should I extend VPI in Icarus to allow returning strings or is there another, more elegant solution to the problem? Regards, Orson |
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From: Kevin C. <iv...@gr...> - 2015-12-06 01:41:42
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Hi All, Thought I would forward this info I just got - ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ A group of people interested in open source EDA tools have created a group we called Freecellera. website: http://freecellera.org mailing list: fre...@go... It's very new... |
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From: Stephen W. <st...@ic...> - 2015-12-04 16:57:47
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Awesome. I'll try to get to it today. On 12/04/2015 06:16 AM, Maciej Sumiński wrote: > Hi Steve, > > There is a new branch [1] and associated tests [2] proposed for > merging. > > The patches add basic support for std.textio / > ieee.std_logic_textio libraries & while loops, and a number of > minor fixes. > > Regards, Orson > > 1. https://github.com/steveicarus/iverilog/pull/86 2. > https://github.com/orsonmmz/ivtest/tree/files_test > - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlZhxgMACgkQrPt1Sc2b3ilP3ACg0NfOyjMAgKn5K9V2igZG284J EUUAoK7XeNTMxoYjNVuVqRlv8ddtVyPc =oDNL -----END PGP SIGNATURE----- |
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From: Maciej S. <mac...@ce...> - 2015-12-04 14:17:28
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Hi Steve, There is a new branch [1] and associated tests [2] proposed for merging. The patches add basic support for std.textio / ieee.std_logic_textio libraries & while loops, and a number of minor fixes. Regards, Orson 1. https://github.com/steveicarus/iverilog/pull/86 2. https://github.com/orsonmmz/ivtest/tree/files_test |
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