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hppaqemu-cvs — CVS commits for the HPPA target for QEMU
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From: Stuart B. <zu...@us...> - 2007-03-22 15:48:53
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv14411 Modified Files: translate.c Log Message: Implement and use assemble_17() and assemble_21(). Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.38 retrieving revision 1.39 diff -u -d -r1.38 -r1.39 --- translate.c 21 Mar 2007 23:37:38 -0000 1.38 +++ translate.c 22 Mar 2007 15:48:50 -0000 1.39 @@ -100,6 +100,18 @@ return (y << 11) | ((x & 1) << 10) | ((x >> 1) & ~(~0 << 10)); } +static uint32_t assemble_17(uint32_t x, uint32_t y, uint32_t z) { + return (z << 16) | (x << 11) | ((y & 1) << 10) | ((y >> 1) & ~(~0 << 10)); +} + +static uint32_t assemble_21(uint32_t x) { + return ((x & 1) << 20) | + (((x >> 1) & ~(~0 << 11)) << 9) | + (((x >> 14) & ~(~0 << 2)) << 7) | + (((x >> 16) & ~(~0 << 5)) << 2) | + ((x >> 12) & ~(~0 << 2)); +} + static GenOpFunc *gen_op_movl_TN_reg[3][32] = { { @@ -1629,7 +1641,7 @@ uint32_t t, im21; t = field(insn, 21, 5); if(t) { - im21 = field(insn, 0, 21) << (32 - 21); + im21 = assemble_21(field(insn, 0, 21)) << (32 - 21); gen_movl_T0_im(im21); gen_movl_reg_T0(t); } @@ -1653,7 +1665,7 @@ { uint32_t r, im21; r = field(insn, 21, 5); - im21 = field(insn, 0, 21) << (32 - 21); + im21 = assemble_21(field(insn, 0, 21)) << (32 - 21); gen_movl_T1_reg(r); gen_movl_T0_im(im21); gen_op_addl_T1_T0(); @@ -2001,12 +2013,12 @@ { uint32_t b, w1, s, w2, n, w, disp; b = field(insn, 21, 5); - w1 = field_signext(insn, 16, 5); + w1 = field(insn, 16, 5); s = field(insn, 13, 3); w2 = field(insn, 2, 11); n = field(insn, 1, 1); w = field(insn, 0, 1); - disp = (((((w1 << 11) | w2) << 1) | w) << 2); + disp = signext(assemble_17(w1,w2,w),17) << 2; /* */ /* FIXME */ @@ -2019,11 +2031,11 @@ uint32_t t, w, w1, ext3, w2, n, disp; ext3 = field(insn, 13, 3); t = field(insn, 21, 5); - w1 = field_signext(insn, 16, 5); + w1 = field(insn, 16, 5); w2 = field(insn, 2, 11); n = field(insn, 1, 1); w = field(insn, 0, 1); - disp = (((((w1 << 11) | w2) << 1) | w) << 2); + disp = signext(assemble_17(w1,w2,w),17) << 2; switch(ext3) { case 0: /* BL */ /* TODO: dc->iaoq[1] + 4 into t */ |
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From: Stuart B. <zu...@us...> - 2007-03-21 23:37:41
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv11730 Modified Files: translate.c Log Message: Fix bug in assemble_12() -- bit 9 was lost. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.37 retrieving revision 1.38 diff -u -d -r1.37 -r1.38 --- translate.c 21 Mar 2007 23:07:45 -0000 1.37 +++ translate.c 21 Mar 2007 23:37:38 -0000 1.38 @@ -97,7 +97,7 @@ } static uint32_t assemble_12(uint32_t x, uint32_t y) { - return (y << 11) | ((x & 1) << 10) | ((x >> 1) & ~(~0 << 9)); + return (y << 11) | ((x & 1) << 10) | ((x >> 1) & ~(~0 << 10)); } static GenOpFunc *gen_op_movl_TN_reg[3][32] = |
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From: Stuart B. <zu...@us...> - 2007-03-21 23:07:48
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv32004 Modified Files: translate.c Log Message: Fix branch displacement calculation for COMI?B[TF] and ADDI?B[TF]. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.36 retrieving revision 1.37 diff -u -d -r1.36 -r1.37 --- translate.c 21 Mar 2007 20:20:00 -0000 1.36 +++ translate.c 21 Mar 2007 23:07:45 -0000 1.37 @@ -96,6 +96,10 @@ return val; } +static uint32_t assemble_12(uint32_t x, uint32_t y) { + return (y << 11) | ((x & 1) << 10) | ((x >> 1) & ~(~0 << 9)); +} + static GenOpFunc *gen_op_movl_TN_reg[3][32] = { { @@ -1783,10 +1787,10 @@ } } c = field(insn, 13, 3); - w1 = field_signext(insn, 2, 11); + w1 = field(insn, 2, 11); n = field(insn, 1, 1); w = field(insn, 0, 1); - disp = (((w1 << 1) | w) << 2); + disp = signext(assemble_12(w1, w), 12) << 2; gen_cond_sub[c](); gen_branch_cond(dc, (long)dc->tb, disp, n, 0); @@ -1874,10 +1878,10 @@ } } c = field(insn, 13, 3); - w1 = field_signext(insn, 2, 11); + w1 = field(insn, 2, 11); n = field(insn, 1, 1); w = field(insn, 0, 1); - disp = (((w1 << 1) | w) << 2); + disp = signext(assemble_12(w1, w), 12) << 2; gen_cond_add[c](); gen_branch_cond(dc, (long)dc->tb, disp, n, 0); @@ -1919,6 +1923,7 @@ case 0x31: /* BB */ case 0x32: /* MOVB */ case 0x33: /* MOVIB */ + /* disp = signext(assemble_12(w1, w), 12) << 2; */ /* FIXME */ dc->is_br = 1; break; |
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From: Stuart B. <zu...@us...> - 2007-03-21 21:17:57
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv9083 Modified Files: op.c Log Message: Fix bug in op_goto_tb1() (passed the wrong TB number to GOTO_TB). Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.26 retrieving revision 1.27 diff -u -d -r1.26 -r1.27 --- op.c 16 Mar 2007 21:33:42 -0000 1.26 +++ op.c 21 Mar 2007 21:17:50 -0000 1.27 @@ -741,7 +741,7 @@ void OPPROTO op_goto_tb1(void) { - GOTO_TB(op_goto_tb1, PARAM1, 0); + GOTO_TB(op_goto_tb1, PARAM1, 1); } void OPPROTO op_exit_tb(void) |
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From: Stuart B. <zu...@us...> - 2007-03-21 20:20:13
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv13669 Modified Files: translate.c Log Message: Restore iaoq[1] from tb->cs_base. Don't call gen_op_exit_tb() twice for branches. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.35 retrieving revision 1.36 diff -u -d -r1.35 -r1.36 --- translate.c 21 Mar 2007 00:42:45 -0000 1.35 +++ translate.c 21 Mar 2007 20:20:00 -0000 1.36 @@ -803,9 +803,9 @@ dc->tb = tb; pc_start = tb->pc; dc->iaoq[0] = pc_start; - dc->iaoq[1] = pc_start + 4; + dc->iaoq[1] = (target_ulong) tb->cs_base; last_pc = dc->iaoq[0]; - dc->iasq[0] = dc->iasq[1] = tb->cs_base; + dc->iasq[0] = dc->iasq[1] = 0; /* FIXME */ gen_opc_ptr = gen_opc_buf; gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; gen_opparam_ptr = gen_opparam_buf; @@ -859,8 +859,8 @@ { save_state(dc); gen_goto_tb(dc, 0, dc->iaoq[0], dc->iaoq[1]); + gen_op_exit_tb(); } - gen_op_exit_tb(); exit_gen_loop: *gen_opc_ptr = INDEX_op_end; |
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From: Stuart B. <zu...@us...> - 2007-03-21 00:42:52
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv28359 Modified Files: translate.c Log Message: Fix silly bug in field_lowsignext(). Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.34 retrieving revision 1.35 diff -u -d -r1.34 -r1.35 --- translate.c 20 Mar 2007 01:41:13 -0000 1.34 +++ translate.c 21 Mar 2007 00:42:45 -0000 1.35 @@ -82,10 +82,10 @@ static uint32_t field_lowsignext(uint32_t val, int start, int length) { if (val & (1 << start)) { val >>= start + 1; - val |= ~0 << length; + val |= ~0 << (length - 1); } else { val >>= start + 1; - val &= ~(~0 << length); + val &= ~(~0 << (length - 1)); } return val; } |
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From: Stuart B. <zu...@us...> - 2007-03-20 01:55:25
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv28433 Modified Files: translate.c Log Message: Comment on the direct use of gen_op_*_raw and gen_op_*_phys. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.33 retrieving revision 1.34 diff -u -d -r1.33 -r1.34 --- translate.c 20 Mar 2007 01:12:56 -0000 1.33 +++ translate.c 20 Mar 2007 01:41:13 -0000 1.34 @@ -1564,6 +1564,10 @@ { uint32_t ext4 = field(insn, 6, 4); switch(ext4) { + /* XXX: gen_op_*_raw only works for user-mode emulation + * we really need gen_load and gen_store to be macros + * to allow _phys and _virtual to be used + */ case 0x00: /* LDBX, LDBS */ gen_load(insn, 0, gen_op_ldb_raw); break; |
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From: Stuart B. <zu...@us...> - 2007-03-20 01:12:59
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv17422 Modified Files: translate.c Log Message: Fix LDO translation. (Stored the result in T1 but returned T0.) Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.32 retrieving revision 1.33 diff -u -d -r1.32 -r1.33 --- translate.c 19 Mar 2007 23:41:11 -0000 1.32 +++ translate.c 20 Mar 2007 01:12:56 -0000 1.33 @@ -1677,7 +1677,7 @@ im14 = field_lowsignext(insn, 0, 14); gen_movl_T0_reg(b); gen_movl_T1_im(im14); - gen_op_addl_T0_T1(); + gen_op_addl_T1_T0(); gen_movl_reg_T0(t); break; } |
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From: Stuart B. <zu...@us...> - 2007-03-20 00:22:44
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv13117 Modified Files: translate.c Log Message: Use the correct gen_op_movl_* micro-ops in the gen_op_movl_* arrays. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.31 retrieving revision 1.32 diff -u -d -r1.31 -r1.32 --- translate.c 17 Mar 2007 01:51:31 -0000 1.31 +++ translate.c 19 Mar 2007 23:41:11 -0000 1.32 @@ -99,110 +99,6 @@ static GenOpFunc *gen_op_movl_TN_reg[3][32] = { { - gen_op_movl_gr0_T0, - gen_op_movl_gr1_T0, - gen_op_movl_gr2_T0, - gen_op_movl_gr3_T0, - gen_op_movl_gr4_T0, - gen_op_movl_gr5_T0, - gen_op_movl_gr6_T0, - gen_op_movl_gr7_T0, - gen_op_movl_gr8_T0, - gen_op_movl_gr9_T0, - gen_op_movl_gr10_T0, - gen_op_movl_gr11_T0, - gen_op_movl_gr12_T0, - gen_op_movl_gr13_T0, - gen_op_movl_gr14_T0, - gen_op_movl_gr15_T0, - gen_op_movl_gr16_T0, - gen_op_movl_gr17_T0, - gen_op_movl_gr18_T0, - gen_op_movl_gr19_T0, - gen_op_movl_gr20_T0, - gen_op_movl_gr21_T0, - gen_op_movl_gr22_T0, - gen_op_movl_gr23_T0, - gen_op_movl_gr24_T0, - gen_op_movl_gr25_T0, - gen_op_movl_gr26_T0, - gen_op_movl_gr27_T0, - gen_op_movl_gr28_T0, - gen_op_movl_gr29_T0, - gen_op_movl_gr30_T0, - gen_op_movl_gr31_T0, - }, { - gen_op_movl_gr0_T1, - gen_op_movl_gr1_T1, - gen_op_movl_gr2_T1, - gen_op_movl_gr3_T1, - gen_op_movl_gr4_T1, - gen_op_movl_gr5_T1, - gen_op_movl_gr6_T1, - gen_op_movl_gr7_T1, - gen_op_movl_gr8_T1, - gen_op_movl_gr9_T1, - gen_op_movl_gr10_T1, - gen_op_movl_gr11_T1, - gen_op_movl_gr12_T1, - gen_op_movl_gr13_T1, - gen_op_movl_gr14_T1, - gen_op_movl_gr15_T1, - gen_op_movl_gr16_T1, - gen_op_movl_gr17_T1, - gen_op_movl_gr18_T1, - gen_op_movl_gr19_T1, - gen_op_movl_gr20_T1, - gen_op_movl_gr21_T1, - gen_op_movl_gr22_T1, - gen_op_movl_gr23_T1, - gen_op_movl_gr24_T1, - gen_op_movl_gr25_T1, - gen_op_movl_gr26_T1, - gen_op_movl_gr27_T1, - gen_op_movl_gr28_T1, - gen_op_movl_gr29_T1, - gen_op_movl_gr30_T1, - gen_op_movl_gr31_T1, - }, { - gen_op_movl_gr0_T2, - gen_op_movl_gr1_T2, - gen_op_movl_gr2_T2, - gen_op_movl_gr3_T2, - gen_op_movl_gr4_T2, - gen_op_movl_gr5_T2, - gen_op_movl_gr6_T2, - gen_op_movl_gr7_T2, - gen_op_movl_gr8_T2, - gen_op_movl_gr9_T2, - gen_op_movl_gr10_T2, - gen_op_movl_gr11_T2, - gen_op_movl_gr12_T2, - gen_op_movl_gr13_T2, - gen_op_movl_gr14_T2, - gen_op_movl_gr15_T2, - gen_op_movl_gr16_T2, - gen_op_movl_gr17_T2, - gen_op_movl_gr18_T2, - gen_op_movl_gr19_T2, - gen_op_movl_gr20_T2, - gen_op_movl_gr21_T2, - gen_op_movl_gr22_T2, - gen_op_movl_gr23_T2, - gen_op_movl_gr24_T2, - gen_op_movl_gr25_T2, - gen_op_movl_gr26_T2, - gen_op_movl_gr27_T2, - gen_op_movl_gr28_T2, - gen_op_movl_gr29_T2, - gen_op_movl_gr30_T2, - gen_op_movl_gr31_T2, - } -}; - -static GenOpFunc *gen_op_movl_reg_TN[3][32] = -{ - { gen_op_movl_T0_gr0, gen_op_movl_T0_gr1, gen_op_movl_T0_gr2, @@ -304,78 +200,111 @@ } }; -static GenOpFunc *gen_op_movl_TN_cr[2][32] = +static GenOpFunc *gen_op_movl_reg_TN[3][32] = { { - gen_op_movl_cr0_T0, - gen_op_movl_cr1_T0, - gen_op_movl_cr2_T0, - gen_op_movl_cr3_T0, - gen_op_movl_cr4_T0, - gen_op_movl_cr5_T0, - gen_op_movl_cr6_T0, - gen_op_movl_cr7_T0, - gen_op_movl_cr8_T0, - gen_op_movl_cr9_T0, - gen_op_movl_cr10_T0, - gen_op_movl_cr11_T0, - gen_op_movl_cr12_T0, - gen_op_movl_cr13_T0, - gen_op_movl_cr14_T0, - gen_op_movl_cr15_T0, - gen_op_movl_cr16_T0, - gen_op_movl_cr17_T0, - gen_op_movl_cr18_T0, - gen_op_movl_cr19_T0, - gen_op_movl_cr20_T0, - gen_op_movl_cr21_T0, - gen_op_movl_cr22_T0, - gen_op_movl_cr23_T0, - gen_op_movl_cr24_T0, - gen_op_movl_cr25_T0, - gen_op_movl_cr26_T0, - gen_op_movl_cr27_T0, - gen_op_movl_cr28_T0, - gen_op_movl_cr29_T0, - gen_op_movl_cr30_T0, - gen_op_movl_cr31_T0, + gen_op_movl_gr0_T0, + gen_op_movl_gr1_T0, + gen_op_movl_gr2_T0, + gen_op_movl_gr3_T0, + gen_op_movl_gr4_T0, + gen_op_movl_gr5_T0, + gen_op_movl_gr6_T0, + gen_op_movl_gr7_T0, + gen_op_movl_gr8_T0, + gen_op_movl_gr9_T0, + gen_op_movl_gr10_T0, + gen_op_movl_gr11_T0, + gen_op_movl_gr12_T0, + gen_op_movl_gr13_T0, + gen_op_movl_gr14_T0, + gen_op_movl_gr15_T0, + gen_op_movl_gr16_T0, + gen_op_movl_gr17_T0, + gen_op_movl_gr18_T0, + gen_op_movl_gr19_T0, + gen_op_movl_gr20_T0, + gen_op_movl_gr21_T0, + gen_op_movl_gr22_T0, + gen_op_movl_gr23_T0, + gen_op_movl_gr24_T0, + gen_op_movl_gr25_T0, + gen_op_movl_gr26_T0, + gen_op_movl_gr27_T0, + gen_op_movl_gr28_T0, + gen_op_movl_gr29_T0, + gen_op_movl_gr30_T0, + gen_op_movl_gr31_T0, }, { - gen_op_movl_cr0_T1, - gen_op_movl_cr1_T1, - gen_op_movl_cr2_T1, - gen_op_movl_cr3_T1, - gen_op_movl_cr4_T1, - gen_op_movl_cr5_T1, - gen_op_movl_cr6_T1, - gen_op_movl_cr7_T1, - gen_op_movl_cr8_T1, - gen_op_movl_cr9_T1, - gen_op_movl_cr10_T1, - gen_op_movl_cr11_T1, - gen_op_movl_cr12_T1, - gen_op_movl_cr13_T1, - gen_op_movl_cr14_T1, - gen_op_movl_cr15_T1, - gen_op_movl_cr16_T1, - gen_op_movl_cr17_T1, - gen_op_movl_cr18_T1, - gen_op_movl_cr19_T1, - gen_op_movl_cr20_T1, - gen_op_movl_cr21_T1, - gen_op_movl_cr22_T1, - gen_op_movl_cr23_T1, - gen_op_movl_cr24_T1, - gen_op_movl_cr25_T1, - gen_op_movl_cr26_T1, - gen_op_movl_cr27_T1, - gen_op_movl_cr28_T1, - gen_op_movl_cr29_T1, - gen_op_movl_cr30_T1, - gen_op_movl_cr31_T1, + gen_op_movl_gr0_T1, + gen_op_movl_gr1_T1, + gen_op_movl_gr2_T1, + gen_op_movl_gr3_T1, + gen_op_movl_gr4_T1, + gen_op_movl_gr5_T1, + gen_op_movl_gr6_T1, + gen_op_movl_gr7_T1, + gen_op_movl_gr8_T1, + gen_op_movl_gr9_T1, + gen_op_movl_gr10_T1, + gen_op_movl_gr11_T1, + gen_op_movl_gr12_T1, + gen_op_movl_gr13_T1, + gen_op_movl_gr14_T1, + gen_op_movl_gr15_T1, + gen_op_movl_gr16_T1, + gen_op_movl_gr17_T1, + gen_op_movl_gr18_T1, + gen_op_movl_gr19_T1, + gen_op_movl_gr20_T1, + gen_op_movl_gr21_T1, + gen_op_movl_gr22_T1, + gen_op_movl_gr23_T1, + gen_op_movl_gr24_T1, + gen_op_movl_gr25_T1, + gen_op_movl_gr26_T1, + gen_op_movl_gr27_T1, + gen_op_movl_gr28_T1, + gen_op_movl_gr29_T1, + gen_op_movl_gr30_T1, + gen_op_movl_gr31_T1, + }, { + gen_op_movl_gr0_T2, + gen_op_movl_gr1_T2, + gen_op_movl_gr2_T2, + gen_op_movl_gr3_T2, + gen_op_movl_gr4_T2, + gen_op_movl_gr5_T2, + gen_op_movl_gr6_T2, + gen_op_movl_gr7_T2, + gen_op_movl_gr8_T2, + gen_op_movl_gr9_T2, + gen_op_movl_gr10_T2, + gen_op_movl_gr11_T2, + gen_op_movl_gr12_T2, + gen_op_movl_gr13_T2, + gen_op_movl_gr14_T2, + gen_op_movl_gr15_T2, + gen_op_movl_gr16_T2, + gen_op_movl_gr17_T2, + gen_op_movl_gr18_T2, + gen_op_movl_gr19_T2, + gen_op_movl_gr20_T2, + gen_op_movl_gr21_T2, + gen_op_movl_gr22_T2, + gen_op_movl_gr23_T2, + gen_op_movl_gr24_T2, + gen_op_movl_gr25_T2, + gen_op_movl_gr26_T2, + gen_op_movl_gr27_T2, + gen_op_movl_gr28_T2, + gen_op_movl_gr29_T2, + gen_op_movl_gr30_T2, + gen_op_movl_gr31_T2, } }; -static GenOpFunc *gen_op_movl_cr_TN[2][32] = +static GenOpFunc *gen_op_movl_TN_cr[2][32] = { { gen_op_movl_T0_cr0, @@ -446,30 +375,78 @@ } }; -static GenOpFunc *gen_op_movl_TN_sr[2][8] = +static GenOpFunc *gen_op_movl_cr_TN[2][32] = { { - gen_op_movl_sr0_T0, - gen_op_movl_sr1_T0, - gen_op_movl_sr2_T0, - gen_op_movl_sr3_T0, - gen_op_movl_sr4_T0, - gen_op_movl_sr5_T0, - gen_op_movl_sr6_T0, - gen_op_movl_sr7_T0, + gen_op_movl_cr0_T0, + gen_op_movl_cr1_T0, + gen_op_movl_cr2_T0, + gen_op_movl_cr3_T0, + gen_op_movl_cr4_T0, + gen_op_movl_cr5_T0, + gen_op_movl_cr6_T0, + gen_op_movl_cr7_T0, + gen_op_movl_cr8_T0, + gen_op_movl_cr9_T0, + gen_op_movl_cr10_T0, + gen_op_movl_cr11_T0, + gen_op_movl_cr12_T0, + gen_op_movl_cr13_T0, + gen_op_movl_cr14_T0, + gen_op_movl_cr15_T0, + gen_op_movl_cr16_T0, + gen_op_movl_cr17_T0, + gen_op_movl_cr18_T0, + gen_op_movl_cr19_T0, + gen_op_movl_cr20_T0, + gen_op_movl_cr21_T0, + gen_op_movl_cr22_T0, + gen_op_movl_cr23_T0, + gen_op_movl_cr24_T0, + gen_op_movl_cr25_T0, + gen_op_movl_cr26_T0, + gen_op_movl_cr27_T0, + gen_op_movl_cr28_T0, + gen_op_movl_cr29_T0, + gen_op_movl_cr30_T0, + gen_op_movl_cr31_T0, }, { - gen_op_movl_sr0_T1, - gen_op_movl_sr1_T1, - gen_op_movl_sr2_T1, - gen_op_movl_sr3_T1, - gen_op_movl_sr4_T1, - gen_op_movl_sr5_T1, - gen_op_movl_sr6_T1, - gen_op_movl_sr7_T1, + gen_op_movl_cr0_T1, + gen_op_movl_cr1_T1, + gen_op_movl_cr2_T1, + gen_op_movl_cr3_T1, + gen_op_movl_cr4_T1, + gen_op_movl_cr5_T1, + gen_op_movl_cr6_T1, + gen_op_movl_cr7_T1, + gen_op_movl_cr8_T1, + gen_op_movl_cr9_T1, + gen_op_movl_cr10_T1, + gen_op_movl_cr11_T1, + gen_op_movl_cr12_T1, + gen_op_movl_cr13_T1, + gen_op_movl_cr14_T1, + gen_op_movl_cr15_T1, + gen_op_movl_cr16_T1, + gen_op_movl_cr17_T1, + gen_op_movl_cr18_T1, + gen_op_movl_cr19_T1, + gen_op_movl_cr20_T1, + gen_op_movl_cr21_T1, + gen_op_movl_cr22_T1, + gen_op_movl_cr23_T1, + gen_op_movl_cr24_T1, + gen_op_movl_cr25_T1, + gen_op_movl_cr26_T1, + gen_op_movl_cr27_T1, + gen_op_movl_cr28_T1, + gen_op_movl_cr29_T1, + gen_op_movl_cr30_T1, + gen_op_movl_cr31_T1, } }; -static GenOpFunc *gen_op_movl_sr_TN[2][32] = +static GenOpFunc *gen_op_movl_TN_sr[2][8] = { { gen_op_movl_T0_sr0, @@ -480,7 +457,7 @@ gen_op_movl_T0_sr5, gen_op_movl_T0_sr6, gen_op_movl_T0_sr7, - }, { + }, { gen_op_movl_T1_sr0, gen_op_movl_T1_sr1, gen_op_movl_T1_sr2, @@ -492,6 +469,29 @@ } }; +static GenOpFunc *gen_op_movl_sr_TN[2][32] = +{ + { + gen_op_movl_sr0_T0, + gen_op_movl_sr1_T0, + gen_op_movl_sr2_T0, + gen_op_movl_sr3_T0, + gen_op_movl_sr4_T0, + gen_op_movl_sr5_T0, + gen_op_movl_sr6_T0, + gen_op_movl_sr7_T0, + }, { + gen_op_movl_sr0_T1, + gen_op_movl_sr1_T1, + gen_op_movl_sr2_T1, + gen_op_movl_sr3_T1, + gen_op_movl_sr4_T1, + gen_op_movl_sr5_T1, + gen_op_movl_sr6_T1, + gen_op_movl_sr7_T1, + } +}; + static GenOpFunc1 *gen_op_movl_TN_im[3] = { gen_op_movl_T0_im, gen_op_movl_T1_im, @@ -1248,7 +1248,7 @@ case 10: /* CCR/SCR */ case 11: /* SAR - handled differently on 64-bit */ gen_movl_T0_reg(r); - gen_op_movl_T1_im(0xffff); + gen_movl_T1_im(0xffff); gen_op_and_T1_T0(); gen_movl_cr_T0(10); break; |
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From: Stuart B. <zu...@us...> - 2007-03-19 02:41:46
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv9102 Modified Files: translate.c Log Message: Condition tests should be generated if c or f is set. (Was checking that they were both set, which was incorrect.) Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.28 retrieving revision 1.29 diff -u -d -r1.28 -r1.29 --- translate.c 16 Mar 2007 20:58:57 -0000 1.28 +++ translate.c 17 Mar 2007 00:30:51 -0000 1.29 @@ -1341,32 +1341,32 @@ /* Opcode Extensions */ switch(ext6) { case 0x18: /* ADD */ - if (c && f) + if (c || f) gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; case 0x38: /* ADDO */ gen_op_eval_add_sv(); /* gen_op_overflow_trap(); */ - if (c && f) + if (c || f) gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; case 0x1C: /* ADDC */ - if (c && f) + if (c || f) gen_cond_addc[c](); gen_op_addc_T1_T0_cc(); break; case 0x3C: /* ADDCO */ gen_op_eval_addc_sv(); /* gen_op_overflow_trap(); */ - if (c && f) + if (c || f) gen_cond_addc[c](); gen_op_addc_T1_T0_cc(); break; case 0x19: /* SH1ADD */ gen_shift_T0(1); - if (c && f) + if (c || f) gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; @@ -1374,13 +1374,13 @@ gen_op_eval_add_sv(); /* FIXME */ /* gen_op_overflow_trap(); */ gen_shift_T0(1); - if (c && f) + if (c || f) gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; case 0x1a: /* SH2ADD */ gen_shift_T0(2); - if (c && f) + if (c || f) gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; @@ -1388,13 +1388,13 @@ gen_op_eval_add_sv(); /* FIXME */ /* gen_op_overflow_trap(); */ gen_shift_T0(2); - if (c && f) + if (c || f) gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; case 0x1b: /* SH3ADD */ gen_shift_T0(3); - if (c && f) + if (c || f) gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; @@ -1402,24 +1402,24 @@ gen_op_eval_add_sv(); /* FIXME */ /* gen_op_overflow_trap(); */ gen_shift_T0(3); - if (c && f) + if (c || f) gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; case 0x10: /* SUB */ - if (c && f) + if (c || f) gen_cond_sub[c](); gen_op_sub_T1_T0_cc(); break; case 0x30: /* SUBO */ gen_op_eval_sub_sv(); /* gen_op_overflow_trap(); */ - if (c && f) + if (c || f) gen_cond_sub[c](); gen_op_sub_T1_T0_cc(); break; case 0x13: /* SUBT */ - if (c && f) + if (c || f) gen_cond_sub[c](); /* gen_cond_trap(); */ gen_op_sub_T1_T0_cc(); @@ -1427,91 +1427,91 @@ case 0x33: /* SUBTO */ gen_op_eval_sub_sv(); /* gen_op_overflow_trap(); */ - if (c && f) + if (c || f) gen_cond_sub[c](); /* gen_cond_trap(); */ gen_op_sub_T1_T0_cc(); break; case 0x14: /* SUBB */ - if (c && f) + if (c || f) gen_cond_subb[c](); gen_op_subb_T1_T0_cc(); break; case 0x34: /* SUBBO */ gen_op_eval_subb_sv(); /* gen_op_overflow_trap(); */ - if (c && f) + if (c || f) gen_cond_subb[c](); gen_op_subb_T1_T0_cc(); break; case 0x11: /* DS */ - /* if (c && f) + /* if (c || f) gen_cond_ds[c](); */ gen_op_ds_T1_T0(); break; case 0x00: /* ANDCM */ gen_op_andcm_T1_T0(); - if (c && f) + if (c || f) gen_cond_log[c](); break; case 0x08: /* AND */ gen_op_and_T1_T0(); - if (c && f) + if (c || f) gen_cond_log[c](); break; case 0x09: /* OR */ gen_op_or_T1_T0(); - if (c && f) + if (c || f) gen_cond_log[c](); break; case 0x0A: /* XOR */ gen_op_xor_T1_T0(); - if (c && f) + if (c || f) gen_cond_log[c](); break; case 0x0E: /* UXOR */ gen_op_uxor_T1_T0(); - if (c && f) + if (c || f) gen_cond_unit[c](); break; case 0x22: /* COMCLR */ - if (c && f) + if (c || f) gen_cond_sub[c](); gen_movl_T0_im(0); break; case 0x26: /* UADDCM */ /* FIXME: 'c' specifies unit size */ gen_op_uaddcm_T1_T0(); - if (c && f) + if (c || f) gen_cond_unit[c](); break; case 0x27: /* UADDCMT */ /* FIXME: 'c' specifies unit size */ gen_op_uaddcm_T1_T0(); - if (c && f) + if (c || f) gen_cond_unit[c](); /* gen_cond_trap(); */ break; case 0x28: /* ADDL */ - if (c && f) + if (c || f) gen_cond_add[c](); gen_op_addl_T1_T0(); break; case 0x29: /* SH1ADDL */ gen_shift_T0(1); - if (c && f) + if (c || f) gen_cond_add[c](); gen_op_addl_T1_T0(); break; case 0x2A: /* SH2ADDL */ gen_shift_T0(2); - if (c && f) + if (c || f) gen_cond_add[c](); gen_op_addl_T1_T0(); break; case 0x2B: /* SH3ADDL */ gen_shift_T0(3); - if (c && f) + if (c || f) gen_cond_add[c](); gen_op_addl_T1_T0(); break; @@ -1536,7 +1536,7 @@ break; } gen_movl_reg_T0(t); - if (c && f) + if (c || f) gen_nullify_cond(dc, (long)dc->tb, f); break; } |
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From: Stuart B. <zu...@us...> - 2007-03-19 01:37:45
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv15948 Modified Files: translate.c Log Message: Implement field_lowsignext (lsb of the field is used for the sign), and use this for most ops. Branches use field_signext for their displacements. Fix numerous gen_op_movls that were the wrong way round. Improve comments for indexed loads and short displacement loads/stores. Add condition tests for COMICLR, SUBI/SUBIO and ADDI/ADDIO/ADDIT/ADDITO. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.29 retrieving revision 1.30 diff -u -d -r1.29 -r1.30 --- translate.c 17 Mar 2007 00:30:51 -0000 1.29 +++ translate.c 17 Mar 2007 00:49:09 -0000 1.30 @@ -79,6 +79,17 @@ return val; } +static uint32_t field_lowsignext(uint32_t val, int start, int length) { + if (val & (1 << start)) { + val >>= start + 1; + val |= ~0 << length; + } else { + val >>= start + 1; + val &= ~(~0 << length); + } + return val; +} + static uint32_t signext(uint32_t val, int length) { if (val & (1 << (length - 1))) val |= ~0 << length; @@ -969,7 +980,7 @@ } else { - uint32_t im5 = field_signext(insn, 16, 5); + uint32_t im5 = field_lowsignext(insn, 16, 5); gen_movl_T0_im(im5); } @@ -1006,7 +1017,7 @@ static void gen_store(uint32_t insn, GenOpFunc *op) { - uint32_t im5 = field_signext(insn, 0, 5); + uint32_t im5 = field_lowsignext(insn, 0, 5); uint32_t r = field(insn, 16, 5); uint32_t b = field(insn, 21, 5); int cmplt = get_ldst_cmplt(insn); @@ -1488,9 +1499,10 @@ case 0x27: /* UADDCMT */ /* FIXME: 'c' specifies unit size */ gen_op_uaddcm_T1_T0(); - if (c || f) + if (c || f) { gen_cond_unit[c](); - /* gen_cond_trap(); */ + /* gen_cond_trap(); */ + } break; case 0x28: /* ADDL */ if (c || f) @@ -1545,36 +1557,36 @@ { uint32_t ext4 = field(insn, 6, 4); switch(ext4) { - case 0x00: /* LDB */ + case 0x00: /* LDBX, LDBS */ gen_load(insn, 0, gen_op_ldb_raw); break; - case 0x01: /* LDH */ + case 0x01: /* LDHX, LDHS */ gen_load(insn, 1, gen_op_ldh_raw); break; - case 0x02: /* LDW */ + case 0x02: /* LDWX, LDWS */ gen_load(insn, 2, gen_op_ldw_raw); break; - case 0x06: /* LDWA */ + case 0x06: /* LDWAX, LDWAS */ gen_op_check_priv0(); gen_load(insn, 2, gen_op_ldw_phys); break; - case 0x07: /* LDCW */ + case 0x07: /* LDCWX, LDCWS */ gen_load(insn, 2, gen_op_ldcw_raw); break; - case 0x08: /* STB */ + case 0x08: /* STBS */ gen_store(insn, gen_op_stb_raw); break; - case 0x09: /* STH */ + case 0x09: /* STHS */ gen_store(insn, gen_op_sth_raw); break; - case 0x0A: /* STW */ + case 0x0A: /* STWS */ gen_store(insn, gen_op_stw_raw); break; - case 0x0C: /* STBY */ + case 0x0C: /* STBYS */ break; - case 0x0E: /* STWA */ + case 0x0E: /* STWAS */ gen_store(insn, gen_op_stw_phys); break; @@ -1655,11 +1667,11 @@ uint32_t b, t, im14; b = field(insn, 21, 5); t = field(insn, 16, 5); - im14 = field_signext(insn, 0, 14); - gen_movl_reg_T0(b); + im14 = field_lowsignext(insn, 0, 14); + gen_movl_T0_reg(b); gen_movl_T1_im(im14); gen_op_addl_T0_T1(); - gen_movl_T0_reg(t); + gen_movl_reg_T0(t); break; } @@ -1675,8 +1687,8 @@ b = field(insn, 21, 5); t = field(insn, 16, 5); s = field(insn, 14, 2); - im14 = field_signext(insn, 0, 14); - gen_movl_reg_T0(b); + im14 = field_lowsignext(insn, 0, 14); + gen_movl_T0_reg(b); gen_movl_T1_im(s); /* gen_op_space_sel_T0_T1(); */ gen_movl_T1_im(im14); @@ -1692,7 +1704,7 @@ gen_op_ldst(ldw); break; } - gen_movl_T1_reg(t); + gen_movl_reg_T1(t); break; } @@ -1703,17 +1715,17 @@ case 0x19: /* STH */ case 0x1a: /* STW */ { - uint32_t b, t, s, im14; + uint32_t b, r, s, im14; b = field(insn, 21, 5); - t = field(insn, 16, 5); + r = field(insn, 16, 5); s = field(insn, 14, 2); - im14 = field_signext(insn, 0, 14); - gen_movl_reg_T0(b); + im14 = field_lowsignext(insn, 0, 14); + gen_movl_T0_reg(b); /* gen_movl_T1_im(s); */ /* gen_op_space_sel_T0_T1(); */ gen_movl_T1_im(im14); gen_op_addl_T0_T1(); - gen_movl_reg_T1(t); + gen_movl_reg_T1(r); switch(op) { case 0x18: /* STB */ gen_op_ldst(stb); @@ -1753,7 +1765,7 @@ { uint32_t r, im5; r = field(insn, 21, 5); - im5 = field_signext(insn, 16, 5); + im5 = field_lowsignext(insn, 16, 5); gen_movl_T0_im(im5); gen_movl_T1_reg(r); break; @@ -1783,24 +1795,38 @@ t = field(insn, 16, 5); c = field(insn, 13, 3); f = field(insn, 12, 1); - im11 = field_signext(insn, 0, 11); - gen_movl_reg_T0(r); + im11 = field_lowsignext(insn, 0, 11); + gen_movl_T0_reg(r); gen_movl_T1_im(im11); - gen_op_add_T1_T0(); + if (c || f) + gen_cond_sub[c](); gen_movl_T0_im(0); - gen_movl_T0_reg(t); - break; + gen_movl_reg_T0(t); + if (c || f) + gen_nullify_cond(dc, (long)dc->tb, f); } + break; } case 0x25: /* SUBI, SUBIO */ { - uint32_t r, t, im11; + uint32_t r, t, c, f, o, im11; r = field(insn, 21, 5); t = field(insn, 16, 5); - im11 = field_signext(insn, 0, 11); - gen_movl_reg_T0(r); + c = field(insn, 13, 3); + f = field(insn, 12, 1); + o = field(insn, 11, 1); + im11 = field_lowsignext(insn, 0, 11); + gen_movl_T0_reg(r); + if (o) { + gen_op_eval_sub_sv(); + /* gen_op_overflow_trap(); */ + } + if (c || f) + gen_cond_sub[c](); gen_op_sub_T1_T0_cc(); + if (c || f) + gen_nullify_cond(dc, (long)dc->tb, f); break; } @@ -1830,7 +1856,7 @@ { uint32_t r, im5; r = field(insn, 21, 5); - im5 = field_signext(insn, 16, 5); + im5 = field_lowsignext(insn, 16, 5); gen_movl_T0_im(im5); gen_movl_T1_reg(r); break; @@ -1853,17 +1879,28 @@ case 0x2c: /* ADDIT, ADDITO */ case 0x2d: /* ADDI, ADDIO */ { - uint32_t r, t, im11; + uint32_t r, t, c, f, o, im11; r = field(insn, 21, 5); t = field(insn, 16, 5); - im11 = field_signext(insn, 0, 11); - gen_movl_reg_T0(r); - gen_movl_T0_im(im11); - if(!field(insn, 11, 1)) - gen_op_addit_T0(); - else - gen_op_addito_T0(); - gen_movl_T0_reg(t); + c = field(insn, 13, 3); + f = field(insn, 12, 1); + o = field(insn, 11, 1); + im11 = field_lowsignext(insn, 0, 11); + gen_movl_T0_reg(r); + gen_movl_T1_im(im11); + if (o) { + gen_op_eval_add_sv(); + /* gen_op_overflow_trap(); */ + } + if (c || f) { + gen_cond_add[c](); + if (op == 0x2c) /* ADDIT, ADDITO: */ + ; /* gen_cond_trap(); */ + } + gen_op_add_T1_T0_cc(); + if ((c || f) && (op == 0x2d)) /* ADDI, ADDIO: */ + gen_nullify_cond(dc, (long)dc->tb, f); + gen_movl_reg_T0(t); break; } |
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From: Stuart B. <zu...@us...> - 2007-03-18 22:55:51
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv8774 Modified Files: translate.c Log Message: Update TODO list. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.30 retrieving revision 1.31 diff -C2 -d -r1.30 -r1.31 *** translate.c 17 Mar 2007 00:49:09 -0000 1.30 --- translate.c 17 Mar 2007 01:51:31 -0000 1.31 *************** *** 1113,1121 **** /* TODO: * branches * nullification * conditions * carry - * refactoring */ --- 1113,1128 ---- /* TODO: + * traps + * signals + * spaces + * floating point ops + * misc ops + * refactoring + * + * Mostly done: * branches * nullification * conditions * carry */ |
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From: Stuart B. <zu...@us...> - 2007-03-16 21:33:51
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv4568 Modified Files: op.c Log Message: Better (bitwise) signed overflow tests. Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.25 retrieving revision 1.26 diff -C2 -d -r1.25 -r1.26 *** op.c 16 Mar 2007 21:01:54 -0000 1.25 --- op.c 16 Mar 2007 21:33:42 -0000 1.26 *************** *** 753,762 **** #define signed_overflow_add(op1, op2, res) \ ! ((((int32_t)(op1) < 0) == ((int32_t)(op2) < 0)) && \ ! (((int32_t)(op1) < 0) != ((int32_t)(res) < 0))) #define signed_overflow_sub(op1, op2, res) \ ! ((((int32_t)(op1) < 0) != ((int32_t)(op2) < 0)) && \ ! (((int32_t)(op1) < 0) != ((int32_t)(res) < 0))) void OPPROTO op_eval_never(void) --- 753,760 ---- #define signed_overflow_add(op1, op2, res) \ ! (!!(((op1 ^ op2 ^ ~0) & (op1 ^ res)) >> 31)) #define signed_overflow_sub(op1, op2, res) \ ! (!!(((op1 ^ op2) & (op1 ^ res)) >> 31)) void OPPROTO op_eval_never(void) *************** *** 814,818 **** int32_t res = T0 + T1; T2 = signed_overflow_add(T0, T1, res); - FORCE_RET(); } --- 812,815 ---- |
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From: Stuart B. <zu...@us...> - 2007-03-16 21:02:01
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv24657 Modified Files: op.c Log Message: Remove some unneeded micro-ops. Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.24 retrieving revision 1.25 diff -C2 -d -r1.24 -r1.25 *** op.c 16 Mar 2007 20:58:57 -0000 1.24 --- op.c 16 Mar 2007 21:01:54 -0000 1.25 *************** *** 573,586 **** } - void OPPROTO op_addo_T1_T0(void) - { - /* XXX */ - } - - void OPPROTO op_addco_T1_T0(void) - { - /* XXX */ - } - void OPPROTO op_shift1_T0(void) { --- 573,576 ---- *************** *** 643,661 **** } - void OPPROTO op_subo_T1_T0(void) - { - /* XXX */ - } - - void OPPROTO op_subt_T1_T0(void) - { - /* XXX */ - } - - void OPPROTO op_subto_T1_T0(void) - { - /* XXX */ - } - void OPPROTO op_subb_T1_T0_cc(void) { --- 633,636 ---- *************** *** 688,696 **** } - void OPPROTO op_subbo_T1_T0(void) - { - /* XXX */ - } - void OPPROTO op_ds_T1_T0(void) { --- 663,666 ---- |
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From: Stuart B. <zu...@us...> - 2007-03-16 20:59:19
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv22626 Modified Files: op.c translate.c Log Message: Implement conditions for addc/subb. Cleanup of arithmetic ops/conditions. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.27 retrieving revision 1.28 diff -C2 -d -r1.27 -r1.28 *** translate.c 13 Mar 2007 05:57:44 -0000 1.27 --- translate.c 16 Mar 2007 20:58:57 -0000 1.28 *************** *** 653,665 **** /* T0 == opd1, T1 == opd2 */ ! static GenOpFunc * const gen_cond_cmp[8] = { gen_op_eval_never, ! gen_op_eval_cmp_eq, ! gen_op_eval_cmp_slt, ! gen_op_eval_cmp_slteq, ! gen_op_eval_cmp_ult, ! gen_op_eval_cmp_ulteq, ! gen_op_eval_cmp_sv, ! gen_op_eval_cmp_od, }; --- 653,689 ---- /* T0 == opd1, T1 == opd2 */ ! static GenOpFunc * const gen_cond_sub[8] = { gen_op_eval_never, ! gen_op_eval_sub_eq, ! gen_op_eval_sub_slt, ! gen_op_eval_sub_slteq, ! gen_op_eval_sub_ult, ! gen_op_eval_sub_ulteq, ! gen_op_eval_sub_sv, ! gen_op_eval_sub_od, ! }; ! ! /* T0 == opd1, T1 == opd2 */ ! static GenOpFunc * const gen_cond_addc[8] = { ! gen_op_eval_never, ! gen_op_eval_addc_eq, ! gen_op_eval_addc_slt, ! gen_op_eval_addc_slteq, ! gen_op_eval_addc_nuv, ! gen_op_eval_addc_znv, ! gen_op_eval_addc_sv, ! gen_op_eval_addc_od, ! }; ! ! /* T0 == opd1, T1 == opd2 */ ! static GenOpFunc * const gen_cond_subb[8] = { ! gen_op_eval_never, ! gen_op_eval_subb_eq, ! gen_op_eval_subb_slt, ! gen_op_eval_subb_slteq, ! gen_op_eval_subb_ult, ! gen_op_eval_subb_ulteq, ! gen_op_eval_subb_sv, ! gen_op_eval_subb_od, }; *************** *** 1330,1401 **** break; case 0x1C: /* ADDC */ gen_op_addc_T1_T0_cc(); break; case 0x3C: /* ADDCO */ ! gen_op_addco_T1_T0(); break; case 0x19: /* SH1ADD */ gen_shift_T0(1); if (c && f) ! gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; case 0x39: /* SH1ADDO */ gen_shift_T0(1); if (c && f) ! gen_cond_add[c](); ! gen_op_addo_T1_T0(); break; case 0x1a: /* SH2ADD */ gen_shift_T0(2); if (c && f) ! gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; case 0x3a: /* SH2ADDO */ gen_shift_T0(2); if (c && f) ! gen_cond_add[c](); ! gen_op_addo_T1_T0(); break; case 0x1b: /* SH3ADD */ gen_shift_T0(3); if (c && f) ! gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; case 0x3b: /* SH3ADDO */ gen_shift_T0(3); if (c && f) ! gen_cond_add[c](); ! gen_op_addo_T1_T0(); break; case 0x10: /* SUB */ if (c && f) ! gen_cond_cmp[c](); gen_op_sub_T1_T0_cc(); break; case 0x30: /* SUBO */ if (c && f) ! gen_cond_cmp[c](); ! gen_op_sub_T1_T0(); break; case 0x13: /* SUBT */ if (c && f) ! gen_cond_cmp[c](); ! gen_op_subt_T1_T0(); break; case 0x33: /* SUBTO */ if (c && f) ! gen_cond_cmp[c](); ! gen_op_subto_T1_T0(); break; case 0x14: /* SUBB */ gen_op_subb_T1_T0_cc(); break; case 0x34: /* SUBBO */ ! gen_op_subbo_T1_T0(); break; case 0x11: /* DS */ gen_op_ds_T1_T0(); break; --- 1354,1451 ---- break; case 0x1C: /* ADDC */ + if (c && f) + gen_cond_addc[c](); gen_op_addc_T1_T0_cc(); break; case 0x3C: /* ADDCO */ ! gen_op_eval_addc_sv(); ! /* gen_op_overflow_trap(); */ ! if (c && f) ! gen_cond_addc[c](); ! gen_op_addc_T1_T0_cc(); break; case 0x19: /* SH1ADD */ gen_shift_T0(1); if (c && f) ! gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; case 0x39: /* SH1ADDO */ + gen_op_eval_add_sv(); /* FIXME */ + /* gen_op_overflow_trap(); */ gen_shift_T0(1); if (c && f) ! gen_cond_add[c](); /* FIXME */ ! gen_op_add_T1_T0_cc(); break; case 0x1a: /* SH2ADD */ gen_shift_T0(2); if (c && f) ! gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; case 0x3a: /* SH2ADDO */ + gen_op_eval_add_sv(); /* FIXME */ + /* gen_op_overflow_trap(); */ gen_shift_T0(2); if (c && f) ! gen_cond_add[c](); /* FIXME */ ! gen_op_add_T1_T0_cc(); break; case 0x1b: /* SH3ADD */ gen_shift_T0(3); if (c && f) ! gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; case 0x3b: /* SH3ADDO */ + gen_op_eval_add_sv(); /* FIXME */ + /* gen_op_overflow_trap(); */ gen_shift_T0(3); if (c && f) ! gen_cond_add[c](); /* FIXME */ ! gen_op_add_T1_T0_cc(); break; case 0x10: /* SUB */ if (c && f) ! gen_cond_sub[c](); gen_op_sub_T1_T0_cc(); break; case 0x30: /* SUBO */ + gen_op_eval_sub_sv(); + /* gen_op_overflow_trap(); */ if (c && f) ! gen_cond_sub[c](); ! gen_op_sub_T1_T0_cc(); break; case 0x13: /* SUBT */ if (c && f) ! gen_cond_sub[c](); ! /* gen_cond_trap(); */ ! gen_op_sub_T1_T0_cc(); break; case 0x33: /* SUBTO */ + gen_op_eval_sub_sv(); + /* gen_op_overflow_trap(); */ if (c && f) ! gen_cond_sub[c](); ! /* gen_cond_trap(); */ ! gen_op_sub_T1_T0_cc(); break; case 0x14: /* SUBB */ + if (c && f) + gen_cond_subb[c](); gen_op_subb_T1_T0_cc(); break; case 0x34: /* SUBBO */ ! gen_op_eval_subb_sv(); ! /* gen_op_overflow_trap(); */ ! if (c && f) ! gen_cond_subb[c](); ! gen_op_subb_T1_T0_cc(); break; case 0x11: /* DS */ + /* if (c && f) + gen_cond_ds[c](); */ gen_op_ds_T1_T0(); break; *************** *** 1427,1431 **** case 0x22: /* COMCLR */ if (c && f) ! gen_cond_cmp[c](); gen_movl_T0_im(0); break; --- 1477,1481 ---- case 0x22: /* COMCLR */ if (c && f) ! gen_cond_sub[c](); gen_movl_T0_im(0); break; *************** *** 1716,1720 **** disp = (((w1 << 1) | w) << 2); ! gen_cond_cmp[c](); gen_branch_cond(dc, (long)dc->tb, disp, n, 0); --- 1766,1770 ---- disp = (((w1 << 1) | w) << 2); ! gen_cond_sub[c](); gen_branch_cond(dc, (long)dc->tb, disp, n, 0); Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.23 retrieving revision 1.24 diff -C2 -d -r1.23 -r1.24 *** op.c 13 Mar 2007 05:57:44 -0000 1.23 --- op.c 16 Mar 2007 20:58:57 -0000 1.24 *************** *** 782,785 **** --- 782,793 ---- /* Compare operations */ + #define signed_overflow_add(op1, op2, res) \ + ((((int32_t)(op1) < 0) == ((int32_t)(op2) < 0)) && \ + (((int32_t)(op1) < 0) != ((int32_t)(res) < 0))) + + #define signed_overflow_sub(op1, op2, res) \ + ((((int32_t)(op1) < 0) != ((int32_t)(op2) < 0)) && \ + (((int32_t)(op1) < 0) != ((int32_t)(res) < 0))) + void OPPROTO op_eval_never(void) { *************** *** 799,803 **** void OPPROTO op_eval_add_eq(void) { ! T2 = (T0 == -T1); } --- 807,812 ---- void OPPROTO op_eval_add_eq(void) { ! uint32_t res = T0 + T1; ! T2 = (res == 0); } *************** *** 805,809 **** void OPPROTO op_eval_add_slt(void) { ! T2 = ((int32_t)T0 < -(int32_t)T1); } --- 814,819 ---- void OPPROTO op_eval_add_slt(void) { ! int32_t res = T0 + T1; ! T2 = ((res < 0) != signed_overflow_add(T0, T1, res)); } *************** *** 811,815 **** void OPPROTO op_eval_add_slteq(void) { ! T2 = ((int32_t)T0 <= -(int32_t)T1); } --- 821,826 ---- void OPPROTO op_eval_add_slteq(void) { ! int32_t res = T0 + T1; ! T2 = ((res == 0) || ((res < 0) != signed_overflow_add(T0, T1, res))); } *************** *** 817,821 **** void OPPROTO op_eval_add_nuv(void) { ! T2 = (T0 + T1 >= T0); } --- 828,833 ---- void OPPROTO op_eval_add_nuv(void) { ! uint32_t res = T0 + T1; ! T2 = (res >= T0); } *************** *** 823,827 **** void OPPROTO op_eval_add_znv(void) { ! T2 = ((T0 + T1 == 0) || (T0 + T1 >= T0)); } --- 835,840 ---- void OPPROTO op_eval_add_znv(void) { ! uint32_t res = T0 + T1; ! T2 = ((res == 0) || (res >= T0)); } *************** *** 829,845 **** void OPPROTO op_eval_add_sv(void) { ! if ((((int32_t)T0 < 0) == ((int32_t)T1 < 0)) && ! (((int32_t)T0 < 0) != ((int32_t)(T0 + T1) < 0))) ! T2 = 0; else ! T2 = 1; FORCE_RET(); } /* od */ ! void OPPROTO op_eval_add_od(void) { ! T2 = ((T0 + T1) & 1); } --- 842,914 ---- void OPPROTO op_eval_add_sv(void) { ! int32_t res = T0 + T1; ! T2 = signed_overflow_add(T0, T1, res); ! FORCE_RET(); ! } ! ! /* od */ ! void OPPROTO op_eval_add_od(void) ! { ! uint32_t res = T0 + T1; ! T2 = (res & 1); ! } ! ! /* Addition conditions with carry */ ! ! /* = */ ! void OPPROTO op_eval_addc_eq(void) ! { ! uint32_t res = T0 + T1 + !!(env->psw & PSW_CB7); ! T2 = (res == 0); ! } ! ! /* < */ ! void OPPROTO op_eval_addc_slt(void) ! { ! int32_t res = T0 + T1 + !!(env->psw & PSW_CB7); ! T2 = ((res < 0) != signed_overflow_add(T0, T1, res)); ! } ! ! /* <= */ ! void OPPROTO op_eval_addc_slteq(void) ! { ! int32_t res = T0 + T1 + !!(env->psw & PSW_CB7); ! T2 = ((res == 0) || ((res < 0) != signed_overflow_add(T0, T1, res))); ! } ! ! /* nuv */ ! void OPPROTO op_eval_addc_nuv(void) ! { ! uint32_t res = T0 + T1 + !!(env->psw & PSW_CB7); ! if (env->psw & PSW_CB7) ! T2 = (res > T0); else ! T2 = (res >= T0); ! FORCE_RET(); ! } + /* znv */ + void OPPROTO op_eval_addc_znv(void) + { + uint32_t res = T0 + T1 + !!(env->psw & PSW_CB7); + if (env->psw & PSW_CB7) + T2 = ((res == 0) || (res > T0)); + else + T2 = ((res == 0) || (res >= T0)); FORCE_RET(); } + /* sv */ + void OPPROTO op_eval_addc_sv(void) + { + int32_t res = T0 + T1 + !!(env->psw & PSW_CB7); + T2 = signed_overflow_add(T0, T1, res); + } + /* od */ ! void OPPROTO op_eval_addc_od(void) { ! uint32_t res = T0 + T1 + !!(env->psw & PSW_CB7); ! T2 = (res & 1); } *************** *** 849,897 **** /* = */ ! void OPPROTO op_eval_cmp_eq(void) { ! T2 = (T0 == T1); } /* < */ ! void OPPROTO op_eval_cmp_slt(void) { ! T2 = ((int32_t)T0 < (int32_t)T1); } /* <= */ ! void OPPROTO op_eval_cmp_slteq(void) { ! T2 = ((int32_t)T0 <= (int32_t)T1); } /* << */ ! void OPPROTO op_eval_cmp_ult(void) { ! T2 = (T0 < T1); } /* <<= */ ! void OPPROTO op_eval_cmp_ulteq(void) { ! T2 = (T0 <= T1); } /* sv */ ! void OPPROTO op_eval_cmp_sv(void) { ! if ((((int32_t)T0 < 0) != ((int32_t)T1 < 0)) && ! (((int32_t)T0 < 0) != ((int32_t)(T0 - T1) < 0))) ! T2 = 1; ! else ! T2 = 0; ! FORCE_RET(); } /* od */ ! void OPPROTO op_eval_cmp_od(void) { ! T2 = ((T0 - T1) & 1); } --- 918,1018 ---- /* = */ ! void OPPROTO op_eval_sub_eq(void) { ! uint32_t res = T0 - T1; ! T2 = (res == 0); } /* < */ ! void OPPROTO op_eval_sub_slt(void) { ! int32_t res = T0 - T1; ! T2 = ((res < 0) != signed_overflow_sub(T0, T1, res)); } /* <= */ ! void OPPROTO op_eval_sub_slteq(void) { ! int32_t res = T0 - T1; ! T2 = ((res == 0) || ((res < 0) != signed_overflow_sub(T0, T1, res))); } /* << */ ! void OPPROTO op_eval_sub_ult(void) { ! uint32_t res = T0 - T1; ! T2 = (res < 0); } /* <<= */ ! void OPPROTO op_eval_sub_ulteq(void) { ! uint32_t res = T0 - T1; ! T2 = ((res == 0) || (res < T0)); } /* sv */ ! void OPPROTO op_eval_sub_sv(void) { ! int32_t res = T0 - T1; ! T2 = signed_overflow_sub(T0, T1, res); ! } ! /* od */ ! void OPPROTO op_eval_sub_od(void) ! { ! int32_t res = T0 - T1; ! T2 = (res & 1); ! } ! ! /* Compare operations with borrow */ ! ! /* = */ ! void OPPROTO op_eval_subb_eq(void) ! { ! uint32_t res = T0 - T1 - !(env->psw & PSW_CB7); ! T2 = (res == 0); ! } ! ! /* < */ ! void OPPROTO op_eval_subb_slt(void) ! { ! int32_t res = T0 - T1 - !(env->psw & PSW_CB7); ! T2 = ((res < 0) != signed_overflow_sub(T0, T1, res)); ! } ! ! /* <= */ ! void OPPROTO op_eval_subb_slteq(void) ! { ! int32_t res = T0 - T1 - !(env->psw & PSW_CB7); ! T2 = ((res == 0) || ((res < 0) != signed_overflow_sub(T0, T1, res))); ! } ! ! /* << */ ! void OPPROTO op_eval_subb_ult(void) ! { ! uint32_t res = T0 - T1 - !(env->psw & PSW_CB7); ! T2 = (res < 0); ! } ! ! /* <<= */ ! void OPPROTO op_eval_subb_ulteq(void) ! { ! uint32_t res = T0 - T1 - !(env->psw & PSW_CB7); ! T2 = ((res == 0) || (res < T0)); ! } ! ! /* sv */ ! void OPPROTO op_eval_subb_sv(void) ! { ! int32_t res = T0 - T1 - !(env->psw & PSW_CB7); ! T2 = signed_overflow_sub(T0, T1, res); } /* od */ ! void OPPROTO op_eval_subb_od(void) { ! int32_t res = T0 - T1 - !(env->psw & PSW_CB7); ! T2 = (res & 1); } |
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From: Stuart B. <zu...@us...> - 2007-03-13 05:58:03
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv17867/target-hppa Modified Files: op.c translate.c Log Message: UADDCM comments/fixes. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.26 retrieving revision 1.27 diff -C2 -d -r1.26 -r1.27 *** translate.c 13 Mar 2007 05:37:19 -0000 1.26 --- translate.c 13 Mar 2007 05:57:44 -0000 1.27 *************** *** 1431,1442 **** break; case 0x26: /* UADDCM */ ! gen_op_com_T1(); ! gen_op_addl_T1_T0(); if (c && f) gen_cond_unit[c](); break; case 0x27: /* UADDCMT */ ! gen_op_com_T1(); ! gen_op_addl_T1_T0(); if (c && f) gen_cond_unit[c](); --- 1431,1442 ---- break; case 0x26: /* UADDCM */ ! /* FIXME: 'c' specifies unit size */ ! gen_op_uaddcm_T1_T0(); if (c && f) gen_cond_unit[c](); break; case 0x27: /* UADDCMT */ ! /* FIXME: 'c' specifies unit size */ ! gen_op_uaddcm_T1_T0(); if (c && f) gen_cond_unit[c](); Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.22 retrieving revision 1.23 diff -C2 -d -r1.22 -r1.23 *** op.c 13 Mar 2007 05:37:19 -0000 1.22 --- op.c 13 Mar 2007 05:57:44 -0000 1.23 *************** *** 708,714 **** } ! void OPPROTO op_uaddcmt_T1_T0(void) { /* XXX */ } --- 708,715 ---- } ! void OPPROTO op_uaddcm_T1_T0(void) { /* XXX */ + /* store carry in T2 */ } |
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From: Stuart B. <zu...@us...> - 2007-03-13 05:37:26
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv9452/target-hppa Modified Files: op.c translate.c Log Message: Implement nullification, and logical and unit conditions. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.25 retrieving revision 1.26 diff -C2 -d -r1.25 -r1.26 *** translate.c 13 Mar 2007 02:50:44 -0000 1.25 --- translate.c 13 Mar 2007 05:37:19 -0000 1.26 *************** *** 640,643 **** --- 640,644 ---- } + /* T0 == opd1, T1 == opd2 */ static GenOpFunc * const gen_cond_add[8] = { gen_op_eval_never, *************** *** 651,654 **** --- 652,656 ---- }; + /* T0 == opd1, T1 == opd2 */ static GenOpFunc * const gen_cond_cmp[8] = { gen_op_eval_never, *************** *** 662,665 **** --- 664,703 ---- }; + /* T0 == res */ + static GenOpFunc * const gen_cond_log[8] = { + gen_op_eval_never, + gen_op_eval_log_eq, + gen_op_eval_log_slt, + gen_op_eval_log_slteq, + gen_op_eval_never, /* undefined */ + gen_op_eval_never, /* undefined */ + gen_op_eval_never, /* undefined */ + gen_op_eval_log_od, + }; + + /* T0 == res */ + static GenOpFunc * const gen_cond_unit[8] = { + gen_op_eval_never, + gen_op_eval_never, /* undefined */ + gen_op_eval_unit_sbz, + gen_op_eval_unit_shz, + gen_op_eval_unit_sdc, + gen_op_eval_never, /* undefined */ + gen_op_eval_unit_sbc, + gen_op_eval_unit_shc, + }; + + /* T0 == res, T2 == carry */ + static GenOpFunc * const gen_cond_sed[8] = { + gen_op_eval_never, + gen_op_eval_log_eq, + gen_op_eval_log_slt, + gen_op_eval_log_od, + gen_op_eval_always, + gen_op_eval_log_neq, + gen_op_eval_log_sgteq, + gen_op_eval_log_ev, + }; + static void gen_branch_cond(DisasContext *dc, long tb, target_ulong disp, int n, int f) { *************** *** 671,677 **** if (f) - gen_op_jz_T2_label(l1); - else gen_op_jnz_T2_label(l1); /* taken branch */ --- 709,715 ---- if (f) gen_op_jnz_T2_label(l1); + else + gen_op_jz_T2_label(l1); /* taken branch */ *************** *** 690,693 **** --- 728,754 ---- } + static void gen_nullify_cond(DisasContext *dc, long tb, int f) + { + int l1; + + l1 = gen_new_label(); + + if (f) + gen_op_jnz_T2_label(l1); + else + gen_op_jz_T2_label(l1); + + /* nullify */ + gen_goto_tb(dc, 0, dc->iaoq[1] + 4, dc->iaoq[1] + 8); + + gen_set_label(l1); + + /* don't nullify */ + gen_goto_tb(dc, 1, dc->iaoq[1], dc->iaoq[1] + 4); + + /* FIXME */ + dc->is_br = 1; + } + static void save_state(DisasContext *dc) { *************** *** 1024,1039 **** */ - /* two possible ways to do nullification - * easiest is probably to generate code to check the N flag on each insn - * (which also sucks) - * - * actually can use the DisasContext so that checking is only done - * where the insn could be anulled - */ - - /* possily anulled? */ - - /* if so, check N flag. if set, branch and clear flag */ - /* Major Opcodes */ switch(op) { --- 1085,1088 ---- *************** *** 1256,1262 **** case 0x02: /* Arith/Log */ { ! uint32_t t, r1, r2; r2 = field(insn, 21, 5); r1 = field(insn, 16, 5); ext6 = field(insn, 6, 6); t = field(insn, 0, 5); --- 1305,1313 ---- case 0x02: /* Arith/Log */ { ! uint32_t t, f, c, r1, r2; r2 = field(insn, 21, 5); r1 = field(insn, 16, 5); + c = field(insn, 13, 3); + f = field(insn, 12, 1); ext6 = field(insn, 6, 6); t = field(insn, 0, 5); *************** *** 1267,1278 **** switch(ext6) { case 0x18: /* ADD */ gen_op_add_T1_T0_cc(); break; case 0x38: /* ADDO */ ! gen_op_copy_T2_T0(); ! gen_op_addo_T1_T0(); ! /* if sign(T0) != sign(T1) && ! sign(T1) == sign(T2) ! overflow(); */ break; case 0x1C: /* ADDC */ --- 1318,1331 ---- switch(ext6) { case 0x18: /* ADD */ + if (c && f) + gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; case 0x38: /* ADDO */ ! gen_op_eval_add_sv(); ! /* gen_op_overflow_trap(); */ ! if (c && f) ! gen_cond_add[c](); ! gen_op_add_T1_T0_cc(); break; case 0x1C: /* ADDC */ *************** *** 1284,1319 **** case 0x19: /* SH1ADD */ gen_shift_T0(1); gen_op_add_T1_T0_cc(); break; case 0x39: /* SH1ADDO */ gen_shift_T0(1); gen_op_addo_T1_T0(); break; case 0x1a: /* SH2ADD */ gen_shift_T0(2); gen_op_add_T1_T0_cc(); break; case 0x3a: /* SH2ADDO */ gen_shift_T0(2); gen_op_addo_T1_T0(); break; case 0x1b: /* SH3ADD */ gen_shift_T0(3); gen_op_add_T1_T0_cc(); break; case 0x3b: /* SH3ADDO */ gen_shift_T0(3); gen_op_addo_T1_T0(); break; case 0x10: /* SUB */ gen_op_sub_T1_T0_cc(); break; case 0x30: /* SUBO */ ! gen_op_subo_T1_T0(); break; case 0x13: /* SUBT */ gen_op_subt_T1_T0(); break; case 0x33: /* SUBTO */ gen_op_subto_T1_T0(); break; --- 1337,1392 ---- case 0x19: /* SH1ADD */ gen_shift_T0(1); + if (c && f) + gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; case 0x39: /* SH1ADDO */ gen_shift_T0(1); + if (c && f) + gen_cond_add[c](); gen_op_addo_T1_T0(); break; case 0x1a: /* SH2ADD */ gen_shift_T0(2); + if (c && f) + gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; case 0x3a: /* SH2ADDO */ gen_shift_T0(2); + if (c && f) + gen_cond_add[c](); gen_op_addo_T1_T0(); break; case 0x1b: /* SH3ADD */ gen_shift_T0(3); + if (c && f) + gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; case 0x3b: /* SH3ADDO */ gen_shift_T0(3); + if (c && f) + gen_cond_add[c](); gen_op_addo_T1_T0(); break; case 0x10: /* SUB */ + if (c && f) + gen_cond_cmp[c](); gen_op_sub_T1_T0_cc(); break; case 0x30: /* SUBO */ ! if (c && f) ! gen_cond_cmp[c](); ! gen_op_sub_T1_T0(); break; case 0x13: /* SUBT */ + if (c && f) + gen_cond_cmp[c](); gen_op_subt_T1_T0(); break; case 0x33: /* SUBTO */ + if (c && f) + gen_cond_cmp[c](); gen_op_subto_T1_T0(); break; *************** *** 1329,1368 **** case 0x00: /* ANDCM */ gen_op_andcm_T1_T0(); break; case 0x08: /* AND */ gen_op_and_T1_T0(); break; case 0x09: /* OR */ gen_op_or_T1_T0(); break; case 0x0A: /* XOR */ gen_op_xor_T1_T0(); break; case 0x0E: /* UXOR */ gen_op_uxor_T1_T0(); break; case 0x22: /* COMCLR */ ! gen_op_comclr_T1_T0(); break; case 0x26: /* UADDCM */ gen_op_com_T1(); gen_op_addl_T1_T0(); break; case 0x27: /* UADDCMT */ ! gen_op_uaddcmt_T1_T0(); break; case 0x28: /* ADDL */ gen_op_addl_T1_T0(); break; case 0x29: /* SH1ADDL */ gen_shift_T0(1); gen_op_addl_T1_T0(); break; case 0x2A: /* SH2ADDL */ gen_shift_T0(2); gen_op_addl_T1_T0(); break; case 0x2B: /* SH3ADDL */ gen_shift_T0(3); gen_op_addl_T1_T0(); break; --- 1402,1467 ---- case 0x00: /* ANDCM */ gen_op_andcm_T1_T0(); + if (c && f) + gen_cond_log[c](); break; case 0x08: /* AND */ gen_op_and_T1_T0(); + if (c && f) + gen_cond_log[c](); break; case 0x09: /* OR */ gen_op_or_T1_T0(); + if (c && f) + gen_cond_log[c](); break; case 0x0A: /* XOR */ gen_op_xor_T1_T0(); + if (c && f) + gen_cond_log[c](); break; case 0x0E: /* UXOR */ gen_op_uxor_T1_T0(); + if (c && f) + gen_cond_unit[c](); break; case 0x22: /* COMCLR */ ! if (c && f) ! gen_cond_cmp[c](); ! gen_movl_T0_im(0); break; case 0x26: /* UADDCM */ gen_op_com_T1(); gen_op_addl_T1_T0(); + if (c && f) + gen_cond_unit[c](); break; case 0x27: /* UADDCMT */ ! gen_op_com_T1(); ! gen_op_addl_T1_T0(); ! if (c && f) ! gen_cond_unit[c](); ! /* gen_cond_trap(); */ break; case 0x28: /* ADDL */ + if (c && f) + gen_cond_add[c](); gen_op_addl_T1_T0(); break; case 0x29: /* SH1ADDL */ gen_shift_T0(1); + if (c && f) + gen_cond_add[c](); gen_op_addl_T1_T0(); break; case 0x2A: /* SH2ADDL */ gen_shift_T0(2); + if (c && f) + gen_cond_add[c](); gen_op_addl_T1_T0(); break; case 0x2B: /* SH3ADDL */ gen_shift_T0(3); + if (c && f) + gen_cond_add[c](); gen_op_addl_T1_T0(); break; *************** *** 1388,1391 **** --- 1487,1492 ---- } gen_movl_reg_T0(t); + if (c && f) + gen_nullify_cond(dc, (long)dc->tb, f); break; } Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.21 retrieving revision 1.22 diff -C2 -d -r1.21 -r1.22 *** op.c 13 Mar 2007 02:50:44 -0000 1.21 --- op.c 13 Mar 2007 05:37:19 -0000 1.22 *************** *** 786,789 **** --- 786,794 ---- } + void OPPROTO op_eval_always(void) + { + T2 = 1; + } + /* Addition conditions: * See table 5-4 in PA1.1 Specification *************** *** 890,893 **** --- 895,977 ---- } + /* Logical conditions: + * See table 5-5 in PA1.1 Specification + */ + + /* = */ + void OPPROTO op_eval_log_eq(void) + { + T2 = (T0 == 0); + } + + /* < */ + void OPPROTO op_eval_log_slt(void) + { + T2 = ((int32_t)T0 < 0); + } + + /* <= */ + void OPPROTO op_eval_log_slteq(void) + { + T2 = ((int32_t)T1 <= 0); + } + + /* od */ + void OPPROTO op_eval_log_od(void) + { + T2 = (T0 & 1); + } + + /* Unit conditions: + * See table 5-6 in PA1.1 Specification + */ + + void OPPROTO op_eval_unit_sbz(void) + { + T2 = ((T0 - 0x01010101) & ~T0 & 0x80808080); + } + + void OPPROTO op_eval_unit_shz(void) + { + T2 = ((T0 - 0x00010001) & ~T0 & 0x80008000); + } + + void OPPROTO op_eval_unit_sdc(void) + { + T2 &= 0x88888888; + } + + void OPPROTO op_eval_unit_sbc(void) + { + T2 &= 0x80808080; + } + + void OPPROTO op_eval_unit_shc(void) + { + T2 &= 0x80008000; + } + + /* Shift/extract/deposit conditions + * See table 5-7 in PA1.1 Specification + */ + + /* <> */ + void OPPROTO op_eval_log_neq(void) + { + T2 = (T0 != 0); + } + + /* >= */ + void OPPROTO op_eval_log_sgteq(void) + { + T2 = ((int32_t)T0 >= 0); + } + + /* ev */ + void OPPROTO op_eval_log_ev(void) + { + T2 = !(T0 & 1); + } + /* ------ */ |
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From: Stuart B. <zu...@us...> - 2007-03-13 02:50:48
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv9286 Modified Files: op.c translate.c Log Message: Update copyright notices. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.24 retrieving revision 1.25 diff -C2 -d -r1.24 -r1.25 *** translate.c 13 Mar 2007 01:06:01 -0000 1.24 --- translate.c 13 Mar 2007 02:50:44 -0000 1.25 *************** *** 2,6 **** * HPPA translation * ! * Copyright (c) 2005 Stuart Brady <sd...@nt...> * Copyright (c) 2003 Thomas M. Ogrisegg <to...@fn...> * Copyright (c) 2003 Fabrice Bellard --- 2,7 ---- * HPPA translation * ! * Copyright (c) 2005-2007 Stuart Brady <sd...@nt...> ! * Copyright (c) 2007 Randolph Chung <ta...@de...> * Copyright (c) 2003 Thomas M. Ogrisegg <to...@fn...> * Copyright (c) 2003 Fabrice Bellard Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.20 retrieving revision 1.21 diff -C2 -d -r1.20 -r1.21 *** op.c 13 Mar 2007 01:06:01 -0000 1.20 --- op.c 13 Mar 2007 02:50:44 -0000 1.21 *************** *** 2,6 **** * HPPA micro operations * ! * Copyright (c) 2005 Stuart Brady <sd...@nt...> * * This library is free software; you can redistribute it and/or --- 2,7 ---- * HPPA micro operations * ! * Copyright (c) 2005-2007 Stuart Brady <sd...@nt...> ! * Copyright (c) 2007 Randolph Chung <ta...@de...> * * This library is free software; you can redistribute it and/or |
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From: Stuart B. <zu...@us...> - 2007-03-13 01:06:05
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv31735/target-hppa Modified Files: op.c translate.c Log Message: Implement addition conditions. Initial version of ADDBT, ADDIBT, ADDBF and ADDIBF. Fix typo in comment (ADDIOT -> ADDITO). Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.23 retrieving revision 1.24 diff -C2 -d -r1.23 -r1.24 *** translate.c 13 Mar 2007 00:57:45 -0000 1.23 --- translate.c 13 Mar 2007 01:06:01 -0000 1.24 *************** *** 639,642 **** --- 639,653 ---- } + static GenOpFunc * const gen_cond_add[8] = { + gen_op_eval_never, + gen_op_eval_add_eq, + gen_op_eval_add_slt, + gen_op_eval_add_slteq, + gen_op_eval_add_nuv, + gen_op_eval_add_znv, + gen_op_eval_add_sv, + gen_op_eval_add_od, + }; + static GenOpFunc * const gen_cond_cmp[8] = { gen_op_eval_never, *************** *** 1643,1653 **** case 0x26: /* FPYSUB */ case 0x28: /* ADDBT */ case 0x29: /* ADDIBT */ case 0x2a: /* ADDBF */ case 0x2b: /* ADDIBF */ break; ! case 0x2c: /* ADDIT, ADDIOT */ case 0x2d: /* ADDI, ADDIO */ { --- 1654,1703 ---- case 0x26: /* FPYSUB */ + /* TODO */ + break; + case 0x28: /* ADDBT */ case 0x29: /* ADDIBT */ case 0x2a: /* ADDBF */ case 0x2b: /* ADDIBF */ + { + uint32_t c, w1, n, w, disp; + switch(op) { + case 0x28: /* ADDBT */ + case 0x2a: /* ADDBF */ + { + uint32_t r1, r2; + r2 = field(insn, 21, 5); + r1 = field(insn, 16, 5); + gen_movl_T0_reg(r1); + gen_movl_T1_reg(r2); + break; + } + case 0x29: /* ADDIBT */ + case 0x2b: /* ADDIBF */ + { + uint32_t r, im5; + r = field(insn, 21, 5); + im5 = field_signext(insn, 16, 5); + gen_movl_T0_im(im5); + gen_movl_T1_reg(r); + break; + } + } + c = field(insn, 13, 3); + w1 = field_signext(insn, 2, 11); + n = field(insn, 1, 1); + w = field(insn, 0, 1); + disp = (((w1 << 1) | w) << 2); + + gen_cond_add[c](); + gen_branch_cond(dc, (long)dc->tb, disp, n, 0); + + /* FIXME */ + dc->is_br = 1; break; + } ! case 0x2c: /* ADDIT, ADDITO */ case 0x2d: /* ADDI, ADDIO */ { Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.19 retrieving revision 1.20 diff -C2 -d -r1.19 -r1.20 *** op.c 13 Mar 2007 00:57:45 -0000 1.19 --- op.c 13 Mar 2007 01:06:01 -0000 1.20 *************** *** 785,788 **** --- 785,840 ---- } + /* Addition conditions: + * See table 5-4 in PA1.1 Specification + */ + + /* = */ + void OPPROTO op_eval_add_eq(void) + { + T2 = (T0 == -T1); + } + + /* < */ + void OPPROTO op_eval_add_slt(void) + { + T2 = ((int32_t)T0 < -(int32_t)T1); + } + + /* <= */ + void OPPROTO op_eval_add_slteq(void) + { + T2 = ((int32_t)T0 <= -(int32_t)T1); + } + + /* nuv */ + void OPPROTO op_eval_add_nuv(void) + { + T2 = (T0 + T1 >= T0); + } + + /* znv */ + void OPPROTO op_eval_add_znv(void) + { + T2 = ((T0 + T1 == 0) || (T0 + T1 >= T0)); + } + + /* sv */ + void OPPROTO op_eval_add_sv(void) + { + if ((((int32_t)T0 < 0) == ((int32_t)T1 < 0)) && + (((int32_t)T0 < 0) != ((int32_t)(T0 + T1) < 0))) + T2 = 0; + else + T2 = 1; + + FORCE_RET(); + } + + /* od */ + void OPPROTO op_eval_add_od(void) + { + T2 = ((T0 + T1) & 1); + } + /* Compare/subtract conditions: * See table 5-3 in PA1.1 Specification *************** *** 837,841 **** } - /* ------ */ --- 889,892 ---- |
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From: Stuart B. <zu...@us...> - 2007-03-13 00:57:49
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv28906/target-hppa Modified Files: op.c translate.c Log Message: Eliminate condition tests for f = 1. Instead, add 'f' parameter to gen_branch_cond() to negate the condition. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.22 retrieving revision 1.23 diff -C2 -d -r1.22 -r1.23 *** translate.c 12 Mar 2007 20:00:46 -0000 1.22 --- translate.c 13 Mar 2007 00:57:45 -0000 1.23 *************** *** 639,666 **** } ! static GenOpFunc * const gen_cond[2][8] = { ! { ! gen_op_eval_cmp_never, ! gen_op_eval_cmp_eq, ! gen_op_eval_cmp_slt, ! gen_op_eval_cmp_slteq, ! gen_op_eval_cmp_ult, ! gen_op_eval_cmp_ulteq, ! gen_op_eval_cmp_sv, ! gen_op_eval_cmp_od, ! }, ! { ! gen_op_eval_cmp_tr, ! gen_op_eval_cmp_neq, ! gen_op_eval_cmp_sgteq, ! gen_op_eval_cmp_sgt, ! gen_op_eval_cmp_ugteq, ! gen_op_eval_cmp_ugt, ! gen_op_eval_cmp_nsv, ! gen_op_eval_cmp_ev, ! }, }; ! static void gen_branch_cond(DisasContext *dc, long tb, target_ulong disp, int n) { int l1; --- 639,654 ---- } ! static GenOpFunc * const gen_cond_cmp[8] = { ! gen_op_eval_never, ! gen_op_eval_cmp_eq, ! gen_op_eval_cmp_slt, ! gen_op_eval_cmp_slteq, ! gen_op_eval_cmp_ult, ! gen_op_eval_cmp_ulteq, ! gen_op_eval_cmp_sv, ! gen_op_eval_cmp_od, }; ! static void gen_branch_cond(DisasContext *dc, long tb, target_ulong disp, int n, int f) { int l1; *************** *** 670,674 **** l1 = gen_new_label(); ! gen_op_jnz_T2_label(l1); /* taken branch */ --- 658,665 ---- l1 = gen_new_label(); ! if (f) ! gen_op_jz_T2_label(l1); ! else ! gen_op_jnz_T2_label(l1); /* taken branch */ *************** *** 1612,1617 **** disp = (((w1 << 1) | w) << 2); ! gen_cond[0][c](); ! gen_branch_cond(dc, (long)dc->tb, disp, n); /* FIXME */ --- 1603,1608 ---- disp = (((w1 << 1) | w) << 2); ! gen_cond_cmp[c](); ! gen_branch_cond(dc, (long)dc->tb, disp, n, 0); /* FIXME */ Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.18 retrieving revision 1.19 diff -C2 -d -r1.18 -r1.19 *** op.c 12 Mar 2007 20:00:46 -0000 1.18 --- op.c 13 Mar 2007 00:57:45 -0000 1.19 *************** *** 778,792 **** } ! /* Compare/subtract conditions: ! * See table 5-3 in PA1.1 Specification ! */ ! ! /* f = 0 */ ! void OPPROTO op_eval_cmp_never(void) { T2 = 0; } void OPPROTO op_eval_cmp_eq(void) { --- 778,793 ---- } ! /* Compare operations */ ! void OPPROTO op_eval_never(void) { T2 = 0; } + /* Compare/subtract conditions: + * See table 5-3 in PA1.1 Specification + */ + + /* = */ void OPPROTO op_eval_cmp_eq(void) { *************** *** 794,797 **** --- 795,799 ---- } + /* < */ void OPPROTO op_eval_cmp_slt(void) { *************** *** 799,802 **** --- 801,805 ---- } + /* <= */ void OPPROTO op_eval_cmp_slteq(void) { *************** *** 804,807 **** --- 807,811 ---- } + /* << */ void OPPROTO op_eval_cmp_ult(void) { *************** *** 809,812 **** --- 813,817 ---- } + /* <<= */ void OPPROTO op_eval_cmp_ulteq(void) { *************** *** 814,821 **** } void OPPROTO op_eval_cmp_sv(void) { if ((((int32_t)T0 < 0) != ((int32_t)T1 < 0)) && ! (((int32_t)T1 < 0) == ((int32_t)(T0 - T1) < 0))) T2 = 1; else --- 819,827 ---- } + /* sv */ void OPPROTO op_eval_cmp_sv(void) { if ((((int32_t)T0 < 0) != ((int32_t)T1 < 0)) && ! (((int32_t)T0 < 0) != ((int32_t)(T0 - T1) < 0))) T2 = 1; else *************** *** 825,828 **** --- 831,835 ---- } + /* od */ void OPPROTO op_eval_cmp_od(void) { *************** *** 830,878 **** } - /* f = 1 */ - - void OPPROTO op_eval_cmp_tr(void) - { - T2 = 1; - } - - void OPPROTO op_eval_cmp_neq(void) - { - T2 = (T0 != T1); - } - - void OPPROTO op_eval_cmp_sgteq(void) - { - T2 = ((int32_t)T0 >= (int32_t)T1); - } ! void OPPROTO op_eval_cmp_sgt(void) ! { ! T2 = ((int32_t)T0 > (int32_t)T1); ! } ! ! void OPPROTO op_eval_cmp_ugteq(void) ! { ! T2 = (T0 > T1); ! } ! ! void OPPROTO op_eval_cmp_ugt(void) ! { ! T2 = (T0 >= T1); ! } ! ! void OPPROTO op_eval_cmp_nsv(void) ! { ! if ((((int32_t)T0 < 0) != ((int32_t)T1 < 0)) && ! (((int32_t)T1 < 0) == ((int32_t)(T0 - T1) < 0))) ! T2 = 0; ! else ! T2 = 1; ! } ! ! void OPPROTO op_eval_cmp_ev(void) ! { ! T2 = !((T0 - T1) & 1); ! } void OPPROTO op_jmp_im(void) --- 837,842 ---- } ! /* ------ */ void OPPROTO op_jmp_im(void) *************** *** 888,889 **** --- 852,860 ---- FORCE_RET(); } + + void OPPROTO op_jz_T2_label(void) + { + if (!T2) + GOTO_LABEL_PARAM(1); + FORCE_RET(); + } |
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From: Stuart B. <zu...@us...> - 2007-03-12 20:00:50
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv8042/target-hppa Modified Files: op.c translate.c Log Message: Implement compare conditions. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.21 retrieving revision 1.22 diff -C2 -d -r1.21 -r1.22 *** translate.c 12 Mar 2007 18:29:51 -0000 1.21 --- translate.c 12 Mar 2007 20:00:46 -0000 1.22 *************** *** 639,642 **** --- 639,665 ---- } + static GenOpFunc * const gen_cond[2][8] = { + { + gen_op_eval_cmp_never, + gen_op_eval_cmp_eq, + gen_op_eval_cmp_slt, + gen_op_eval_cmp_slteq, + gen_op_eval_cmp_ult, + gen_op_eval_cmp_ulteq, + gen_op_eval_cmp_sv, + gen_op_eval_cmp_od, + }, + { + gen_op_eval_cmp_tr, + gen_op_eval_cmp_neq, + gen_op_eval_cmp_sgteq, + gen_op_eval_cmp_sgt, + gen_op_eval_cmp_ugteq, + gen_op_eval_cmp_ugt, + gen_op_eval_cmp_nsv, + gen_op_eval_cmp_ev, + }, + }; + static void gen_branch_cond(DisasContext *dc, long tb, target_ulong disp, int n) { *************** *** 647,651 **** l1 = gen_new_label(); ! gen_op_jz_T2_label(l1); /* taken branch */ --- 670,674 ---- l1 = gen_new_label(); ! gen_op_jnz_T2_label(l1); /* taken branch */ *************** *** 1568,1573 **** r2 = field(insn, 21, 5); r1 = field(insn, 16, 5); ! gen_op_movl_T0_reg(r1); ! gen_op_movl_T1_reg(r2); break; } --- 1591,1596 ---- r2 = field(insn, 21, 5); r1 = field(insn, 16, 5); ! gen_movl_T0_reg(r1); ! gen_movl_T1_reg(r2); break; } *************** *** 1578,1583 **** r = field(insn, 21, 5); im5 = field_signext(insn, 16, 5); ! gen_op_movl_T0_im(im5); ! gen_op_movl_T1_reg(r); break; } --- 1601,1606 ---- r = field(insn, 21, 5); im5 = field_signext(insn, 16, 5); ! gen_movl_T0_im(im5); ! gen_movl_T1_reg(r); break; } *************** *** 1589,1593 **** disp = (((w1 << 1) | w) << 2); ! /* gen_cond(c); */ gen_branch_cond(dc, (long)dc->tb, disp, n); --- 1612,1616 ---- disp = (((w1 << 1) | w) << 2); ! gen_cond[0][c](); gen_branch_cond(dc, (long)dc->tb, disp, n); Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.17 retrieving revision 1.18 diff -C2 -d -r1.17 -r1.18 *** op.c 12 Mar 2007 18:01:01 -0000 1.17 --- op.c 12 Mar 2007 20:00:46 -0000 1.18 *************** *** 778,781 **** --- 778,879 ---- } + /* Compare/subtract conditions: + * See table 5-3 in PA1.1 Specification + */ + + /* f = 0 */ + + void OPPROTO op_eval_cmp_never(void) + { + T2 = 0; + } + + void OPPROTO op_eval_cmp_eq(void) + { + T2 = (T0 == T1); + } + + void OPPROTO op_eval_cmp_slt(void) + { + T2 = ((int32_t)T0 < (int32_t)T1); + } + + void OPPROTO op_eval_cmp_slteq(void) + { + T2 = ((int32_t)T0 <= (int32_t)T1); + } + + void OPPROTO op_eval_cmp_ult(void) + { + T2 = (T0 < T1); + } + + void OPPROTO op_eval_cmp_ulteq(void) + { + T2 = (T0 <= T1); + } + + void OPPROTO op_eval_cmp_sv(void) + { + if ((((int32_t)T0 < 0) != ((int32_t)T1 < 0)) && + (((int32_t)T1 < 0) == ((int32_t)(T0 - T1) < 0))) + T2 = 1; + else + T2 = 0; + + FORCE_RET(); + } + + void OPPROTO op_eval_cmp_od(void) + { + T2 = ((T0 - T1) & 1); + } + + /* f = 1 */ + + void OPPROTO op_eval_cmp_tr(void) + { + T2 = 1; + } + + void OPPROTO op_eval_cmp_neq(void) + { + T2 = (T0 != T1); + } + + void OPPROTO op_eval_cmp_sgteq(void) + { + T2 = ((int32_t)T0 >= (int32_t)T1); + } + + void OPPROTO op_eval_cmp_sgt(void) + { + T2 = ((int32_t)T0 > (int32_t)T1); + } + + void OPPROTO op_eval_cmp_ugteq(void) + { + T2 = (T0 > T1); + } + + void OPPROTO op_eval_cmp_ugt(void) + { + T2 = (T0 >= T1); + } + + void OPPROTO op_eval_cmp_nsv(void) + { + if ((((int32_t)T0 < 0) != ((int32_t)T1 < 0)) && + (((int32_t)T1 < 0) == ((int32_t)(T0 - T1) < 0))) + T2 = 0; + else + T2 = 1; + } + + void OPPROTO op_eval_cmp_ev(void) + { + T2 = !((T0 - T1) & 1); + } + void OPPROTO op_jmp_im(void) { *************** *** 784,790 **** } ! void OPPROTO op_jz_T2_label(void) { ! if (!T2) GOTO_LABEL_PARAM(1); FORCE_RET(); --- 882,888 ---- } ! void OPPROTO op_jnz_T2_label(void) { ! if (T2) GOTO_LABEL_PARAM(1); FORCE_RET(); |
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From: Stuart B. <zu...@us...> - 2007-03-12 18:29:58
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv3672 Modified Files: translate.c Log Message: Decode COMB[TF] and COMIB[TF] properly. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.20 retrieving revision 1.21 diff -C2 -d -r1.20 -r1.21 *** translate.c 12 Mar 2007 18:01:01 -0000 1.20 --- translate.c 12 Mar 2007 18:29:51 -0000 1.21 *************** *** 1560,1566 **** case 0x23: /* COMIBF */ { ! uint32_t r1, r2, c, w1, n, w, disp; ! r2 = field(insn, 21, 5); ! r1 = field(insn, 16, 5); c = field(insn, 13, 3); w1 = field_signext(insn, 2, 11); --- 1560,1586 ---- case 0x23: /* COMIBF */ { ! uint32_t c, w1, n, w, disp; ! switch(op) { ! case 0x20: /* COMBT */ ! case 0x22: /* COMBF */ ! { ! uint32_t r1, r2; ! r2 = field(insn, 21, 5); ! r1 = field(insn, 16, 5); ! gen_op_movl_T0_reg(r1); ! gen_op_movl_T1_reg(r2); ! break; ! } ! case 0x21: /* COMIBT */ ! case 0x23: /* COMIBF */ ! { ! uint32_t r, im5; ! r = field(insn, 21, 5); ! im5 = field_signext(insn, 16, 5); ! gen_op_movl_T0_im(im5); ! gen_op_movl_T1_reg(r); ! break; ! } ! } c = field(insn, 13, 3); w1 = field_signext(insn, 2, 11); |
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From: Stuart B. <zu...@us...> - 2007-03-12 18:01:08
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv22475 Modified Files: op.c translate.c Log Message: Beginnings of conditional branch support. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.19 retrieving revision 1.20 diff -C2 -d -r1.19 -r1.20 *** translate.c 12 Mar 2007 15:54:19 -0000 1.19 --- translate.c 12 Mar 2007 18:01:01 -0000 1.20 *************** *** 639,642 **** --- 639,667 ---- } + static void gen_branch_cond(DisasContext *dc, long tb, target_ulong disp, int n) + { + int l1; + target_ulong target; + target = dc->iaoq[0] + disp + 8; + + l1 = gen_new_label(); + + gen_op_jz_T2_label(l1); + + /* taken branch */ + if (n && ((int32_t)disp >= 0)) + gen_goto_tb(dc, 0, target, target + 4); + else + gen_goto_tb(dc, 0, dc->iaoq[1], target); + + gen_set_label(l1); + + /* failed branch */ + if (n && ((int32_t)disp < 0)) + gen_goto_tb(dc, 1, dc->iaoq[1] + 4, dc->iaoq[1] + 8); + else + gen_goto_tb(dc, 1, dc->iaoq[1], dc->iaoq[1] + 4); + } + static void save_state(DisasContext *dc) { *************** *** 1527,1535 **** --- 1552,1579 ---- case 0x1b: /* STWM */ + /* FIXME */ + break; + case 0x20: /* COMBT */ case 0x21: /* COMIBT */ case 0x22: /* COMBF */ case 0x23: /* COMIBF */ + { + uint32_t r1, r2, c, w1, n, w, disp; + r2 = field(insn, 21, 5); + r1 = field(insn, 16, 5); + c = field(insn, 13, 3); + w1 = field_signext(insn, 2, 11); + n = field(insn, 1, 1); + w = field(insn, 0, 1); + disp = (((w1 << 1) | w) << 2); + + /* gen_cond(c); */ + gen_branch_cond(dc, (long)dc->tb, disp, n); + + /* FIXME */ + dc->is_br = 1; break; + } case 0x24: /* COMICLR */ Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.16 retrieving revision 1.17 diff -C2 -d -r1.16 -r1.17 *** op.c 12 Mar 2007 15:54:19 -0000 1.16 --- op.c 12 Mar 2007 18:01:01 -0000 1.17 *************** *** 783,784 **** --- 783,791 ---- env->iaoq[1] = env->iaoq[0] + 4; } + + void OPPROTO op_jz_T2_label(void) + { + if (!T2) + GOTO_LABEL_PARAM(1); + FORCE_RET(); + } |
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From: Stuart B. <zu...@us...> - 2007-03-12 15:54:28
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv6875 Modified Files: op.c translate.c Log Message: Whitespace cleanup. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.18 retrieving revision 1.19 diff -C2 -d -r1.18 -r1.19 *** translate.c 12 Mar 2007 15:50:26 -0000 1.18 --- translate.c 12 Mar 2007 15:54:19 -0000 1.19 *************** *** 625,633 **** gen_op_goto_tb1(TBPARAM(tb)); gen_op_save_pc(pc, npc); ! gen_movl_T0_im((long)tb + tb_num); gen_op_exit_tb(); } else { gen_op_save_pc(pc, npc); ! gen_movl_T0_im(0); gen_op_exit_tb(); } --- 625,633 ---- gen_op_goto_tb1(TBPARAM(tb)); gen_op_save_pc(pc, npc); ! gen_movl_T0_im((long)tb + tb_num); gen_op_exit_tb(); } else { gen_op_save_pc(pc, npc); ! gen_movl_T0_im(0); gen_op_exit_tb(); } *************** *** 701,716 **** generate an exception */ if (env->singlestep_enabled) ! break; } if (env->singlestep_enabled) { save_state(dc); ! gen_op_debug(); ! goto exit_gen_loop; } else if (!dc->is_br) { save_state(dc); ! gen_goto_tb(dc, 0, dc->iaoq[0], dc->iaoq[1]); } gen_op_exit_tb(); --- 701,716 ---- generate an exception */ if (env->singlestep_enabled) ! break; } if (env->singlestep_enabled) { save_state(dc); ! gen_op_debug(); ! goto exit_gen_loop; } else if (!dc->is_br) { save_state(dc); ! gen_goto_tb(dc, 0, dc->iaoq[0], dc->iaoq[1]); } gen_op_exit_tb(); *************** *** 882,902 **** { case LDST_CMPLT_MB: ! gen_movl_T1_reg(b); ! gen_op_copy_T2_T0(); /* T2 = dx */ ! gen_op_addl_T1_T0(); /* offset = GR[b] + dx */ ! gen_op_addl_T2_T1(); /* GR[b] += dx */ ! gen_movl_reg_T1(b); ! break; case LDST_CMPLT_MA: ! gen_movl_T1_reg(b); ! gen_op_copy_T2_T1(); /* T2 = GR[b] */ ! gen_op_addl_T0_T1(); /* GR[b] += dx */ ! gen_movl_reg_T1(b); ! gen_op_copy_T0_T2(); /* offset = GR[b] */ ! break; ! default: ! gen_movl_T1_reg(b); ! gen_op_addl_T1_T0(); /* offset = GR[b] + dx */ ! break; } gen_movl_T1_reg(r); --- 882,902 ---- { case LDST_CMPLT_MB: ! gen_movl_T1_reg(b); ! gen_op_copy_T2_T0(); /* T2 = dx */ ! gen_op_addl_T1_T0(); /* offset = GR[b] + dx */ ! gen_op_addl_T2_T1(); /* GR[b] += dx */ ! gen_movl_reg_T1(b); ! break; case LDST_CMPLT_MA: ! gen_movl_T1_reg(b); ! gen_op_copy_T2_T1(); /* T2 = GR[b] */ ! gen_op_addl_T0_T1(); /* GR[b] += dx */ ! gen_movl_reg_T1(b); ! gen_op_copy_T0_T2(); /* offset = GR[b] */ ! break; ! default: ! gen_movl_T1_reg(b); ! gen_op_addl_T1_T0(); /* offset = GR[b] + dx */ ! break; } gen_movl_T1_reg(r); *************** *** 910,914 **** uint32_t r2 = field(insn, 21, 5); uint32_t t = field(insn, 0, 5); ! gen_movl_T1_reg(r1); gen_movl_T2_reg(r2); --- 910,914 ---- uint32_t r2 = field(insn, 21, 5); uint32_t t = field(insn, 0, 5); ! gen_movl_T1_reg(r1); gen_movl_T2_reg(r2); *************** *** 972,976 **** * refactoring */ ! /* two possible ways to do nullification * easiest is probably to generate code to check the N flag on each insn --- 972,976 ---- * refactoring */ ! /* two possible ways to do nullification * easiest is probably to generate code to check the N flag on each insn *************** *** 1019,1023 **** gen_movl_reg_T0(field(insn, 0, 5)); break; ! case 0x73: /* RSM */ gen_op_check_priv0(); --- 1019,1023 ---- gen_movl_reg_T0(field(insn, 0, 5)); break; ! case 0x73: /* RSM */ gen_op_check_priv0(); *************** *** 1114,1118 **** break; } ! case 0x45: /* MFCTL */ { --- 1114,1118 ---- break; } ! case 0x45: /* MFCTL */ { *************** *** 1361,1371 **** break; case 0x08: /* STB */ ! gen_store(insn, gen_op_stb_raw); ! break; case 0x09: /* STH */ ! gen_store(insn, gen_op_sth_raw); ! break; case 0x0A: /* STW */ ! gen_store(insn, gen_op_stw_raw); break; --- 1361,1371 ---- break; case 0x08: /* STB */ ! gen_store(insn, gen_op_stb_raw); ! break; case 0x09: /* STH */ ! gen_store(insn, gen_op_sth_raw); ! break; case 0x0A: /* STW */ ! gen_store(insn, gen_op_stw_raw); break; *************** *** 1374,1378 **** case 0x0E: /* STWA */ ! gen_store(insn, gen_op_stw_phys); break; --- 1374,1378 ---- case 0x0E: /* STWA */ ! gen_store(insn, gen_op_stw_phys); break; *************** *** 1388,1392 **** break; } ! case 0x04: /* SPOPn */ break; --- 1388,1392 ---- break; } ! case 0x04: /* SPOPn */ break; *************** *** 1395,1399 **** case 0x06: /* FMPYADD */ break; ! case 0x08: /* LDIL */ { --- 1395,1399 ---- case 0x06: /* FMPYADD */ break; ! case 0x08: /* LDIL */ { *************** *** 1465,1469 **** case 0x0f: /* Product Specific */ break; ! case 0x10: /* LDB */ case 0x11: /* LDH */ --- 1465,1469 ---- case 0x0f: /* Product Specific */ break; ! case 0x10: /* LDB */ case 0x11: /* LDH */ *************** *** 1525,1529 **** } } ! case 0x1b: /* STWM */ case 0x20: /* COMBT */ --- 1525,1529 ---- } } ! case 0x1b: /* STWM */ case 0x20: /* COMBT */ *************** *** 1570,1574 **** case 0x2b: /* ADDIBF */ break; ! case 0x2c: /* ADDIT, ADDIOT */ case 0x2d: /* ADDI, ADDIO */ --- 1570,1574 ---- case 0x2b: /* ADDIBF */ break; ! case 0x2c: /* ADDIT, ADDIOT */ case 0x2d: /* ADDI, ADDIO */ *************** *** 1595,1599 **** dc->is_br = 1; break; ! case 0x34: /* Extract */ { --- 1595,1599 ---- dc->is_br = 1; break; ! case 0x34: /* Extract */ { *************** *** 1602,1632 **** switch(ext3) { case 0: /* VSHD = SHRPW with SAR */ ! gen_movl_T0_cr(11); ! gen_shrpw(insn); ! break; case 2: /* SHD = SHRPW */ ! { ! uint32_t sa = 31 - field(insn, 5, 5); ! gen_movl_T0_im(sa); ! gen_shrpw(insn); ! break; ! } case 4: /* VEXTRU = EXTRW,U with SAR */ case 5: /* VEXTRS = EXTRW,S with SAR */ ! gen_movl_T0_cr(11); ! gen_extrw(insn); ! break; case 6: /* EXTRU = EXTRW,U */ case 7: /* EXTRS = EXTRW,S */ ! { ! uint32_t pos = field(insn, 5, 5); ! gen_movl_T0_im(pos); ! gen_extrw(insn); break; ! } } break; } ! case 0x35: /* Deposit */ { --- 1602,1632 ---- switch(ext3) { case 0: /* VSHD = SHRPW with SAR */ ! gen_movl_T0_cr(11); ! gen_shrpw(insn); ! break; case 2: /* SHD = SHRPW */ ! { ! uint32_t sa = 31 - field(insn, 5, 5); ! gen_movl_T0_im(sa); ! gen_shrpw(insn); ! break; ! } case 4: /* VEXTRU = EXTRW,U with SAR */ case 5: /* VEXTRS = EXTRW,S with SAR */ ! gen_movl_T0_cr(11); ! gen_extrw(insn); ! break; case 6: /* EXTRU = EXTRW,U */ case 7: /* EXTRS = EXTRW,S */ ! { ! uint32_t pos = field(insn, 5, 5); ! gen_movl_T0_im(pos); ! gen_extrw(insn); break; ! } } break; } ! case 0x35: /* Deposit */ { *************** *** 1636,1667 **** case 0: /* VZDEP = DEPW,Z with SAR */ case 1: /* VDEP = DEPW with SAR */ ! gen_movl_T0_cr(11); ! gen_depw(insn); ! break; case 2: /* ZDEP = DEPW,Z */ case 3: /* DEP = DEPW */ ! { ! uint32_t cpos = field(insn, 5, 5); ! gen_movl_T0_im(cpos); ! gen_depw(insn); ! break; ! } case 4: /* VZDEPI = DEPW,Z */ case 5: /* VDEPI = DEPW,Z */ ! gen_movl_T0_cr(11); ! gen_depwi(insn); ! break; case 6: /* ZDEPI = DEPWI,Z */ case 7: /* DEPI = DEPWI */ ! { ! uint32_t cpos = field(insn, 5, 5); ! gen_movl_T0_im(cpos); ! gen_depwi(insn); ! break; ! } } break; } ! case 0x38: /* BE */ case 0x39: /* BLE */ --- 1636,1667 ---- case 0: /* VZDEP = DEPW,Z with SAR */ case 1: /* VDEP = DEPW with SAR */ ! gen_movl_T0_cr(11); ! gen_depw(insn); ! break; case 2: /* ZDEP = DEPW,Z */ case 3: /* DEP = DEPW */ ! { ! uint32_t cpos = field(insn, 5, 5); ! gen_movl_T0_im(cpos); ! gen_depw(insn); ! break; ! } case 4: /* VZDEPI = DEPW,Z */ case 5: /* VDEPI = DEPW,Z */ ! gen_movl_T0_cr(11); ! gen_depwi(insn); ! break; case 6: /* ZDEPI = DEPWI,Z */ case 7: /* DEPI = DEPWI */ ! { ! uint32_t cpos = field(insn, 5, 5); ! gen_movl_T0_im(cpos); ! gen_depwi(insn); ! break; ! } } break; } ! case 0x38: /* BE */ case 0x39: /* BLE */ *************** *** 1681,1685 **** break; } ! case 0x3a: /* Branch */ { --- 1681,1685 ---- break; } ! case 0x3a: /* Branch */ { *************** *** 1712,1716 **** break; } ! default: /* Illegal Instruction */ gen_op_ill_insn(); --- 1712,1716 ---- break; } ! default: /* Illegal Instruction */ gen_op_ill_insn(); Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.15 retrieving revision 1.16 diff -C2 -d -r1.15 -r1.16 *** op.c 12 Mar 2007 15:50:26 -0000 1.15 --- op.c 12 Mar 2007 15:54:19 -0000 1.16 *************** *** 269,283 **** void OPPROTO op_movl_T0_im(void) { ! T0 = PARAM1; } void OPPROTO op_movl_T1_im(void) { ! T1 = PARAM1; } void OPPROTO op_movl_T2_im(void) { ! T2 = PARAM1; } --- 269,283 ---- void OPPROTO op_movl_T0_im(void) { ! T0 = PARAM1; } void OPPROTO op_movl_T1_im(void) { ! T1 = PARAM1; } void OPPROTO op_movl_T2_im(void) { ! T2 = PARAM1; } *************** *** 440,444 **** tmp = T0; T0 += T1; ! /* calculate carry flags */ carry = (tmp & T1) | ((tmp | T1) & ~T0); --- 440,444 ---- tmp = T0; T0 += T1; ! /* calculate carry flags */ carry = (tmp & T1) | ((tmp | T1) & ~T0); *************** *** 471,475 **** tmp = T0; T0 += T1; ! /* add the carry */ if (env->psw & PSW_CB7) { --- 471,475 ---- tmp = T0; T0 += T1; ! /* add the carry */ if (env->psw & PSW_CB7) { |
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From: Stuart B. <zu...@us...> - 2007-03-12 15:50:30
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv4348/target-hppa Modified Files: op.c translate.c Log Message: Make the ordering of operands in microop names more consistent. Fix BL (branch and link). Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.17 retrieving revision 1.18 diff -C2 -d -r1.17 -r1.18 *** translate.c 12 Mar 2007 14:41:14 -0000 1.17 --- translate.c 12 Mar 2007 15:50:26 -0000 1.18 *************** *** 844,849 **** gen_movl_T1_reg(b); gen_op_copy_T2_T0(); /* copy dx to T2 */ ! gen_op_addl_T0_T1(); /* T0 = GR[b] + dx */ ! gen_op_addl_T1_T2(); /* GR[b] += dx */ gen_movl_reg_T1(b); break; --- 844,849 ---- gen_movl_T1_reg(b); gen_op_copy_T2_T0(); /* copy dx to T2 */ ! gen_op_addl_T1_T0(); /* T0 = GR[b] + dx */ ! gen_op_addl_T2_T1(); /* GR[b] += dx */ gen_movl_reg_T1(b); break; *************** *** 854,858 **** gen_movl_T1_reg(b); gen_op_copy_T2_T1(); ! gen_op_addl_T1_T0(); /* GR[b] += dx */ gen_movl_reg_T1(b); gen_op_copy_T0_T2(); /* T0 = GR[b] */ --- 854,858 ---- gen_movl_T1_reg(b); gen_op_copy_T2_T1(); ! gen_op_addl_T0_T1(); /* GR[b] += dx */ gen_movl_reg_T1(b); gen_op_copy_T0_T2(); /* T0 = GR[b] */ *************** *** 861,865 **** /* dx in T0 */ gen_movl_T1_reg(b); ! gen_op_addl_T0_T1(); /* T0 = GR[b] + dx */ break; } --- 861,865 ---- /* dx in T0 */ gen_movl_T1_reg(b); ! gen_op_addl_T1_T0(); /* T0 = GR[b] + dx */ break; } *************** *** 884,889 **** gen_movl_T1_reg(b); gen_op_copy_T2_T0(); /* T2 = dx */ ! gen_op_addl_T0_T1(); /* offset = GR[b] + dx */ ! gen_op_addl_T1_T2(); /* GR[b] += dx */ gen_movl_reg_T1(b); break; --- 884,889 ---- gen_movl_T1_reg(b); gen_op_copy_T2_T0(); /* T2 = dx */ ! gen_op_addl_T1_T0(); /* offset = GR[b] + dx */ ! gen_op_addl_T2_T1(); /* GR[b] += dx */ gen_movl_reg_T1(b); break; *************** *** 891,895 **** gen_movl_T1_reg(b); gen_op_copy_T2_T1(); /* T2 = GR[b] */ ! gen_op_addl_T1_T0(); /* GR[b] += dx */ gen_movl_reg_T1(b); gen_op_copy_T0_T2(); /* offset = GR[b] */ --- 891,895 ---- gen_movl_T1_reg(b); gen_op_copy_T2_T1(); /* T2 = GR[b] */ ! gen_op_addl_T0_T1(); /* GR[b] += dx */ gen_movl_reg_T1(b); gen_op_copy_T0_T2(); /* offset = GR[b] */ *************** *** 897,901 **** default: gen_movl_T1_reg(b); ! gen_op_addl_T0_T1(); /* offset = GR[b] + dx */ break; } --- 897,901 ---- default: gen_movl_T1_reg(b); ! gen_op_addl_T1_T0(); /* offset = GR[b] + dx */ break; } *************** *** 1210,1215 **** ext6 = field(insn, 6, 6); t = field(insn, 0, 5); ! gen_movl_reg_T0(r1); ! gen_movl_reg_T1(r2); /* Opcode Extensions */ --- 1210,1215 ---- ext6 = field(insn, 6, 6); t = field(insn, 0, 5); ! gen_movl_T0_reg(r1); ! gen_movl_T1_reg(r2); /* Opcode Extensions */ *************** *** 1219,1223 **** break; case 0x38: /* ADDO */ ! gen_op_movl_T0_T2(); gen_op_addo_T1_T0(); /* if sign(T0) != sign(T1) && --- 1219,1223 ---- break; case 0x38: /* ADDO */ ! gen_op_copy_T2_T0(); gen_op_addo_T1_T0(); /* if sign(T0) != sign(T1) && *************** *** 1296,1300 **** case 0x26: /* UADDCM */ gen_op_com_T1(); ! gen_op_addl_T0_T1(); break; case 0x27: /* UADDCMT */ --- 1296,1300 ---- case 0x26: /* UADDCM */ gen_op_com_T1(); ! gen_op_addl_T1_T0(); break; case 0x27: /* UADDCMT */ *************** *** 1302,1318 **** break; case 0x28: /* ADDL */ ! gen_op_addl_T0_T1(); break; case 0x29: /* SH1ADDL */ gen_shift_T0(1); ! gen_op_addl_T0_T1(); break; case 0x2A: /* SH2ADDL */ gen_shift_T0(2); ! gen_op_addl_T0_T1(); break; case 0x2B: /* SH3ADDL */ gen_shift_T0(3); ! gen_op_addl_T0_T1(); break; case 0x2E: /* DCOR */ --- 1302,1318 ---- break; case 0x28: /* ADDL */ ! gen_op_addl_T1_T0(); break; case 0x29: /* SH1ADDL */ gen_shift_T0(1); ! gen_op_addl_T1_T0(); break; case 0x2A: /* SH2ADDL */ gen_shift_T0(2); ! gen_op_addl_T1_T0(); break; case 0x2B: /* SH3ADDL */ gen_shift_T0(3); ! gen_op_addl_T1_T0(); break; case 0x2E: /* DCOR */ *************** *** 1336,1340 **** break; } ! gen_movl_T0_reg(t); break; } --- 1336,1340 ---- break; } ! gen_movl_reg_T0(t); break; } *************** *** 1694,1701 **** switch(ext3) { case 0: /* BL */ ! /* generate (iaoq_next <- iaoq_front + disp + 8) */ ! gen_branch(dc, 0, dc->iaoq[0] + disp + 8, dc->iaoq[0] + disp + 12); ! /* generate (copy iaoq_back + 4 into t) */ ! /* if (n) generate (psw |= PSW_N); */ break; case 2: /* BLR */ --- 1694,1703 ---- switch(ext3) { case 0: /* BL */ ! /* TODO: dc->iaoq[1] + 4 into t */ ! if (n) { ! gen_branch(dc, 0, dc->iaoq[0] + disp + 8, dc->iaoq[0] + disp + 12); ! } else { ! gen_branch(dc, 0, dc->iaoq[1], dc->iaoq[0] + disp + 8); ! } break; case 2: /* BLR */ Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.14 retrieving revision 1.15 diff -C2 -d -r1.14 -r1.15 *** op.c 12 Mar 2007 14:27:29 -0000 1.14 --- op.c 12 Mar 2007 15:50:26 -0000 1.15 *************** *** 499,503 **** /* add logical */ ! void OPPROTO op_addl_T0_T1(void) { T0 += T1; --- 499,503 ---- /* add logical */ ! void OPPROTO op_addl_T1_T0(void) { T0 += T1; *************** *** 505,514 **** } ! void OPPROTO op_addl_T1_T0(void) { T1 += T0; } ! void OPPROTO op_addl_T1_T2(void) { T1 += T2; --- 505,514 ---- } ! void OPPROTO op_addl_T0_T1(void) { T1 += T0; } ! void OPPROTO op_addl_T2_T1(void) { T1 += T2; *************** *** 572,580 **** } - void OPPROTO op_movl_T0_T2(void) - { - /* XXX */ - } - void OPPROTO op_addo_T1_T0(void) { --- 572,575 ---- |
