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From: Stuart B. <zu...@us...> - 2008-02-22 20:19:09
|
Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv6263 Modified Files: translate.c Log Message: List PA2.0 instructions, and use PA2.0 instruction names with PA1.1 names in brackets. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.44 retrieving revision 1.45 diff -u -d -r1.44 -r1.45 --- translate.c 22 Feb 2008 14:45:00 -0000 1.44 +++ translate.c 22 Feb 2008 20:18:58 -0000 1.45 @@ -1153,7 +1153,7 @@ gen_op_break(); break; - case 0x20: /* SYNC, SYNCDMAA */ + case 0x20: /* SYNC/SYNCDMA */ if (field(insn, 20, 1)) gen_op_syncdma(); else @@ -1165,7 +1165,7 @@ dc->is_br = 1; break; - case 0x65: /* RFIR */ + case 0x65: /* RFI,R (RFIR) */ gen_op_rfi(); gen_op_restore_shadow(); dc->is_br = 1; @@ -1206,6 +1206,7 @@ gen_movl_sr_T0(sr); break; } + case 0x25: /* MFSP */ { uint32_t sr = field(insn, 13, 3); @@ -1216,6 +1217,12 @@ gen_movl_reg_T0(t); break; } + +#ifdef TARGET_HPPA64 + case 0xa5: /* MFIA */ + break; +#endif + case 0xc2: /* MTCTL */ { uint32_t t, r; @@ -1272,7 +1279,12 @@ break; } - case 0x45: /* MFCTL */ +#ifdef TARGET_HPPA64 + case 0xc6: /* MTSARCM */ + break; +#endif + + case 0x45: /* MFCTL/MFCTL,W */ { uint32_t r, t; r = field(insn, 21, 5); @@ -1319,12 +1331,17 @@ ext7 = field(insn, 6, 7); switch(ext7) { - case 0x01: /* IITLBA */ - case 0x00: /* IITLBP */ case 0x08: /* PITLB */ case 0x09: /* PITLBE */ - case 0x0a: /* FIC */ + case 0x0a: /* FIC,0A (FIC) */ case 0x0b: /* FICE */ +#ifdef TARGET_HPPA64 + case 0x20: /* IITLBT */ + case 0x18: /* PITLB,L */ +#else + case 0x01: /* IITLBA */ + case 0x00: /* IITLBP */ +#endif break; default: @@ -1337,19 +1354,25 @@ switch (ext8) { - case 0x40: /* IDTLBP */ - case 0x41: /* IDTLBA */ case 0x48: /* PDTLB */ case 0x49: /* PDTLBE */ - case 0x4a: /* FDC */ + case 0x4a: /* FDC (index) */ case 0x4b: /* FDCE */ case 0x4e: /* PDC */ - case 0x46: /* PROBER */ - case 0xc6: /* PROBERI */ - case 0x47: /* PROBEW */ - case 0xc7: /* PROBEWI */ + case 0x46: /* PROBE,R (PROBER) */ + case 0xc6: /* PROBEI,R (PROBERI) */ + case 0x47: /* PROBE,W (PROBEW) */ + case 0xc7: /* PROBEI,W (PROBEWI) */ case 0x4d: /* LPA */ case 0x4c: /* LCI */ +#ifdef TARGET_HPPA64 + case 0x60: /* IDTLBT */ + case 0x58: /* PDTLB,L */ + case 0xca: /* FDC (imm) */ +#else + case 0x41: /* IDTLBA */ + case 0x40: /* IDTLBP */ +#endif break; default: @@ -1379,32 +1402,43 @@ gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; - case 0x38: /* ADDO */ + case 0x28: /* ADD,L (ADDL) */ + if (c || f) + gen_cond_add[c](); + gen_op_addl_T1_T0(); + break; + case 0x38: /* ADD,TSV (ADDO) */ gen_op_eval_add_sv(); /* gen_op_overflow_trap(); */ if (c || f) gen_cond_add[c](); gen_op_add_T1_T0_cc(); break; - case 0x1C: /* ADDC */ + case 0x1c: /* ADD,C (ADDC) */ if (c || f) gen_cond_addc[c](); gen_op_addc_T1_T0_cc(); break; - case 0x3C: /* ADDCO */ + case 0x3c: /* ADD,C,TSV (ADDCO) */ gen_op_eval_addc_sv(); /* gen_op_overflow_trap(); */ if (c || f) gen_cond_addc[c](); gen_op_addc_T1_T0_cc(); break; - case 0x19: /* SH1ADD */ + case 0x19: /* SHLADD (1) (SH1ADD) */ gen_shift_T0(1); if (c || f) gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; - case 0x39: /* SH1ADDO */ + case 0x29: /* SHLADD,L (1) (SH1ADDL) */ + gen_shift_T0(1); + if (c || f) + gen_cond_add[c](); + gen_op_addl_T1_T0(); + break; + case 0x39: /* SHLADD,TSV (1) (SH1ADDO) */ gen_op_eval_add_sv(); /* FIXME */ /* gen_op_overflow_trap(); */ gen_shift_T0(1); @@ -1412,13 +1446,19 @@ gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; - case 0x1a: /* SH2ADD */ + case 0x1a: /* SHLADD (2) (SH2ADD) */ gen_shift_T0(2); if (c || f) gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; - case 0x3a: /* SH2ADDO */ + case 0x2a: /* SHLADD,L (2) (SH2ADDL) */ + gen_shift_T0(2); + if (c || f) + gen_cond_add[c](); + gen_op_addl_T1_T0(); + break; + case 0x3a: /* SHLADD,TSV (2) (SH2ADDO) */ gen_op_eval_add_sv(); /* FIXME */ /* gen_op_overflow_trap(); */ gen_shift_T0(2); @@ -1426,13 +1466,19 @@ gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; - case 0x1b: /* SH3ADD */ + case 0x1b: /* SHLADD (3) (SH3ADD) */ gen_shift_T0(3); if (c || f) gen_cond_add[c](); /* FIXME */ gen_op_add_T1_T0_cc(); break; - case 0x3b: /* SH3ADDO */ + case 0x2b: /* SHLADD,L (3) (SH3ADDL) */ + gen_shift_T0(3); + if (c || f) + gen_cond_add[c](); + gen_op_addl_T1_T0(); + break; + case 0x3b: /* SHLADD,TSV (3) (SH3ADDO) */ gen_op_eval_add_sv(); /* FIXME */ /* gen_op_overflow_trap(); */ gen_shift_T0(3); @@ -1445,20 +1491,20 @@ gen_cond_sub[c](); gen_op_sub_T1_T0_cc(); break; - case 0x30: /* SUBO */ + case 0x30: /* SUB,TSV (SUBO) */ gen_op_eval_sub_sv(); /* gen_op_overflow_trap(); */ if (c || f) gen_cond_sub[c](); gen_op_sub_T1_T0_cc(); break; - case 0x13: /* SUBT */ + case 0x13: /* SUB,TC (SUBT) */ if (c || f) gen_cond_sub[c](); /* gen_cond_trap(); */ gen_op_sub_T1_T0_cc(); break; - case 0x33: /* SUBTO */ + case 0x33: /* SUB,TSV,TC (SUBTO) */ gen_op_eval_sub_sv(); /* gen_op_overflow_trap(); */ if (c || f) @@ -1466,12 +1512,12 @@ /* gen_cond_trap(); */ gen_op_sub_T1_T0_cc(); break; - case 0x14: /* SUBB */ + case 0x14: /* SUB,B (SUBB) */ if (c || f) gen_cond_subb[c](); gen_op_subb_T1_T0_cc(); break; - case 0x34: /* SUBBO */ + case 0x34: /* SUB,B,TSV (SUBBO) */ gen_op_eval_subb_sv(); /* gen_op_overflow_trap(); */ if (c || f) @@ -1498,17 +1544,17 @@ if (c || f) gen_cond_log[c](); break; - case 0x0A: /* XOR */ + case 0x0a: /* XOR */ gen_op_xor_T1_T0(); if (c || f) gen_cond_log[c](); break; - case 0x0E: /* UXOR */ + case 0x0e: /* UXOR */ gen_op_uxor_T1_T0(); if (c || f) gen_cond_unit[c](); break; - case 0x22: /* COMCLR */ + case 0x22: /* CMPCLR (COMCLR) */ if (c || f) gen_cond_sub[c](); gen_movl_T0_im(0); @@ -1519,7 +1565,7 @@ if (c || f) gen_cond_unit[c](); break; - case 0x27: /* UADDCMT */ + case 0x27: /* UADDCM,TC (UADDCMT) */ /* FIXME: 'c' specifies unit size */ gen_op_uaddcm_T1_T0(); if (c || f) { @@ -1527,30 +1573,7 @@ /* gen_cond_trap(); */ } break; - case 0x28: /* ADDL */ - if (c || f) - gen_cond_add[c](); - gen_op_addl_T1_T0(); - break; - case 0x29: /* SH1ADDL */ - gen_shift_T0(1); - if (c || f) - gen_cond_add[c](); - gen_op_addl_T1_T0(); - break; - case 0x2A: /* SH2ADDL */ - gen_shift_T0(2); - if (c || f) - gen_cond_add[c](); - gen_op_addl_T1_T0(); - break; - case 0x2B: /* SH3ADDL */ - gen_shift_T0(3); - if (c || f) - gen_cond_add[c](); - gen_op_addl_T1_T0(); - break; - case 0x2E: /* DCOR */ + case 0x2e: /* DCOR */ if (r1 != 0) gen_op_undef_insn(); else { @@ -1558,7 +1581,7 @@ gen_op_dcor_T0(); } break; - case 0x2F: /* IDCOR */ + case 0x2f: /* DCOR,I (IDCOR) */ if (r1 != 0) gen_op_undef_insn(); else { @@ -1566,6 +1589,23 @@ gen_op_idcor_T0(); } break; + /* FIXME: include MAX-1 (see PA7300LC ERS) */ +#ifdef TARGET_HPPA64 + case 0x0f: /* HADD */ + case 0x0d: /* HADD,SS */ + case 0x0c: /* HADD,US */ + case 0x07: /* HSUB */ + case 0x05: /* HSUB,SS */ + case 0x04: /* HSUB,US */ + case 0x0b: /* HAVG */ + case 0x1d: /* HSHLADD (1) */ + case 0x1e: /* HSHLADD (2) */ + case 0x1f: /* HSHLADD (3) */ + case 0x15: /* HSHRADD (1) */ + case 0x16: /* HSHRADD (2) */ + case 0x17: /* HSHRADD (3) */ + break; +#endif default: /* Undefined Instruction */ gen_op_undef_insn(); break; @@ -1584,52 +1624,57 @@ * we really need gen_load and gen_store to be macros * to allow _phys and _virtual to be used */ - case 0x00: /* LDBX, LDBS */ + case 0x00: /* LDB (index/short) (LDBX/LDBS) */ gen_load(insn, 0, gen_op_ldb_raw); break; - case 0x01: /* LDHX, LDHS */ + case 0x01: /* LDH (index/short) (LDHX/LDHS) */ gen_load(insn, 1, gen_op_ldh_raw); break; - case 0x02: /* LDWX, LDWS */ + case 0x02: /* LDW (index/short) (LDWX/LDWS) */ gen_load(insn, 2, gen_op_ldw_raw); break; - case 0x06: /* LDWAX, LDWAS */ + case 0x06: /* LDWA (index/short) (LDWAX/LDWAS) */ gen_op_check_priv0(); gen_load(insn, 2, gen_op_ldw_phys); break; - case 0x07: /* LDCWX, LDCWS */ + case 0x07: /* LDCW (index/short) (LDCWX/LDCWS) */ gen_load(insn, 2, gen_op_ldcw_raw); break; - case 0x08: /* STBS */ + case 0x08: /* STB (short) (STBS) */ gen_store(insn, gen_op_stb_raw); break; - case 0x09: /* STHS */ + case 0x09: /* STH (short) (STHS) */ gen_store(insn, gen_op_sth_raw); break; - case 0x0A: /* STWS */ + case 0x0a: /* STW (short) (STWS) */ gen_store(insn, gen_op_stw_raw); break; - - case 0x0C: /* STBYS */ + case 0x0c: /* STBY (short) (STBYS) */ + /* XXX */ break; - - case 0x0E: /* STWAS */ + case 0x0e: /* STWA (short) (STWAS) */ gen_store(insn, gen_op_stw_phys); break; - case 0x03: /* LDD */ - case 0x04: /* LDDA */ - case 0x05: /* LDCD */ - case 0x0B: /* STD */ - case 0x0D: /* STDBY */ - case 0x0F: /* STDA */ +#ifdef TARGET_HPPA64 + case 0x03: /* LDD (index/short) */ + case 0x04: /* LDDA (index/short) */ + case 0x05: /* LDCD (index/short) */ + case 0x0b: /* STD (short) */ + case 0x0d: /* STDBY (short) */ + case 0x0f: /* STDA (short) */ /* XXX - pa20 */ break; +#endif } break; } case 0x04: /* SPOPn */ + /* SPOP0 */ + /* SPOP1 */ + /* SPOP2 */ + /* SPOP3 */ break; case 0x05: /* DIAG */ @@ -1651,14 +1696,14 @@ case 0x09: /* Copr_w */ if(!field(insn, 12, 1)) if(!field(insn, 9, 1)) - /* CLDWX */ {} + /* CLDW (index) (CLDWX) */ {} else - /* CSTWX */ {} + /* CSTW (index) (CSTWX) */ {} else if(!field(insn, 9, 1)) - /* CLDWS */ {} + /* CLDW (short) (CLDWS) */ {} else - /* CSTWS */ {} + /* CSTW (short) (CSTWS) */ {} break; case 0x0a: /* ADDIL */ @@ -1676,14 +1721,14 @@ case 0x0b: /* Copr_dw */ if(!field(insn, 12, 1)) if(!field(insn, 9, 1)) - /* CLDDX */ {} + /* CLDD (index) (CLDDX) */ {} else - /* CSTDX */ {} + /* CSTD (index) (CLTDX) */ {} else if(!field(insn, 9, 1)) - /* CLDDS */ {} + /* CLDD (short) (CLDDS) */ {} else - /* CSTDS */ {} + /* CSTD (short) (CSTDS) */ {} break; case 0x0c: /* COPR */ @@ -1735,7 +1780,7 @@ break; } - case 0x13: /* LDWM */ + case 0x13: /* LDW,M (LDWM) post-incr/pre-decr */ { uint32_t b, t, s, im14; b = field(insn, 21, 5); @@ -1760,6 +1805,16 @@ break; } +#ifdef TARGET_HPPA64 + case 0x14: /* Load_dw */ + /* LDD/FLDD (long) */ + break; + + case 0x16: /* FLDW,M */ + case 0x17: /* LDW,M pre-incr/post-decr */ + break; +#endif + case 0x18: /* STB */ case 0x19: /* STH */ case 0x1a: /* STW */ @@ -1789,7 +1844,7 @@ break; } - case 0x1b: /* STWM */ + case 0x1b: /* STW,M (STWM) post-incr/pre-decr */ { uint32_t b, r, s, im14; b = field(insn, 21, 5); @@ -1814,15 +1869,25 @@ break; } - case 0x20: /* COMBT */ - case 0x21: /* COMIBT */ - case 0x22: /* COMBF */ - case 0x23: /* COMIBF */ +#ifdef TARGET_HPPA64 + case 0x1c: /* Store_dw */ + /* STD/FSTD (long) */ + break; + + case 0x1e: /* FSTW,M */ + case 0x1f: /* STW,M pre-incr/post-decr */ + break; +#endif + + case 0x20: /* CMPB (true) (COMBT) */ + case 0x21: /* CMPIB (true) (COMIBT) */ + case 0x22: /* CMPB (false) (COMBF) */ + case 0x23: /* CMPIB (false) (COMIBF) */ { uint32_t f, c, w1, n, w, disp; switch(op) { - case 0x20: /* COMBT */ - case 0x22: /* COMBF */ + case 0x20: /* CMPB (true) (COMBT) */ + case 0x22: /* CMPB (false) (COMBF) */ { uint32_t r1, r2; r2 = field(insn, 21, 5); @@ -1831,8 +1896,8 @@ gen_movl_T1_reg(r2); break; } - case 0x21: /* COMIBT */ - case 0x23: /* COMIBF */ + case 0x21: /* CMPIB (true) (COMIBT) */ + case 0x23: /* CMPIB (false) (COMIBF) */ { uint32_t r, im5; r = field(insn, 21, 5); @@ -1857,7 +1922,7 @@ break; } - case 0x24: /* COMICLR */ + case 0x24: /* CMPICLR (COMICLR) */ { uint32_t r, t, c, f, im11; if (field(insn, 11, 1)) @@ -1880,7 +1945,7 @@ break; } - case 0x25: /* SUBI, SUBIO */ + case 0x25: /* SUBI / SUBI,TSV (SUBIO) */ { uint32_t r, t, c, f, o, im11; r = field(insn, 21, 5); @@ -1902,19 +1967,24 @@ break; } - case 0x26: /* FPYSUB */ + case 0x26: /* FMPYSUB */ /* TODO */ break; - case 0x28: /* ADDBT */ - case 0x29: /* ADDIBT */ - case 0x2a: /* ADDBF */ - case 0x2b: /* ADDIBF */ +#ifdef TARGET_HPPA64 + case 0x27: /* CMPB (dw true) */ + break; +#endif + + case 0x28: /* ADDB (true) (ADDBT) */ + case 0x29: /* ADDIB (true) (ADDIBT) */ + case 0x2a: /* ADDB (false) (ADDBF) */ + case 0x2b: /* ADDIB (false) (ADDIBF) */ { uint32_t f, c, w1, n, w, disp; switch(op) { - case 0x28: /* ADDBT */ - case 0x2a: /* ADDBF */ + case 0x28: /* ADDB (true) (ADDBT) */ + case 0x2a: /* ADDB (false) (ADDBF) */ { uint32_t r1, r2; r2 = field(insn, 21, 5); @@ -1923,8 +1993,8 @@ gen_movl_T1_reg(r2); break; } - case 0x29: /* ADDIBT */ - case 0x2b: /* ADDIBF */ + case 0x29: /* ADDIB (true) (ADDIBT) */ + case 0x2b: /* ADDIB (false) (ADDIBF) */ { uint32_t r, im5; r = field(insn, 21, 5); @@ -1949,8 +2019,8 @@ break; } - case 0x2c: /* ADDIT, ADDITO */ - case 0x2d: /* ADDI, ADDIO */ + case 0x2c: /* ADDI,TC (ADDIT) / ADDI,TSV,TC (ADDITO) */ + case 0x2d: /* ADDI / ADDI,TSV (ADDIO) */ { uint32_t r, t, c, f, o, im11; r = field(insn, 21, 5); @@ -1967,17 +2037,23 @@ } if (c || f) { gen_cond_add[c](); - if (op == 0x2c) /* ADDIT, ADDITO: */ + if (op == 0x2c) /* ADDI,TC (ADDIT) / ADDI,TSV,TC (ADDITO) */ ; /* gen_cond_trap(); */ } gen_op_add_T1_T0_cc(); - if ((c || f) && (op == 0x2d)) /* ADDI, ADDIO: */ + if ((c || f) && (op == 0x2d)) /* ADDI / ADDI,TSV (ADDIO) */ gen_nullify_cond(dc, (long)dc->tb, f); gen_movl_reg_T0(t); break; } - case 0x30: /* BVB */ +#ifdef TARGET_HPPA64 + case 0x2e: /* Fp_fused */ + case 0x2f: /* CMPB (dw false) */ + break; +#endif + + case 0x30: /* BB (sar) (BVB) */ case 0x31: /* BB */ case 0x32: /* MOVB */ case 0x33: /* MOVIB */ @@ -1986,7 +2062,7 @@ dc->is_br = 1; break; - case 0x34: /* Extract */ + case 0x34: /* Shift/Extract */ { uint32_t ext3; ext3 = field(insn, 10, 3); @@ -2054,8 +2130,13 @@ break; } +#ifdef TARGET_HPPA64 + case 0x36: /* EXTRD */ + break; +#endif + case 0x38: /* BE */ - case 0x39: /* BLE */ + case 0x39: /* BE,L (BLE) */ { uint32_t b, w1, s, w2, n, w, disp; b = field(insn, 21, 5); @@ -2083,7 +2164,7 @@ w = field(insn, 0, 1); disp = signext(assemble_17(w1,w2,w),17) << 2; switch(ext3) { - case 0: /* BL */ + case 0: /* B,L (BL) */ /* TODO: dc->iaoq[1] + 4 into t */ if (n) { gen_branch(dc, 0, dc->iaoq[0] + disp + 8, dc->iaoq[0] + disp + 12); @@ -2094,7 +2175,7 @@ case 2: /* BLR */ /* if w == 0 ( ill_insn ) */ case 6: /* BV */ - case 1: /* GATE */ + case 1: /* B,GATE (GATE) */ break; } @@ -2103,6 +2184,26 @@ break; } + case 0x3b: /* CMPIB (dw) */ + break; + +#ifdef TARGET_HPPA64 + case 0x3c: /* DEPD */ + case 0x3d: /* DEPI */ + break; + + case 0x3e: /* Multimedia */ + /* PERMH */ + /* HSHL */ + /* HSHR,U */ + /* HSHR,S */ + /* MIXW,L */ + /* MIXW,R */ + /* MIXH,L */ + /* MIXH,R */ + break; +#endif + default: /* Illegal Instruction */ gen_op_ill_insn(); break; |
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From: Stuart B. <sd...@nt...> - 2008-02-22 16:42:04
|
On Fri, Feb 22, 2008 at 08:00:39AM -0800, Randolph Chung wrote: > I don't remember if there was a specific reason for this, but: > > > + im14 = field_lowsignext(insn, 0, 14); > > is there a reason why field_lowsignext() doesn't return a signed value? > > then we don't have to test for the MSBit explicitly.... I'm not aware of any particular reason -- I think most of our uint32_t variables should be target_ulongs, target_longs, and plain ints. The 14-bit sign-extended immediate values should really be target_longs. The gen_movl_T*_im() functions are also wrong, as they take ints! However, the field_* functions obviously do not need to take values larger than 32 bits, so we should use uint32_t for field() and int32_t for field_signext(), field_lowsignext() and signext(). We do certainly want to support PA2.0 at some point, so definitely worth getting this right! (At the moment, I'm finding out which instructions are added in PA2.0...) Cheers! -- Stuart Brady |
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From: Randolph C. <ran...@ta...> - 2008-02-22 16:00:01
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I don't remember if there was a specific reason for this, but: > + im14 = field_lowsignext(insn, 0, 14); is there a reason why field_lowsignext() doesn't return a signed value? then we don't have to test for the MSBit explicitly.... randolph |
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From: Stuart B. <zu...@us...> - 2008-02-22 14:45:05
|
Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv30515 Modified Files: translate.c Log Message: Implement LDWM and STWM. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.43 retrieving revision 1.44 diff -u -d -r1.43 -r1.44 --- translate.c 22 Feb 2008 02:21:10 -0000 1.43 +++ translate.c 22 Feb 2008 14:45:00 -0000 1.44 @@ -1736,7 +1736,29 @@ } case 0x13: /* LDWM */ + { + uint32_t b, t, s, im14; + b = field(insn, 21, 5); + t = field(insn, 16, 5); + s = field(insn, 14, 2); + im14 = field_lowsignext(insn, 0, 14); + gen_movl_T0_reg(b); + /* gen_movl_T1_im(s); */ + /* gen_op_space_sel_T0_T1(); */ + /* XXX: check this */ + if(im14 & (1 << 31)) { + gen_movl_T1_im(im14); + gen_op_addl_T1_T0(); + } + gen_op_ldst(ldw); + gen_movl_reg_T1(t); + if(!(im14 & (1 << 31))) { + gen_movl_T1_im(im14); + gen_op_addl_T1_T0(); + } + gen_movl_reg_T0(b); break; + } case 0x18: /* STB */ case 0x19: /* STH */ @@ -1768,8 +1790,29 @@ } case 0x1b: /* STWM */ - /* FIXME */ + { + uint32_t b, r, s, im14; + b = field(insn, 21, 5); + r = field(insn, 16, 5); + s = field(insn, 14, 2); + im14 = field_lowsignext(insn, 0, 14); + gen_movl_T0_reg(b); + /* gen_movl_T1_im(s); */ + /* gen_op_space_sel_T0_T1(); */ + /* XXX: check this */ + if(im14 & (1 << 31)) { + gen_movl_T1_im(im14); + gen_op_addl_T1_T0(); + } + gen_movl_T1_reg(r); + gen_op_ldst(stw); + if(!(im14 & (1 << 31))) { + gen_movl_T1_im(im14); + gen_op_addl_T1_T0(); + } + gen_movl_reg_T0(b); break; + } case 0x20: /* COMBT */ case 0x21: /* COMIBT */ |
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From: Stuart B. <zu...@us...> - 2008-02-22 02:21:13
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv18863 Modified Files: translate.c Log Message: Fix offset addition for STB/STH/STW. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.42 retrieving revision 1.43 diff -u -d -r1.42 -r1.43 --- translate.c 22 Feb 2008 01:10:33 -0000 1.42 +++ translate.c 22 Feb 2008 02:21:10 -0000 1.43 @@ -1751,7 +1751,7 @@ /* gen_movl_T1_im(s); */ /* gen_op_space_sel_T0_T1(); */ gen_movl_T1_im(im14); - gen_op_addl_T0_T1(); + gen_op_addl_T1_T0(); gen_movl_T1_reg(r); switch(op) { case 0x18: /* STB */ @@ -1764,7 +1764,7 @@ gen_op_ldst(stw); break; } - break; + break; } case 0x1b: /* STWM */ |
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From: Stuart B. <zu...@us...> - 2008-02-22 01:10:37
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv22557 Modified Files: translate.c Log Message: Fix COMBF/COMIBF/ADDBF/ADDIBF. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.41 retrieving revision 1.42 diff -u -d -r1.41 -r1.42 --- translate.c 22 Feb 2008 00:02:12 -0000 1.41 +++ translate.c 22 Feb 2008 01:10:33 -0000 1.42 @@ -1776,7 +1776,7 @@ case 0x22: /* COMBF */ case 0x23: /* COMIBF */ { - uint32_t c, w1, n, w, disp; + uint32_t f, c, w1, n, w, disp; switch(op) { case 0x20: /* COMBT */ case 0x22: /* COMBF */ @@ -1799,6 +1799,7 @@ break; } } + f = field(insn, 27, 1); c = field(insn, 13, 3); w1 = field(insn, 2, 11); n = field(insn, 1, 1); @@ -1806,7 +1807,7 @@ disp = signext(assemble_12(w1, w), 12) << 2; gen_cond_sub[c](); - gen_branch_cond(dc, (long)dc->tb, disp, n, 0); + gen_branch_cond(dc, (long)dc->tb, disp, n, f); /* FIXME */ dc->is_br = 1; @@ -1867,7 +1868,7 @@ case 0x2a: /* ADDBF */ case 0x2b: /* ADDIBF */ { - uint32_t c, w1, n, w, disp; + uint32_t f, c, w1, n, w, disp; switch(op) { case 0x28: /* ADDBT */ case 0x2a: /* ADDBF */ @@ -1890,6 +1891,7 @@ break; } } + f = field(insn, 27, 1); c = field(insn, 13, 3); w1 = field(insn, 2, 11); n = field(insn, 1, 1); @@ -1897,7 +1899,7 @@ disp = signext(assemble_12(w1, w), 12) << 2; gen_cond_add[c](); - gen_branch_cond(dc, (long)dc->tb, disp, n, 0); + gen_branch_cond(dc, (long)dc->tb, disp, n, f); /* FIXME */ dc->is_br = 1; |
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From: Stuart B. <zu...@us...> - 2008-02-22 00:25:09
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Update of /cvsroot/hppaqemu/hppaqemu In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv3808 Modified Files: gdbstub.c Log Message: Fix reading/writing of general purpose registers for GDB. Index: gdbstub.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/gdbstub.c,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- gdbstub.c 19 Feb 2008 12:14:30 -0000 1.5 +++ gdbstub.c 22 Feb 2008 00:24:58 -0000 1.6 @@ -865,8 +865,8 @@ registers[0] = tswapl(env->psw); /* gr0 is hardwired to zero */ /* fill in gr1..gr32 */ - for(i = 0; i < 31; i++) { - registers[i + 1] = tswapl(env->gr[i]); + for(i = 1; i < 32; i++) { + registers[i] = tswapl(env->gr[i]); } /* registers[32] = sar; */ registers[32] = 0; @@ -896,8 +896,8 @@ env->psw = tswapl(registers[0]); /* gr0 is hardwired to zero */ /* fill in gr1..gr32 */ - for(i = 0; i < 31; i++) { - env->gr[i] = tswapl(registers[i + 1]); + for(i = 1; i < 32; i++) { + env->gr[i] = tswapl(registers[i]); } /* sar = registers[32]; */ env->iaoq[0] = tswapl(registers[33]); |
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From: Stuart B. <zu...@us...> - 2008-02-22 00:02:21
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv27692 Modified Files: translate.c Log Message: Fix STB/STH/STW. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.40 retrieving revision 1.41 diff -u -d -r1.40 -r1.41 --- translate.c 18 Feb 2008 05:24:54 -0000 1.40 +++ translate.c 22 Feb 2008 00:02:12 -0000 1.41 @@ -1752,7 +1752,7 @@ /* gen_op_space_sel_T0_T1(); */ gen_movl_T1_im(im14); gen_op_addl_T0_T1(); - gen_movl_reg_T1(r); + gen_movl_T1_reg(r); switch(op) { case 0x18: /* STB */ gen_op_ldst(stb); @@ -1764,6 +1764,7 @@ gen_op_ldst(stw); break; } + break; } case 0x1b: /* STWM */ |
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From: Stuart B. <zu...@us...> - 2008-02-20 04:49:03
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv15605/linux-user Modified Files: main.c Log Message: Handle EXCP_DEBUG, which is needed for breakpoints and single-stepping. Index: main.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/linux-user/main.c,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- main.c 18 Feb 2008 05:24:48 -0000 1.6 +++ main.c 20 Feb 2008 04:48:51 -0000 1.7 @@ -1812,6 +1812,20 @@ trapnr = cpu_hppa_exec(env); switch (trapnr) { + case EXCP_DEBUG: + { + int sig; + + sig = gdb_handlesig (env, TARGET_SIGTRAP); + if (sig) + { + info.si_signo = sig; + info.si_errno = 0; + info.si_code = TARGET_TRAP_BRKPT; + queue_signal(info.si_signo, &info); + } + } + break; default: fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); |
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From: Stuart B. <zu...@us...> - 2008-02-19 14:00:57
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv13082/target-hppa Modified Files: cpu.h Log Message: Enable breakpoint/singlestep support. Index: cpu.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- cpu.h 18 Feb 2008 15:10:17 -0000 1.9 +++ cpu.h 19 Feb 2008 14:00:50 -0000 1.10 @@ -35,6 +35,8 @@ #include "softfloat.h" +#define TARGET_HAS_ICE + #define ELF_MACHINE EM_PARISC /* Group 1 interruptions */ |
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From: Stuart B. <zu...@us...> - 2008-02-19 12:14:44
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Update of /cvsroot/hppaqemu/hppaqemu In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv27814 Modified Files: gdbstub.c Log Message: Add support for GDB. (PSW, General registers and IAOQ/IASQ only.) Index: gdbstub.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/gdbstub.c,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- gdbstub.c 18 Feb 2008 05:24:38 -0000 1.4 +++ gdbstub.c 19 Feb 2008 12:14:30 -0000 1.5 @@ -856,6 +856,57 @@ for (i = 0; i < 16; i++) LOAD(env->regs[i]); LOAD (env->pc); } +#elif defined (TARGET_HPPA) +static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) +{ + target_ulong *registers = (target_ulong *)mem_buf; + int i; + + registers[0] = tswapl(env->psw); + /* gr0 is hardwired to zero */ + /* fill in gr1..gr32 */ + for(i = 0; i < 31; i++) { + registers[i + 1] = tswapl(env->gr[i]); + } + /* registers[32] = sar; */ + registers[32] = 0; + registers[33] = tswapl(env->iaoq[0]); + registers[34] = tswap32(env->iasq[0]); + registers[35] = tswapl(env->iaoq[1]); + registers[36] = tswap32(env->iasq[1]); + /* ... */ +#ifndef TARGET_HPPA64 + for(i = 37; i < 128; i++) { + registers[i] = 0; + } + return 128 * sizeof(target_ulong); +#else + for(i = 37; i < 96; i++) { + registers[i] = 0; + } + return 96 * sizeof(target_ulong); +#endif +} + +static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) +{ + target_ulong *registers = (target_ulong *)mem_buf; + int i; + + env->psw = tswapl(registers[0]); + /* gr0 is hardwired to zero */ + /* fill in gr1..gr32 */ + for(i = 0; i < 31; i++) { + env->gr[i] = tswapl(registers[i + 1]); + } + /* sar = registers[32]; */ + env->iaoq[0] = tswapl(registers[33]); + env->iasq[0] = tswap32(registers[34]); + env->iaoq[1] = tswapl(registers[35]); + env->iasq[1] = tswap32(registers[36]); + /* ... */ +} + #else static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) { @@ -906,6 +957,9 @@ env->PC[env->current_tc] = addr; #elif defined (TARGET_CRIS) env->pc = addr; +#elif defined (TARGET_HPPA) + env->iaoq[0] = addr; + env->iaoq[1] = addr + 4; #endif } #ifdef CONFIG_USER_ONLY @@ -932,6 +986,9 @@ env->PC[env->current_tc] = addr; #elif defined (TARGET_CRIS) env->pc = addr; +#elif defined (TARGET_HPPA) + env->iaoq[0] = addr; + env->iaoq[1] = addr + 4; #endif } cpu_single_step(env, 1); |
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From: <tio...@qu...> - 2008-02-19 03:14:34
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No problems! -----Mensagem original----- De: hpp...@li... [mailto:hpp...@li...] Em nome de Stuart Brady Enviada em: domingo, 17 de fevereiro de 2008 21:31 Para: hpp...@li... Assunto: [HPPAQEMU-CVS] Commit emails Hello, My apologies to anyone bothered by the huge amount of spam produced by the recent merge to QEMU CVS from 2007-06-01. I plan to do a few more of these updates, but I will make sure that the notification is turned off before I do so. I had thought that there would be a single huge update, which would be blocked by mailman due to being over 40 KiB in size. However, as I now use SVN most of the time, I'd forgotten that CVS sends an email out for each directory updated! Again, my apologies for any inconvenience. -- Stuart Brady ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ _______________________________________________ HPPAQEMU-CVS mailing list HPP...@li... https://lists.sourceforge.net/lists/listinfo/hppaqemu-cvs No virus found in this incoming message. Checked by AVG Free Edition. Version: 7.5.516 / Virus Database: 269.20.7/1286 - Release Date: 18/2/2008 18:49 No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.5.516 / Virus Database: 269.20.7/1286 - Release Date: 18/2/2008 18:49 |
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From: Stuart B. <zu...@us...> - 2008-02-18 15:10:32
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv7181 Modified Files: cpu.h Log Message: Define TARGET_LONG_BITS to 64 for TARGET_HPPA64. Index: cpu.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- cpu.h 18 Feb 2008 05:24:54 -0000 1.8 +++ cpu.h 18 Feb 2008 15:10:17 -0000 1.9 @@ -23,7 +23,12 @@ #include "config.h" +#if !defined(TARGET_HPPA64) #define TARGET_LONG_BITS 32 +#else +#define TARGET_LONG_BITS 64 +#endif + #include "cpu-defs.h" #include <setjmp.h> @@ -161,7 +166,7 @@ #include "cpu-all.h" -CPUHPPAState *cpu_hppa_init(const char *model); +CPUHPPAState *cpu_hppa_init(const char *cpu_model); int cpu_hppa_exec(CPUHPPAState *s); #endif |
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From: Stuart B. <zu...@us...> - 2008-02-18 05:25:30
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv27557/target-hppa Modified Files: cpu.h translate.c Log Message: Update to QEMU 0.9.1. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.39 retrieving revision 1.40 diff -u -d -r1.39 -r1.40 --- translate.c 22 Mar 2007 15:48:50 -0000 1.39 +++ translate.c 18 Feb 2008 05:24:54 -0000 1.40 @@ -2066,7 +2066,7 @@ dc->iaoq[1] = dc->iaoq[1] + 4; } -CPUHPPAState *cpu_hppa_init(void) +CPUHPPAState *cpu_hppa_init(const char *cpu_model) { CPUHPPAState *env; Index: cpu.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- cpu.h 18 Feb 2008 03:04:59 -0000 1.7 +++ cpu.h 18 Feb 2008 05:24:54 -0000 1.8 @@ -102,6 +102,8 @@ #define PSW_CB_SHIFT 8 +#define NB_MMU_MODES 2 + typedef struct CPUHPPAState { target_ulong gr[32]; /* General Registers */ target_ulong shr[7]; /* SHadow Registers */ @@ -144,9 +146,22 @@ #define cpu_gen_code cpu_hppa_gen_code #define cpu_signal_handler cpu_hppa_signal_handler +/* MMU modes definitions */ +#define MMU_MODE0_SUFFIX _kernel +#define MMU_MODE1_SUFFIX _user +#define MMU_USER_IDX 0 +static inline int cpu_mmu_index (CPUState *env) +{ +#if defined(CONFIG_USER_ONLY) + return 0; +#else + return (env->iaoq[0] & 3) != 0 ? 1 : 0; +#endif +} + #include "cpu-all.h" -CPUHPPAState *cpu_hppa_init(void); +CPUHPPAState *cpu_hppa_init(const char *model); int cpu_hppa_exec(CPUHPPAState *s); #endif |
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From: Stuart B. <zu...@us...> - 2008-02-18 05:01:20
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/cris In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv17954/cris Log Message: Directory /cvsroot/hppaqemu/hppaqemu/linux-user/cris added to the repository |
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From: Stuart B. <zu...@us...> - 2008-02-18 05:00:31
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Update of /cvsroot/hppaqemu/hppaqemu/target-cris In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv17516/target-cris Log Message: Directory /cvsroot/hppaqemu/hppaqemu/target-cris added to the repository |
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From: Stuart B. <zu...@us...> - 2008-02-18 05:00:31
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Update of /cvsroot/hppaqemu/hppaqemu/tests/cris In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv17516/tests/cris Log Message: Directory /cvsroot/hppaqemu/hppaqemu/tests/cris added to the repository |
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From: Stuart B. <zu...@us...> - 2008-02-18 03:05:36
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv813/target-hppa Modified Files: cpu.h exec.h Log Message: Update to QEMU CVS from 2007-10-01. Index: cpu.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- cpu.h 20 Apr 2007 14:21:57 -0000 1.6 +++ cpu.h 18 Feb 2008 03:04:59 -0000 1.7 @@ -137,6 +137,13 @@ } CPUHPPAState; #define TARGET_PAGE_BITS 12 + +#define CPUState CPUHPPAState +#define cpu_init cpu_hppa_init +#define cpu_exec cpu_hppa_exec +#define cpu_gen_code cpu_hppa_gen_code +#define cpu_signal_handler cpu_hppa_signal_handler + #include "cpu-all.h" CPUHPPAState *cpu_hppa_init(void); Index: exec.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/exec.h,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- exec.h 9 Mar 2007 15:57:31 -0000 1.4 +++ exec.h 18 Feb 2008 03:04:59 -0000 1.5 @@ -41,6 +41,17 @@ { } +static inline int cpu_halted(CPUState *env) { + if (!env->halted) + return 0; + if (env->interrupt_request & + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { + env->halted = 0; + return 0; + } + return EXCP_HALTED; +} + void raise_exception(int tt); void cpu_loop_exit(void); |
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From: Stuart B. <zu...@us...> - 2008-02-18 03:04:54
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv813/linux-user/hppa Added Files: target_signal.h Log Message: Update to QEMU CVS from 2007-10-01. --- NEW FILE: target_signal.h --- #ifndef TARGET_SIGNAL_H #define TARGET_SIGNAL_H #include "cpu.h" /* this struct defines a stack used during syscall handling */ typedef struct target_sigaltstack { target_ulong ss_sp; target_long ss_flags; target_ulong ss_size; } target_stack_t; /* * sigaltstack controls */ #define TARGET_SS_ONSTACK 1 #define TARGET_SS_DISABLE 2 #define TARGET_MINSIGSTKSZ 2048 #define TARGET_SIGSTKSZ 8192 static inline target_ulong get_sp_from_cpustate(CPUHPPAState *state) { return state->gr[30]; } #endif /* TARGET_SIGNAL_H */ |
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From: Stuart B. <zu...@us...> - 2008-02-18 02:51:02
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/mipsn32 In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv28210/mipsn32 Log Message: Directory /cvsroot/hppaqemu/hppaqemu/linux-user/mipsn32 added to the repository |
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From: Stuart B. <zu...@us...> - 2008-02-18 02:51:02
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/mips64 In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv28210/mips64 Log Message: Directory /cvsroot/hppaqemu/hppaqemu/linux-user/mips64 added to the repository |
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From: Stuart B. <zu...@us...> - 2008-02-18 00:53:33
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Update of /cvsroot/hppaqemu/hppaqemu/target-alpha In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv8904/target-alpha Log Message: Directory /cvsroot/hppaqemu/hppaqemu/target-alpha added to the repository |
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From: Stuart B. <sd...@nt...> - 2008-02-18 00:31:34
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Hello, My apologies to anyone bothered by the huge amount of spam produced by the recent merge to QEMU CVS from 2007-06-01. I plan to do a few more of these updates, but I will make sure that the notification is turned off before I do so. I had thought that there would be a single huge update, which would be blocked by mailman due to being over 40 KiB in size. However, as I now use SVN most of the time, I'd forgotten that CVS sends an email out for each directory updated! Again, my apologies for any inconvenience. -- Stuart Brady |
Update of /cvsroot/hppaqemu/hppaqemu/target-m68k In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv24609/target-m68k Modified Files: cpu.h exec.h helper.c op-hacks.h op.c qregs.def translate.c Added Files: op_helper.c op_mem.h Log Message: Update to QEMU CVS from 2007-06-01. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-m68k/translate.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- translate.c 23 Feb 2007 21:44:39 -0000 1.1.1.1 +++ translate.c 18 Feb 2008 00:13:58 -0000 1.2 @@ -1,7 +1,7 @@ /* * m68k translation * - * Copyright (c) 2005-2006 CodeSourcery + * Copyright (c) 2005-2007 CodeSourcery * Written by Paul Brook * * This library is free software; you can redistribute it and/or @@ -30,6 +30,8 @@ #include "disas.h" #include "m68k-qreg.h" [...1922 lines suppressed...] -target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) -{ - return addr; -} - -#if defined(CONFIG_USER_ONLY) - -int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw, - int is_user, int is_softmmu) -{ - env->exception_index = EXCP_ACCESS; - env->mmu.ar = address; - return 1; -} - -#else - -#error not implemented - -#endif Index: helper.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-m68k/helper.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- helper.c 23 Feb 2007 21:44:39 -0000 1.1.1.1 +++ helper.c 18 Feb 2008 00:13:58 -0000 1.2 @@ -1,7 +1,7 @@ /* * m68k op helpers * - * Copyright (c) 2006 CodeSourcery + * Copyright (c) 2006-2007 CodeSourcery * Written by Paul Brook * * This library is free software; you can redistribute it and/or @@ -20,11 +20,74 @@ */ #include <stdio.h> +#include <string.h> #include "config.h" #include "cpu.h" #include "exec-all.h" +enum m68k_cpuid { + M68K_CPUID_M5206, + M68K_CPUID_CFV4E, + M68K_CPUID_ANY, +}; + +struct m68k_def_t { + const char * name; + enum m68k_cpuid id; +}; + +static m68k_def_t m68k_cpu_defs[] = { + {"m5206", M68K_CPUID_M5206}, + {"cfv4e", M68K_CPUID_CFV4E}, + {"any", M68K_CPUID_ANY}, + {NULL, 0}, +}; + +static void m68k_set_feature(CPUM68KState *env, int feature) +{ + env->features |= (1u << feature); +} + +int cpu_m68k_set_model(CPUM68KState *env, const char * name) +{ + m68k_def_t *def; + + for (def = m68k_cpu_defs; def->name; def++) { + if (strcmp(def->name, name) == 0) + break; + } + if (!def->name) + return 1; + + switch (def->id) { + case M68K_CPUID_M5206: + m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); + break; + case M68K_CPUID_CFV4E: + m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); + m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); + m68k_set_feature(env, M68K_FEATURE_CF_ISA_C); + m68k_set_feature(env, M68K_FEATURE_CF_FPU); + m68k_set_feature(env, M68K_FEATURE_CF_EMAC); + break; + case M68K_CPUID_ANY: + m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); + m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); + m68k_set_feature(env, M68K_FEATURE_CF_ISA_C); + m68k_set_feature(env, M68K_FEATURE_CF_FPU); + /* MAC and EMAC are mututally exclusive, so pick EMAC. + It's mostly backwards compatible. */ + m68k_set_feature(env, M68K_FEATURE_CF_EMAC); + m68k_set_feature(env, M68K_FEATURE_EXT_FULL); + break; + } + + register_m68k_insns(env); + + return 0; +} + void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) { int flags; @@ -147,3 +210,99 @@ } return res; } + +void helper_movec(CPUM68KState *env, int reg, uint32_t val) +{ + switch (reg) { + case 0x02: /* CACR */ + /* Ignored. */ + break; + case 0x801: /* VBR */ + env->vbr = val; + break; + /* TODO: Implement control registers. */ + default: + cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n", + reg, val); + } +} + +void m68k_set_macsr(CPUM68KState *env, uint32_t val) +{ + uint32_t acc; + int8_t exthigh; + uint8_t extlow; + uint64_t regval; + int i; + if ((env->macsr ^ val) & (MACSR_FI | MACSR_SU)) { + for (i = 0; i < 4; i++) { + regval = env->macc[i]; + exthigh = regval >> 40; + if (env->macsr & MACSR_FI) { + acc = regval >> 8; + extlow = regval; + } else { + acc = regval; + extlow = regval >> 32; + } + if (env->macsr & MACSR_FI) { + regval = (((uint64_t)acc) << 8) | extlow; + regval |= ((int64_t)exthigh) << 40; + } else if (env->macsr & MACSR_SU) { + regval = acc | (((int64_t)extlow) << 32); + regval |= ((int64_t)exthigh) << 40; + } else { + regval = acc | (((uint64_t)extlow) << 32); + regval |= ((uint64_t)(uint8_t)exthigh) << 40; + } + env->macc[i] = regval; + } + } + env->macsr = val; +} + +/* MMU */ + +/* TODO: This will need fixing once the MMU is implemented. */ +target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +{ + return addr; +} + +#if defined(CONFIG_USER_ONLY) + +int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw, + int is_user, int is_softmmu) +{ + env->exception_index = EXCP_ACCESS; + env->mmu.ar = address; + return 1; +} + +#else + +int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw, + int is_user, int is_softmmu) +{ + int prot; + + address &= TARGET_PAGE_MASK; + prot = PAGE_READ | PAGE_WRITE; + return tlb_set_page(env, address, address, prot, is_user, is_softmmu); +} + +/* Notify CPU of a pending interrupt. Prioritization and vectoring should + be handled by the interrupt controller. Real hardware only requests + the vector when the interrupt is acknowledged by the CPU. For + simplicitly we calculate it when the interrupt is signalled. */ +void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector) +{ + env->pending_level = level; + env->pending_vector = vector; + if (level) + cpu_interrupt(env, CPU_INTERRUPT_HARD); + else + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); +} + +#endif Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-m68k/op.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- op.c 23 Feb 2007 21:44:39 -0000 1.1.1.1 +++ op.c 18 Feb 2008 00:13:58 -0000 1.2 @@ -1,7 +1,7 @@ /* * m68k micro operations * - * Copyright (c) 2006 CodeSourcery + * Copyright (c) 2006-2007 CodeSourcery * Written by Paul Brook * * This library is free software; you can redistribute it and/or @@ -48,23 +48,23 @@ uint32_t get_op(int qreg) { - if (qreg == QREG_T0) { + if (qreg >= TARGET_NUM_QREGS) { + return env->qregs[qreg - TARGET_NUM_QREGS]; + } else if (qreg == QREG_T0) { return T0; - } else if (qreg < TARGET_NUM_QREGS) { - return *(uint32_t *)(((long)env) + qreg_offsets[qreg]); } else { - return env->qregs[qreg - TARGET_NUM_QREGS]; + return *(uint32_t *)(((long)env) + qreg_offsets[qreg]); } } void set_op(int qreg, uint32_t val) { - if (qreg == QREG_T0) { + if (qreg >= TARGET_NUM_QREGS) { + env->qregs[qreg - TARGET_NUM_QREGS] = val; + } else if (qreg == QREG_T0) { T0 = val; - } else if (qreg < TARGET_NUM_QREGS) { - *(uint32_t *)(((long)env) + qreg_offsets[qreg]) = val; } else { - env->qregs[qreg - TARGET_NUM_QREGS] = val; + *(uint32_t *)(((long)env) + qreg_offsets[qreg]) = val; } } @@ -86,7 +86,7 @@ } } -#define OP(name) void OPPROTO op_##name (void) +#define OP(name) void OPPROTO glue(op_,name) (void) OP(mov32) { @@ -170,7 +170,17 @@ FORCE_RET(); } -OP(addx_cc) +OP(ff1) +{ + uint32_t arg = get_op(PARAM2); + int n; + for (n = 32; arg; n--) + arg >>= 1; + set_op(PARAM1, n); + FORCE_RET(); +} + +OP(subx_cc) { uint32_t op1 = get_op(PARAM1); uint32_t op2 = get_op(PARAM2); @@ -188,7 +198,7 @@ FORCE_RET(); } -OP(subx_cc) +OP(addx_cc) { uint32_t op1 = get_op(PARAM1); uint32_t op2 = get_op(PARAM2); @@ -275,6 +285,16 @@ FORCE_RET(); } +OP(sar32) +{ + int32_t op2 = get_op(PARAM2); + uint32_t op3 = get_op(PARAM3); + uint32_t result; + result = op2 >> op3; + set_op(PARAM1, result); + FORCE_RET(); +} + OP(sar_cc) { int32_t op1 = get_op(PARAM1); @@ -316,77 +336,6 @@ FORCE_RET(); } -/* Load/store ops. */ -OP(ld8u32) -{ - uint32_t addr = get_op(PARAM2); - set_op(PARAM1, ldub(addr)); - FORCE_RET(); -} - -OP(ld8s32) -{ - uint32_t addr = get_op(PARAM2); - set_op(PARAM1, ldsb(addr)); - FORCE_RET(); -} - -OP(ld16u32) -{ - uint32_t addr = get_op(PARAM2); - set_op(PARAM1, lduw(addr)); - FORCE_RET(); -} - -OP(ld16s32) -{ - uint32_t addr = get_op(PARAM2); - set_op(PARAM1, ldsw(addr)); - FORCE_RET(); -} - -OP(ld32) -{ - uint32_t addr = get_op(PARAM2); - set_op(PARAM1, ldl(addr)); - FORCE_RET(); -} - -OP(st8) -{ - uint32_t addr = get_op(PARAM1); - stb(addr, get_op(PARAM2)); - FORCE_RET(); -} - -OP(st16) -{ - uint32_t addr = get_op(PARAM1); - stw(addr, get_op(PARAM2)); - FORCE_RET(); -} - -OP(st32) -{ - uint32_t addr = get_op(PARAM1); - stl(addr, get_op(PARAM2)); - FORCE_RET(); -} - -OP(ldf64) -{ - uint32_t addr = get_op(PARAM2); - set_opf64(PARAM1, ldfq(addr)); - FORCE_RET(); -} - -OP(stf64) -{ - uint32_t addr = get_op(PARAM1); - stfq(addr, get_opf64(PARAM2)); - FORCE_RET(); -} - OP(flush_flags) { int cc_op = PARAM1; @@ -454,6 +403,20 @@ FORCE_RET(); } +/* Halt is special because it may be a semihosting call. */ +OP(halt) +{ + RAISE_EXCEPTION(EXCP_HALT_INSN); + FORCE_RET(); +} + +OP(stop) +{ + env->halted = 1; + RAISE_EXCEPTION(EXCP_HLT); + FORCE_RET(); +} + OP(raise_exception) { RAISE_EXCEPTION(PARAM1); @@ -679,3 +642,429 @@ set_op(PARAM1, float64_compare_quiet(op0, op1, &CPU_FP_STATUS)); FORCE_RET(); } + +OP(movec) +{ + int op1 = get_op(PARAM1); + uint32_t op2 = get_op(PARAM2); + helper_movec(env, op1, op2); +} + +/* Memory access. */ + +#define MEMSUFFIX _raw +#include "op_mem.h" + +#if !defined(CONFIG_USER_ONLY) +#define MEMSUFFIX _user +#include "op_mem.h" +#define MEMSUFFIX _kernel +#include "op_mem.h" +#endif + +/* MAC unit. */ +/* TODO: The MAC instructions use 64-bit arithmetic fairly extensively. + This results in fairly large ops (and sometimes other issues) on 32-bit + hosts. Maybe move most of them into helpers. */ +OP(macmuls) +{ + uint32_t op1 = get_op(PARAM1); + uint32_t op2 = get_op(PARAM2); + int64_t product; + int64_t res; + + product = (uint64_t)op1 * op2; + res = (product << 24) >> 24; + if (res != product) { + env->macsr |= MACSR_V; + if (env->macsr & MACSR_OMC) { + /* Make sure the accumulate operation overflows. */ + if (product < 0) + res = ~(1ll << 50); + else + res = 1ll << 50; + } + } + env->mactmp = res; + FORCE_RET(); +} + +OP(macmulu) +{ + uint32_t op1 = get_op(PARAM1); + uint32_t op2 = get_op(PARAM2); + uint64_t product; + + product = (uint64_t)op1 * op2; + if (product & (0xffffffull << 40)) { + env->macsr |= MACSR_V; + if (env->macsr & MACSR_OMC) { + /* Make sure the accumulate operation overflows. */ + product = 1ll << 50; + } else { + product &= ((1ull << 40) - 1); + } + } + env->mactmp = product; + FORCE_RET(); +} + +OP(macmulf) +{ + int32_t op1 = get_op(PARAM1); + int32_t op2 = get_op(PARAM2); + uint64_t product; + uint32_t remainder; + + product = (uint64_t)op1 * op2; + if (env->macsr & MACSR_RT) { + remainder = product & 0xffffff; + product >>= 24; + if (remainder > 0x800000) + product++; + else if (remainder == 0x800000) + product += (product & 1); + } else { + product >>= 24; + } + env->mactmp = product; + FORCE_RET(); +} + +OP(macshl) +{ + env->mactmp <<= 1; +} + +OP(macshr) +{ + env->mactmp >>= 1; +} + +OP(macadd) +{ + int acc = PARAM1; + env->macc[acc] += env->mactmp; + FORCE_RET(); +} + +OP(macsub) +{ + int acc = PARAM1; + env->macc[acc] -= env->mactmp; + FORCE_RET(); +} + +OP(macsats) +{ + int acc = PARAM1; + int64_t sum; + int64_t result; + + sum = env->macc[acc]; + result = (sum << 16) >> 16; + if (result != sum) { + env->macsr |= MACSR_V; + } + if (env->macsr & MACSR_V) { + env->macsr |= MACSR_PAV0 << acc; + if (env->macsr & MACSR_OMC) { + /* The result is saturated to 32 bits, despite overflow occuring + at 48 bits. Seems weird, but that's what the hardware docs + say. */ + result = (result >> 63) ^ 0x7fffffff; + } + } + env->macc[acc] = result; + FORCE_RET(); +} + +OP(macsatu) +{ + int acc = PARAM1; + uint64_t sum; + + sum = env->macc[acc]; + if (sum & (0xffffull << 48)) { + env->macsr |= MACSR_V; + } + if (env->macsr & MACSR_V) { + env->macsr |= MACSR_PAV0 << acc; + if (env->macsr & MACSR_OMC) { + if (sum > (1ull << 53)) + sum = 0; + else + sum = (1ull << 48) - 1; + } else { + sum &= ((1ull << 48) - 1); + } + } + FORCE_RET(); +} + +OP(macsatf) +{ + int acc = PARAM1; + int64_t sum; + int64_t result; + + sum = env->macc[acc]; + result = (sum << 16) >> 16; + if (result != sum) { + env->macsr |= MACSR_V; + } + if (env->macsr & MACSR_V) { + env->macsr |= MACSR_PAV0 << acc; + if (env->macsr & MACSR_OMC) { + result = (result >> 63) ^ 0x7fffffffffffll; + } + } + env->macc[acc] = result; + FORCE_RET(); +} + +OP(mac_clear_flags) +{ + env->macsr &= ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV); +} + +OP(mac_set_flags) +{ + int acc = PARAM1; + uint64_t val; + val = env->macc[acc]; + if (val == 0) + env->macsr |= MACSR_Z; + else if (val & (1ull << 47)); + env->macsr |= MACSR_N; + if (env->macsr & (MACSR_PAV0 << acc)) { + env->macsr |= MACSR_V; + } + if (env->macsr & MACSR_FI) { + val = ((int64_t)val) >> 40; + if (val != 0 && val != -1) + env->macsr |= MACSR_EV; + } else if (env->macsr & MACSR_SU) { + val = ((int64_t)val) >> 32; + if (val != 0 && val != -1) + env->macsr |= MACSR_EV; + } else { + if ((val >> 32) != 0) + env->macsr |= MACSR_EV; + } + FORCE_RET(); +} + +OP(get_macf) +{ + int acc = PARAM2; + int64_t val; + int rem; + uint32_t result; + + val = env->macc[acc]; + if (env->macsr & MACSR_SU) { + /* 16-bit rounding. */ + rem = val & 0xffffff; + val = (val >> 24) & 0xffffu; + if (rem > 0x800000) + val++; + else if (rem == 0x800000) + val += (val & 1); + } else if (env->macsr & MACSR_RT) { + /* 32-bit rounding. */ + rem = val & 0xff; + val >>= 8; + if (rem > 0x80) + val++; + else if (rem == 0x80) + val += (val & 1); + } else { + /* No rounding. */ + val >>= 8; + } + if (env->macsr & MACSR_OMC) { + /* Saturate. */ + if (env->macsr & MACSR_SU) { + if (val != (uint16_t) val) { + result = ((val >> 63) ^ 0x7fff) & 0xffff; + } else { + result = val & 0xffff; + } + } else { + if (val != (uint32_t)val) { + result = ((uint32_t)(val >> 63) & 0x7fffffff); + } else { + result = (uint32_t)val; + } + } + } else { + /* No saturation. */ + if (env->macsr & MACSR_SU) { + result = val & 0xffff; + } else { + result = (uint32_t)val; + } + } + set_op(PARAM1, result); + FORCE_RET(); +} + +OP(get_maci) +{ + int acc = PARAM2; + set_op(PARAM1, (uint32_t)env->macc[acc]); + FORCE_RET(); +} + +OP(get_macs) +{ + int acc = PARAM2; + int64_t val = env->macc[acc]; + uint32_t result; + if (val == (int32_t)val) { + result = (int32_t)val; + } else { + result = (val >> 61) ^ 0x7fffffff; + } + set_op(PARAM1, result); + FORCE_RET(); +} + +OP(get_macu) +{ + int acc = PARAM2; + uint64_t val = env->macc[acc]; + uint32_t result; + if ((val >> 32) == 0) { + result = (uint32_t)val; + } else { + result = 0xffffffffu; + } + set_op(PARAM1, result); + FORCE_RET(); +} + +OP(clear_mac) +{ + int acc = PARAM1; + + env->macc[acc] = 0; + env->macsr &= ~(MACSR_PAV0 << acc); + FORCE_RET(); +} + +OP(move_mac) +{ + int dest = PARAM1; + int src = PARAM2; + uint32_t mask; + env->macc[dest] = env->macc[src]; + mask = MACSR_PAV0 << dest; + if (env->macsr & (MACSR_PAV0 << src)) + env->macsr |= mask; + else + env->macsr &= ~mask; + FORCE_RET(); +} + +OP(get_mac_extf) +{ + uint32_t val; + int acc = PARAM2; + val = env->macc[acc] & 0x00ff; + val = (env->macc[acc] >> 32) & 0xff00; + val |= (env->macc[acc + 1] << 16) & 0x00ff0000; + val |= (env->macc[acc + 1] >> 16) & 0xff000000; + set_op(PARAM1, val); + FORCE_RET(); +} + +OP(get_mac_exti) +{ + uint32_t val; + int acc = PARAM2; + val = (env->macc[acc] >> 32) & 0xffff; + val |= (env->macc[acc + 1] >> 16) & 0xffff0000; + set_op(PARAM1, val); + FORCE_RET(); +} + +OP(set_macf) +{ + int acc = PARAM2; + int32_t val = get_op(PARAM1); + env->macc[acc] = ((int64_t)val) << 8; + env->macsr &= ~(MACSR_PAV0 << acc); + FORCE_RET(); +} + +OP(set_macs) +{ + int acc = PARAM2; + int32_t val = get_op(PARAM1); + env->macc[acc] = val; + env->macsr &= ~(MACSR_PAV0 << acc); + FORCE_RET(); +} + +OP(set_macu) +{ + int acc = PARAM2; + uint32_t val = get_op(PARAM1); + env->macc[acc] = val; + env->macsr &= ~(MACSR_PAV0 << acc); + FORCE_RET(); +} + +OP(set_mac_extf) +{ + int acc = PARAM2; + int32_t val = get_op(PARAM1); + int64_t res; + int32_t tmp; + res = env->macc[acc] & 0xffffffff00ull; + tmp = (int16_t)(val & 0xff00); + res |= ((int64_t)tmp) << 32; + res |= val & 0xff; + env->macc[acc] = res; + res = env->macc[acc + 1] & 0xffffffff00ull; + tmp = (val & 0xff000000); + res |= ((int64_t)tmp) << 16; + res |= (val >> 16) & 0xff; + env->macc[acc + 1] = res; +} + +OP(set_mac_exts) +{ + int acc = PARAM2; + int32_t val = get_op(PARAM1); + int64_t res; + int32_t tmp; + res = (uint32_t)env->macc[acc]; + tmp = (int16_t)val; + res |= ((int64_t)tmp) << 32; + env->macc[acc] = res; + res = (uint32_t)env->macc[acc + 1]; + tmp = val & 0xffff0000; + res |= (int64_t)tmp << 16; + env->macc[acc + 1] = res; +} + +OP(set_mac_extu) +{ + int acc = PARAM2; + int32_t val = get_op(PARAM1); + uint64_t res; + res = (uint32_t)env->macc[acc]; + res |= ((uint64_t)(val & 0xffff)) << 32; + env->macc[acc] = res; + res = (uint32_t)env->macc[acc + 1]; + res |= (uint64_t)(val & 0xffff0000) << 16; + env->macc[acc + 1] = res; +} + +OP(set_macsr) +{ + m68k_set_macsr(env, get_op(PARAM1)); +} --- NEW FILE: op_helper.c --- /* * M68K helper routines * * Copyright (c) 2007 CodeSourcery * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "exec.h" #if defined(CONFIG_USER_ONLY) void do_interrupt(int is_hw) { env->exception_index = -1; } #else extern int semihosting_enabled; #define MMUSUFFIX _mmu #define GETPC() (__builtin_return_address(0)) #define SHIFT 0 #include "softmmu_template.h" #define SHIFT 1 #include "softmmu_template.h" #define SHIFT 2 #include "softmmu_template.h" #define SHIFT 3 #include "softmmu_template.h" /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) { TranslationBlock *tb; CPUState *saved_env; target_phys_addr_t pc; int ret; /* XXX: hack to restore env in all cases, even if not called from generated code */ saved_env = env; env = cpu_single_env; ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, is_user, 1); if (__builtin_expect(ret, 0)) { if (retaddr) { /* now we have a real cpu fault */ pc = (target_phys_addr_t)retaddr; tb = tb_find_pc(pc); if (tb) { /* the PC is inside the translated code. It means that we have a virtual CPU fault */ cpu_restore_state(tb, env, pc, NULL); } } cpu_loop_exit(); } env = saved_env; } static void do_rte(void) { uint32_t sp; uint32_t fmt; sp = env->aregs[7]; fmt = ldl_kernel(sp); env->pc = ldl_kernel(sp + 4); sp |= (fmt >> 28) & 3; env->sr = fmt & 0xffff; env->aregs[7] = sp + 8; } void do_interrupt(int is_hw) { uint32_t sp; uint32_t fmt; uint32_t retaddr; uint32_t vector; fmt = 0; retaddr = env->pc; if (!is_hw) { switch (env->exception_index) { case EXCP_RTE: /* Return from an exception. */ do_rte(); return; case EXCP_HALT_INSN: if (semihosting_enabled && (env->sr & SR_S) != 0 && (env->pc & 3) == 0 && lduw_code(env->pc - 4) == 0x4e71 && ldl_code(env->pc) == 0x4e7bf000) { env->pc += 4; do_m68k_semihosting(env, env->dregs[0]); return; } env->halted = 1; env->exception_index = EXCP_HLT; cpu_loop_exit(); return; } if (env->exception_index >= EXCP_TRAP0 && env->exception_index <= EXCP_TRAP15) { /* Move the PC after the trap instruction. */ retaddr += 2; } } /* TODO: Implement USP. */ sp = env->aregs[7]; vector = env->exception_index << 2; fmt |= 0x40000000; fmt |= (sp & 3) << 28; fmt |= vector << 16; fmt |= env->sr; /* ??? This could cause MMU faults. */ sp &= ~3; sp -= 4; stl_kernel(sp, retaddr); sp -= 4; stl_kernel(sp, fmt); env->aregs[7] = sp; env->sr |= SR_S; if (is_hw) { env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT); } /* Jump to vector. */ env->pc = ldl_kernel(env->vbr + vector); } #endif Index: op-hacks.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-m68k/op-hacks.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- op-hacks.h 23 Feb 2007 21:44:39 -0000 1.1.1.1 +++ op-hacks.h 18 Feb 2008 00:13:58 -0000 1.2 @@ -27,16 +27,38 @@ return qreg; } -static inline void gen_op_ldf32(int dest, int addr) +static inline void gen_op_ldf32_raw(int dest, int addr) { - gen_op_ld32(dest, addr); + gen_op_ld32_raw(dest, addr); } -static inline void gen_op_stf32(int addr, int dest) +static inline void gen_op_stf32_raw(int addr, int dest) { - gen_op_st32(addr, dest); + gen_op_st32_raw(addr, dest); +} + +#if !defined(CONFIG_USER_ONLY) +static inline void gen_op_ldf32_user(int dest, int addr) +{ + gen_op_ld32_user(dest, addr); +} + +static inline void gen_op_stf32_user(int addr, int dest) +{ + gen_op_st32_user(addr, dest); } +static inline void gen_op_ldf32_kernel(int dest, int addr) +{ + gen_op_ld32_kernel(dest, addr); +} + +static inline void gen_op_stf32_kernel(int addr, int dest) +{ + gen_op_st32_kernel(addr, dest); +} +#endif + static inline void gen_op_pack_32_f32(int dest, int src) { gen_op_mov32(dest, src); Index: qregs.def =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-m68k/qregs.def,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- qregs.def 23 Feb 2007 21:44:39 -0000 1.1.1.1 +++ qregs.def 18 Feb 2008 00:13:58 -0000 1.2 @@ -24,6 +24,7 @@ DEFF64(F7, fregs[7]) DEFF64(FP_RESULT, fp_result) DEFO32(PC, pc) +DEFO32(SR, sr) DEFO32(CC_OP, cc_op) DEFR(T0, AREG1, QMODE_I32) DEFO32(CC_DEST, cc_dest) @@ -32,3 +33,5 @@ DEFO32(DIV1, div1) DEFO32(DIV2, div2) DEFO32(EXCEPTION, exception_index) +DEFO32(MACSR, macsr) +DEFO32(MAC_MASK, mac_mask) Index: cpu.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-m68k/cpu.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- cpu.h 23 Feb 2007 21:44:39 -0000 1.1.1.1 +++ cpu.h 18 Feb 2008 00:13:58 -0000 1.2 @@ -1,7 +1,7 @@ /* * m68k virtual CPU header * - * Copyright (c) 2005-2006 CodeSourcery + * Copyright (c) 2005-2007 CodeSourcery * Written by Paul Brook * * This library is free software; you can redistribute it and/or @@ -50,6 +50,9 @@ #define EXCP_UNSUPPORTED 61 #define EXCP_ICE 13 +#define EXCP_RTE 0x100 +#define EXCP_HALT_INSN 0x101 + typedef struct CPUM68KState { uint32_t dregs[8]; uint32_t aregs[8]; @@ -68,6 +71,14 @@ uint32_t fpsr; float_status fp_status; + uint64_t mactmp; + /* EMAC Hardware deals with 48-bit values composed of one 32-bit and + two 8-bit parts. We store a single 64-bit value and + rearrange/extend this when changing modes. */ + uint64_t macc[4]; + uint32_t macsr; + uint32_t mac_mask; + /* Temporary storage for DIV helpers. */ uint32_t div1; uint32_t div2; @@ -76,6 +87,14 @@ struct { uint32_t ar; } mmu; + + /* Control registers. */ + uint32_t vbr; + uint32_t mbar; + uint32_t rambar0; + + uint32_t features; + /* ??? remove this. */ uint32_t t1; @@ -84,7 +103,10 @@ int exception_index; int interrupt_request; int user_mode_only; - uint32_t address; + int halted; + + int pending_vector; + int pending_level; uint32_t qregs[MAX_QREGS]; @@ -94,6 +116,7 @@ CPUM68KState *cpu_m68k_init(void); int cpu_m68k_exec(CPUM68KState *s); void cpu_m68k_close(CPUM68KState *s); +void do_interrupt(int is_hw); /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero is returned if the signal was handled by the virtual CPU. */ @@ -120,15 +143,53 @@ #define CCF_V 0x02 #define CCF_Z 0x04 #define CCF_N 0x08 -#define CCF_X 0x01 +#define CCF_X 0x10 + +#define SR_I_SHIFT 8 +#define SR_I 0x0700 +#define SR_M 0x1000 +#define SR_S 0x2000 +#define SR_T 0x8000 + +#define MACSR_PAV0 0x100 +#define MACSR_OMC 0x080 +#define MACSR_SU 0x040 +#define MACSR_FI 0x020 +#define MACSR_RT 0x010 +#define MACSR_N 0x008 +#define MACSR_Z 0x004 +#define MACSR_V 0x002 +#define MACSR_EV 0x001 typedef struct m68k_def_t m68k_def_t; -m68k_def_t *m68k_find_by_name(const char *); -void cpu_m68k_register(CPUM68KState *, m68k_def_t *); +int cpu_m68k_set_model(CPUM68KState *env, const char * name); + +void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector); +void m68k_set_macsr(CPUM68KState *env, uint32_t val); #define M68K_FPCR_PREC (1 << 6) +void do_m68k_semihosting(CPUM68KState *env, int nr); + +enum m68k_features { + M68K_FEATURE_CF_ISA_A, + M68K_FEATURE_CF_ISA_B, + M68K_FEATURE_CF_ISA_C, + M68K_FEATURE_CF_FPU, + M68K_FEATURE_CF_MAC, + M68K_FEATURE_CF_EMAC, + M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ + M68K_FEATURE_WORD_INDEX /* word sized address index registers. */ +}; + +static inline int m68k_feature(CPUM68KState *env, int feature) +{ + return (env->features & (1u << feature)) != 0; +} + +void register_m68k_insns (CPUM68KState *env); + #ifdef CONFIG_USER_ONLY /* Linux uses 8k pages. */ #define TARGET_PAGE_BITS 13 --- NEW FILE: op_mem.h --- /* Load/store ops. */ #define MEM_LD_OP(name,suffix) \ OP(glue(glue(ld,name),MEMSUFFIX)) \ { \ uint32_t addr = get_op(PARAM2); \ set_op(PARAM1, glue(glue(ld,suffix),MEMSUFFIX)(addr)); \ FORCE_RET(); \ } MEM_LD_OP(8u32,ub) MEM_LD_OP(8s32,sb) MEM_LD_OP(16u32,uw) MEM_LD_OP(16s32,sw) MEM_LD_OP(32,l) #undef MEM_LD_OP #define MEM_ST_OP(name,suffix) \ OP(glue(glue(st,name),MEMSUFFIX)) \ { \ uint32_t addr = get_op(PARAM1); \ glue(glue(st,suffix),MEMSUFFIX)(addr, get_op(PARAM2)); \ FORCE_RET(); \ } MEM_ST_OP(8,b) MEM_ST_OP(16,w) MEM_ST_OP(32,l) #undef MEM_ST_OP OP(glue(ldf64,MEMSUFFIX)) { uint32_t addr = get_op(PARAM2); set_opf64(PARAM1, glue(ldfq,MEMSUFFIX)(addr)); FORCE_RET(); } OP(glue(stf64,MEMSUFFIX)) { uint32_t addr = get_op(PARAM1); glue(stfq,MEMSUFFIX)(addr, get_opf64(PARAM2)); FORCE_RET(); } #undef MEMSUFFIX Index: exec.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-m68k/exec.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- exec.h 23 Feb 2007 21:44:39 -0000 1.1.1.1 +++ exec.h 18 Feb 2008 00:13:58 -0000 1.2 @@ -40,8 +40,12 @@ int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int is_user, int is_softmmu); +#if !defined(CONFIG_USER_ONLY) +#include "softmmu_exec.h" +#endif void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op); float64 helper_sub_cmpf64(CPUM68KState *env, float64 src0, float64 src1); +void helper_movec(CPUM68KState *env, int reg, uint32_t val); void cpu_loop_exit(void); |
|
From: Stuart B. <zu...@us...> - 2008-02-18 00:14:34
|
Update of /cvsroot/hppaqemu/hppaqemu/target-i386 In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv24609/target-i386 Modified Files: cpu.h helper.c helper2.c translate.c Log Message: Update to QEMU CVS from 2007-06-01. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-i386/translate.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- translate.c 23 Feb 2007 21:44:39 -0000 1.1.1.1 +++ translate.c 18 Feb 2008 00:13:58 -0000 1.2 @@ -2245,7 +2245,7 @@ } /* an interrupt is different from an exception because of the - priviledge checks */ + privilege checks */ static void gen_interrupt(DisasContext *s, int intno, target_ulong cur_eip, target_ulong next_eip) { @@ -3797,6 +3797,7 @@ mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; + gen_jmp_im(pc_start - s->cs_base); if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_lea_modrm(s, modrm, ®_addr, &offset_addr); Index: helper.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-i386/helper.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- helper.c 23 Feb 2007 21:44:37 -0000 1.1.1.1 +++ helper.c 18 Feb 2008 00:13:57 -0000 1.2 @@ -687,7 +687,7 @@ if (!(e2 & DESC_P_MASK)) raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); if (!(e2 & DESC_C_MASK) && dpl < cpl) { - /* to inner priviledge */ + /* to inner privilege */ get_ss_esp_from_tss(&ss, &esp, dpl); if ((ss & 0xfffc) == 0) raise_exception_err(EXCP0A_TSS, ss & 0xfffc); @@ -708,7 +708,7 @@ sp_mask = get_sp_mask(ss_e2); ssp = get_seg_base(ss_e1, ss_e2); } else if ((e2 & DESC_C_MASK) || dpl == cpl) { - /* to same priviledge */ + /* to same privilege */ if (env->eflags & VM_MASK) raise_exception_err(EXCP0D_GPF, selector & 0xfffc); new_stack = 0; @@ -901,7 +901,7 @@ if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) raise_exception_err(EXCP0D_GPF, selector & 0xfffc); if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) { - /* to inner priviledge */ + /* to inner privilege */ if (ist != 0) esp = get_rsp_from_tss(ist + 3); else @@ -910,7 +910,7 @@ ss = 0; new_stack = 1; } else if ((e2 & DESC_C_MASK) || dpl == cpl) { - /* to same priviledge */ + /* to same privilege */ if (env->eflags & VM_MASK) raise_exception_err(EXCP0D_GPF, selector & 0xfffc); new_stack = 0; @@ -1193,6 +1193,40 @@ } /* + * Check nested exceptions and change to double or triple fault if + * needed. It should only be called, if this is not an interrupt. + * Returns the new exception number. + */ +int check_exception(int intno, int *error_code) +{ + char first_contributory = env->old_exception == 0 || + (env->old_exception >= 10 && + env->old_exception <= 13); + char second_contributory = intno == 0 || + (intno >= 10 && intno <= 13); + + if (loglevel & CPU_LOG_INT) + fprintf(logfile, "check_exception old: %x new %x\n", + env->old_exception, intno); + + if (env->old_exception == EXCP08_DBLE) + cpu_abort(env, "triple fault"); + + if ((first_contributory && second_contributory) + || (env->old_exception == EXCP0E_PAGE && + (second_contributory || (intno == EXCP0E_PAGE)))) { + intno = EXCP08_DBLE; + *error_code = 0; + } + + if (second_contributory || (intno == EXCP0E_PAGE) || + (intno == EXCP08_DBLE)) + env->old_exception = intno; + + return intno; +} + +/* * Signal an interruption. It is executed in the main CPU loop. * is_int is TRUE if coming from the int instruction. next_eip is the * EIP value AFTER the interrupt instruction. It is only relevant if @@ -1201,6 +1235,9 @@ void raise_interrupt(int intno, int is_int, int error_code, int next_eip_addend) { + if (!is_int) + intno = check_exception(intno, &error_code); + env->exception_index = intno; env->error_code = error_code; env->exception_is_int = is_int; @@ -1211,6 +1248,8 @@ /* same as raise_exception_err, but do not restore global registers */ static void raise_exception_err_norestore(int exception_index, int error_code) { + exception_index = check_exception(exception_index, &error_code); + env->exception_index = exception_index; env->error_code = error_code; env->exception_is_int = 0; @@ -1614,7 +1653,7 @@ break; case 1: EAX = env->cpuid_version; - EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ + EBX = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ ECX = env->cpuid_ext_features; EDX = env->cpuid_features; break; @@ -1825,8 +1864,11 @@ raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); #ifdef TARGET_X86_64 if (env->hflags & HF_LMA_MASK) { - uint32_t e3; + uint32_t e3, e4; e3 = ldl_kernel(ptr + 8); + e4 = ldl_kernel(ptr + 12); + if ((e4 >> DESC_TYPE_SHIFT) & 0xf) + raise_exception_err(EXCP0D_GPF, selector & 0xfffc); load_seg_cache_raw_dt(&env->tr, e1, e2); env->tr.base |= (target_ulong)e3 << 32; } else @@ -2166,7 +2208,7 @@ raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc); if (!(e2 & DESC_C_MASK) && dpl < cpl) { - /* to inner priviledge */ + /* to inner privilege */ get_ss_esp_from_tss(&ss, &sp, dpl); #ifdef DEBUG_PCALL if (loglevel & CPU_LOG_PCALL) @@ -2213,7 +2255,7 @@ } new_stack = 1; } else { - /* to same priviledge */ + /* to same privilege */ sp = ESP; sp_mask = get_sp_mask(env->segs[R_SS].flags); ssp = env->segs[R_SS].base; @@ -2395,7 +2437,7 @@ get_seg_limit(e1, e2), e2); } else { - /* return to different priviledge level */ + /* return to different privilege level */ #ifdef TARGET_X86_64 if (shift == 2) { POPQ(sp, new_esp); @@ -3097,30 +3139,51 @@ CPU86_LDouble dblq, fpsrcop, fptemp; CPU86_LDoubleU fpsrcop1, fptemp1; int expdif; - int q; + signed long long int q; + + if (isinf(ST0) || isnan(ST0) || isnan(ST1) || (ST1 == 0.0)) { + ST0 = 0.0 / 0.0; /* NaN */ + env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ + return; + } fpsrcop = ST0; fptemp = ST1; fpsrcop1.d = fpsrcop; fptemp1.d = fptemp; expdif = EXPD(fpsrcop1) - EXPD(fptemp1); + + if (expdif < 0) { + /* optimisation? taken from the AMD docs */ + env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ + /* ST0 is unchanged */ + return; + } + if (expdif < 53) { dblq = fpsrcop / fptemp; - dblq = (dblq < 0.0)? ceil(dblq): floor(dblq); - ST0 = fpsrcop - fptemp*dblq; - q = (int)dblq; /* cutting off top bits is assumed here */ + /* round dblq towards nearest integer */ + dblq = rint(dblq); + ST0 = fpsrcop - fptemp * dblq; + + /* convert dblq to q by truncating towards zero */ + if (dblq < 0.0) + q = (signed long long int)(-dblq); + else + q = (signed long long int)dblq; + env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ - /* (C0,C1,C3) <-- (q2,q1,q0) */ - env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */ - env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */ - env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */ + /* (C0,C3,C1) <-- (q2,q1,q0) */ + env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */ + env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */ + env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */ } else { env->fpus |= 0x400; /* C2 <-- 1 */ - fptemp = pow(2.0, expdif-50); + fptemp = pow(2.0, expdif - 50); fpsrcop = (ST0 / ST1) / fptemp; - /* fpsrcop = integer obtained by rounding to the nearest */ - fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)? - floor(fpsrcop): ceil(fpsrcop); + /* fpsrcop = integer obtained by chopping */ + fpsrcop = (fpsrcop < 0.0) ? + -(floor(fabs(fpsrcop))) : floor(fpsrcop); ST0 -= (ST1 * fpsrcop * fptemp); } } @@ -3130,30 +3193,52 @@ CPU86_LDouble dblq, fpsrcop, fptemp; CPU86_LDoubleU fpsrcop1, fptemp1; int expdif; - int q; - - fpsrcop = ST0; - fptemp = ST1; + signed long long int q; + + if (isinf(ST0) || isnan(ST0) || isnan(ST1) || (ST1 == 0.0)) { + ST0 = 0.0 / 0.0; /* NaN */ + env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ + return; + } + + fpsrcop = (CPU86_LDouble)ST0; + fptemp = (CPU86_LDouble)ST1; fpsrcop1.d = fpsrcop; fptemp1.d = fptemp; expdif = EXPD(fpsrcop1) - EXPD(fptemp1); + + if (expdif < 0) { + /* optimisation? taken from the AMD docs */ + env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ + /* ST0 is unchanged */ + return; + } + if ( expdif < 53 ) { - dblq = fpsrcop / fptemp; - dblq = (dblq < 0.0)? ceil(dblq): floor(dblq); - ST0 = fpsrcop - fptemp*dblq; - q = (int)dblq; /* cutting off top bits is assumed here */ + dblq = fpsrcop/*ST0*/ / fptemp/*ST1*/; + /* round dblq towards zero */ + dblq = (dblq < 0.0) ? ceil(dblq) : floor(dblq); + ST0 = fpsrcop/*ST0*/ - fptemp * dblq; + + /* convert dblq to q by truncating towards zero */ + if (dblq < 0.0) + q = (signed long long int)(-dblq); + else + q = (signed long long int)dblq; + env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */ - /* (C0,C1,C3) <-- (q2,q1,q0) */ - env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */ - env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */ - env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */ + /* (C0,C3,C1) <-- (q2,q1,q0) */ + env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */ + env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */ + env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */ } else { + int N = 32 + (expdif % 32); /* as per AMD docs */ env->fpus |= 0x400; /* C2 <-- 1 */ - fptemp = pow(2.0, expdif-50); + fptemp = pow(2.0, (double)(expdif - N)); fpsrcop = (ST0 / ST1) / fptemp; /* fpsrcop = integer obtained by chopping */ - fpsrcop = (fpsrcop < 0.0)? - -(floor(fabs(fpsrcop))): floor(fpsrcop); + fpsrcop = (fpsrcop < 0.0) ? + -(floor(fabs(fpsrcop))) : floor(fpsrcop); ST0 -= (ST1 * fpsrcop * fptemp); } } @@ -3535,50 +3620,6 @@ add128(plow, phigh, 1, 0); } -static void mul64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b) -{ - uint32_t a0, a1, b0, b1; - uint64_t v; - - a0 = a; - a1 = a >> 32; - - b0 = b; - b1 = b >> 32; - - v = (uint64_t)a0 * (uint64_t)b0; - *plow = v; - *phigh = 0; - - v = (uint64_t)a0 * (uint64_t)b1; - add128(plow, phigh, v << 32, v >> 32); - - v = (uint64_t)a1 * (uint64_t)b0; - add128(plow, phigh, v << 32, v >> 32); - - v = (uint64_t)a1 * (uint64_t)b1; - *phigh += v; -#ifdef DEBUG_MULDIV - printf("mul: 0x%016" PRIx64 " * 0x%016" PRIx64 " = 0x%016" PRIx64 "%016" PRIx64 "\n", - a, b, *phigh, *plow); -#endif -} - -static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b) -{ - int sa, sb; - sa = (a < 0); - if (sa) - a = -a; - sb = (b < 0); - if (sb) - b = -b; - mul64(plow, phigh, a, b); - if (sa ^ sb) { - neg128(plow, phigh); - } -} - /* return TRUE if overflow */ static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b) { @@ -3646,7 +3687,7 @@ { uint64_t r0, r1; - mul64(&r0, &r1, EAX, T0); + mulu64(&r1, &r0, EAX, T0); EAX = r0; EDX = r1; CC_DST = r0; @@ -3657,7 +3698,7 @@ { uint64_t r0, r1; - imul64(&r0, &r1, EAX, T0); + muls64(&r1, &r0, EAX, T0); EAX = r0; EDX = r1; CC_DST = r0; @@ -3668,7 +3709,7 @@ { uint64_t r0, r1; - imul64(&r0, &r1, T0, T1); + muls64(&r1, &r0, T0, T1); T0 = r0; CC_DST = r0; CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63)); Index: helper2.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-i386/helper2.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- helper2.c 23 Feb 2007 21:44:37 -0000 1.1.1.1 +++ helper2.c 18 Feb 2008 00:13:57 -0000 1.2 @@ -578,7 +578,7 @@ return 1; } -target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { return addr; } @@ -670,7 +670,7 @@ #endif { /* XXX: load them when cr3 is loaded ? */ - pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 30) << 3)) & + pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & env->a20_mask; pdpe = ldq_phys(pdpe_addr); if (!(pdpe & PG_PRESENT_MASK)) { @@ -765,7 +765,7 @@ uint32_t pde; /* page directory entry */ - pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & + pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask; pde = ldl_phys(pde_addr); if (!(pde & PG_PRESENT_MASK)) { @@ -876,7 +876,7 @@ return 1; } -target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) { uint32_t pde_addr, pte_addr; uint32_t pde, pte, paddr, page_offset, page_size; @@ -910,7 +910,7 @@ } else #endif { - pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 30) << 3)) & + pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & env->a20_mask; pdpe = ldl_phys(pdpe_addr); if (!(pdpe & PG_PRESENT_MASK)) @@ -940,7 +940,7 @@ page_size = 4096; } else { /* page directory entry */ - pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & env->a20_mask; + pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask; pde = ldl_phys(pde_addr); if (!(pde & PG_PRESENT_MASK)) return -1; Index: cpu.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-i386/cpu.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- cpu.h 23 Feb 2007 21:44:37 -0000 1.1.1.1 +++ cpu.h 18 Feb 2008 00:13:57 -0000 1.2 @@ -515,6 +515,7 @@ uint32_t smbase; int interrupt_request; int user_mode_only; /* user mode only simulation */ + int old_exception; /* exception in flight */ CPU_COMMON @@ -529,6 +530,7 @@ uint32_t cpuid_xlevel; uint32_t cpuid_model[12]; uint32_t cpuid_ext2_features; + uint32_t cpuid_apic_id; #ifdef USE_KQEMU int kqemu_enabled; |
