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hppaqemu-cvs — CVS commits for the HPPA target for QEMU
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Update of /cvsroot/hppaqemu/hppaqemu/target-m68k In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/target-m68k Removed Files: cpu.h exec.h helper.c m68k-qreg.h op-hacks.h op.c op_helper.c op_mem.h qregs.def translate.c Log Message: Remove everything --- translate.c DELETED --- --- helper.c DELETED --- --- m68k-qreg.h DELETED --- --- op.c DELETED --- --- op_helper.c DELETED --- --- op-hacks.h DELETED --- --- qregs.def DELETED --- --- cpu.h DELETED --- --- op_mem.h DELETED --- --- exec.h DELETED --- |
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From: Stuart B. <zu...@us...> - 2009-02-06 22:54:43
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/m68k In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/linux-user/m68k Removed Files: syscall.h syscall_nr.h target_signal.h termbits.h Log Message: Remove everything --- syscall.h DELETED --- --- target_signal.h DELETED --- --- syscall_nr.h DELETED --- --- termbits.h DELETED --- |
Update of /cvsroot/hppaqemu/hppaqemu/linux-user In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/linux-user Removed Files: elfload.c elfload32.c errno_defs.h flat.h flatload.c ioctls.h linuxload.c m68k-sim.c main.c mmap.c path.c qemu.h signal.c socket.h strace.c strace.list syscall.c syscall_defs.h syscall_types.h uaccess.c vm86.c Log Message: Remove everything --- m68k-sim.c DELETED --- --- flatload.c DELETED --- --- syscall.c DELETED --- --- ioctls.h DELETED --- --- elfload32.c DELETED --- --- strace.list DELETED --- --- main.c DELETED --- --- syscall_defs.h DELETED --- --- strace.c DELETED --- --- flat.h DELETED --- --- path.c DELETED --- --- elfload.c DELETED --- --- linuxload.c DELETED --- --- uaccess.c DELETED --- --- syscall_types.h DELETED --- --- socket.h DELETED --- --- errno_defs.h DELETED --- --- vm86.c DELETED --- --- qemu.h DELETED --- --- mmap.c DELETED --- --- signal.c DELETED --- |
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From: Stuart B. <zu...@us...> - 2009-02-06 22:54:42
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/arm In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/linux-user/arm Removed Files: syscall.h syscall_nr.h target_signal.h termbits.h Log Message: Remove everything --- syscall.h DELETED --- --- target_signal.h DELETED --- --- syscall_nr.h DELETED --- --- termbits.h DELETED --- |
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From: Stuart B. <zu...@us...> - 2009-02-06 22:54:42
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/hppa In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/linux-user/hppa Removed Files: syscall.h syscall_nr.h target_signal.h termbits.h Log Message: Remove everything --- syscall.h DELETED --- --- target_signal.h DELETED --- --- syscall_nr.h DELETED --- --- termbits.h DELETED --- |
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From: Stuart B. <zu...@us...> - 2009-02-06 22:54:42
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Update of /cvsroot/hppaqemu/hppaqemu/target-arm/nwfpe In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/target-arm/nwfpe Removed Files: double_cpdo.c extended_cpdo.c fpa11.c fpa11.h fpa11.inl fpa11_cpdo.c fpa11_cpdt.c fpa11_cprt.c fpopcode.c fpopcode.h fpsr.h single_cpdo.c Log Message: Remove everything --- fpa11.h DELETED --- --- fpa11_cpdt.c DELETED --- --- fpa11.c DELETED --- --- single_cpdo.c DELETED --- --- fpa11_cpdo.c DELETED --- --- fpopcode.h DELETED --- --- fpsr.h DELETED --- --- extended_cpdo.c DELETED --- --- double_cpdo.c DELETED --- --- fpopcode.c DELETED --- --- fpa11.inl DELETED --- --- fpa11_cprt.c DELETED --- |
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From: Stuart B. <zu...@us...> - 2009-02-06 22:54:42
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/i386 In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/linux-user/i386 Removed Files: syscall.h syscall_nr.h target_signal.h termbits.h Log Message: Remove everything --- syscall.h DELETED --- --- target_signal.h DELETED --- --- syscall_nr.h DELETED --- --- termbits.h DELETED --- |
Update of /cvsroot/hppaqemu/hppaqemu/keymaps In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/keymaps Removed Files: ar common da de de-ch en-gb en-us es et fi fo fr fr-be fr-ca fr-ch hr hu is it ja lt lv mk modifiers nl nl-be no pl pt pt-br ru sl sv th tr Log Message: Remove everything --- is DELETED --- --- en-us DELETED --- --- it DELETED --- --- fr-be DELETED --- --- ar DELETED --- --- pt-br DELETED --- --- de-ch DELETED --- --- et DELETED --- --- nl-be DELETED --- --- es DELETED --- --- en-gb DELETED --- --- ru DELETED --- --- nl DELETED --- --- pt DELETED --- --- no DELETED --- --- tr DELETED --- --- lv DELETED --- --- fr-ca DELETED --- --- lt DELETED --- --- th DELETED --- --- pl DELETED --- --- fr-ch DELETED --- --- fr DELETED --- --- hr DELETED --- --- de DELETED --- --- hu DELETED --- --- fi DELETED --- --- da DELETED --- --- ja DELETED --- --- fo DELETED --- --- modifiers DELETED --- --- sv DELETED --- --- mk DELETED --- --- common DELETED --- --- sl DELETED --- |
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From: Stuart B. <zu...@us...> - 2009-02-06 22:54:42
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Update of /cvsroot/hppaqemu/hppaqemu/darwin-user In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/darwin-user Removed Files: commpage.c ioctls.h ioctls_types.h machload.c main.c mmap.c qemu.h signal.c syscall.c syscalls.h Log Message: Remove everything --- syscall.c DELETED --- --- ioctls.h DELETED --- --- ioctls_types.h DELETED --- --- qemu.h DELETED --- --- syscalls.h DELETED --- --- machload.c DELETED --- --- signal.c DELETED --- --- commpage.c DELETED --- --- main.c DELETED --- --- mmap.c DELETED --- |
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From: Stuart B. <zu...@us...> - 2009-02-06 22:54:42
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Update of /cvsroot/hppaqemu/hppaqemu/target-alpha In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/target-alpha Removed Files: STATUS cpu.h exec.h helper.c op.c op_helper.c op_helper.h op_helper_mem.h op_mem.h op_template.h translate.c Log Message: Remove everything --- translate.c DELETED --- --- op_helper.h DELETED --- --- STATUS DELETED --- --- helper.c DELETED --- --- op_helper.c DELETED --- --- op.c DELETED --- --- op_template.h DELETED --- --- op_mem.h DELETED --- --- op_helper_mem.h DELETED --- --- cpu.h DELETED --- --- exec.h DELETED --- |
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From: Stuart B. <zu...@us...> - 2009-02-06 22:54:42
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/mips In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/linux-user/mips Removed Files: syscall.h syscall_nr.h target_signal.h termbits.h Log Message: Remove everything --- syscall.h DELETED --- --- target_signal.h DELETED --- --- syscall_nr.h DELETED --- --- termbits.h DELETED --- |
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From: Stuart B. <zu...@us...> - 2009-02-06 22:54:42
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user/cris In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv8933/linux-user/cris Removed Files: syscall.h syscall_nr.h target_signal.h termbits.h Log Message: Remove everything --- syscall.h DELETED --- --- target_signal.h DELETED --- --- syscall_nr.h DELETED --- --- termbits.h DELETED --- |
Update of /cvsroot/hppaqemu/hppaqemu In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv1564 Modified Files: Makefile.target configure cpu-all.h cpu-exec.c disas.c dyngen-exec.h dyngen.c dyngen.h exec-all.h exec.c Log Message: Remove HPPA host support, in preparation for the move to separate Git trees for host and target support. Index: dyngen-exec.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/dyngen-exec.h,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- dyngen-exec.h 18 Feb 2008 05:24:38 -0000 1.5 +++ dyngen-exec.h 29 Feb 2008 01:47:57 -0000 1.6 @@ -124,11 +124,6 @@ #define AREG1 "r4" #define AREG2 "r5" #define AREG3 "r6" -#elif defined(__hppa__) -#define AREG0 "r17" -#define AREG1 "r14" -#define AREG2 "r15" -#define AREG3 "r16" #elif defined(__mips__) #define AREG0 "fp" #define AREG1 "s0" @@ -284,11 +279,6 @@ #elif defined(__mips__) #define EXIT_TB() asm volatile ("jr $ra") #define GOTO_LABEL_PARAM(n) asm volatile (".set noat; la $1, " ASM_NAME(__op_gen_label) #n "; jr $1; .set at") -#elif defined(__hppa__) -#define EXIT_TB() asm volatile ("ldil L'exec_loop, %r1\n" \ - "ldo R'exec_loop(%r1), %r1\n" \ - "bv,n %r0(%r1)\n") -#define GOTO_LABEL_PARAM(n) asm volatile ("b,n " ASM_NAME(__op_gen_label) #n) #else #error unsupported CPU #endif Index: dyngen.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/dyngen.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- dyngen.h 18 Feb 2008 05:24:38 -0000 1.6 +++ dyngen.h 29 Feb 2008 01:47:58 -0000 1.7 @@ -62,20 +62,6 @@ asm volatile ("sync" : : : "memory"); asm volatile ("isync" : : : "memory"); } -#elif defined(__hppa__) -static inline void flush_icache_range(unsigned long start, unsigned long stop) -{ - start &= ~31; - while (start < stop) - { - asm volatile ("fdc 0(%0)\n" - "sync\n" - "fic 0(%%sr4, %0)\n" - "sync\n" - : : "r"(start) : "memory"); - start += 32; - } -} #elif defined(__alpha__) static inline void flush_icache_range(unsigned long start, unsigned long stop) { @@ -244,138 +230,6 @@ #endif /* __arm__ */ -#ifdef __hppa__ - -/* Field selection types defined by hppa */ -#define rnd(x) (((x)+0x1000)&~0x1fff) -/* lsel: select left 21 bits */ -#define lsel(v,a) (((v)+(a))>>11) -/* rsel: select right 11 bits */ -#define rsel(v,a) (((v)+(a))&0x7ff) -/* lrsel with rounding of addend to nearest 8k */ -#define lrsel(v,a) (((v)+rnd(a))>>11) -/* rrsel with rounding of addend to nearest 8k */ -#define rrsel(v,a) ((((v)+rnd(a))&0x7ff)+((a)-rnd(a))) - -#define mask(x,sz) ((x) & ~((1<<(sz))-1)) - -static inline int reassemble_14(int as14) -{ - return (((as14 & 0x1fff) << 1) | - ((as14 & 0x2000) >> 13)); -} - -static inline int reassemble_17(int as17) -{ - return (((as17 & 0x10000) >> 16) | - ((as17 & 0x0f800) << 5) | - ((as17 & 0x00400) >> 8) | - ((as17 & 0x003ff) << 3)); -} - -static inline int reassemble_21(int as21) -{ - return (((as21 & 0x100000) >> 20) | - ((as21 & 0x0ffe00) >> 8) | - ((as21 & 0x000180) << 7) | - ((as21 & 0x00007c) << 14) | - ((as21 & 0x000003) << 12)); -} - -struct hppa_branch_stub { - uint32_t *location; - long target; - struct hppa_branch_stub *next; -}; - -#define HPPA_RECORD_BRANCH(LIST, LOC, TARGET) \ -do { \ - struct hppa_branch_stub *stub = alloca(sizeof(struct hppa_branch_stub)); \ - stub->location = LOC; \ - stub->target = TARGET; \ - stub->next = LIST; \ - LIST = stub; \ -} while (0) - -static inline void hppa_patch21l(uint32_t *insn, int val, int addend) -{ - val = lrsel(val, addend); - *insn = mask(*insn, 21) | reassemble_21(val); -} - -static inline void hppa_patch14r(uint32_t *insn, int val, int addend) -{ - val = rrsel(val, addend); - *insn = mask(*insn, 14) | reassemble_14(val); -} - -static inline void hppa_patch17r(uint32_t *insn, int val, int addend) -{ - val = rrsel(val, addend); - *insn = (*insn & ~0x1f1ffd) | reassemble_17(val); -} - - -static inline void hppa_patch21l_dprel(uint32_t *insn, int val, int addend) -{ - register unsigned int dp asm("r27"); - hppa_patch21l(insn, val - dp, addend); -} - -static inline void hppa_patch14r_dprel(uint32_t *insn, int val, int addend) -{ - register unsigned int dp asm("r27"); - hppa_patch14r(insn, val - dp, addend); -} - -static inline void hppa_patch17f(uint32_t *insn, int val, int addend) -{ - int dot = (int)insn & ~0x3; - int v = ((val + addend) - dot - 8) / 4; - if (v > (1 << 16) || v < -(1 << 16)) { - printf("cannot fit branch to offset %d [%08x->%08x]\n", v, dot, val); - abort(); - } - *insn = (*insn & ~0x1f1ffd) | reassemble_17(v); -} - -static inline void hppa_load_imm21l(uint32_t *insn, int val, int addend) -{ - /* Transform addil L'sym(%dp) to ldil L'val, %r1 */ - *insn = 0x20200000 | reassemble_21(lrsel(val, 0)); -} - -static inline void hppa_load_imm14r(uint32_t *insn, int val, int addend) -{ - /* Transform ldw R'sym(%r1), %rN to ldo R'sym(%r1), %rN */ - hppa_patch14r(insn, val, addend); - /* HACK */ - if (addend == 0) - *insn = (*insn & ~0xfc000000) | (0x0d << 26); -} - -static inline void hppa_process_stubs(struct hppa_branch_stub *stub, uint8_t **gen_code_pp) -{ - uint32_t *p = (uint32_t *)*gen_code_pp; - for (; stub != NULL; stub = stub->next) - { - unsigned long l = (unsigned long)p; - /* stub: - * ldil L'target, %r1 - * be,n R'target(%r1) - */ - *p++ = 0x20200000 | reassemble_21(lrsel(stub->target, 0)); - *p++ = 0xe0200002 | reassemble_17(rrsel(stub->target, 0) >> 2); - hppa_patch17f(stub->location, l, 0); - } - *gen_code_pp = (uint8_t *)p; -} - -/* supplied by libgcc */ -extern void *__canonicalize_funcptr_for_compare(void *); - -#endif - #ifdef __ia64 /* Patch instruction with "val" where "mask" has 1 bits. */ Index: configure =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/configure,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- configure 18 Feb 2008 05:24:37 -0000 1.7 +++ configure 29 Feb 2008 01:47:57 -0000 1.8 @@ -47,9 +47,6 @@ "Power Macintosh"|ppc|ppc64) cpu="powerpc" ;; - parisc|parisc64) - cpu="hppa" - ;; mips) cpu="mips" ;; @@ -564,7 +561,7 @@ else # if cross compiling, cannot launch a program, so make a static guess -if test "$cpu" = "powerpc" -o "$cpu" = "mips" -o "$cpu" = "mips64" -o "$cpu" = "s390" -o "$cpu" = "sparc" -o "$cpu" = "sparc64" -o "$cpu" = "m68k" -o "$cpu" = "armv4b" -o "$cpu" = "hppa"; then +if test "$cpu" = "powerpc" -o "$cpu" = "mips" -o "$cpu" = "mips64" -o "$cpu" = "s390" -o "$cpu" = "sparc" -o "$cpu" = "sparc64" -o "$cpu" = "m68k" -o "$cpu" = "armv4b"; then bigendian="yes" fi @@ -805,9 +802,6 @@ elif test "$cpu" = "powerpc" ; then echo "ARCH=ppc" >> $config_mak echo "#define HOST_PPC 1" >> $config_h -elif test "$cpu" = "hppa" ; then - echo "ARCH=hppa" >> $config_mak - echo "#define HOST_HPPA 1" >> $config_h elif test "$cpu" = "mips" ; then echo "ARCH=mips" >> $config_mak echo "#define HOST_MIPS 1" >> $config_h Index: dyngen.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/dyngen.c,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- dyngen.c 18 Feb 2008 05:24:38 -0000 1.5 +++ dyngen.c 29 Feb 2008 01:47:58 -0000 1.6 @@ -117,13 +117,6 @@ #define elf_check_arch(x) ((x) == EM_68K) #define ELF_USES_RELOCA -#elif defined(HOST_HPPA) - -#define ELF_CLASS ELFCLASS32 -#define ELF_ARCH EM_PARISC -#define elf_check_arch(x) ((x) == EM_PARISC) -#define ELF_USES_RELOCA - #elif defined(HOST_MIPS) #define ELF_CLASS ELFCLASS32 @@ -1228,7 +1221,7 @@ } else if (strstart(sym_name, "__op_gen_label", &p)) { snprintf(name, name_size, "gen_labels[param%s]", p); } else { -#if defined(HOST_SPARC) || defined(HOST_HPPA) +#ifdef HOST_SPARC if (sym_name[0] == '.') snprintf(name, name_size, "(long)(&__dot_%s)", @@ -1663,43 +1656,6 @@ error("rts expected at the end of %s", name); copy_size = p - p_start; } -#elif defined(HOST_HPPA) - { - uint8_t *p; - p = p_start; - while (p < p_end) { - uint32_t insn = get32((uint32_t *)p); - if (insn == 0x6bc23fd9 || - insn == 0x08030241 || - insn == 0x081e0243 || - (insn & 0x37de0000) == 0x37de0000 || - (insn & 0xffffc000) == 0x6fc10000) - p += 4; - else - break; - } - start_offset += p - p_start; - p_start = p; - p = p_end - 4; - - while (p > p_start) { - uint32_t insn = get32((uint32_t *)p); - if ((insn & 0xffffc000) == 0x347e0000 || - (insn & 0x0fc010e0) == 0x0fc01080 || - (insn & 0x37de0000) == 0x37de0000 || - insn == 0x48623fd9 || - insn == 0xe840c000 || - insn == 0xe840c002) - p -= 4; - else - break; - } - p += 4; - if (p <= p_start) - error("empty code for %s", name); - - copy_size = p - p_start; - } #elif defined(HOST_MIPS) || defined(HOST_MIPS64) { #define INSN_RETURN 0x03e00008 @@ -1785,7 +1741,7 @@ !strstart(sym_name, "__op_param", NULL) && !strstart(sym_name, "__op_jmp", NULL) && !strstart(sym_name, "__op_gen_label", NULL)) { -#if defined(HOST_SPARC) || defined(HOST_HPPA) +#if defined(HOST_SPARC) if (sym_name[0] == '.') { fprintf(outfile, "extern char __dot_%s __asm__(\"%s\");\n", @@ -1813,15 +1769,8 @@ } } -#ifndef __hppa__ fprintf(outfile, " memcpy(gen_code_ptr, (void *)((char *)&%s+%d), %d);\n", name, (int)(start_offset - offset), copy_size); -#else - fprintf(outfile, " memcpy(gen_code_ptr, (void *)((char *)__canonicalize_funcptr_for_compare(%s)+%d), %d);\n", - name, (int)(start_offset - offset), copy_size); - - -#endif /* emit code offset information */ { @@ -2582,73 +2531,6 @@ } } } -#elif defined(HOST_HPPA) - { - char name[256]; - int type; - int addend; - int reloc_offset; - for(i = 0, rel = relocs;i < nb_relocs; i++, rel++) { - if (rel->r_offset >= start_offset && - rel->r_offset < start_offset + copy_size) { - sym_name = get_rel_sym_name(rel); - sym_name = strtab + symtab[ELF32_R_SYM(rel->r_info)].st_name; - get_reloc_expr(name, sizeof(name), sym_name); - type = ELF32_R_TYPE(rel->r_info); - addend = rel->r_addend; - reloc_offset = rel->r_offset - start_offset; - - switch(type) { - case R_PARISC_DIR21L: - fprintf(outfile, - " hppa_patch21l((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", - reloc_offset, name, addend); - break; - case R_PARISC_DIR14R: - fprintf(outfile, - " hppa_patch14r((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", - reloc_offset, name, addend); - break; - case R_PARISC_DIR17R: - fprintf(outfile, - " hppa_patch17r((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", - reloc_offset, name, addend); - break; - case R_PARISC_PCREL17F: - if (strstart(sym_name, "__op_gen_label", NULL)) { - fprintf(outfile, - " hppa_patch17f((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", - reloc_offset, name, addend); - } else { - fprintf(outfile, - " HPPA_RECORD_BRANCH(hppa_stubs, (uint32_t *)(gen_code_ptr + %d), %s);\n", - reloc_offset, name); - } - break; - case R_PARISC_DPREL21L: - if (strstart(sym_name, "__op_param", &p)) - fprintf(outfile, " hppa_load_imm21l((uint32_t *)(gen_code_ptr + %d), param%s, %d);\n", - reloc_offset, p, addend); - else - fprintf(outfile, - " hppa_patch21l_dprel((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", - reloc_offset, name, addend); - break; - case R_PARISC_DPREL14R: - if (strstart(sym_name, "__op_param", &p)) - fprintf(outfile, " hppa_load_imm14r((uint32_t *)(gen_code_ptr + %d), param%s, %d);\n", - reloc_offset, p, addend); - else - fprintf(outfile, - " hppa_patch14r_dprel((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", - reloc_offset, name, addend); - break; - default: - error("unsupported hppa relocation (%d)", type); - } - } - } - } #elif defined(HOST_MIPS) || defined(HOST_MIPS64) { for (i = 0, rel = relocs; i < nb_relocs; i++, rel++) { @@ -2907,10 +2789,6 @@ } #endif -#ifdef HOST_HPPA - fprintf(outfile, " struct hppa_branch_stub *hppa_stubs = NULL;\n"); -#endif - fprintf(outfile, "\n" " gen_code_ptr = gen_code_buf;\n" @@ -2992,11 +2870,6 @@ " gen_code_ptr = arm_flush_ldr(gen_code_ptr, arm_ldr_table, " "arm_ldr_ptr, arm_data_ptr, arm_data_table + ARM_LDR_TABLE_SIZE, 0);\n"); #endif - -#ifdef HOST_HPPA - fprintf(outfile, "hppa_process_stubs(hppa_stubs, &gen_code_ptr);\n"); -#endif - /* flush instruction cache */ fprintf(outfile, "flush_icache_range((unsigned long)gen_code_buf, (unsigned long)gen_code_ptr);\n"); Index: cpu-exec.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/cpu-exec.c,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- cpu-exec.c 18 Feb 2008 05:24:38 -0000 1.9 +++ cpu-exec.c 29 Feb 2008 01:47:57 -0000 1.10 @@ -681,15 +681,6 @@ : /* no outputs */ : "r" (gen_func) : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); -#elif defined(__hppa__) - asm volatile ("bv %%r0(%0)\n" - "nop\n" - ".global exec_loop\n" - "exec_loop:\n" - : /* no outputs */ - : "r" (gen_func) - : "r1", "r20", "r21", "r22", "r23", - "r24", "r25", "r27", "r28"); #elif defined(__ia64) struct fptr { void *ip; @@ -1552,24 +1543,6 @@ is_write, &uc->uc_sigmask, puc); } -#elif defined(__hppa__) - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - struct siginfo *info = pinfo; - struct ucontext *uc = puc; - unsigned long pc; - int is_write; - - pc = uc->uc_mcontext.sc_iaoq[0]; - /* FIXME: compute is_write */ - is_write = 0; - return handle_cpu_signal(pc, (unsigned long)info->si_addr, - is_write, - &uc->uc_sigmask, puc); -} - #else #error host CPU specific signal handler needed Index: exec.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/exec.c,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- exec.c 18 Feb 2008 05:24:38 -0000 1.5 +++ exec.c 29 Feb 2008 01:47:58 -0000 1.6 @@ -78,10 +78,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif -#ifdef __hppa__ -unsigned int hppa_lock[4] = {1, 1, 1, 1}; -#endif - TranslationBlock tbs[CODE_GEN_MAX_BLOCKS]; TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; int nb_tbs; Index: Makefile.target =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/Makefile.target,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- Makefile.target 18 Feb 2008 05:24:35 -0000 1.8 +++ Makefile.target 29 Feb 2008 01:47:57 -0000 1.9 @@ -181,11 +181,6 @@ BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld endif -ifeq ($(ARCH),hppa) -OP_CFLAGS=-O1 -fno-delayed-branch -BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld -endif - ifeq ($(ARCH),ia64) BASE_CFLAGS+=-mno-sdata OP_CFLAGS+=-mno-sdata Index: exec-all.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/exec-all.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- exec-all.h 18 Feb 2008 05:24:38 -0000 1.6 +++ exec-all.h 29 Feb 2008 01:47:58 -0000 1.7 @@ -326,10 +326,10 @@ cache flushing, but slower because of indirect jump) */ #define GOTO_TB(opname, tbparam, n)\ do {\ - static volatile void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\ - static volatile void __attribute__((used)) *__op_label ## n \ + static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\ + static void __attribute__((used)) *__op_label ## n \ __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ - goto *(void *)(((volatile TranslationBlock *)tbparam)->tb_next[n]);\ + goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ label ## n: ;\ dummy_label ## n: ;\ } while (0) @@ -439,50 +439,6 @@ : "cc","memory"); return ret; } -#elif defined(__hppa__) - -#if 0 -#define __ldcw(a) ({ \ - unsigned __ret; \ - __asm__ __volatile__("ldcw 0(%1),%0" \ - : "=r" (__ret) : "r" (a)); \ - __ret; \ -}) - -#define __PA_LDCW_ALIGNMENT 16 -#define __ldcw_align(a) ({ \ - unsigned long __ret = (unsigned long) &(a); \ - __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \ - & ~(__PA_LDCW_ALIGNMENT - 1); \ - (volatile unsigned int *) __ret; \ -}) - -static inline int testandset (int *p) -{ - extern unsigned int hppa_lock[4]; - volatile unsigned int *lock = __ldcw_align(hppa_lock[0]); - int old; - - while (__ldcw(lock)) - while (__ldcw(lock)) - /* spin */; - - old = *p; - *p = 1; - - *lock = 1; - - return old != 0; -} -#endif -static inline int testandset (int *p) -{ - int old; - old = *p; - *p = 1; - return old != 0; -} - #elif defined(__ia64) #include <ia64intrin.h> Index: disas.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/disas.c,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- disas.c 18 Feb 2008 05:24:38 -0000 1.6 +++ disas.c 29 Feb 2008 01:47:57 -0000 1.7 @@ -282,8 +282,6 @@ print_insn = print_insn_m68k; #elif defined(__s390__) print_insn = print_insn_s390; -#elif defined(__hppa__) - print_insn = print_insn_hppa; #else fprintf(out, "0x%lx: Asm output not supported on this arch\n", (long) code); Index: cpu-all.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/cpu-all.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- cpu-all.h 18 Feb 2008 05:24:38 -0000 1.6 +++ cpu-all.h 29 Feb 2008 01:47:57 -0000 1.7 @@ -947,15 +947,6 @@ return val; } -#elif defined(__hppa__) - -static inline int64_t cpu_get_real_ticks(void) -{ - int val; - asm volatile ("mfctl %%cr16, %0" : "=r"(val)); - return val; -} - #elif defined(__ia64) static inline int64_t cpu_get_real_ticks(void) |
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From: Stuart B. <zu...@us...> - 2008-02-29 01:30:27
|
Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv29303/target-hppa Modified Files: translate.c Log Message: Revert previous commit. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.53 retrieving revision 1.54 diff -u -d -r1.53 -r1.54 --- translate.c 27 Feb 2008 20:43:59 -0000 1.53 +++ translate.c 29 Feb 2008 01:30:21 -0000 1.54 @@ -907,9 +907,6 @@ tb->size = last_pc + 4 - pc_start; } #ifdef DEBUG_DISAS - if (loglevel & CPU_LOG_TB_CPU) { - cpu_dump_state(env, logfile, fprintf, 0); - } if (loglevel & CPU_LOG_TB_IN_ASM) { fprintf(logfile, "--------------\n"); fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); |
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From: Stuart B. <zu...@us...> - 2008-02-27 20:44:07
|
Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv1397 Modified Files: translate.c Log Message: Add support for the -d cpu option, by Aurelien Jarno. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.52 retrieving revision 1.53 diff -u -d -r1.52 -r1.53 --- translate.c 27 Feb 2008 15:12:09 -0000 1.52 +++ translate.c 27 Feb 2008 20:43:59 -0000 1.53 @@ -907,6 +907,9 @@ tb->size = last_pc + 4 - pc_start; } #ifdef DEBUG_DISAS + if (loglevel & CPU_LOG_TB_CPU) { + cpu_dump_state(env, logfile, fprintf, 0); + } if (loglevel & CPU_LOG_TB_IN_ASM) { fprintf(logfile, "--------------\n"); fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); |
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From: Stuart B. <zu...@us...> - 2008-02-27 15:12:16
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv23612 Modified Files: translate.c Log Message: Fix single stepping for most instructions -- still not fixed for branches. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.51 retrieving revision 1.52 diff -u -d -r1.51 -r1.52 --- translate.c 23 Feb 2008 20:57:32 -0000 1.51 +++ translate.c 27 Feb 2008 15:12:09 -0000 1.52 @@ -840,8 +840,10 @@ if (env->nb_breakpoints > 0) { for (j = 0; j < env->nb_breakpoints; j++) { if (env->breakpoints[j] == dc->iaoq[0]) { - save_state(dc); + gen_op_save_pc(dc->iaoq[0], dc->iaoq[1]); + gen_op_movl_T0_im(0); gen_op_debug(); + gen_op_exit_tb(); dc->is_br = 1; goto exit_gen_loop; } @@ -874,12 +876,13 @@ break; } if (env->singlestep_enabled) { - save_state(dc); + gen_op_save_pc(dc->iaoq[0], dc->iaoq[1]); + gen_movl_T0_im(0); gen_op_debug(); - goto exit_gen_loop; + gen_op_exit_tb(); } else if (!dc->is_br) { - save_state(dc); - gen_goto_tb(dc, 0, dc->iaoq[0], dc->iaoq[1]); + gen_op_save_pc(dc->iaoq[0], dc->iaoq[1]); + gen_movl_T0_im(0); gen_op_exit_tb(); } |
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From: Stuart B. <zu...@us...> - 2008-02-23 21:50:44
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv2258 Modified Files: op.c Log Message: Remove op_add_T1_T0(). Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.32 retrieving revision 1.33 diff -u -d -r1.32 -r1.33 --- op.c 22 Feb 2008 21:11:57 -0000 1.32 +++ op.c 23 Feb 2008 21:50:40 -0000 1.33 @@ -446,11 +446,6 @@ env->psw |= carry << PSW_CB_SHIFT; } -void OPPROTO op_add_T1_T0(void) -{ - T0 += T1; -} - /* TODO: lazy PSW */ void OPPROTO op_addc_T1_T0_cc(void) { |
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From: Stuart B. <zu...@us...> - 2008-02-23 20:57:36
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv12782 Modified Files: translate.c Log Message: Compilation fix. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.50 retrieving revision 1.51 diff -u -d -r1.50 -r1.51 --- translate.c 23 Feb 2008 14:29:23 -0000 1.50 +++ translate.c 23 Feb 2008 20:57:32 -0000 1.51 @@ -669,7 +669,7 @@ } static void gen_branch(DisasContext *dc, long tb, -static void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc) + target_ulong pc, target_ulong npc) { gen_goto_tb(dc, tb, pc, npc); } |
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From: Stuart B. <zu...@us...> - 2008-02-23 16:44:30
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Update of /cvsroot/hppaqemu/hppaqemu/linux-user In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv9809 Modified Files: elfload.c Log Message: Store argc in gr25, argv in gr24 and the entry point in gr31. Index: elfload.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/linux-user/elfload.c,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- elfload.c 18 Feb 2008 05:24:48 -0000 1.6 +++ elfload.c 23 Feb 2008 16:44:14 -0000 1.7 @@ -465,9 +465,15 @@ static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) { - regs->iaoq[0] = infop->entry; - regs->iaoq[1]= regs->iaoq[0] + 4; - regs->gr[30] = infop->start_stack ; + abi_ulong stack = infop->start_stack; + abi_ulong entry = infop->entry; + + regs->iaoq[0] = entry; + regs->iaoq[1] = entry + 4; + get_user_ual(regs->gr[25], stack); /* argc */ + get_user_ual(regs->gr[24], stack + 4); /* argv */ + regs->gr[30] = stack; + regs->gr[31] = entry; } #endif |
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From: Stuart B. <zu...@us...> - 2008-02-23 14:29:27
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv21684 Modified Files: translate.c Log Message: Coding style fixes. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.49 retrieving revision 1.50 diff -u -d -r1.49 -r1.50 --- translate.c 23 Feb 2008 01:33:59 -0000 1.49 +++ translate.c 23 Feb 2008 14:29:23 -0000 1.50 @@ -64,13 +64,15 @@ static void disas_hppa_insn(DisasContext * dc); -static uint32_t field(uint32_t val, int start, int length) { +static uint32_t field(uint32_t val, int start, int length) +{ val >>= start; val &= ~(~0 << length); return val; } -static int32_t field_signext(uint32_t val, int start, int length) { +static int32_t field_signext(uint32_t val, int start, int length) +{ val >>= start; if (val & (1 << (length - 1))) val |= ~0 << length; @@ -79,7 +81,8 @@ return val; } -static int32_t field_lowsignext(uint32_t val, int start, int length) { +static int32_t field_lowsignext(uint32_t val, int start, int length) +{ if (val & (1 << start)) { val >>= start + 1; val |= ~0 << (length - 1); @@ -90,21 +93,25 @@ return val; } -static int32_t signext(uint32_t val, int length) { +static int32_t signext(uint32_t val, int length) +{ if (val & (1 << (length - 1))) val |= ~0 << length; return val; } -static uint32_t assemble_12(uint32_t x, uint32_t y) { +static uint32_t assemble_12(uint32_t x, uint32_t y) +{ return (y << 11) | ((x & 1) << 10) | ((x >> 1) & ~(~0 << 10)); } -static uint32_t assemble_17(uint32_t x, uint32_t y, uint32_t z) { +static uint32_t assemble_17(uint32_t x, uint32_t y, uint32_t z) +{ return (z << 16) | (x << 11) | ((y & 1) << 10) | ((y >> 1) & ~(~0 << 10)); } -static uint32_t assemble_21(uint32_t x) { +static uint32_t assemble_21(uint32_t x) +{ return ((x & 1) << 20) | (((x >> 1) & ~(~0 << 11)) << 9) | (((x >> 14) & ~(~0 << 2)) << 7) | @@ -539,7 +546,7 @@ /* General registers */ static void gen_movl_reg_TN(int reg, int t) { - gen_op_movl_reg_TN[t][reg] (); + gen_op_movl_reg_TN[t][reg](); } static void gen_movl_reg_T0(int reg) @@ -559,7 +566,7 @@ static void gen_movl_TN_reg(int reg, int t) { - gen_op_movl_TN_reg[t][reg] (); + gen_op_movl_TN_reg[t][reg](); } static void gen_movl_T0_reg(int reg) @@ -661,6 +668,7 @@ } } +static void gen_branch(DisasContext *dc, long tb, static void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc) { gen_goto_tb(dc, tb, pc, npc); @@ -750,7 +758,8 @@ gen_op_eval_log_ev, }; -static void gen_branch_cond(DisasContext *dc, long tb, target_ulong disp, int n, int f) +static void gen_branch_cond(DisasContext *dc, long tb, target_ulong disp, + int n, int f) { int l1; target_ulong target; @@ -807,8 +816,8 @@ } static int gen_intermediate_code_internal(CPUState *env, - TranslationBlock *tb, - int search_pc) + TranslationBlock *tb, + int search_pc) { target_ulong pc_start, last_pc; uint16_t *gen_opc_end; @@ -827,10 +836,9 @@ gen_opparam_ptr = gen_opparam_buf; nb_gen_labels = 0; - while (!dc->is_br && gen_opc_ptr < gen_opc_end) - { + while (!dc->is_br && gen_opc_ptr < gen_opc_end) { if (env->nb_breakpoints > 0) { - for(j = 0; j < env->nb_breakpoints; j++) { + for (j = 0; j < env->nb_breakpoints; j++) { if (env->breakpoints[j] == dc->iaoq[0]) { save_state(dc); gen_op_debug(); @@ -865,14 +873,11 @@ if (env->singlestep_enabled) break; } - if (env->singlestep_enabled) - { + if (env->singlestep_enabled) { save_state(dc); gen_op_debug(); goto exit_gen_loop; - } - else if (!dc->is_br) - { + } else if (!dc->is_br) { save_state(dc); gen_goto_tb(dc, 0, dc->iaoq[0], dc->iaoq[1]); gen_op_exit_tb(); @@ -934,8 +939,7 @@ static int get_ldst_cmplt(uint32_t insn) { int indexed_load = (field(insn, 12, 1) == 0); - if (indexed_load) - { + if (indexed_load) { int u = field(insn, 13, 1); int m = field(insn, 5, 1); @@ -947,9 +951,7 @@ return LDST_CMPLT_S; else if (u == 1 && m == 1) return LDST_CMPLT_SM; - } - else - { + } else { int a = field(insn, 13, 1); int m = field(insn, 5, 1); uint32_t ext4 = field(insn, 6, 4); @@ -978,11 +980,9 @@ /* load value at address T0 to T1 */ - if (indexed_load) - { + if (indexed_load) { int x = field(insn, 16, 5); - switch (cmplt) - { + switch (cmplt) { case LDST_CMPLT_S: case LDST_CMPLT_SM: gen_movl_T0_reg(x); @@ -993,15 +993,12 @@ gen_movl_T0_reg(x); break; } - } - else - { + } else { target_long im5 = field_lowsignext(insn, 16, 5); gen_movl_T0_im(im5); } - switch (cmplt) - { + switch (cmplt) { case LDST_CMPLT_MB: /* dx in T0 */ gen_movl_T1_reg(b); @@ -1041,8 +1038,7 @@ /* store T1 at address T0 */ gen_movl_T0_im(im5); - switch (cmplt) - { + switch (cmplt) { case LDST_CMPLT_MB: gen_movl_T1_reg(b); gen_op_copy_T2_T0(); /* T2 = dx */ @@ -1143,12 +1139,12 @@ */ /* Major Opcodes */ - switch(op) { + switch (op) { case 0x00: /* System_op */ { int ext8; ext8 = field(insn, 5, 6); - switch(ext8) { + switch (ext8) { case 0x00: /* BREAK */ gen_op_break(); break; @@ -1232,8 +1228,7 @@ break; if (t != 11) gen_op_check_priv0(); - switch (t) - { + switch (t) { case 0: /* recovery counter */ /* TODO: mask 32-bits for 64-bit op */ case 14: @@ -1296,19 +1291,14 @@ if (r == 16) /* interval timer */ gen_op_check_int_timer_priv(); - if ((r >= 17 && r <= 22) || (r == 0)) - { + if ((r >= 17 && r <= 22) || (r == 0)) { gen_movl_T0_cr(r); gen_movl_reg_T0(t); - } - else if (r == 11) /* SAR */ - { + } else if (r == 11) { /* SAR */ /* Check - may need to mask and shift */ gen_movl_T0_cr(r); gen_movl_reg_T0(t); - } - else if (r >= 8) - { + } else if (r >= 8) { gen_movl_T0_cr(r); gen_movl_reg_T0(t); } @@ -1326,11 +1316,10 @@ { int ext5; ext5 = field(insn, 0, 5); - if(!field(insn, 12, 1)) { + if (!field(insn, 12, 1)) { int ext7; ext7 = field(insn, 6, 7); - switch(ext7) - { + switch (ext7) { case 0x08: /* PITLB */ case 0x09: /* PITLBE */ case 0x0a: /* FIC,0A (FIC) */ @@ -1352,8 +1341,7 @@ int ext8; ext8 = field(insn, 6, 8); - switch (ext8) - { + switch (ext8) { case 0x48: /* PDTLB */ case 0x49: /* PDTLBE */ case 0x4a: /* FDC (index) */ @@ -1396,7 +1384,7 @@ gen_movl_T1_reg(r2); /* Opcode Extensions */ - switch(ext6) { + switch (ext6) { case 0x18: /* ADD */ if (c || f) gen_cond_add[c](); @@ -1619,7 +1607,7 @@ case 0x03: /* Index_Mem */ { int ext4 = field(insn, 6, 4); - switch(ext4) { + switch (ext4) { /* XXX: gen_op_*_raw only works for user-mode emulation * we really need gen_load and gen_store to be macros * to allow _phys and _virtual to be used @@ -1686,7 +1674,7 @@ int t; target_ulong im21; t = field(insn, 21, 5); - if(t) { + if (t) { im21 = assemble_21(field(insn, 0, 21)) << (32 - 21); gen_movl_T0_im(im21); gen_movl_reg_T0(t); @@ -1695,13 +1683,13 @@ } case 0x09: /* Copr_w */ - if(!field(insn, 12, 1)) - if(!field(insn, 9, 1)) + if (!field(insn, 12, 1)) + if (!field(insn, 9, 1)) /* CLDW (index) (CLDWX) */ {} else /* CSTW (index) (CSTWX) */ {} else - if(!field(insn, 9, 1)) + if (!field(insn, 9, 1)) /* CLDW (short) (CLDWS) */ {} else /* CSTW (short) (CSTWS) */ {} @@ -1721,13 +1709,13 @@ } case 0x0b: /* Copr_dw */ - if(!field(insn, 12, 1)) - if(!field(insn, 9, 1)) + if (!field(insn, 12, 1)) + if (!field(insn, 9, 1)) /* CLDD (index) (CLDDX) */ {} else /* CSTD (index) (CLTDX) */ {} else - if(!field(insn, 9, 1)) + if (!field(insn, 9, 1)) /* CLDD (short) (CLDDS) */ {} else /* CSTD (short) (CSTDS) */ {} @@ -1769,7 +1757,7 @@ /* gen_op_space_sel_T0_T1(); */ gen_movl_T1_im(im14); gen_op_addl_T1_T0(); - switch(op) { + switch (op) { case 0x10: /* LDB */ gen_op_ldst(ldb); break; @@ -1796,13 +1784,13 @@ /* gen_movl_T1_im(s); */ /* gen_op_space_sel_T0_T1(); */ /* XXX: check this */ - if(im14 & (1 << 31)) { + if (im14 & (1 << 31)) { gen_movl_T1_im(im14); gen_op_addl_T1_T0(); } gen_op_ldst(ldw); gen_movl_reg_T1(t); - if(!(im14 & (1 << 31))) { + if (!(im14 & (1 << 31))) { gen_movl_T1_im(im14); gen_op_addl_T1_T0(); } @@ -1836,7 +1824,7 @@ gen_movl_T1_im(im14); gen_op_addl_T1_T0(); gen_movl_T1_reg(r); - switch(op) { + switch (op) { case 0x18: /* STB */ gen_op_ldst(stb); break; @@ -1862,13 +1850,13 @@ /* gen_movl_T1_im(s); */ /* gen_op_space_sel_T0_T1(); */ /* XXX: check this */ - if(im14 & (1 << 31)) { + if (im14 & (1 << 31)) { gen_movl_T1_im(im14); gen_op_addl_T1_T0(); } gen_movl_T1_reg(r); gen_op_ldst(stw); - if(!(im14 & (1 << 31))) { + if (!(im14 & (1 << 31))) { gen_movl_T1_im(im14); gen_op_addl_T1_T0(); } @@ -1893,7 +1881,7 @@ { int f, c, w1, n, w; target_long disp; - switch(op) { + switch (op) { case 0x20: /* CMPB (true) (COMBT) */ case 0x22: /* CMPB (false) (COMBF) */ { @@ -1994,7 +1982,7 @@ { int f, c, w1, n, w; target_long disp; - switch(op) { + switch (op) { case 0x28: /* ADDB (true) (ADDBT) */ case 0x2a: /* ADDB (false) (ADDBF) */ { @@ -2080,7 +2068,7 @@ { int ext3; ext3 = field(insn, 10, 3); - switch(ext3) { + switch (ext3) { case 0: /* VSHD = SHRPW with SAR */ gen_movl_T0_cr(11); gen_shrpw(insn); @@ -2113,7 +2101,7 @@ { int ext3; ext3 = field(insn, 10, 3); - switch(ext3) { + switch (ext3) { case 0: /* VZDEP = DEPW,Z with SAR */ case 1: /* VDEP = DEPW with SAR */ gen_movl_T0_cr(11); @@ -2179,7 +2167,7 @@ n = field(insn, 1, 1); w = field(insn, 0, 1); disp = signext(assemble_17(w1,w2,w),17) << 2; - switch(ext3) { + switch (ext3) { case 0: /* B,L (BL) */ /* TODO: dc->iaoq[1] + 4 into t */ if (n) { @@ -2248,7 +2236,7 @@ int i; cpu_fprintf(f, "PSW = %08X\n", env->psw); - for(i=0;i<31;i++) { + for (i=0; i<31; i++) { cpu_fprintf(f, "R%02d=%08x", i, env->gr[i]); if ((i % 4) == 3) cpu_fprintf(f, "\n"); @@ -2256,7 +2244,7 @@ cpu_fprintf(f, " "); } - for(i=0;i<31;i++) { + for (i=0; i<31; i++) { cpu_fprintf(f, "CR%02d=%08x", i, env->cr[i]); if ((i % 4) == 3) cpu_fprintf(f, "\n"); |
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From: Stuart B. <zu...@us...> - 2008-02-23 01:34:06
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv5013 Modified Files: translate.c Log Message: List MAX-1 instruction names where applicable. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.48 retrieving revision 1.49 diff -u -d -r1.48 -r1.49 --- translate.c 22 Feb 2008 21:40:06 -0000 1.48 +++ translate.c 23 Feb 2008 01:33:59 -0000 1.49 @@ -1589,21 +1589,21 @@ gen_op_idcor_T0(); } break; - /* FIXME: include MAX-1 (see PA7300LC ERS) */ #ifdef TARGET_HPPA64 + /* Also included in MAX-1 (PA-7100LC and PA-7300LC) */ case 0x0f: /* HADD */ case 0x0d: /* HADD,SS */ case 0x0c: /* HADD,US */ case 0x07: /* HSUB */ case 0x05: /* HSUB,SS */ case 0x04: /* HSUB,US */ - case 0x0b: /* HAVG */ - case 0x1d: /* HSHLADD (1) */ - case 0x1e: /* HSHLADD (2) */ - case 0x1f: /* HSHLADD (3) */ - case 0x15: /* HSHRADD (1) */ - case 0x16: /* HSHRADD (2) */ - case 0x17: /* HSHRADD (3) */ + case 0x0b: /* HAVG (HAVE) */ + case 0x1d: /* HSHLADD (1) (HSL1ADD) */ + case 0x1e: /* HSHLADD (2) (HSL2ADD) */ + case 0x1f: /* HSHLADD (3) (HSL3ADD) */ + case 0x15: /* HSHRADD (1) (HSR1ADD) */ + case 0x16: /* HSHRADD (2) (HSR2ADD) */ + case 0x17: /* HSHRADD (3) (HSR3ADD) */ break; #endif default: /* Undefined Instruction */ @@ -2208,7 +2208,7 @@ case 0x3d: /* DEPI */ break; - case 0x3e: /* Multimedia */ + case 0x3e: /* Multimedia (MAX-2) */ /* PERMH */ /* HSHL */ /* HSHR,U */ |
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From: Stuart B. <zu...@us...> - 2008-02-22 21:40:11
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv4909 Modified Files: translate.c Log Message: Replace last remaining use of gen_op_add_T1_T0() with gen_op_addl_T1_T0(). Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.47 retrieving revision 1.48 diff -u -d -r1.47 -r1.48 --- translate.c 22 Feb 2008 21:32:48 -0000 1.47 +++ translate.c 22 Feb 2008 21:40:06 -0000 1.48 @@ -1768,7 +1768,7 @@ gen_movl_T1_im(s); /* gen_op_space_sel_T0_T1(); */ gen_movl_T1_im(im14); - gen_op_add_T1_T0(); + gen_op_addl_T1_T0(); switch(op) { case 0x10: /* LDB */ gen_op_ldst(ldb); |
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From: Stuart B. <zu...@us...> - 2008-02-22 21:32:53
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv2082 Modified Files: translate.c Log Message: List CMPIB (dw) as PA2.0-specific. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.46 retrieving revision 1.47 diff -u -d -r1.46 -r1.47 --- translate.c 22 Feb 2008 20:56:52 -0000 1.46 +++ translate.c 22 Feb 2008 21:32:48 -0000 1.47 @@ -2200,10 +2200,10 @@ break; } +#ifdef TARGET_HPPA64 case 0x3b: /* CMPIB (dw) */ break; -#ifdef TARGET_HPPA64 case 0x3c: /* DEPD */ case 0x3d: /* DEPI */ break; |
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From: Stuart B. <zu...@us...> - 2008-02-22 21:12:04
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv26064 Modified Files: op.c Log Message: Use target_long/target_ulong for condition evaluation operations. Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.31 retrieving revision 1.32 diff -u -d -r1.31 -r1.32 --- op.c 20 Apr 2007 15:08:05 -0000 1.31 +++ op.c 22 Feb 2008 21:11:57 -0000 1.32 @@ -767,49 +767,49 @@ /* = */ void OPPROTO op_eval_add_eq(void) { - uint32_t res = T0 + T1; + target_ulong res = T0 + T1; T2 = (res == 0); } /* < */ void OPPROTO op_eval_add_slt(void) { - int32_t res = T0 + T1; + target_long res = T0 + T1; T2 = ((res < 0) != signed_overflow_add(T0, T1, res)); } /* <= */ void OPPROTO op_eval_add_slteq(void) { - int32_t res = T0 + T1; + target_long res = T0 + T1; T2 = ((res == 0) || ((res < 0) != signed_overflow_add(T0, T1, res))); } /* nuv */ void OPPROTO op_eval_add_nuv(void) { - uint32_t res = T0 + T1; + target_ulong res = T0 + T1; T2 = (res >= T0); } /* znv */ void OPPROTO op_eval_add_znv(void) { - uint32_t res = T0 + T1; + target_ulong res = T0 + T1; T2 = ((res == 0) || (res >= T0)); } /* sv */ void OPPROTO op_eval_add_sv(void) { - int32_t res = T0 + T1; + target_long res = T0 + T1; T2 = signed_overflow_add(T0, T1, res); } /* od */ void OPPROTO op_eval_add_od(void) { - uint32_t res = T0 + T1; + target_ulong res = T0 + T1; T2 = (res & 1); } @@ -818,28 +818,28 @@ /* = */ void OPPROTO op_eval_addc_eq(void) { - uint32_t res = T0 + T1 + !!(env->psw & PSW_CB7); + target_ulong res = T0 + T1 + !!(env->psw & PSW_CB7); T2 = (res == 0); } /* < */ void OPPROTO op_eval_addc_slt(void) { - int32_t res = T0 + T1 + !!(env->psw & PSW_CB7); + target_long res = T0 + T1 + !!(env->psw & PSW_CB7); T2 = ((res < 0) != signed_overflow_add(T0, T1, res)); } /* <= */ void OPPROTO op_eval_addc_slteq(void) { - int32_t res = T0 + T1 + !!(env->psw & PSW_CB7); + target_long res = T0 + T1 + !!(env->psw & PSW_CB7); T2 = ((res == 0) || ((res < 0) != signed_overflow_add(T0, T1, res))); } /* nuv */ void OPPROTO op_eval_addc_nuv(void) { - uint32_t res = T0 + T1 + !!(env->psw & PSW_CB7); + target_ulong res = T0 + T1 + !!(env->psw & PSW_CB7); if (env->psw & PSW_CB7) T2 = (res > T0); else @@ -850,7 +850,7 @@ /* znv */ void OPPROTO op_eval_addc_znv(void) { - uint32_t res = T0 + T1 + !!(env->psw & PSW_CB7); + target_ulong res = T0 + T1 + !!(env->psw & PSW_CB7); if (env->psw & PSW_CB7) T2 = ((res == 0) || (res > T0)); else @@ -861,14 +861,14 @@ /* sv */ void OPPROTO op_eval_addc_sv(void) { - int32_t res = T0 + T1 + !!(env->psw & PSW_CB7); + target_long res = T0 + T1 + !!(env->psw & PSW_CB7); T2 = signed_overflow_add(T0, T1, res); } /* od */ void OPPROTO op_eval_addc_od(void) { - uint32_t res = T0 + T1 + !!(env->psw & PSW_CB7); + target_ulong res = T0 + T1 + !!(env->psw & PSW_CB7); T2 = (res & 1); } @@ -879,49 +879,49 @@ /* = */ void OPPROTO op_eval_sub_eq(void) { - uint32_t res = T0 - T1; + target_ulong res = T0 - T1; T2 = (res == 0); } /* < */ void OPPROTO op_eval_sub_slt(void) { - int32_t res = T0 - T1; + target_long res = T0 - T1; T2 = ((res < 0) != signed_overflow_sub(T0, T1, res)); } /* <= */ void OPPROTO op_eval_sub_slteq(void) { - int32_t res = T0 - T1; + target_long res = T0 - T1; T2 = ((res == 0) || ((res < 0) != signed_overflow_sub(T0, T1, res))); } /* << */ void OPPROTO op_eval_sub_ult(void) { - uint32_t res = T0 - T1; + target_ulong res = T0 - T1; T2 = (res < 0); } /* <<= */ void OPPROTO op_eval_sub_ulteq(void) { - uint32_t res = T0 - T1; + target_ulong res = T0 - T1; T2 = ((res == 0) || (res < T0)); } /* sv */ void OPPROTO op_eval_sub_sv(void) { - int32_t res = T0 - T1; + target_long res = T0 - T1; T2 = signed_overflow_sub(T0, T1, res); } /* od */ void OPPROTO op_eval_sub_od(void) { - int32_t res = T0 - T1; + target_long res = T0 - T1; T2 = (res & 1); } @@ -930,49 +930,49 @@ /* = */ void OPPROTO op_eval_subb_eq(void) { - uint32_t res = T0 - T1 - !(env->psw & PSW_CB7); + target_ulong res = T0 - T1 - !(env->psw & PSW_CB7); T2 = (res == 0); } /* < */ void OPPROTO op_eval_subb_slt(void) { - int32_t res = T0 - T1 - !(env->psw & PSW_CB7); + target_long res = T0 - T1 - !(env->psw & PSW_CB7); T2 = ((res < 0) != signed_overflow_sub(T0, T1, res)); } /* <= */ void OPPROTO op_eval_subb_slteq(void) { - int32_t res = T0 - T1 - !(env->psw & PSW_CB7); + target_long res = T0 - T1 - !(env->psw & PSW_CB7); T2 = ((res == 0) || ((res < 0) != signed_overflow_sub(T0, T1, res))); } /* << */ void OPPROTO op_eval_subb_ult(void) { - uint32_t res = T0 - T1 - !(env->psw & PSW_CB7); + target_ulong res = T0 - T1 - !(env->psw & PSW_CB7); T2 = (res < 0); } /* <<= */ void OPPROTO op_eval_subb_ulteq(void) { - uint32_t res = T0 - T1 - !(env->psw & PSW_CB7); + target_ulong res = T0 - T1 - !(env->psw & PSW_CB7); T2 = ((res == 0) || (res < T0)); } /* sv */ void OPPROTO op_eval_subb_sv(void) { - int32_t res = T0 - T1 - !(env->psw & PSW_CB7); + target_long res = T0 - T1 - !(env->psw & PSW_CB7); T2 = signed_overflow_sub(T0, T1, res); } /* od */ void OPPROTO op_eval_subb_od(void) { - int32_t res = T0 - T1 - !(env->psw & PSW_CB7); + target_long res = T0 - T1 - !(env->psw & PSW_CB7); T2 = (res & 1); } @@ -989,13 +989,13 @@ /* < */ void OPPROTO op_eval_log_slt(void) { - T2 = ((int32_t)T0 < 0); + T2 = ((target_long)T0 < 0); } /* <= */ void OPPROTO op_eval_log_slteq(void) { - T2 = ((int32_t)T1 <= 0); + T2 = ((target_long)T1 <= 0); } /* od */ @@ -1046,7 +1046,7 @@ /* >= */ void OPPROTO op_eval_log_sgteq(void) { - T2 = ((int32_t)T0 >= 0); + T2 = ((target_long)T0 >= 0); } /* ev */ |
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From: Stuart B. <zu...@us...> - 2008-02-22 20:56:56
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs17.sourceforge.net:/tmp/cvs-serv15079 Modified Files: translate.c Log Message: Use target_long and target_ulong immediate fields and displacements, make *signext() return signed 32-bit ints, and use plain ints for register numbers, spaceids, conditions, shift positions, opcodes, etc. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.45 retrieving revision 1.46 diff -u -d -r1.45 -r1.46 --- translate.c 22 Feb 2008 20:18:58 -0000 1.45 +++ translate.c 22 Feb 2008 20:56:52 -0000 1.46 @@ -70,7 +70,7 @@ return val; } -static uint32_t field_signext(uint32_t val, int start, int length) { +static int32_t field_signext(uint32_t val, int start, int length) { val >>= start; if (val & (1 << (length - 1))) val |= ~0 << length; @@ -79,7 +79,7 @@ return val; } -static uint32_t field_lowsignext(uint32_t val, int start, int length) { +static int32_t field_lowsignext(uint32_t val, int start, int length) { if (val & (1 << start)) { val >>= start + 1; val |= ~0 << (length - 1); @@ -90,7 +90,7 @@ return val; } -static uint32_t signext(uint32_t val, int length) { +static int32_t signext(uint32_t val, int length) { if (val & (1 << (length - 1))) val |= ~0 << length; return val; @@ -514,22 +514,22 @@ gen_op_movl_T2_im, }; -static void gen_movl_TN_im(int reg, int val) +static void gen_movl_TN_im(int reg, target_ulong val) { gen_op_movl_TN_im[reg](val); } -static void gen_movl_T0_im(int val) +static void gen_movl_T0_im(target_ulong val) { gen_movl_TN_im(0, val); } -static void gen_movl_T1_im(int val) +static void gen_movl_T1_im(target_ulong val) { gen_movl_TN_im(1, val); } -static void gen_movl_T2_im(int val) +static void gen_movl_T2_im(target_ulong val) { gen_movl_TN_im(2, val); } @@ -953,7 +953,7 @@ int a = field(insn, 13, 1); int m = field(insn, 5, 1); uint32_t ext4 = field(insn, 6, 4); - uint32_t im5; + target_long im5; if (ext4 <= 7) /* load */ im5 = field_signext(insn, 16, 5); else /* store */ @@ -973,14 +973,14 @@ { int indexed_load = (field(insn, 12, 1) == 0); int cmplt = get_ldst_cmplt(insn); - uint32_t b = field(insn, 21, 5); - uint32_t t = field(insn, 0, 5); + int b = field(insn, 21, 5); + int t = field(insn, 0, 5); /* load value at address T0 to T1 */ if (indexed_load) { - uint32_t x = field(insn, 16, 5); + int x = field(insn, 16, 5); switch (cmplt) { case LDST_CMPLT_S: @@ -996,7 +996,7 @@ } else { - uint32_t im5 = field_lowsignext(insn, 16, 5); + target_long im5 = field_lowsignext(insn, 16, 5); gen_movl_T0_im(im5); } @@ -1033,9 +1033,9 @@ static void gen_store(uint32_t insn, GenOpFunc *op) { - uint32_t im5 = field_lowsignext(insn, 0, 5); - uint32_t r = field(insn, 16, 5); - uint32_t b = field(insn, 21, 5); + target_long im5 = field_lowsignext(insn, 0, 5); + int r = field(insn, 16, 5); + int b = field(insn, 21, 5); int cmplt = get_ldst_cmplt(insn); /* store T1 at address T0 */ @@ -1069,9 +1069,9 @@ static void gen_shrpw(uint32_t insn) { - uint32_t r1 = field(insn, 16, 5); - uint32_t r2 = field(insn, 21, 5); - uint32_t t = field(insn, 0, 5); + int r1 = field(insn, 16, 5); + int r2 = field(insn, 21, 5); + int t = field(insn, 0, 5); gen_movl_T1_reg(r1); gen_movl_T2_reg(r2); @@ -1081,9 +1081,9 @@ static void gen_extrw(uint32_t insn) { - uint32_t r = field(insn, 21, 5); - uint32_t t = field(insn, 16, 5); - uint32_t clen = 32 - field(insn, 0, 5); + int r = field(insn, 21, 5); + int t = field(insn, 16, 5); + int clen = 32 - field(insn, 0, 5); int se = field(insn, 10, 1); gen_movl_T1_im(clen); @@ -1094,9 +1094,9 @@ static void gen_depw(uint32_t insn) { - uint32_t t = field(insn, 21, 5); - uint32_t r = field(insn, 16, 5); - uint32_t clen = 32 - field(insn, 0, 5); + int t = field(insn, 21, 5); + int r = field(insn, 16, 5); + int clen = 32 - field(insn, 0, 5); int nz = field(insn, 10, 1); gen_movl_T1_im(clen); @@ -1107,9 +1107,9 @@ static void gen_depwi(uint32_t insn) { - uint32_t t = field(insn, 21, 5); - uint32_t im5 = field_signext(insn, 16, 5); - uint32_t clen = 32 - field(insn, 0, 5); + int t = field(insn, 21, 5); + target_long im5 = field_signext(insn, 16, 5); + int clen = 32 - field(insn, 0, 5); int nz = field(insn, 10, 1); gen_movl_T1_im(clen); @@ -1120,7 +1120,7 @@ static void disas_hppa_insn(DisasContext * dc) { - unsigned int insn; + uint32_t insn; int op; int ext6; @@ -1146,7 +1146,7 @@ switch(op) { case 0x00: /* System_op */ { - uint32_t ext8; + int ext8; ext8 = field(insn, 5, 6); switch(ext8) { case 0x00: /* BREAK */ @@ -1191,7 +1191,7 @@ case 0x85: /* LDSID */ { - uint32_t s, b, t; + int s, b, t; s = field(insn, 14, 2); b = field(insn, 21, 5); t = field(insn, 0, 5); @@ -1200,8 +1200,8 @@ case 0xc1: /* MTSP */ { - uint32_t sr = field(insn, 13, 3); - uint32_t r = field(insn, 16, 5); + int sr = field(insn, 13, 3); + int r = field(insn, 16, 5); gen_movl_T0_reg(r); gen_movl_sr_T0(sr); break; @@ -1209,8 +1209,8 @@ case 0x25: /* MFSP */ { - uint32_t sr = field(insn, 13, 3); - uint32_t t = field(insn, 0, 5); + int sr = field(insn, 13, 3); + int t = field(insn, 0, 5); if (sr >= 3) gen_op_check_priv0(); gen_movl_T0_sr(sr); @@ -1225,7 +1225,7 @@ case 0xc2: /* MTCTL */ { - uint32_t t, r; + int t, r; t = field(insn, 21, 5); r = field(insn, 16, 5); if (t >= 1 && t < 7) @@ -1286,7 +1286,7 @@ case 0x45: /* MFCTL/MFCTL,W */ { - uint32_t r, t; + int r, t; r = field(insn, 21, 5); t = field(insn, 0, 5); if (r >= 1 && r < 7) @@ -1324,10 +1324,10 @@ case 0x01: /* Mem_Mgmt */ { - uint32_t ext5; + int ext5; ext5 = field(insn, 0, 5); if(!field(insn, 12, 1)) { - uint32_t ext7; + int ext7; ext7 = field(insn, 6, 7); switch(ext7) { @@ -1349,7 +1349,7 @@ break; } } else { - uint32_t ext8; + int ext8; ext8 = field(insn, 6, 8); switch (ext8) @@ -1385,7 +1385,7 @@ case 0x02: /* Arith/Log */ { - uint32_t t, f, c, r1, r2; + int t, f, c, r1, r2; r2 = field(insn, 21, 5); r1 = field(insn, 16, 5); c = field(insn, 13, 3); @@ -1618,7 +1618,7 @@ case 0x03: /* Index_Mem */ { - uint32_t ext4 = field(insn, 6, 4); + int ext4 = field(insn, 6, 4); switch(ext4) { /* XXX: gen_op_*_raw only works for user-mode emulation * we really need gen_load and gen_store to be macros @@ -1683,7 +1683,8 @@ case 0x08: /* LDIL */ { - uint32_t t, im21; + int t; + target_ulong im21; t = field(insn, 21, 5); if(t) { im21 = assemble_21(field(insn, 0, 21)) << (32 - 21); @@ -1708,7 +1709,8 @@ case 0x0a: /* ADDIL */ { - uint32_t r, im21; + int r; + target_ulong im21; r = field(insn, 21, 5); im21 = assemble_21(field(insn, 0, 21)) << (32 - 21); gen_movl_T1_reg(r); @@ -1736,7 +1738,8 @@ case 0x0d: /* LDO - Load Offset */ { - uint32_t b, t, im14; + int b, t; + target_long im14; b = field(insn, 21, 5); t = field(insn, 16, 5); im14 = field_lowsignext(insn, 0, 14); @@ -1755,7 +1758,8 @@ case 0x11: /* LDH */ case 0x12: /* LDW */ { - uint32_t b, t, s, im14; + int b, t, s; + target_long im14; b = field(insn, 21, 5); t = field(insn, 16, 5); s = field(insn, 14, 2); @@ -1782,7 +1786,8 @@ case 0x13: /* LDW,M (LDWM) post-incr/pre-decr */ { - uint32_t b, t, s, im14; + int b, t, s; + target_long im14; b = field(insn, 21, 5); t = field(insn, 16, 5); s = field(insn, 14, 2); @@ -1819,7 +1824,8 @@ case 0x19: /* STH */ case 0x1a: /* STW */ { - uint32_t b, r, s, im14; + int b, r, s; + target_long im14; b = field(insn, 21, 5); r = field(insn, 16, 5); s = field(insn, 14, 2); @@ -1846,7 +1852,8 @@ case 0x1b: /* STW,M (STWM) post-incr/pre-decr */ { - uint32_t b, r, s, im14; + int b, r, s; + target_long im14; b = field(insn, 21, 5); r = field(insn, 16, 5); s = field(insn, 14, 2); @@ -1884,12 +1891,13 @@ case 0x22: /* CMPB (false) (COMBF) */ case 0x23: /* CMPIB (false) (COMIBF) */ { - uint32_t f, c, w1, n, w, disp; + int f, c, w1, n, w; + target_long disp; switch(op) { case 0x20: /* CMPB (true) (COMBT) */ case 0x22: /* CMPB (false) (COMBF) */ { - uint32_t r1, r2; + int r1, r2; r2 = field(insn, 21, 5); r1 = field(insn, 16, 5); gen_movl_T0_reg(r1); @@ -1899,7 +1907,8 @@ case 0x21: /* CMPIB (true) (COMIBT) */ case 0x23: /* CMPIB (false) (COMIBF) */ { - uint32_t r, im5; + int r; + target_long im5; r = field(insn, 21, 5); im5 = field_lowsignext(insn, 16, 5); gen_movl_T0_im(im5); @@ -1924,7 +1933,8 @@ case 0x24: /* CMPICLR (COMICLR) */ { - uint32_t r, t, c, f, im11; + int r, t, c, f; + target_long im11; if (field(insn, 11, 1)) gen_op_undef_insn(); else { @@ -1947,7 +1957,8 @@ case 0x25: /* SUBI / SUBI,TSV (SUBIO) */ { - uint32_t r, t, c, f, o, im11; + int r, t, c, f, o; + target_long im11; r = field(insn, 21, 5); t = field(insn, 16, 5); c = field(insn, 13, 3); @@ -1981,12 +1992,13 @@ case 0x2a: /* ADDB (false) (ADDBF) */ case 0x2b: /* ADDIB (false) (ADDIBF) */ { - uint32_t f, c, w1, n, w, disp; + int f, c, w1, n, w; + target_long disp; switch(op) { case 0x28: /* ADDB (true) (ADDBT) */ case 0x2a: /* ADDB (false) (ADDBF) */ { - uint32_t r1, r2; + int r1, r2; r2 = field(insn, 21, 5); r1 = field(insn, 16, 5); gen_movl_T0_reg(r1); @@ -1996,7 +2008,8 @@ case 0x29: /* ADDIB (true) (ADDIBT) */ case 0x2b: /* ADDIB (false) (ADDIBF) */ { - uint32_t r, im5; + int r; + target_long im5; r = field(insn, 21, 5); im5 = field_lowsignext(insn, 16, 5); gen_movl_T0_im(im5); @@ -2022,7 +2035,8 @@ case 0x2c: /* ADDI,TC (ADDIT) / ADDI,TSV,TC (ADDITO) */ case 0x2d: /* ADDI / ADDI,TSV (ADDIO) */ { - uint32_t r, t, c, f, o, im11; + int r, t, c, f, o; + target_long im11; r = field(insn, 21, 5); t = field(insn, 16, 5); c = field(insn, 13, 3); @@ -2064,7 +2078,7 @@ case 0x34: /* Shift/Extract */ { - uint32_t ext3; + int ext3; ext3 = field(insn, 10, 3); switch(ext3) { case 0: /* VSHD = SHRPW with SAR */ @@ -2073,7 +2087,7 @@ break; case 2: /* SHD = SHRPW */ { - uint32_t sa = 31 - field(insn, 5, 5); + int sa = 31 - field(insn, 5, 5); gen_movl_T0_im(sa); gen_shrpw(insn); break; @@ -2086,7 +2100,7 @@ case 6: /* EXTRU = EXTRW,U */ case 7: /* EXTRS = EXTRW,S */ { - uint32_t pos = field(insn, 5, 5); + int pos = field(insn, 5, 5); gen_movl_T0_im(pos); gen_extrw(insn); break; @@ -2097,7 +2111,7 @@ case 0x35: /* Deposit */ { - uint32_t ext3; + int ext3; ext3 = field(insn, 10, 3); switch(ext3) { case 0: /* VZDEP = DEPW,Z with SAR */ @@ -2108,7 +2122,7 @@ case 2: /* ZDEP = DEPW,Z */ case 3: /* DEP = DEPW */ { - uint32_t cpos = field(insn, 5, 5); + int cpos = field(insn, 5, 5); gen_movl_T0_im(cpos); gen_depw(insn); break; @@ -2121,7 +2135,7 @@ case 6: /* ZDEPI = DEPWI,Z */ case 7: /* DEPI = DEPWI */ { - uint32_t cpos = field(insn, 5, 5); + int cpos = field(insn, 5, 5); gen_movl_T0_im(cpos); gen_depwi(insn); break; @@ -2138,7 +2152,8 @@ case 0x38: /* BE */ case 0x39: /* BE,L (BLE) */ { - uint32_t b, w1, s, w2, n, w, disp; + int b, w1, s, w2, n, w; + target_long disp; b = field(insn, 21, 5); w1 = field(insn, 16, 5); s = field(insn, 13, 3); @@ -2155,7 +2170,8 @@ case 0x3a: /* Branch */ { - uint32_t t, w, w1, ext3, w2, n, disp; + int t, w, w1, ext3, w2, n; + target_long disp; ext3 = field(insn, 13, 3); t = field(insn, 21, 5); w1 = field(insn, 16, 5); |
