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hppaqemu-cvs — CVS commits for the HPPA target for QEMU
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From: Randolph C. <ta...@us...> - 2007-03-04 15:16:32
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Update of /cvsroot/hppaqemu/hppaqemu/hw In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv12958/hw Added Files: hppa.c Log Message: beginning of hppa target support --- NEW FILE: hppa.c --- #include "vl.h" #define BIOS_FILENAME "hppa_pdc.bin" #define BIOS_ADDRESS 0xF0000000 void DMA_run(void) { /* XXXXX */ } void irq_info(void) { /* XXXXX */ } void pic_set_irq(int irq, int level) { /* XXXXX */ } void pic_info() { /* XXXXX */ } void vga_update_display() { /* XXXXX */ } void vga_invalidate_display() { /* XXXXX */ } void vga_screen_dump(const char *filename) { /* XXXXX */ } void hppa_init(int ram_size, int vga_ram_size, int boot_device, DisplayState * ds, const char **fd_filename, int snapshot, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename) { } QEMUMachine hppa_machine = { "hppa", "hppa card", hppa_init }; |
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From: Randolph C. <ta...@us...> - 2007-03-04 15:16:32
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv12958/target-hppa Modified Files: cpu.h exec.h op.c translate.c Log Message: beginning of hppa target support Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** translate.c 2 Mar 2007 23:47:46 -0000 1.3 --- translate.c 4 Mar 2007 15:16:27 -0000 1.4 *************** *** 20,23 **** --- 20,28 ---- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + #include <stdarg.h> + #include <stdlib.h> + #include <stdio.h> + #include <string.h> + #include <inttypes.h> #include "cpu.h" *************** *** 31,34 **** --- 36,52 ---- } DisasContext; + static uint16_t *gen_opc_ptr; + static uint32_t *gen_opparam_ptr; + extern FILE *logfile; + extern int loglevel; + + enum { + #define DEF(s,n,copy_size) INDEX_op_ ## s, + #include "opc.h" + #undef DEF + NB_OPS + }; + #include "gen-op.h" + static inline uint32_t field(uint32_t val, int start, int length) { val >>= start; *************** *** 208,217 **** static inline void gen_movl_imm_T0(int val) { ! gen_movl_imm_T0(0, val); } static inline void gen_movl_imm_T1(int val) { ! gen_movl_imm_T1(1, val); } --- 226,235 ---- static inline void gen_movl_imm_T0(int val) { ! gen_movl_imm_TN(0, val); } static inline void gen_movl_imm_T1(int val) { ! gen_movl_imm_TN(1, val); } *************** *** 314,318 **** uint32_t ext7; ext7 = field(insn, 6, 7); ! swtich(ext7) { case 0x01: /* IITLBA */ --- 332,336 ---- uint32_t ext7; ext7 = field(insn, 6, 7); ! switch(ext7) { case 0x01: /* IITLBA */ *************** *** 329,334 **** } } else { ! uint32_t ext7; ext8 = field(insn, 6, 8); { case 0x40: /* IDTLBP */ --- 347,354 ---- } } else { ! uint32_t ext8; ext8 = field(insn, 6, 8); + + switch (ext8) { case 0x40: /* IDTLBP */ *************** *** 632,636 **** case 0x1a: /* STW */ { ! uint32_t b, r, s, im14; b = field(insn, 21, 5); t = field(insn, 16, 5); --- 652,656 ---- case 0x1a: /* STW */ { ! uint32_t b, t, r, s, im14; b = field(insn, 21, 5); t = field(insn, 16, 5); *************** *** 685,688 **** --- 705,709 ---- case 0x25: /* SUBI, SUBIO */ { + uint32_t r, t, im11; r = field(insn, 21, 5); t = field(insn, 16, 5); *************** *** 760,764 **** case 0x39: /* BLE */ { ! uint32_t b, w1, s, w2, n, w; b = field(insn, 21, 5); w1 = field_signext(insn, 16, 5); --- 781,785 ---- case 0x39: /* BLE */ { ! uint32_t b, w1, s, w2, n, w, disp; b = field(insn, 21, 5); w1 = field_signext(insn, 16, 5); *************** *** 774,778 **** case 0x3a: /* Branch */ { ! uint32_t t, w1, ext3, w2, n, disp; ext3 = field(insn, 13, 3); t = field(insn, 21, 5); --- 795,799 ---- case 0x3a: /* Branch */ { ! uint32_t t, w, w1, ext3, w2, n, disp; ext3 = field(insn, 13, 3); t = field(insn, 21, 5); *************** *** 802,803 **** --- 823,864 ---- } } + + CPUHPPAState *cpu_hppa_init(void) + { + CPUHPPAState *env; + + env = qemu_mallocz(sizeof(CPUHPPAState)); + if (!env) + return NULL; + cpu_exec_init(env); + tlb_flush(env, 1); + return env; + } + + void cpu_dump_state(CPUState *env, FILE *f, + int (*cpu_fprintf)(FILE *f, const char *fmt, ...), + int flags) + { + int i; + + cpu_fprintf(f, "PSW = %08X\n", env->psw); + for(i=0;i<31;i++) { + cpu_fprintf(f, "R%02d=%08x", i, env->gr[i]); + if ((i % 4) == 3) + cpu_fprintf(f, "\n"); + else + cpu_fprintf(f, " "); + } + + for(i=0;i<31;i++) { + cpu_fprintf(f, "CR%02d=%08x", i, env->cr[i]); + if ((i % 4) == 3) + cpu_fprintf(f, "\n"); + else + cpu_fprintf(f, " "); + } + + cpu_fprintf(f, "IAOQ = %08X %08X\tIASQ = %08X %08X\n", + env->iaoq[0], env->iaoq[1], env->iasq[0], env->iasq[1]); + } + Index: cpu.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** cpu.h 27 Feb 2007 23:21:24 -0000 1.2 --- cpu.h 4 Mar 2007 15:16:27 -0000 1.3 *************** *** 22,30 **** #define CPU_HPPA_H #define TARGET_LONG_BITS 32 #include "cpu-defs.h" /* the shadow registers map to the following general registers */ ! int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 }; #define PSW_Y 0x00000001 --- 22,38 ---- #define CPU_HPPA_H + #include "config.h" + #define TARGET_LONG_BITS 32 #include "cpu-defs.h" + #include <setjmp.h> + + #include "softfloat.h" + + #define ELF_MACHINE EM_PARISC + /* the shadow registers map to the following general registers */ ! // int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 }; #define PSW_Y 0x00000001 *************** *** 60,63 **** --- 68,73 ---- #define PSW_I 0x80000000 + #define PSW_CB7_SHIFT 7 /* CHECK */ + typedef struct CPUHPPAState { target_ulong gr[32]; /* General Registers */ *************** *** 78,82 **** --- 88,108 ---- * gr[31] : link register for BLE */ + + jmp_buf jmp_env; + int user_mode_only; + int exception_index; + int interrupt_index; + int interrupt_request; + int halted; + + CPU_COMMON + } CPUHPPAState; + #define TARGET_PAGE_BITS 12 + #include "cpu-all.h" + + CPUHPPAState *cpu_hppa_init(void); + int cpu_hppa_exec(CPUHPPAState *s); + #endif Index: exec.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/exec.h,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** exec.h 2 Mar 2007 23:47:46 -0000 1.2 --- exec.h 4 Mar 2007 15:16:27 -0000 1.3 *************** *** 20,24 **** --- 20,28 ---- */ + #ifndef EXEC_HPPA_H + #define EXEC_HPPA_H + #include "dyngen-exec.h" + #include "config.h" register struct CPUHPPAState *env asm(AREG0); *************** *** 28,29 **** --- 32,44 ---- #include "cpu.h" + #include "exec-all.h" + + static inline void env_to_regs(void) + { + } + + static inline void regs_to_env(void) + { + } + + #endif Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** op.c 2 Mar 2007 23:47:46 -0000 1.3 --- op.c 4 Mar 2007 15:16:27 -0000 1.4 *************** *** 21,24 **** --- 21,27 ---- #include "exec.h" + #define REGNAME gr0 + #define REG (env->gr[0]) + #include "op_template.h" #define REGNAME gr1 #define REG (env->gr[1]) *************** *** 27,33 **** #define REG (env->gr[2]) #include "op_template.h" - #define REGNAME gr2 - #define REG (env->gr[2]) - #include "op_template.h" #define REGNAME gr3 #define REG (env->gr[3]) --- 30,33 ---- *************** *** 118,145 **** #include "op_template.h" ! void OPPROTO op_mov_T0_GR0(void) { T0 = 0; } ! void OPPROTO op_mov_T1_GR0(void) { T1 = 0; } ! void OPPROTO op_mov_GR0_T0(void) { } ! void OPPROTO op_mov_GR0_T1(void) { } ! void OPPROTO op_mov_T0_im(void) { T0 = PARAM1; } ! void OPPROTO op_mov_T1_im(void) { T1 = PARAM1; --- 118,145 ---- #include "op_template.h" ! void OPPROTO op_movl_T0_GR0(void) { T0 = 0; } ! void OPPROTO op_movl_T1_GR0(void) { T1 = 0; } ! void OPPROTO op_movl_GR0_T0(void) { } ! void OPPROTO op_movl_GR0_T1(void) { } ! void OPPROTO op_movl_T0_im(void) { T0 = PARAM1; } ! void OPPROTO op_movl_T1_im(void) { T1 = PARAM1; *************** *** 171,175 **** carry &= 0x000000ff; /* 000000000000000000000000abcdefgh */ ! env->psw &= ~PSW_CB env->psw |= carry << PSW_CB7_SHIFT; } --- 171,175 ---- carry &= 0x000000ff; /* 000000000000000000000000abcdefgh */ ! env->psw &= ~PSW_CB; env->psw |= carry << PSW_CB7_SHIFT; } *************** *** 201,205 **** carry &= 0x000000ff; /* 000000000000000000000000abcdefgh */ ! env->psw &= ~PSW_CB env->psw |= carry << PSW_CB7_SHIFT; } --- 201,205 ---- carry &= 0x000000ff; /* 000000000000000000000000abcdefgh */ ! env->psw &= ~PSW_CB; env->psw |= carry << PSW_CB7_SHIFT; } *************** *** 274,278 **** borrow &= 0x000000ff; /* 000000000000000000000000abcdefgh */ ! env->psw &= ~PSW_CB env->psw |= ~borrow << PSW_CB7_SHIFT; } --- 274,278 ---- borrow &= 0x000000ff; /* 000000000000000000000000abcdefgh */ ! env->psw &= ~PSW_CB; env->psw |= ~borrow << PSW_CB7_SHIFT; } *************** *** 280,286 **** void OPPROTO op_next_insn(void) { ! iaoq[0] = iaoq[1]; ! iasq[0] = iasq[1]; ! iaoq[1] += 4; } --- 280,286 ---- void OPPROTO op_next_insn(void) { ! env->iaoq[0] = env->iaoq[1]; ! env->iasq[0] = env->iasq[1]; ! env->iaoq[1] += 4; } |
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From: Randolph C. <ta...@us...> - 2007-03-04 15:16:31
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Update of /cvsroot/hppaqemu/hppaqemu In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv12958 Modified Files: Makefile.target configure cpu-all.h cpu-exec.c exec-all.h softmmu_header.h vl.c vl.h Log Message: beginning of hppa target support Index: vl.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/vl.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** vl.h 23 Feb 2007 21:44:12 -0000 1.1.1.1 --- vl.h 4 Mar 2007 15:16:27 -0000 1.2 *************** *** 1090,1093 **** --- 1090,1096 ---- extern QEMUMachine shix_machine; + /* hppa.c */ + extern QEMUMachine hppa_machine; + #ifdef TARGET_PPC ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq); Index: configure =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/configure,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** configure 4 Mar 2007 15:03:22 -0000 1.2 --- configure 4 Mar 2007 15:16:26 -0000 1.3 *************** *** 419,423 **** # these targets are portable if [ "$softmmu" = "yes" ] ; then ! target_list="i386-softmmu ppc-softmmu sparc-softmmu x86_64-softmmu mips-softmmu mipsel-softmmu arm-softmmu" fi # the following are Linux specific --- 419,423 ---- # these targets are portable if [ "$softmmu" = "yes" ] ; then ! target_list="i386-softmmu ppc-softmmu sparc-softmmu x86_64-softmmu mips-softmmu mipsel-softmmu arm-softmmu hppa-softmmu" fi # the following are Linux specific *************** *** 808,811 **** --- 808,812 ---- [ "$target_cpu" = "sh4eb" ] && target_bigendian=yes [ "$target_cpu" = "m68k" ] && target_bigendian=yes + [ "$target_cpu" = "hppa" ] && target_bigendian=yes target_softmmu="no" if expr $target : '.*-softmmu' > /dev/null ; then *************** *** 918,921 **** --- 919,927 ---- echo "#define TARGET_M68K 1" >> $config_h bflt="yes" + elif test "$target_cpu" = "hppa" ; then + echo "TARGET_ARCH=hppa" >> $config_mak + echo "#define TARGET_ARCH \"hppa\"" >> $config_h + echo "#define TARGET_HPPA 1" >> $config_h + bflt="yes" else echo "Unsupported target CPU" Index: softmmu_header.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/softmmu_header.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** softmmu_header.h 23 Feb 2007 21:44:09 -0000 1.1.1.1 --- softmmu_header.h 4 Mar 2007 15:16:27 -0000 1.2 *************** *** 64,67 **** --- 64,69 ---- #elif defined (TARGET_SH4) #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) + #elif defined (TARGET_HPPA) + #define CPU_MEM_INDEX 0 /* FIXME */ #else #error unsupported CPU *************** *** 83,86 **** --- 85,90 ---- #elif defined (TARGET_SH4) #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0) + #elif defined (TARGET_HPPA) + #define CPU_MEM_INDEX 0 /* FIXME */ #else #error unsupported CPU Index: vl.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/vl.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** vl.c 23 Feb 2007 21:44:12 -0000 1.1.1.1 --- vl.c 4 Mar 2007 15:16:27 -0000 1.2 *************** *** 5320,5323 **** --- 5320,5335 ---- } + #elif defined(TARGET_HPPA) + + /* ??? Need to implement these. */ + void cpu_save(QEMUFile *f, void *opaque) + { + } + + int cpu_load(QEMUFile *f, void *opaque, int version_id) + { + return 0; + } + #else *************** *** 6369,6372 **** --- 6381,6386 ---- #elif defined(TARGET_SH4) qemu_register_machine(&shix_machine); + #elif defined(TARGET_HPPA) + qemu_register_machine(&hppa_machine); #else #error unsupported CPU Index: cpu-exec.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/cpu-exec.c,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** cpu-exec.c 4 Mar 2007 15:03:22 -0000 1.2 --- cpu-exec.c 4 Mar 2007 15:16:27 -0000 1.3 *************** *** 203,206 **** --- 203,210 ---- cs_base = 0; /* XXXXX */ pc = env->pc; + #elif defined(TARGET_HPPA) + flags = env->psw; + cs_base = 0; + pc = env->iaoq[0]; #else #error unsupported CPU *************** *** 325,328 **** --- 329,333 ---- #elif defined(TARGET_MIPS) #elif defined(TARGET_SH4) + #elif defined(TARGET_HPPA) /* XXXXX */ #else *************** *** 594,597 **** --- 599,604 ---- #elif defined(TARGET_SH4) cpu_dump_state(env, logfile, fprintf, 0); + #elif defined(TARGET_HPPA) + cpu_dump_state(env, logfile, fprintf, 0); #else #error unsupported target CPU *************** *** 794,797 **** --- 801,805 ---- #elif defined(TARGET_MIPS) #elif defined(TARGET_SH4) + #elif defined(TARGET_HPPA) /* XXXXX */ #else *************** *** 1180,1183 **** --- 1188,1227 ---- return 1; } + #elif defined(TARGET_HPPA) + static inline int handle_cpu_signal(unsigned long pc, unsigned long address, + int is_write, sigset_t *old_set, + void *puc) + { + TranslationBlock *tb; + int ret; + + if (cpu_single_env) + env = cpu_single_env; /* XXX: find a correct solution for multithread */ + #if defined(DEBUG_SIGNAL) + printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", + pc, address, is_write, *(unsigned long *)old_set); + #endif + /* XXX: locking issue */ + if (is_write && page_unprotect(h2g(address), pc, puc)) { + return 1; + } + /* see if it is an MMU fault */ + ret = cpu_hppa_handle_mmu_fault(env, address, is_write, 1, 0); + if (ret < 0) + return 0; /* not an MMU fault */ + if (ret == 0) + return 1; /* the MMU fault was handled without causing real CPU fault */ + /* now we have a real cpu fault */ + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, puc); + } + /* we restore the process signal mask as the sigreturn should + do it (XXX: use sigsetjmp) */ + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit(); + } #else #error unsupported target CPU Index: Makefile.target =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/Makefile.target,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** Makefile.target 4 Mar 2007 15:03:22 -0000 1.2 --- Makefile.target 4 Mar 2007 15:16:26 -0000 1.3 *************** *** 415,418 **** --- 415,421 ---- VL_OBJS+= shix.o sh7750.o sh7750_regnames.o tc58128.o endif + ifeq ($(TARGET_BASE_ARCH), hppa) + VL_OBJS+= hppa.o + endif ifdef CONFIG_GDBSTUB VL_OBJS+=gdbstub.o Index: exec-all.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/exec-all.h,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** exec-all.h 4 Mar 2007 15:03:23 -0000 1.2 --- exec-all.h 4 Mar 2007 15:16:27 -0000 1.3 *************** *** 619,622 **** --- 619,624 ---- #elif defined (TARGET_SH4) is_user = ((env->sr & SR_MD) == 0); + #elif defined (TARGET_HPPA) + is_user = ((env->iaoq[0] & 3) != 0); #else #error unimplemented CPU Index: cpu-all.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/cpu-all.h,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** cpu-all.h 4 Mar 2007 15:03:22 -0000 1.2 --- cpu-all.h 4 Mar 2007 15:16:27 -0000 1.3 *************** *** 747,750 **** --- 747,756 ---- #define cpu_signal_handler cpu_sh4_signal_handler + #elif defined(TARGET_HPPA) + #define CPUState CPUHPPAState + #define cpu_init cpu_hppa_init + #define cpu_exec cpu_hppa_exec + #define cpu_gen_code cpu_hppa_gen_code + #define cpu_signal_handler cpu_hppa_signal_handler #else |
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From: Randolph C. <ta...@us...> - 2007-03-04 15:13:19
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Update of /cvsroot/hppaqemu/hppaqemu/hppa-softmmu In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv11749/hppa-softmmu Log Message: Directory /cvsroot/hppaqemu/hppaqemu/hppa-softmmu added to the repository |
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From: Randolph C. <ta...@us...> - 2007-03-04 15:07:49
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Update of /cvsroot/hppaqemu/hppaqemu In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv9333 Added Files: hppa-dis.c Log Message: hppa disassembly support --- NEW FILE: hppa-dis.c --- /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c. Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc. Contributed by the Center for Software Science at the University of Utah (pa-...@cs...). This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software [...2795 lines suppressed...] } case 'X': (*info->print_address_func) (memaddr + 8 + extract_22 (insn), info); break; case 'L': fputs_filtered (",rp", info); break; default: (*info->fprintf_func) (info->stream, "%c", *s); break; } } return sizeof (insn); } } (*info->fprintf_func) (info->stream, "#%8x", insn); return sizeof (insn); } |
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From: Randolph C. <ta...@us...> - 2007-03-04 15:03:27
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Update of /cvsroot/hppaqemu/hppaqemu In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv6947 Modified Files: Makefile.target configure cpu-all.h cpu-exec.c disas.c dyngen-exec.h dyngen.c dyngen.h exec-all.h exec.c Log Message: host support for hppa, mostly works :) Index: dyngen-exec.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/dyngen-exec.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** dyngen-exec.h 23 Feb 2007 21:44:02 -0000 1.1.1.1 --- dyngen-exec.h 4 Mar 2007 15:03:22 -0000 1.2 *************** *** 124,127 **** --- 124,133 ---- #define AREG3 "r6" #endif + #ifdef __hppa__ + #define AREG0 "r17" + #define AREG1 "r14" + #define AREG2 "r15" + #define AREG3 "r16" + #endif #ifdef __mips__ #define AREG0 "s3" *************** *** 276,279 **** --- 282,291 ---- #define EXIT_TB() asm volatile ("rts") #endif + #ifdef __hppa__ + #define EXIT_TB() asm volatile ("ldil L'exec_loop, %r1\n" \ + "ldo R'exec_loop(%r1), %r1\n" \ + "bv,n %r0(%r1)\n") + #define GOTO_LABEL_PARAM(n) asm volatile ("b,n " ASM_NAME(__op_gen_label) #n) + #endif #endif /* !defined(__DYNGEN_EXEC_H__) */ Index: dyngen.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/dyngen.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** dyngen.h 23 Feb 2007 21:44:03 -0000 1.1.1.1 --- dyngen.h 4 Mar 2007 15:03:22 -0000 1.2 *************** *** 81,84 **** --- 81,100 ---- #endif + #ifdef __hppa__ + static inline void flush_icache_range(unsigned long start, unsigned long stop) + { + start &= ~31; + while (start < stop) + { + asm volatile ("fdc 0(%0)\n" + "sync\n" + "fic 0(%%sr4, %0)\n" + "sync\n" + : : "r"(start) : "memory"); + start += 32; + } + } + #endif + #ifdef __alpha__ static inline void flush_icache_range(unsigned long start, unsigned long stop) *************** *** 247,250 **** --- 263,395 ---- #endif /* __arm__ */ + #ifdef __hppa__ + + /* Field selection types defined by hppa */ + #define rnd(x) (((x)+0x1000)&~0x1fff) + /* lsel: select left 21 bits */ + #define lsel(v,a) (((v)+(a))>>11) + /* rsel: select right 11 bits */ + #define rsel(v,a) (((v)+(a))&0x7ff) + /* lrsel with rounding of addend to nearest 8k */ + #define lrsel(v,a) (((v)+rnd(a))>>11) + /* rrsel with rounding of addend to nearest 8k */ + #define rrsel(v,a) ((((v)+rnd(a))&0x7ff)+((a)-rnd(a))) + + #define mask(x,sz) ((x) & ~((1<<(sz))-1)) + + static inline int reassemble_14(int as14) + { + return (((as14 & 0x1fff) << 1) | + ((as14 & 0x2000) >> 13)); + } + + static inline int reassemble_17(int as17) + { + return (((as17 & 0x10000) >> 16) | + ((as17 & 0x0f800) << 5) | + ((as17 & 0x00400) >> 8) | + ((as17 & 0x003ff) << 3)); + } + + static inline int reassemble_21(int as21) + { + return (((as21 & 0x100000) >> 20) | + ((as21 & 0x0ffe00) >> 8) | + ((as21 & 0x000180) << 7) | + ((as21 & 0x00007c) << 14) | + ((as21 & 0x000003) << 12)); + } + + struct hppa_branch_stub { + uint32_t *location; + long target; + struct hppa_branch_stub *next; + }; + + #define HPPA_RECORD_BRANCH(LIST, LOC, TARGET) \ + do { \ + struct hppa_branch_stub *stub = alloca(sizeof(struct hppa_branch_stub)); \ + stub->location = LOC; \ + stub->target = TARGET; \ + stub->next = LIST; \ + LIST = stub; \ + } while (0) + + static inline void hppa_patch21l(uint32_t *insn, int val, int addend) + { + val = lrsel(val, addend); + *insn = mask(*insn, 21) | reassemble_21(val); + } + + static inline void hppa_patch14r(uint32_t *insn, int val, int addend) + { + val = rrsel(val, addend); + *insn = mask(*insn, 14) | reassemble_14(val); + } + + static inline void hppa_patch17r(uint32_t *insn, int val, int addend) + { + val = rrsel(val, addend); + *insn = (*insn & ~0x1f1ffd) | reassemble_17(val); + } + + + static inline void hppa_patch21l_dprel(uint32_t *insn, int val, int addend) + { + register unsigned int dp asm("r27"); + hppa_patch21l(insn, val - dp, addend); + } + + static inline void hppa_patch14r_dprel(uint32_t *insn, int val, int addend) + { + register unsigned int dp asm("r27"); + hppa_patch14r(insn, val - dp, addend); + } + + static inline void hppa_patch17f(uint32_t *insn, int val, int addend) + { + int dot = (int)insn & ~0x3; + int v = ((val + addend) - dot - 8) / 4; + if (v > (1 << 16) || v < -(1 << 16)) { + printf("cannot fit branch to offset %d [%08x->%08x]\n", v, dot, val); + abort(); + } + *insn = (*insn & ~0x1f1ffd) | reassemble_17(v); + } + + static inline void hppa_load_imm21l(uint32_t *insn, int val, int addend) + { + /* Transform addil L'sym(%dp) to ldil L'val, %r1 */ + *insn = 0x20200000 | reassemble_21(lrsel(val, 0)); + } + + static inline void hppa_load_imm14r(uint32_t *insn, int val, int addend) + { + /* Transform ldw R'sym(%r1), %rN to ldo R'sym(%r1), %rN */ + hppa_patch14r(insn, val, addend); + /* HACK */ + if (addend == 0) + *insn = (*insn & ~0xfc000000) | (0x0d << 26); + } + + static inline void hppa_process_stubs(struct hppa_branch_stub *stub, uint8_t **gen_code_pp) + { + uint32_t *p = (uint32_t *)*gen_code_pp; + for (; stub != NULL; stub = stub->next) + { + unsigned long l = (unsigned long)p; + /* stub: + * ldil L'target, %r1 + * be,n R'target(%r1) + */ + *p++ = 0x20200000 | reassemble_21(lrsel(stub->target, 0)); + *p++ = 0xe0200002 | reassemble_17(rrsel(stub->target, 0) >> 2); + hppa_patch17f(stub->location, l, 0); + } + *gen_code_pp = (uint8_t *)p; + } + + #endif + #ifdef __ia64 Index: configure =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/configure,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** configure 23 Feb 2007 21:44:02 -0000 1.1.1.1 --- configure 4 Mar 2007 15:03:22 -0000 1.2 *************** *** 48,51 **** --- 48,54 ---- cpu="powerpc" ;; + parisc|parisc64) + cpu="hppa" + ;; mips) cpu="mips" *************** *** 455,459 **** # if cross compiling, cannot launch a program, so make a static guess ! if test "$cpu" = "powerpc" -o "$cpu" = "mips" -o "$cpu" = "s390" -o "$cpu" = "sparc" -o "$cpu" = "sparc64" -o "$cpu" = "m68k" -o "$cpu" = "armv4b"; then bigendian="yes" fi --- 458,462 ---- # if cross compiling, cannot launch a program, so make a static guess ! if test "$cpu" = "powerpc" -o "$cpu" = "mips" -o "$cpu" = "s390" -o "$cpu" = "sparc" -o "$cpu" = "sparc64" -o "$cpu" = "m68k" -o "$cpu" = "armv4b" -o "$cpu" = "hppa"; then bigendian="yes" fi *************** *** 677,680 **** --- 680,686 ---- echo "ARCH=ppc" >> $config_mak echo "#define HOST_PPC 1" >> $config_h + elif test "$cpu" = "hppa" ; then + echo "ARCH=hppa" >> $config_mak + echo "#define HOST_HPPA 1" >> $config_h elif test "$cpu" = "mips" ; then echo "ARCH=mips" >> $config_mak Index: dyngen.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/dyngen.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** dyngen.c 23 Feb 2007 21:44:03 -0000 1.1.1.1 --- dyngen.c 4 Mar 2007 15:03:22 -0000 1.2 *************** *** 118,121 **** --- 118,128 ---- #define ELF_USES_RELOCA + #elif defined(HOST_HPPA) + + #define ELF_CLASS ELFCLASS32 + #define ELF_ARCH EM_PARISC + #define elf_check_arch(x) ((x) == EM_PARISC) + #define ELF_USES_RELOCA + #else #error unsupported CPU - please update the code *************** *** 1207,1211 **** snprintf(name, name_size, "gen_labels[param%s]", p); } else { ! #ifdef HOST_SPARC if (sym_name[0] == '.') snprintf(name, name_size, --- 1214,1218 ---- snprintf(name, name_size, "gen_labels[param%s]", p); } else { ! #if defined(HOST_SPARC) || defined(HOST_HPPA) if (sym_name[0] == '.') snprintf(name, name_size, *************** *** 1642,1645 **** --- 1649,1689 ---- copy_size = p - p_start; } + #elif defined(HOST_HPPA) + { + uint8_t *p; + p = p_start; + while (p < p_end) { + uint32_t insn = get32((uint32_t *)p); + if (insn == 0x6bc23fd9 || + insn == 0x08030241 || + insn == 0x081e0243 || + (insn & 0x37de0000) == 0x37de0000 || + (insn & 0xffffc000) == 0x6fc10000) + p += 4; + else + break; + } + start_offset += p - p_start; + p_start = p; + p = p_end - 4; + + while (p > p_start) { + uint32_t insn = get32((uint32_t *)p); + if ((insn & 0xffffc000) == 0x347e0000 || + (insn & 0x0fc010e0) == 0x0fc01080 || + (insn & 0x37de0000) == 0x37de0000 || + insn == 0x48623fd9 || + insn == 0xe840c000 || + insn == 0xe840c002) + p -= 4; + else + break; + } + p += 4; + if (p <= p_start) + error("empty code for %s", name); + + copy_size = p - p_start; + } #else #error unsupported CPU *************** *** 1707,1711 **** !strstart(sym_name, "__op_jmp", NULL) && !strstart(sym_name, "__op_gen_label", NULL)) { ! #if defined(HOST_SPARC) if (sym_name[0] == '.') { fprintf(outfile, --- 1751,1755 ---- !strstart(sym_name, "__op_jmp", NULL) && !strstart(sym_name, "__op_gen_label", NULL)) { ! #if defined(HOST_SPARC) || defined(HOST_HPPA) if (sym_name[0] == '.') { fprintf(outfile, *************** *** 1734,1739 **** --- 1778,1790 ---- } + #ifndef __hppa__ fprintf(outfile, " memcpy(gen_code_ptr, (void *)((char *)&%s+%d), %d);\n", name, (int)(start_offset - offset), copy_size); + #else + fprintf(outfile, " memcpy(gen_code_ptr, (void *)((char *)__canonicalize_funcptr_for_compare(%s)+%d), %d);\n", + name, (int)(start_offset - offset), copy_size); + + + #endif /* emit code offset information */ *************** *** 2457,2460 **** --- 2508,2578 ---- } } + #elif defined(HOST_HPPA) + { + char name[256]; + int type; + int addend; + int reloc_offset; + for(i = 0, rel = relocs;i < nb_relocs; i++, rel++) { + if (rel->r_offset >= start_offset && + rel->r_offset < start_offset + copy_size) { + sym_name = get_rel_sym_name(rel); + sym_name = strtab + symtab[ELF32_R_SYM(rel->r_info)].st_name; + get_reloc_expr(name, sizeof(name), sym_name); + type = ELF32_R_TYPE(rel->r_info); + addend = rel->r_addend; + reloc_offset = rel->r_offset - start_offset; + + switch(type) { + case R_PARISC_DIR21L: + fprintf(outfile, + " hppa_patch21l((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", + reloc_offset, name, addend); + break; + case R_PARISC_DIR14R: + fprintf(outfile, + " hppa_patch14r((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", + reloc_offset, name, addend); + break; + case R_PARISC_DIR17R: + fprintf(outfile, + " hppa_patch17r((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", + reloc_offset, name, addend); + break; + case R_PARISC_PCREL17F: + if (strstart(sym_name, "__op_gen_label", NULL)) { + fprintf(outfile, + " hppa_patch17f((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", + reloc_offset, name, addend); + } else { + fprintf(outfile, + " HPPA_RECORD_BRANCH(hppa_stubs, (uint32_t *)(gen_code_ptr + %d), %s);\n", + reloc_offset, name); + } + break; + case R_PARISC_DPREL21L: + if (strstart(sym_name, "__op_param", &p)) + fprintf(outfile, " hppa_load_imm21l((uint32_t *)(gen_code_ptr + %d), param%s, %d);\n", + reloc_offset, p, addend); + else + fprintf(outfile, + " hppa_patch21l_dprel((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", + reloc_offset, name, addend); + break; + case R_PARISC_DPREL14R: + if (strstart(sym_name, "__op_param", &p)) + fprintf(outfile, " hppa_load_imm14r((uint32_t *)(gen_code_ptr + %d), param%s, %d);\n", + reloc_offset, p, addend); + else + fprintf(outfile, + " hppa_patch14r_dprel((uint32_t *)(gen_code_ptr + %d), %s, %d);\n", + reloc_offset, name, addend); + break; + default: + error("unsupported hppa relocation (%d)", type); + } + } + } + } #else #error unsupported CPU *************** *** 2640,2643 **** --- 2758,2765 ---- #endif + #ifdef HOST_HPPA + fprintf(outfile, " struct hppa_branch_stub *hppa_stubs = NULL;\n"); + #endif + fprintf(outfile, "\n" *************** *** 2721,2724 **** --- 2843,2851 ---- "arm_ldr_ptr, arm_data_ptr, arm_data_table + ARM_LDR_TABLE_SIZE, 0);\n"); #endif + + #ifdef HOST_HPPA + fprintf(outfile, "hppa_process_stubs(hppa_stubs, &gen_code_ptr);\n"); + #endif + /* flush instruction cache */ fprintf(outfile, "flush_icache_range((unsigned long)gen_code_buf, (unsigned long)gen_code_ptr);\n"); Index: cpu-exec.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/cpu-exec.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** cpu-exec.c 23 Feb 2007 21:44:02 -0000 1.1.1.1 --- cpu-exec.c 4 Mar 2007 15:03:22 -0000 1.2 *************** *** 653,656 **** --- 653,665 ---- : "r" (gen_func) : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); + #elif defined(__hppa__) + asm volatile ("bv %%r0(%0)\n" + "nop\n" + ".global exec_loop\n" + "exec_loop:\n" + : /* no outputs */ + : "r" (gen_func) + : "r1", "r20", "r21", "r22", "r23", + "r24", "r25", "r27", "r28"); #elif defined(TARGET_I386) && defined(USE_CODE_COPY) { *************** *** 1479,1482 **** --- 1488,1509 ---- } + #elif defined(__hppa__) + + int cpu_signal_handler(int host_signum, void *pinfo, + void *puc) + { + struct siginfo *info = pinfo; + struct ucontext *uc = puc; + unsigned long pc; + int is_write; + + pc = uc->uc_mcontext.sc_iaoq[0]; + /* FIXME: compute is_write */ + is_write = 0; + return handle_cpu_signal(pc, (unsigned long)info->si_addr, + is_write, + &uc->uc_sigmask, puc); + } + #else Index: exec.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/exec.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** exec.c 23 Feb 2007 21:44:03 -0000 1.1.1.1 --- exec.c 4 Mar 2007 15:03:23 -0000 1.2 *************** *** 70,73 **** --- 70,77 ---- #endif + #ifdef __hppa__ + unsigned int hppa_lock[4] = {1, 1, 1, 1}; + #endif + TranslationBlock tbs[CODE_GEN_MAX_BLOCKS]; TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; Index: Makefile.target =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/Makefile.target,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** Makefile.target 23 Feb 2007 21:43:58 -0000 1.1.1.1 --- Makefile.target 4 Mar 2007 15:03:22 -0000 1.2 *************** *** 144,147 **** --- 144,151 ---- endif + ifeq ($(ARCH),hppa) + OP_CFLAGS=-O1 -fno-delayed-branch + endif + ifeq ($(ARCH),ia64) BASE_CFLAGS+=-mno-sdata *************** *** 304,307 **** --- 308,314 ---- LIBOBJS+=sh4-dis.o endif + ifeq ($(findstring hppa, $(TARGET_ARCH) $(ARCH)),hppa) + LIBOBJS+=hppa-dis.o + endif ifdef CONFIG_GDBSTUB Index: exec-all.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/exec-all.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** exec-all.h 23 Feb 2007 21:44:03 -0000 1.1.1.1 --- exec-all.h 4 Mar 2007 15:03:23 -0000 1.2 *************** *** 344,351 **** #define GOTO_TB(opname, tbparam, n)\ do {\ ! static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ ! static void __attribute__((unused)) *__op_label ## n \ __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ ! goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ label ## n: ;\ dummy_label ## n: ;\ --- 344,351 ---- #define GOTO_TB(opname, tbparam, n)\ do {\ ! static volatile void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ ! static volatile void __attribute__((unused)) *__op_label ## n \ __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ ! goto *(void *)(((volatile TranslationBlock *)tbparam)->tb_next[n]);\ label ## n: ;\ dummy_label ## n: ;\ *************** *** 473,476 **** --- 473,522 ---- #endif + #ifdef __hppa__ + + #if 0 + #define __ldcw(a) ({ \ + unsigned __ret; \ + __asm__ __volatile__("ldcw 0(%1),%0" \ + : "=r" (__ret) : "r" (a)); \ + __ret; \ + }) + + #define __PA_LDCW_ALIGNMENT 16 + #define __ldcw_align(a) ({ \ + unsigned long __ret = (unsigned long) &(a); \ + __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \ + & ~(__PA_LDCW_ALIGNMENT - 1); \ + (volatile unsigned int *) __ret; \ + }) + + static inline int testandset (int *p) + { + extern unsigned int hppa_lock[4]; + volatile unsigned int *lock = __ldcw_align(hppa_lock[0]); + int old; + + while (__ldcw(lock)) + while (__ldcw(lock)) + /* spin */; + + old = *p; + *p = 1; + + *lock = 1; + + return old != 0; + } + #endif + static inline int testandset (int *p) + { + int old; + old = *p; + *p = 1; + return old != 0; + } + + #endif + #ifdef __ia64 #include <ia64intrin.h> Index: disas.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/disas.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** disas.c 23 Feb 2007 21:44:02 -0000 1.1.1.1 --- disas.c 4 Mar 2007 15:03:22 -0000 1.2 *************** *** 264,267 **** --- 264,269 ---- #elif defined(__m68k__) print_insn = print_insn_m68k; + #elif defined(__hppa__) + print_insn = print_insn_hppa; #else fprintf(out, "0x%lx: Asm output not supported on this arch\n", Index: cpu-all.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/cpu-all.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** cpu-all.h 23 Feb 2007 21:44:02 -0000 1.1.1.1 --- cpu-all.h 4 Mar 2007 15:03:22 -0000 1.2 *************** *** 963,966 **** --- 963,975 ---- } + #elif defined(__hppa__) + + static inline int64_t cpu_get_real_ticks(void) + { + int val; + asm volatile ("mfctl %%cr16, %0" : "=r"(val)); + return val; + } + #elif defined(__ia64) |
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From: Stuart B. <zu...@us...> - 2007-03-02 23:47:54
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv311 Modified Files: exec.h op.c translate.c Log Message: Most recent version, with better carry flag code and various cleanups. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** translate.c 27 Feb 2007 23:21:24 -0000 1.2 --- translate.c 2 Mar 2007 23:47:46 -0000 1.3 *************** *** 267,270 **** --- 267,282 ---- */ + /* two possible ways to do nullification + * easiest is probably to generate code to check the N flag on each insn + * (which also sucks) + * + * actually can use the DisasContext so that checking is only done + * where the insn could be anulled + */ + + /* possily anulled? */ + + /* if so, check N flag. if set, branch and clear flag */ + /* Major Opcodes */ switch(op) { *************** *** 435,442 **** break; case 0x26: /* UADDCM */ ! genn_op_uaddcm_T1_T0(); break; case 0x27: /* UADDCMT */ ! genn_op_uaddcmt_T1_T0(); break; case 0x28: /* ADDL */ --- 447,455 ---- break; case 0x26: /* UADDCM */ ! gen_com_T1(); ! gen_op_addl_T1_T0(); break; case 0x27: /* UADDCMT */ ! gen_op_uaddcmt_T1_T0(); break; case 0x28: /* ADDL */ *************** *** 545,549 **** gen_movl_T1_reg(r); gen_movl_imm_T0(im21); ! gen_op_add_T1_T0(); gen_movl_reg_T0(1); break; --- 558,562 ---- gen_movl_T1_reg(r); gen_movl_imm_T0(im21); ! gen_op_addl_T1_T0(); gen_movl_reg_T0(1); break; Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** op.c 27 Feb 2007 23:21:24 -0000 1.2 --- op.c 2 Mar 2007 23:47:46 -0000 1.3 *************** *** 2,6 **** * HPPA micro operations * ! * Copyright (c) 2005 Stuart brady <sd...@nt...> * * This library is free software; you can redistribute it and/or --- 2,6 ---- * HPPA micro operations * ! * Copyright (c) 2005 Stuart Brady <sd...@nt...> * * This library is free software; you can redistribute it and/or *************** *** 120,129 **** void OPPROTO op_mov_T0_GR0(void) { ! T0 = 0; } void OPPROTO op_mov_T1_GR0(void) { ! T1 = 0; } --- 120,129 ---- void OPPROTO op_mov_T0_GR0(void) { ! T0 = 0; } void OPPROTO op_mov_T1_GR0(void) { ! T1 = 0; } *************** *** 138,204 **** void OPPROTO op_mov_T0_im(void) { ! T0 = PARAM1; } void OPPROTO op_mov_T1_im(void) { ! T1 = PARAM1; } /* TODO: lazy PSW */ ! void OPPROTO op_addc_T1_T0(void) { ! uint32_t mask; ! uint32_t pswbit; ! int carry; ! int i; ! ! T0 += T1; ! /* add the carry */ ! if (env->psw & PSW_CB7) { ! T0 += 1; ! carry = 1; ! } else { ! carry = 0; ! } /* calculate carry flags */ ! i = 0; env->psw &= ~PSW_CB ! mask = 0xffffffff; ! pswbit = PSW_CB7; ! while(i < 8) { ! if(((T0 & mask) < (T1 & mask)) || ! (carry && ((T0 & mask) == (T1 & mask)))) ! env->psw |= pswbit; ! pswbit >>= 1; ! mask >>= 4; ! mask &= 0x0fffffff; ! i++; ! } } /* TODO: lazy PSW */ ! void OPPROTO op_add_T1_T0(void) { ! uint32_t mask; ! uint32_t pswbit; ! int i; T0 += T1; /* calculate carry flags */ ! i = 0; env->psw &= ~PSW_CB ! mask = 0xffffffff; ! pswbit = PSW_CB7; ! while(i < 8) { ! if((T0 & mask) < (T1 & mask)) ! env->psw |= pswbit; ! pswbit >>= 1; ! mask >>= 4; ! mask &= 0x0fffffff; ! i++; ! } /* gen_op_add_T1_imm(1) -- for ADDC and ADDCO */ --- 138,207 ---- void OPPROTO op_mov_T0_im(void) { ! T0 = PARAM1; } void OPPROTO op_mov_T1_im(void) { ! T1 = PARAM1; } + + /* computation instructions... page 169 PA1.1 specification */ + /* TODO: lazy PSW */ ! void OPPROTO op_add_T1_T0(void) { ! target_ulong carry; ! target_ulong tmp; + tmp = T0; + T0 += T1; + /* calculate carry flags */ ! carry = (tmp & T1) | ((tmp | T1) & ~T0); ! /* extract the MSB from each nibble */ ! /* axxxbxxxcxxxdxxxexxxfxxxgxxxhxxx */ ! carry >>= 3; /* 000axxxbxxxcxxxdxxxexxxfxxxgxxxh */ ! carry &= 0x11111111; /* 000a000b000c000d000e000f000g000h */ ! carry |= carry >> 3; /* 000a00ab00bc00cd00de00ef00fg00gh */ ! carry &= 0x03030303; /* 000000ab000000cd000000ef000000gh */ ! carry |= carry >> 6; /* 000000ab0000abcd000000ef0000efgh */ ! carry &= 0x000f000f; /* 000000000000abcd000000000000efgh */ ! carry |= carry >> 12; /* 000000000000abcd00000000abcdefgh */ ! carry &= 0x000000ff; /* 000000000000000000000000abcdefgh */ ! env->psw &= ~PSW_CB ! env->psw |= carry << PSW_CB7_SHIFT; } /* TODO: lazy PSW */ ! void OPPROTO op_addc_T1_T0(void) { ! target_ulong carry; ! target_ulong tmp; + tmp = T0; T0 += T1; + + /* add the carry */ + if (env->psw & PSW_CB7) { + T0 += 1; + } /* calculate carry flags */ ! carry = (tmp & T1) | ((tmp | T1) & ~T0); ! /* axxxbxxxcxxxdxxxexxxfxxxgxxxhxxx */ ! carry >>= 3; /* 000axxxbxxxcxxxdxxxexxxfxxxgxxxh */ ! carry &= 0x11111111; /* 000a000b000c000d000e000f000g000h */ ! carry |= carry >> 3; /* 000a00ab00bc00cd00de00ef00fg00gh */ ! carry &= 0x03030303; /* 000000ab000000cd000000ef000000gh */ ! carry |= carry >> 6; /* 000000ab0000abcd000000ef0000efgh */ ! carry &= 0x000f000f; /* 000000000000abcd000000000000efgh */ ! carry |= carry >> 12; /* 000000000000abcd00000000abcdefgh */ ! carry &= 0x000000ff; /* 000000000000000000000000abcdefgh */ ! env->psw &= ~PSW_CB ! env->psw |= carry << PSW_CB7_SHIFT; ! } /* gen_op_add_T1_imm(1) -- for ADDC and ADDCO */ *************** *** 206,211 **** /* set condition flags */ /* set nullify if condition met */ - } void OPPROTO op_addl_T1_T0(void) { --- 209,214 ---- /* set condition flags */ /* set nullify if condition met */ + /* add logical */ void OPPROTO op_addl_T1_T0(void) { *************** *** 245,248 **** --- 248,281 ---- } + /* TODO: lazy PSW */ + void OPPROTO op_subc_T1_T0(void) + { + target_ulong borrow; + target_ulong tmp; + + tmp = T0; + T0 -= T1; + + /* subtract the borrow */ + if (!(env->psw & PSW_CB7)) { + T0 -= 1; + } + + /* calculate carry/borrow flags */ + borrow = (~tmp & T1) | (~(tmp ^ T1) & T0); + /* axxxbxxxcxxxdxxxexxxfxxxgxxxhxxx */ + borrow >>= 3; /* 000axxxbxxxcxxxdxxxexxxfxxxgxxxh */ + borrow &= 0x11111111; /* 000a000b000c000d000e000f000g000h */ + borrow |= borrow >> 3; /* 000a00ab00bc00cd00de00ef00fg00gh */ + borrow &= 0x03030303; /* 000000ab000000cd000000ef000000gh */ + borrow |= borrow >> 6; /* 000000ab0000abcd000000ef0000efgh */ + borrow &= 0x000f000f; /* 000000000000abcd000000000000efgh */ + borrow |= borrow >> 12; /* 000000000000abcd00000000abcdefgh */ + borrow &= 0x000000ff; /* 000000000000000000000000abcdefgh */ + + env->psw &= ~PSW_CB + env->psw |= ~borrow << PSW_CB7_SHIFT; + } + void OPPROTO op_next_insn(void) { Index: exec.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/exec.h,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** exec.h 27 Feb 2007 23:20:43 -0000 1.1 --- exec.h 2 Mar 2007 23:47:46 -0000 1.2 *************** *** 2,6 **** * HPPA execution defines * ! * Copyright (c) 2005 Stuart Brady * Copyright (c) 2003 Fabrice Bellard * --- 2,6 ---- * HPPA execution defines * ! * Copyright (c) 2005 Stuart Brady <sd...@nt...> * Copyright (c) 2003 Fabrice Bellard * |
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From: Stuart B. <zu...@us...> - 2007-02-27 23:21:27
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv14538 Modified Files: cpu.h op.c translate.c Log Message: Updated code from 2006-06-10. Index: translate.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/translate.c,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** translate.c 27 Feb 2007 23:20:43 -0000 1.1 --- translate.c 27 Feb 2007 23:21:24 -0000 1.2 *************** *** 21,24 **** --- 21,34 ---- */ + #include "cpu.h" + #include "exec-all.h" + #include "disas.h" + + typedef struct DisasContext { + target_ulong iaoq[2]; + target_ulong iasq[2]; + struct TranslationBlock *tb; + } DisasContext; + static inline uint32_t field(uint32_t val, int start, int length) { val >>= start; *************** *** 246,250 **** int ext6; ! insn = ldl_code((uint8_t *)dc->pc); op = field(insn, 26, 6); --- 256,260 ---- int ext6; ! insn = ldl_code(dc->iaoq[0]); op = field(insn, 26, 6); *************** *** 642,646 **** case 0x24: /* COMICLR */ { ! uint32 r, t, c, f, im11; if (field(insn, 11, 1)) gen_op_undef_insn(); --- 652,656 ---- case 0x24: /* COMICLR */ { ! uint32_t r, t, c, f, im11; if (field(insn, 11, 1)) gen_op_undef_insn(); *************** *** 736,748 **** case 0x38: /* BE */ case 0x39: /* BLE */ break; case 0x3a: /* Branch */ { ! uint32_t ext3; ext3 = field(insn, 13, 3); switch(ext3) { case 0: /* BL */ case 2: /* BLR */ case 6: /* BV */ case 1: /* GATE */ --- 746,780 ---- case 0x38: /* BE */ case 0x39: /* BLE */ + { + uint32_t b, w1, s, w2, n, w; + b = field(insn, 21, 5); + w1 = field_signext(insn, 16, 5); + s = field(insn, 13, 3); + w2 = field(insn, 2, 11); + n = field(insn, 1, 1); + w = field(insn, 0, 1); + disp = (((((w1 << 11) | w2) << 1) | w) << 2); + /* */ break; + } case 0x3a: /* Branch */ { ! uint32_t t, w1, ext3, w2, n, disp; ext3 = field(insn, 13, 3); + t = field(insn, 21, 5); + w1 = field_signext(insn, 16, 5); + w2 = field(insn, 2, 11); + n = field(insn, 1, 1); + w = field(insn, 0, 1); + disp = (((((w1 << 11) | w2) << 1) | w) << 2); switch(ext3) { case 0: /* BL */ + /* generate (iaoq_next <- iaoq_front + disp + 8) */ + /* generate (copy iaoq_back + 4 into t) */ + /* if (n) generate (psw |= PSW_N); */ + break; case 2: /* BLR */ + /* if w == 0 ( ill_insn ) */ case 6: /* BV */ case 1: /* GATE */ Index: cpu.h =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/cpu.h,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** cpu.h 27 Feb 2007 23:20:43 -0000 1.1 --- cpu.h 27 Feb 2007 23:21:24 -0000 1.2 *************** *** 22,25 **** --- 22,28 ---- #define CPU_HPPA_H + #define TARGET_LONG_BITS 32 + #include "cpu-defs.h" + /* the shadow registers map to the following general registers */ int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 }; *************** *** 58,71 **** typedef struct CPUHPPAState { ! uint32_t gr[32]; /* General Registers */ ! uint32_t shr[7]; /* SHadow Registers */ ! uint32_t sr[8]; /* Space Registers */ ! uint32_t cr[32]; /* Control Registers */ ! /* uint32_t cpr[n][8]; */ /* Co-Processor Registers */ ! uint32_t fpr[32]; /* Floating-Point Registers */ ! ! uint32_t psw; /* Processor Status Word */ ! uint32_t iaoq[2]; /* Instruction Address Offset Queue */ ! uint32_t iasq[2]; /* Instruction Address Space Queue */ /* gr[0] : permanently 0 --- 61,76 ---- typedef struct CPUHPPAState { ! target_ulong gr[32]; /* General Registers */ ! target_ulong shr[7]; /* SHadow Registers */ ! uint32_t sr[8]; /* Space Registers */ ! uint32_t cr[32]; /* Control Registers */ ! #if 0 ! uint32_t cpr[n][8]; /* Co-Processor Registers */ ! #endif ! uint32_t fpr[32]; /* Floating-Point Registers */ ! ! uint32_t psw; /* Processor Status Word */ ! target_ulong iaoq[2]; /* Instruction Address Offset Queue */ ! uint32_t iasq[2]; /* Instruction Address Space Queue */ /* gr[0] : permanently 0 Index: op.c =================================================================== RCS file: /cvsroot/hppaqemu/hppaqemu/target-hppa/op.c,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** op.c 27 Feb 2007 23:20:43 -0000 1.1 --- op.c 27 Feb 2007 23:21:24 -0000 1.2 *************** *** 146,173 **** } ! void OPPROTO op_add_T1_T0(void) { ! uint32 src1; ! src1 = T0; T0 += T1; /* TODO: lazy PSW */ env->psw &= ~PSW_CB ! if((T0 & 0x0000000f) < (src1 & 0x0000000f)) ! env->psw |= PSW_CB0; ! if((T0 & 0x000000ff) < (src1 & 0x000000ff)) ! env->psw |= PSW_CB1; ! if((T0 & 0x00000fff) < (src1 & 0x00000fff)) ! env->psw |= PSW_CB2; ! if((T0 & 0x0000ffff) < (src1 & 0x0000ffff)) ! env->psw |= PSW_CB3; ! if((T0 & 0x000fffff) < (src1 & 0x000fffff)) ! env->psw |= PSW_CB4; ! if((T0 & 0x00ffffff) < (src1 & 0x00ffffff)) ! env->psw |= PSW_CB5; ! if((T0 & 0x0fffffff) < (src1 & 0x0fffffff)) ! env->psw |= PSW_CB6; ! if((T0 & 0xffffffff) < (src1 & 0xffffffff)) ! env->psw |= PSW_CB7; /* gen_op_add_T1_imm(1) -- for ADDC and ADDCO */ --- 146,204 ---- } ! /* TODO: lazy PSW */ ! void OPPROTO op_addc_T1_T0(void) { ! uint32_t mask; ! uint32_t pswbit; ! int carry; ! int i; ! T0 += T1; + /* add the carry */ + if (env->psw & PSW_CB7) { + T0 += 1; + carry = 1; + } else { + carry = 0; + } + + /* calculate carry flags */ + i = 0; + env->psw &= ~PSW_CB + mask = 0xffffffff; + pswbit = PSW_CB7; + while(i < 8) { + if(((T0 & mask) < (T1 & mask)) || + (carry && ((T0 & mask) == (T1 & mask)))) + env->psw |= pswbit; + pswbit >>= 1; + mask >>= 4; + mask &= 0x0fffffff; + i++; + } + } /* TODO: lazy PSW */ + void OPPROTO op_add_T1_T0(void) + { + uint32_t mask; + uint32_t pswbit; + int i; + + T0 += T1; + + /* calculate carry flags */ + i = 0; env->psw &= ~PSW_CB ! mask = 0xffffffff; ! pswbit = PSW_CB7; ! while(i < 8) { ! if((T0 & mask) < (T1 & mask)) ! env->psw |= pswbit; ! pswbit >>= 1; ! mask >>= 4; ! mask &= 0x0fffffff; ! i++; ! } /* gen_op_add_T1_imm(1) -- for ADDC and ADDCO */ |
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From: Stuart B. <zu...@us...> - 2007-02-27 23:20:46
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv14299 Added Files: cpu.h exec.h op.c op_mem.h op_template.h translate.c Log Message: Initial HPPA target code from 2005. --- NEW FILE: translate.c --- /* * HPPA translation * * Copyright (c) 2005 Stuart Brady <sd...@nt...> * Copyright (c) 2003 Thomas M. Ogrisegg <to...@fn...> * Copyright (c) 2003 Fabrice Bellard * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ static inline uint32_t field(uint32_t val, int start, int length) { val >>= start; val &= ~(~0 << length); return val; } static inline uint32_t field_signext(uint32_t val, int start, int length) { val >>= start; if (val & (1 << (length - 1))) val |= ~0 << length; else val &= ~(~0 << length); return val; } static inline uint32_t signext(uint32_t val, int length) { if (val & (1 << (length - 1))) val |= ~0 << length; return val; } static GenOpFunc *gen_op_movl_TN_reg[2][32] = { { gen_op_movl_gr0_T0, gen_op_movl_gr1_T0, gen_op_movl_gr2_T0, gen_op_movl_gr3_T0, gen_op_movl_gr4_T0, gen_op_movl_gr5_T0, gen_op_movl_gr6_T0, gen_op_movl_gr7_T0, gen_op_movl_gr8_T0, gen_op_movl_gr9_T0, gen_op_movl_gr10_T0, gen_op_movl_gr11_T0, gen_op_movl_gr12_T0, gen_op_movl_gr13_T0, gen_op_movl_gr14_T0, gen_op_movl_gr15_T0, gen_op_movl_gr16_T0, gen_op_movl_gr17_T0, gen_op_movl_gr18_T0, gen_op_movl_gr19_T0, gen_op_movl_gr20_T0, gen_op_movl_gr21_T0, gen_op_movl_gr22_T0, gen_op_movl_gr23_T0, gen_op_movl_gr24_T0, gen_op_movl_gr25_T0, gen_op_movl_gr26_T0, gen_op_movl_gr27_T0, gen_op_movl_gr28_T0, gen_op_movl_gr29_T0, gen_op_movl_gr30_T0, gen_op_movl_gr31_T0, }, { gen_op_movl_gr0_T1, gen_op_movl_gr1_T1, gen_op_movl_gr2_T1, gen_op_movl_gr3_T1, gen_op_movl_gr4_T1, gen_op_movl_gr5_T1, gen_op_movl_gr6_T1, gen_op_movl_gr7_T1, gen_op_movl_gr8_T1, gen_op_movl_gr9_T1, gen_op_movl_gr10_T1, gen_op_movl_gr11_T1, gen_op_movl_gr12_T1, gen_op_movl_gr13_T1, gen_op_movl_gr14_T1, gen_op_movl_gr15_T1, gen_op_movl_gr16_T1, gen_op_movl_gr17_T1, gen_op_movl_gr18_T1, gen_op_movl_gr19_T1, gen_op_movl_gr20_T1, gen_op_movl_gr21_T1, gen_op_movl_gr22_T1, gen_op_movl_gr23_T1, gen_op_movl_gr24_T1, gen_op_movl_gr25_T1, gen_op_movl_gr26_T1, gen_op_movl_gr27_T1, gen_op_movl_gr28_T1, gen_op_movl_gr29_T1, gen_op_movl_gr30_T1, gen_op_movl_gr31_T1, } }; static GenOpFunc *gen_op_movl_reg_TN[2][32] = { { gen_op_movl_T0_gr0, gen_op_movl_T0_gr1, gen_op_movl_T0_gr2, gen_op_movl_T0_gr3, gen_op_movl_T0_gr4, gen_op_movl_T0_gr5, gen_op_movl_T0_gr6, gen_op_movl_T0_gr7, gen_op_movl_T0_gr8, gen_op_movl_T0_gr9, gen_op_movl_T0_gr10, gen_op_movl_T0_gr11, gen_op_movl_T0_gr12, gen_op_movl_T0_gr13, gen_op_movl_T0_gr14, gen_op_movl_T0_gr15, gen_op_movl_T0_gr16, gen_op_movl_T0_gr17, gen_op_movl_T0_gr18, gen_op_movl_T0_gr19, gen_op_movl_T0_gr20, gen_op_movl_T0_gr21, gen_op_movl_T0_gr22, gen_op_movl_T0_gr23, gen_op_movl_T0_gr24, gen_op_movl_T0_gr25, gen_op_movl_T0_gr26, gen_op_movl_T0_gr27, gen_op_movl_T0_gr28, gen_op_movl_T0_gr29, gen_op_movl_T0_gr30, gen_op_movl_T0_gr31, }, { gen_op_movl_T1_gr0, gen_op_movl_T1_gr1, gen_op_movl_T1_gr2, gen_op_movl_T1_gr3, gen_op_movl_T1_gr4, gen_op_movl_T1_gr5, gen_op_movl_T1_gr6, gen_op_movl_T1_gr7, gen_op_movl_T1_gr8, gen_op_movl_T1_gr9, gen_op_movl_T1_gr10, gen_op_movl_T1_gr11, gen_op_movl_T1_gr12, gen_op_movl_T1_gr13, gen_op_movl_T1_gr14, gen_op_movl_T1_gr15, gen_op_movl_T1_gr16, gen_op_movl_T1_gr17, gen_op_movl_T1_gr18, gen_op_movl_T1_gr19, gen_op_movl_T1_gr20, gen_op_movl_T1_gr21, gen_op_movl_T1_gr22, gen_op_movl_T1_gr23, gen_op_movl_T1_gr24, gen_op_movl_T1_gr25, gen_op_movl_T1_gr26, gen_op_movl_T1_gr27, gen_op_movl_T1_gr28, gen_op_movl_T1_gr29, gen_op_movl_T1_gr30, gen_op_movl_T1_gr31, } }; static GenOpFunc1 *gen_op_movl_TN_im[2] = { gen_op_movl_T0_im, gen_op_movl_T1_im, }; #define gen_op_ldst(name) gen_op_##name##_raw() static inline void gen_movl_imm_TN(int reg, int val) { gen_op_movl_TN_im[reg](val); } static inline void gen_movl_imm_T0(int val) { gen_movl_imm_T0(0, val); } static inline void gen_movl_imm_T1(int val) { gen_movl_imm_T1(1, val); } static inline void gen_movl_reg_TN(int reg, int t) { if (reg) gen_op_movl_reg_TN[t][reg] (); else gen_movl_imm_TN(t, 0); } static inline void gen_movl_reg_T0(int reg) { gen_movl_reg_TN(reg, 0); } static inline void gen_movl_reg_T1(int reg) { gen_movl_reg_TN(reg, 1); } static inline void gen_movl_TN_reg(int reg, int t) { if (reg) gen_op_movl_TN_reg[t][reg] (); } static inline void gen_movl_T0_reg(int reg) { gen_movl_TN_reg(reg, 0); } static inline void gen_movl_T1_reg(int reg) { gen_movl_TN_reg(reg, 1); } static void disas_hppa_insn(DisasContext * dc) { unsigned int insn; int op; int ext6; insn = ldl_code((uint8_t *)dc->pc); op = field(insn, 26, 6); /* TODO: * branches * nullification * conditions * carry * refactoring */ /* Major Opcodes */ switch(op) { case 0x00: /* System_op */ { uint32_t ext8; ext8 = field(insn, 5, 6); switch(ext8) { case 0x00: /* BREAK */ case 0x20: /* SYNC, SYNCDMAA */ case 0x60: /* RFI */ case 0x65: /* RFIR */ case 0x6b: /* SSM */ case 0x73: /* RSM */ case 0xc3: /* MTSM */ case 0x85: /* LDSID */ case 0xc1: /* MTSP */ case 0x25: /* MFSP */ case 0xc2: /* MTCTL */ case 0x45: /* MFCTL */ break; default: gen_op_undef_insn(); break; } break; } case 0x01: /* Mem_Mgmt */ { uint32_t ext5; ext5 = field(insn, 0, 5); if(!field(insn, 12, 1)) { uint32_t ext7; ext7 = field(insn, 6, 7); swtich(ext7) { case 0x01: /* IITLBA */ case 0x00: /* IITLBP */ case 0x08: /* PITLB */ case 0x09: /* PITLBE */ case 0x0a: /* FIC */ case 0x0b: /* FICE */ break; default: gen_op_undef_insn(); break; } } else { uint32_t ext7; ext8 = field(insn, 6, 8); { case 0x40: /* IDTLBP */ case 0x41: /* IDTLBA */ case 0x48: /* PDTLB */ case 0x49: /* PDTLBE */ case 0x4a: /* FDC */ case 0x4b: /* FDCE */ case 0x4e: /* PDC */ case 0x46: /* PROBER */ case 0xc6: /* PROBERI */ case 0x47: /* PROBEW */ case 0xc7: /* PROBEWI */ case 0x4d: /* LPA */ case 0x4c: /* LCI */ break; default: gen_op_undef_insn(); break; } } break; } case 0x02: /* Arith/Log */ { uint32_t t, r1, r2; r2 = field(insn, 21, 5); r1 = field(insn, 16, 5); ext6 = field(insn, 6, 6); t = field(insn, 0, 5); gen_movl_reg_T0(r1); gen_movl_reg_T1(r2); /* Opcode Extensions */ switch(ext6) { case 0x18: /* ADD */ gen_op_add_T1_T0(); break; case 0x38: /* ADDO */ gen_op_movl_T0_T2(); gen_op_addo_T1_T0(); /* if sign(T0) != sign(T1) && sign(T1) == sign(T2) overflow(); */ break; case 0x1C: /* ADDC */ gen_op_addc_T1_T0(); break; case 0x3C: /* ADDCO */ gen_op_addco_T1_T0(); break; case 0x19: /* SH1ADD */ gen_op_shift_T0(1); gen_op_add_T1_T0(); break; case 0x39: /* SH1ADDO */ gen_op_shift_T0(1); gen_op_addo_T1_T0(); break; case 0x1a: /* SH2ADD */ gen_op_shift_T0(2); gen_op_add_T1_T0(); break; case 0x3a: /* SH2ADDO */ gen_op_shift_T0(2); gen_op_addo_T1_T0(); break; case 0x1b: /* SH3ADD */ gen_op_shift_T0(3); gen_op_add_T1_T0(); break; case 0x3b: /* SH3ADDO */ gen_op_shift_T0(3); gen_op_addo_T1_T0(); break; case 0x10: /* SUB */ gen_op_sub_T1_T0(); break; case 0x30: /* SUBO */ gen_op_subo_T1_T0(); break; case 0x13: /* SUBT */ gen_op_subt_T1_T0(); break; case 0x33: /* SUBTO */ gen_op_subto_T1_T0(); break; case 0x14: /* SUBB */ gen_op_subb_T1_T0(); break; case 0x34: /* SUBBO */ gen_op_subbo_T1_T0(); break; case 0x11: /* DS */ gen_op_ds_T1_T0(); break; case 0x00: /* ANDCM */ gen_op_andcm_T1_T0(); break; case 0x08: /* AND */ gen_op_and_T1_T0(); break; case 0x09: /* OR */ gen_op_or_T1_T0(); break; case 0x0A: /* XOR */ gen_op_xor_T1_T0(); break; case 0x0E: /* UXOR */ gen_op_uxor_T1_T0(); break; case 0x22: /* COMCLR */ gen_op_comclr_T1_T0(); break; case 0x26: /* UADDCM */ genn_op_uaddcm_T1_T0(); break; case 0x27: /* UADDCMT */ genn_op_uaddcmt_T1_T0(); break; case 0x28: /* ADDL */ gen_op_addl_T1_T0(); break; case 0x29: /* SH1ADDL */ gen_op_shift_T0(1); gen_op_addl_T1_T0(); break; case 0x2A: /* SH2ADDL */ gen_op_shift_T0(2); gen_op_addl_T1_T0(); break; case 0x2B: /* SH3ADDL */ gen_op_shift_T0(3); gen_op_addl_T1_T0(); break; case 0x2E: /* DCOR */ if (r1 != 0) gen_op_undef_insn(); else gen_op_dcor_T0(); break; case 0x2F: /* IDCOR */ if (r1 != 0) gen_op_undef_insn(); else gen_op_idcor_T0(); break; default: /* Undefined Instruction */ gen_op_undef_insn(); break; } gen_movl_T0_reg(t); break; } case 0x03: /* Index_Mem */ { uint32_t ext4; ext4 = field(insn, 6, 4); if(field(insn, 12, 1)) { switch(ext4) { case 0x00: /* LDBX */ case 0x01: /* LDHX */ case 0x02: /* LDWX */ case 0x06: /* LDWAX */ case 0x07: /* LDCWX */ break; } } else { switch(ext4) { case 0x00: /* LDBS */ case 0x01: /* LDHS */ case 0x02: /* LDWS */ case 0x06: /* LDWAS */ case 0x07: /* LDCWS */ case 0x08: /* STBS */ case 0x09: /* STHS */ case 0x0a: /* STWS */ case 0x0c: /* STBYS */ case 0x0e: /* STWAS */ break; } } break; } case 0x04: /* SPOPn */ break; case 0x05: /* DIAG */ case 0x06: /* FMPYADD */ break; case 0x08: /* LDIL */ { uint32_t t, im21; t = field(insn, 21, 5); if(t) { im21 = field(insn, 0, 21) << (32 - 21); gen_movl_imm_T0(im21); gen_movl_reg_T0(t); } break; } case 0x09: /* Copr_w */ if(!field(insn, 12, 1)) if(!field(insn, 9, 1)) /* CLDWX */ {} else /* CSTWX */ {} else if(!field(insn, 9, 1)) /* CLDWS */ {} else /* CSTWS */ {} break; case 0x0a: /* ADDIL */ { uint32_t r, im21; r = field(insn, 21, 5); im21 = field(insn, 0, 21) << (32 - 21); gen_movl_T1_reg(r); gen_movl_imm_T0(im21); gen_op_add_T1_T0(); gen_movl_reg_T0(1); break; } case 0x0b: /* Copr_dw */ if(!field(insn, 12, 1)) if(!field(insn, 9, 1)) /* CLDDX */ {} else /* CSTDX */ {} else if(!field(insn, 9, 1)) /* CLDDS */ {} else /* CSTDS */ {} break; case 0x0c: /* COPR */ break; case 0x0d: /* LDO - Load Offset */ { uint32_t b, t, im14; b = field(insn, 21, 5); t = field(insn, 16, 5); im14 = field_signext(insn, 0, 14); gen_movl_reg_T0(b); gen_movl_imm_T1(im14); gen_add_T1_T0(); gen_movl_T0_reg(t); break; } case 0x0e: /* Float */ case 0x0f: /* Product Specific */ break; case 0x10: /* LDB */ case 0x11: /* LDH */ case 0x12: /* LDW */ { uint32_t b, t, s, im14; b = field(insn, 21, 5); t = field(insn, 16, 5); s = field(insn, 14, 2); im14 = field_signext(insn, 0, 14); gen_movl_reg_T0(b); gen_movl_imm_T1(s); /* gen_op_space_sel_T0_T1(); */ gen_movl_imm_T1(im14); gen_add_T1_T0(); switch(op) { case 0x10: /* LDB */ gen_op_ldst(ldb); break; case 0x11: /* LDH */ gen_op_ldst(ldh); break; case 0x12: /* LDW */ gen_op_ldst(ldw); break; } gen_movl_T1_reg(t); break; } case 0x13: /* LDWM */ break; case 0x18: /* STB */ case 0x19: /* STH */ case 0x1a: /* STW */ { uint32_t b, r, s, im14; b = field(insn, 21, 5); t = field(insn, 16, 5); s = field(insn, 14, 2); im14 = field_signext(insn, 0, 14); gen_movl_reg_T0(b); gen_movl_imm_T1(s); /* gen_op_space_sel_T0_T1(); */ gen_movl_imm_T1(im14); gen_add_T1_T0(); gen_movl_reg_T1(r); switch(op) { case 0x18: /* STB */ gen_op_ldst(stb); break; case 0x19: /* STH */ gen_op_ldst(sth); break; case 0x1a: /* STW */ gen_op_ldst(stw); break; } } case 0x1b: /* STWM */ case 0x20: /* COMBT */ case 0x21: /* COMIBT */ case 0x22: /* COMBF */ case 0x23: /* COMIBF */ break; case 0x24: /* COMICLR */ { uint32 r, t, c, f, im11; if (field(insn, 11, 1)) gen_op_undef_insn(); else { r = field(insn, 21, 5); t = field(insn, 16, 5); c = field(insn, 13, 3); f = field(insn, 12, 1); im11 = field_signext(insn, 0, 11); gen_movl_reg_T0(r); gen_movl_imm_T1(im11); gen_op_add_T1_T0(); gen_movl_imm_T0(0); gen_movl_TO_reg(t); break; } } case 0x25: /* SUBI, SUBIO */ { r = field(insn, 21, 5); t = field(insn, 16, 5); im11 = field_signext(insn, 0, 11); gen_movl_reg_T0(r); op_sub_T1_T0(); break; } case 0x26: /* FPYSUB */ case 0x28: /* ADDBT */ case 0x29: /* ADDIBT */ case 0x2a: /* ADDBF */ case 0x2b: /* ADDIBF */ break; case 0x2c: /* ADDIT, ADDIOT */ case 0x2d: /* ADDI, ADDIO */ { uint32_t r, t, im11; r = field(insn, 21, 5); t = field(insn, 16, 5); im11 = field_signext(insn, 0, 11); gen_movl_reg_T0(r); gen_movl_imm_T0(im11); if(!field(insn, 11, 1)) gen_op_addit_T0(); else gen_op_addito_T0(); gen_movl_T0_reg(t); break; } case 0x30: /* BVB */ case 0x31: /* BB */ case 0x32: /* MOVB */ case 0x33: /* MOVIB */ break; case 0x34: /* Extract */ { uint32_t ext3; ext3 = field(insn, 10, 3); switch(ext3) { case 0: /* VSHD */ case 2: /* SHD */ case 4: /* VEXTRU */ case 5: /* VEXTRS */ case 6: /* EXTRU */ case 7: /* EXTRS */ break; } break; } case 0x35: /* Deposit */ { uint32_t ext3; ext3 = field(insn, 10, 3); switch(ext3) { case 0: /* VZDEP */ case 1: /* VDEP */ case 2: /* ZDEP */ case 3: /* DEP */ case 4: /* VZDEPI */ case 5: /* VDEPI */ case 6: /* ZDEPI */ case 7: /* DEPI */ break; } break; } case 0x38: /* BE */ case 0x39: /* BLE */ break; case 0x3a: /* Branch */ { uint32_t ext3; ext3 = field(insn, 13, 3); switch(ext3) { case 0: /* BL */ case 2: /* BLR */ case 6: /* BV */ case 1: /* GATE */ break; } break; } default: /* Illegal Instruction */ gen_op_ill_insn(); break; } } --- NEW FILE: cpu.h --- /* * HPPA virtual CPU header * * Copyright (c) 2005 Stuart Brady <sd...@nt...> * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef CPU_HPPA_H #define CPU_HPPA_H /* the shadow registers map to the following general registers */ int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 }; #define PSW_Y 0x00000001 #define PSW_Z 0x00000002 #define PSW_W 0x00000010 #define PSW_E 0x00000020 #define PSW_S 0x00000040 #define PSW_T 0x00000080 #define PSW_H 0x00000100 #define PSW_L 0x00000200 #define PSW_N 0x00000400 #define PSW_X 0x00000800 #define PSW_B 0x00001000 #define PSW_C 0x00002000 #define PSW_V 0x00004000 #define PSW_M 0x00008000 #define PSW_CB 0x00ff0000 #define PSW_CB0 0x00010000 #define PSW_CB1 0x00020000 #define PSW_CB2 0x00040000 #define PSW_CB3 0x00080000 #define PSW_CB4 0x00100000 #define PSW_CB5 0x00200000 #define PSW_CB6 0x00400000 #define PSW_CB7 0x00800000 #define PSW_O 0x01000000 #define PSW_G 0x02000000 #define PSW_F 0x04000000 #define PSW_R 0x08000000 #define PSW_Q 0x10000000 #define PSW_P 0x20000000 #define PSW_D 0x40000000 #define PSW_I 0x80000000 typedef struct CPUHPPAState { uint32_t gr[32]; /* General Registers */ uint32_t shr[7]; /* SHadow Registers */ uint32_t sr[8]; /* Space Registers */ uint32_t cr[32]; /* Control Registers */ /* uint32_t cpr[n][8]; */ /* Co-Processor Registers */ uint32_t fpr[32]; /* Floating-Point Registers */ uint32_t psw; /* Processor Status Word */ uint32_t iaoq[2]; /* Instruction Address Offset Queue */ uint32_t iasq[2]; /* Instruction Address Space Queue */ /* gr[0] : permanently 0 * gr[1] : target for ADDIL * gr[31] : link register for BLE */ } CPUHPPAState; #endif --- NEW FILE: op.c --- /* * HPPA micro operations * * Copyright (c) 2005 Stuart brady <sd...@nt...> * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "exec.h" #define REGNAME gr1 #define REG (env->gr[1]) #include "op_template.h" #define REGNAME gr2 #define REG (env->gr[2]) #include "op_template.h" #define REGNAME gr2 #define REG (env->gr[2]) #include "op_template.h" #define REGNAME gr3 #define REG (env->gr[3]) #include "op_template.h" #define REGNAME gr4 #define REG (env->gr[4]) #include "op_template.h" #define REGNAME gr5 #define REG (env->gr[5]) #include "op_template.h" #define REGNAME gr6 #define REG (env->gr[6]) #include "op_template.h" #define REGNAME gr7 #define REG (env->gr[7]) #include "op_template.h" #define REGNAME gr8 #define REG (env->gr[8]) #include "op_template.h" #define REGNAME gr9 #define REG (env->gr[9]) #include "op_template.h" #define REGNAME gr10 #define REG (env->gr[10]) #include "op_template.h" #define REGNAME gr11 #define REG (env->gr[11]) #include "op_template.h" #define REGNAME gr12 #define REG (env->gr[12]) #include "op_template.h" #define REGNAME gr13 #define REG (env->gr[13]) #include "op_template.h" #define REGNAME gr14 #define REG (env->gr[14]) #include "op_template.h" #define REGNAME gr15 #define REG (env->gr[15]) #include "op_template.h" #define REGNAME gr16 #define REG (env->gr[16]) #include "op_template.h" #define REGNAME gr17 #define REG (env->gr[17]) #include "op_template.h" #define REGNAME gr18 #define REG (env->gr[18]) #include "op_template.h" #define REGNAME gr19 #define REG (env->gr[19]) #include "op_template.h" #define REGNAME gr20 #define REG (env->gr[20]) #include "op_template.h" #define REGNAME gr21 #define REG (env->gr[21]) #include "op_template.h" #define REGNAME gr22 #define REG (env->gr[22]) #include "op_template.h" #define REGNAME gr23 #define REG (env->gr[23]) #include "op_template.h" #define REGNAME gr24 #define REG (env->gr[24]) #include "op_template.h" #define REGNAME gr25 #define REG (env->gr[25]) #include "op_template.h" #define REGNAME gr26 #define REG (env->gr[26]) #include "op_template.h" #define REGNAME gr27 #define REG (env->gr[27]) #include "op_template.h" #define REGNAME gr28 #define REG (env->gr[28]) #include "op_template.h" #define REGNAME gr29 #define REG (env->gr[29]) #include "op_template.h" #define REGNAME gr30 #define REG (env->gr[30]) #include "op_template.h" #define REGNAME gr31 #define REG (env->gr[31]) #include "op_template.h" void OPPROTO op_mov_T0_GR0(void) { T0 = 0; } void OPPROTO op_mov_T1_GR0(void) { T1 = 0; } void OPPROTO op_mov_GR0_T0(void) { } void OPPROTO op_mov_GR0_T1(void) { } void OPPROTO op_mov_T0_im(void) { T0 = PARAM1; } void OPPROTO op_mov_T1_im(void) { T1 = PARAM1; } void OPPROTO op_add_T1_T0(void) { uint32 src1; src1 = T0; T0 += T1; /* TODO: lazy PSW */ env->psw &= ~PSW_CB if((T0 & 0x0000000f) < (src1 & 0x0000000f)) env->psw |= PSW_CB0; if((T0 & 0x000000ff) < (src1 & 0x000000ff)) env->psw |= PSW_CB1; if((T0 & 0x00000fff) < (src1 & 0x00000fff)) env->psw |= PSW_CB2; if((T0 & 0x0000ffff) < (src1 & 0x0000ffff)) env->psw |= PSW_CB3; if((T0 & 0x000fffff) < (src1 & 0x000fffff)) env->psw |= PSW_CB4; if((T0 & 0x00ffffff) < (src1 & 0x00ffffff)) env->psw |= PSW_CB5; if((T0 & 0x0fffffff) < (src1 & 0x0fffffff)) env->psw |= PSW_CB6; if((T0 & 0xffffffff) < (src1 & 0xffffffff)) env->psw |= PSW_CB7; /* gen_op_add_T1_imm(1) -- for ADDC and ADDCO */ /* overflow trap for ADDO */ /* set condition flags */ /* set nullify if condition met */ } void OPPROTO op_addl_T1_T0(void) { T0 += T1; /* if condition met, env->psw |= PSW_N */ } void OPPROTO op_add2_T1_T0(void) { T0 += T1; } void OPPROTO op_comclr_T1_T0(void) { /* T0 - T1; */ T0 = 0; } void OPPROTO op_or_T1_T0(void) { T0 |= T1; } void OPPROTO op_xor_T1_T0(void) { T0 ^= T1; } void OPPROTO op_and_T1_T0(void) { T0 &= T1; } void OPPROTO op_andcm_T1_T0(void) { T0 &= ~T1; } void OPPROTO op_next_insn(void) { iaoq[0] = iaoq[1]; iasq[0] = iasq[1]; iaoq[1] += 4; } #include "op_mem.h" --- NEW FILE: op_template.h --- /* * HPPA micro operations (templates for various register related * operations) * * Copyright (c) 2003 Fabrice Ballard * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ void OPPROTO glue(op_movl_T0_, REGNAME)(void) { T0 = REG; } void OPPROTO glue(op_movl_T1_, REGNAME)(void) { T1 = REG; } void OPPROTO glue(glue(op_movl_, REGNAME), _T0)(void) { REG = T0; } void OPPROTO glue(glue(op_movl_, REGNAME), _T1)(void) { REG = T1; } #undef REG #undef REGNAME --- NEW FILE: op_mem.h --- #define HPPA_LD_OP(name, qp) \ void OPPROTO glue(glue(op_, name), _raw)(void) \ { \ T1 = glue(qp, _raw)((void *)T0); \ } HPPA_LD_OP(ldw, ldl); HPPA_LD_OP(ldh, lduw); HPPA_LD_OP(ldb, ldub); #define HPPA_ST_OP(name, qp) \ void OPPROTO glue(glue(op_, name), _raw)(void) \ { \ glue(qp, _raw)((void *)T0, T1); \ } HPPA_ST_OP(stw, stl); HPPA_ST_OP(sth, stuw); HPPA_ST_OP(stb, stub); --- NEW FILE: exec.h --- /* * HPPA execution defines * * Copyright (c) 2005 Stuart Brady * Copyright (c) 2003 Fabrice Bellard * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include "dyngen-exec.h" register struct CPUHPPAState *env asm(AREG0); register uint32_t T0 asm(AREG1); register uint32_t T1 asm(AREG2); register uint32_t T2 asm(AREG3); #include "cpu.h" |
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From: Stuart B. <zu...@us...> - 2007-02-27 23:14:10
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Update of /cvsroot/hppaqemu/hppaqemu/target-hppa In directory sc8-pr-cvs5.sourceforge.net:/tmp/cvs-serv12051/target-hppa Log Message: Directory /cvsroot/hppaqemu/hppaqemu/target-hppa added to the repository |
