I will begin by designing the datapath.
I worked five hours today (9/29/03) - designing
=====
Today will be spent creating the schematic.
I've worked two hours so far today (1:30-3:30pm 10/1/03)
I've worked an additional five hours today (9pm-2am 10/1/03-10/2/03)
=====
Today, I will finish the schematic excluding connections for hazardDetect and dataForwarding (multiplier will also be excluded since it is not ready yet)
I worked four hours today (6:30-10:30pm 10/2/03)
=====
Today, I will generate cpu.v from the schematic and make sure it is in proper condition to begin testing.
I worked three hours today (10pm-1am 10/3/03-10/4/03)
=====
Today, I will begin working on dataForwarding
I've worked four hours so far today (2:30-6:30pm 10/9/03) - This time was spent updating the datapath, which is now finalized and tested. I will begin working on dataForwarding when I return to lab.
I've worked an additional three hours today (7:00-10:00pm 10/9/03) - I began writing the dataForwarding module
=====
I have been notified that testing on the datapath excluding hazard detection and forwarding is complete. I will now wire these two modules into the datapath and schematic.
I worked for one hour on 10/10/03. [Start and end time not recorded.]
=====
A bug was found in the datapath - I will come to lab to address this issue.
I've worked for two hours today (3:00pm-5:00pm 10/12/03)
The bug was in the dataForwarding logic. The issue was that according to ch. 6 in the textbook, forwarding from the writeback register should not occur if
the rd field in the mem stage is the same as the rd field in the wb stage. However, I neglected to check the regWr control signal in the mem stage.
This bug is now fixed just by checking to be sure regWr (in the mem stage) is high when the rd fields are the same.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
I kept my "online" notebook on my U: drive for lab4. Starting lab5, I will keep my notebook on these forums. Below is what I stored on my U: drive:
--------------------------------------------------
I will begin by designing the datapath.
I worked five hours today (9/29/03) - designing
=====
Today will be spent creating the schematic.
I've worked two hours so far today (1:30-3:30pm 10/1/03)
I've worked an additional five hours today (9pm-2am 10/1/03-10/2/03)
=====
Today, I will finish the schematic excluding connections for hazardDetect and dataForwarding (multiplier will also be excluded since it is not ready yet)
I worked four hours today (6:30-10:30pm 10/2/03)
=====
Today, I will generate cpu.v from the schematic and make sure it is in proper condition to begin testing.
I worked three hours today (10pm-1am 10/3/03-10/4/03)
=====
Today, I will begin working on dataForwarding
I've worked four hours so far today (2:30-6:30pm 10/9/03) - This time was spent updating the datapath, which is now finalized and tested. I will begin working on dataForwarding when I return to lab.
I've worked an additional three hours today (7:00-10:00pm 10/9/03) - I began writing the dataForwarding module
=====
I have been notified that testing on the datapath excluding hazard detection and forwarding is complete. I will now wire these two modules into the datapath and schematic.
I worked for one hour on 10/10/03. [Start and end time not recorded.]
=====
A bug was found in the datapath - I will come to lab to address this issue.
I've worked for two hours today (3:00pm-5:00pm 10/12/03)
The bug was in the dataForwarding logic. The issue was that according to ch. 6 in the textbook, forwarding from the writeback register should not occur if
the rd field in the mem stage is the same as the rd field in the wb stage. However, I neglected to check the regWr control signal in the mem stage.
This bug is now fixed just by checking to be sure regWr (in the mem stage) is high when the rd fields are the same.