Alan has requested that I take over on testWriteBuffer. I will now begin reading the spec for writeBuffer, as well as reading as much of the files writeBuffer.v and testWriteBuffer.v as I need to proceed.
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At some point tonight, my attention was diverted away from this project. When I last worked on it, the test was successful (meaning as far as I could tell, writeBuffer worked as it was explained to me).
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I am in charge of modifying the lab4 datapath to accommode the changes in instmem and in datamem, and to include the arbitrator and the memory controller. I am currently in the process of investigating how easy it will be to migrate from the lab4 schematic or if it will be desirable to just modify the verilog file.
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I have managed to combine the lab 4 files and the lab 5 files into a single directory. I have also managed to update the schematic using the lab 5 files. I will now take a sleep break. When I return in the morning, I plan on hooking up all of the new signals. I am done for tonight.
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I am about to leave lab. The four memory modules have been wired into the datapath. The only thing missing is the control signal memRead. I WILL be in EARLY tomorrow morning to modify controller.v and complete the datapath. Integrated simulation testing can begin tomorrow morning once this is done.
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I just spent an hour updating the schematic. (Most of this time was due to the fact that the dates on the files got messed up when daylight savings time ended :-( The rest was making the modifications that brandon and alan already made to the verilog version.
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This is my Lab 5 online notebook. Comments will be made here about what tasks I am working on.
Alan has requested that I take over on testWriteBuffer. I will now begin reading the spec for writeBuffer, as well as reading as much of the files writeBuffer.v and testWriteBuffer.v as I need to proceed.
Note, I have to change all of the addresses so they are 23 bits, since that's the interface that writeBuffer has.
At some point tonight, my attention was diverted away from this project. When I last worked on it, the test was successful (meaning as far as I could tell, writeBuffer worked as it was explained to me).
I am in charge of modifying the lab4 datapath to accommode the changes in instmem and in datamem, and to include the arbitrator and the memory controller. I am currently in the process of investigating how easy it will be to migrate from the lab4 schematic or if it will be desirable to just modify the verilog file.
I have managed to combine the lab 4 files and the lab 5 files into a single directory. I have also managed to update the schematic using the lab 5 files. I will now take a sleep break. When I return in the morning, I plan on hooking up all of the new signals. I am done for tonight.
I've been in lab since 7:30pm tonight. I have been and will continue working on getting all of the memory modules hooked into the datapath correctly.
I am about to leave lab. The four memory modules have been wired into the datapath. The only thing missing is the control signal memRead. I WILL be in EARLY tomorrow morning to modify controller.v and complete the datapath. Integrated simulation testing can begin tomorrow morning once this is done.
Okay, so I arrived in lab later than I had planned yesterday. Anyway, I will now look into completing the datapath and committing it to cvs.
The datapath has been completed and is ready to be tested. Let's hope it goes well.
I just spent an hour updating the schematic. (Most of this time was due to the fact that the dates on the files got messed up when daylight savings time ended :-( The rest was making the modifications that brandon and alan already made to the verilog version.
memRead is the memToReg in execution stage
Note: This post was a reply to my post in the CPU thread made on 2003-10-22 01:28.
Oops, the time should be 22:07 rather than 01:28