----------------------------------------------
# Reading C:/Modeltech_5.7d/tcl/vsim/pref.tcl
# Updating type .vhd file registration.
# Updating type .v file registration.
# Updating type .wlf file registration.
# // ModelSim SE Viewer 5.7d May 2 2003
# //
# // Copyright Model Technology, a Mentor Graphics Corporation company, 2003
# // All Rights Reserved.
# // UNPUBLISHED, LICENSED SOFTWARE.
# // CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# // PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
project open U:/ModSim.mpf
# Loading project ModSim
vsim work.testBranchControl
# vsim work.testBranchControl
# Loading work.testBranchControl
# Loading work.branchControl
# Loading work.alu
# ** Warning: (vsim-3010) [TSCALE] - Module 'alu' has a `timescale directive in effect, but previous modules do not.
# Region: /testBranchControl/a
run 20us
# Beginning Tests
# Testing beq
# x SUB x = x
# 1 SUB 1 = 0
# 1 SUB 0 = 1
# Testing bne
# 1 SUB 1 = 0
# 1 SUB 0 = 1
# Testing bgez
# 4294967295 SUB 0 = 4294967295
# ERROR at time 12: 4294967295 to 0 = 1, beq=0, bez=1, equal=0, rt=1, regA31=1
#
# Testing bltz
# 1 SUB 0 = 1
# ERROR at time 14: 1 to 0 = 1, beq=0, bez=1, equal=0, rt=0, regA31=0
#
# Testing bltz
# 0 SUB 0 = 0
# 4294967295 SUB 0 = 4294967295
# Tests Done
vsim work.testSltControl
# vsim work.testSltControl
# Loading work.testSltControl
# Loading work.sltControl
# Loading work.alu
# ** Warning: (vsim-3010) [TSCALE] - Module 'alu' has a `timescale directive in effect, but previous modules do not.
# Region: /testSltControl/a
run 20us
# Beginning Tests
# Testing unsigned slt.
#
# x SUB x = x
# 1 SUB 1 = 0
# 1 SUB 2 = 4294967295
# 2 SUB 1 = 1
# Testing signed slt.
#
# 4294967295 SUB 1 = 4294967294
# 0 SUB 4294967294 = 2
# 4294967294 SUB 1 = 4294967293
# 4294967295 SUB 4294967295 = 0
# 0 SUB 4294967295 = 1
# Tests Done
# should be equal to address 0 = 0, 32, 2048, 1
# Beginning Tests
# Writing to DP0
#
# Invalid Address Warning #4: Warning in testDatamem.mem.ram.tempBlock.inst at time 0: Block memory address x (xxxxxxxxxxx) invalid. Valid depth configured as 0 to 2047
# Writing to DP1
#
# Reading from DP0
#
# Reading from DP1
#
# Writing to ioBus
#
# Reading from ioBus
#
# Writing to dead memory
#
# Writing to dead memory
#
# Writing to dead memory
#
# Reading from dead memory
#
# Reading from dead memory
#
# Reading from dead memory
#
# Writing to memory
#
# Writing to memory
#
# Writing to memory
#
# Reading from memory
#
# Reading from memory
#
# Error at time 34: memory read failed.
#
# Reading from memory
#
# Error at time 36: memory read failed.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
- branch was fixed by mod the module and test now works.
- memeory test hangs .. problem is likely due to the imposibility of tesating the memory module. Think the test was good though (for IO and datamem wrapper)
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
----------------------------------------------
# Reading C:/Modeltech_5.7d/tcl/vsim/pref.tcl
# Updating type .vhd file registration.
# Updating type .v file registration.
# Updating type .wlf file registration.
# // ModelSim SE Viewer 5.7d May 2 2003
# //
# // Copyright Model Technology, a Mentor Graphics Corporation company, 2003
# // All Rights Reserved.
# // UNPUBLISHED, LICENSED SOFTWARE.
# // CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# // PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
project open U:/ModSim.mpf
# Loading project ModSim
vsim work.testBranchControl
# vsim work.testBranchControl
# Loading work.testBranchControl
# Loading work.branchControl
# Loading work.alu
# ** Warning: (vsim-3010) [TSCALE] - Module 'alu' has a `timescale directive in effect, but previous modules do not.
# Region: /testBranchControl/a
run 20us
# Beginning Tests
# Testing beq
# x SUB x = x
# 1 SUB 1 = 0
# 1 SUB 0 = 1
# Testing bne
# 1 SUB 1 = 0
# 1 SUB 0 = 1
# Testing bgez
# 4294967295 SUB 0 = 4294967295
# ERROR at time 12: 4294967295 to 0 = 1, beq=0, bez=1, equal=0, rt=1, regA31=1
#
# Testing bltz
# 1 SUB 0 = 1
# ERROR at time 14: 1 to 0 = 1, beq=0, bez=1, equal=0, rt=0, regA31=0
#
# Testing bltz
# 0 SUB 0 = 0
# 4294967295 SUB 0 = 4294967295
# Tests Done
vsim work.testSltControl
# vsim work.testSltControl
# Loading work.testSltControl
# Loading work.sltControl
# Loading work.alu
# ** Warning: (vsim-3010) [TSCALE] - Module 'alu' has a `timescale directive in effect, but previous modules do not.
# Region: /testSltControl/a
run 20us
# Beginning Tests
# Testing unsigned slt.
#
# x SUB x = x
# 1 SUB 1 = 0
# 1 SUB 2 = 4294967295
# 2 SUB 1 = 1
# Testing signed slt.
#
# 4294967295 SUB 1 = 4294967294
# 0 SUB 4294967294 = 2
# 4294967294 SUB 1 = 4294967293
# 4294967295 SUB 4294967295 = 0
# 0 SUB 4294967295 = 1
# Tests Done
# should be equal to address 0 = 0, 32, 2048, 1
# Beginning Tests
# Writing to DP0
#
# Invalid Address Warning #4: Warning in testDatamem.mem.ram.tempBlock.inst at time 0: Block memory address x (xxxxxxxxxxx) invalid. Valid depth configured as 0 to 2047
# Writing to DP1
#
# Reading from DP0
#
# Reading from DP1
#
# Writing to ioBus
#
# Reading from ioBus
#
# Writing to dead memory
#
# Writing to dead memory
#
# Writing to dead memory
#
# Reading from dead memory
#
# Reading from dead memory
#
# Reading from dead memory
#
# Writing to memory
#
# Writing to memory
#
# Writing to memory
#
# Reading from memory
#
# Reading from memory
#
# Error at time 34: memory read failed.
#
# Reading from memory
#
# Error at time 36: memory read failed.
- branch was fixed by mod the module and test now works.
- memeory test hangs .. problem is likely due to the imposibility of tesating the memory module. Think the test was good though (for IO and datamem wrapper)