vsim work.testIncrementer
# vsim work.testIncrementer
# Loading work.testIncrementer
# Loading work.incrementer
# ** Warning: (vsim-3015) U:/lab4/testIncrementer.v(7): [PCDPC] - Port size (30 or 30) does not match connection size (32) for port 'in0'.
# Region: /testIncrementer/inc
# ** Warning: (vsim-3015) U:/lab4/testIncrementer.v(7): [PCDPC] - Port size (30 or 30) does not match connection size (32) for port 'out0'.
# Region: /testIncrementer/inc
run 100us
# Beginning Tests
# Tests Done
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- i think the test is still a pass, as it may not be possible to test the mem module.
# Loading work.testDatamem
# Loading work.datamem
# Loading work.sramblock2048
# Loading work.ramblock2048b
# Loading work.BLKMEMSP_V4_0
# ** Warning: (vsim-3010) [TSCALE] - Module 'BLKMEMSP_V4_0' has a `timescale directive in effect, but previous modules do not.
# Region: /testDatamem/mem/ram/tempBlock/inst
# Loading work.io
# ** Warning: (vsim-3009) [TSCALE] - Module 'io' does not have a `timescale directive in effect, but previous modules do.
# Region: /testDatamem/mem/io
# ** Warning: (vsim-3015) U:/lab4/dataMem.v(20): [PCDPC] - Port size (11 or 11) does not match connection size (32) for port 'addr'.
# Region: /testDatamem/mem/ram
# ** Warning: (vsim-3015) U:/lab4/sramblock2048.v(25): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'en'.
# Region: /testDatamem/mem/ram/tempBlock
run 100us
# should be equal to address 0 = 0, 32, 2048, 1
# Beginning Tests
# Writing to DP0
#
# Invalid Address Warning #4: Warning in testDatamem.mem.ram.tempBlock.inst at time 0: Block memory address x (xxxxxxxxxxx) invalid. Valid depth configured as 0 to 2047
# Writing to DP1
#
# Reading from DP0
#
# Reading from DP1
#
# Writing to ioBus
#
# Reading from ioBus
#
# Writing to dead memory
#
# Writing to dead memory
#
# Writing to dead memory
#
# Reading from dead memory
#
# Reading from dead memory
#
# Reading from dead memory
#
# Writing to memory
#
# Writing to memory
#
# Writing to memory
#
# Reading from memory
#
# Reading from memory
#
# Error at time 34: memory read failed.
#
# Reading from memory
#
# Error at time 36: memory read failed.
#
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Thursday 2-5
- finished componnet testing. Added some random tests.
Fri 2-6:30 , 8 - 9
- began writing test cases for Cpu.
- wrote test for Forwarding, everything worked as per spec.
- began writing test cases for pipeline.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Testing to do:
adder done
incrementer
datamem / io done
multiplier error on load
branchControl error in module
sltControl done
equal
Modules to do:
hazardDetect (8 hr)
shifter(3 hr)
initial testing of data path without data hazard, write corner cases testing for each instruction in mips (7 hr),
lab report (3 hr)
-shifter is written
-shifter tested ok
-shifter compyled in Syn Pro with no errors/warnings
i will be testing hazard ... not writing it.
-equal has been tested
run 100us
# Beginning Tests
# Tests Done
- incrementer has been tested
vsim work.testIncrementer
# vsim work.testIncrementer
# Loading work.testIncrementer
# Loading work.incrementer
# ** Warning: (vsim-3015) U:/lab4/testIncrementer.v(7): [PCDPC] - Port size (30 or 30) does not match connection size (32) for port 'in0'.
# Region: /testIncrementer/inc
# ** Warning: (vsim-3015) U:/lab4/testIncrementer.v(7): [PCDPC] - Port size (30 or 30) does not match connection size (32) for port 'out0'.
# Region: /testIncrementer/inc
run 100us
# Beginning Tests
# Tests Done
- datamem and io have been tested.
- the tesk hung while testing the mem part.
- i think the test is still a pass, as it may not be possible to test the mem module.
# Loading work.testDatamem
# Loading work.datamem
# Loading work.sramblock2048
# Loading work.ramblock2048b
# Loading work.BLKMEMSP_V4_0
# ** Warning: (vsim-3010) [TSCALE] - Module 'BLKMEMSP_V4_0' has a `timescale directive in effect, but previous modules do not.
# Region: /testDatamem/mem/ram/tempBlock/inst
# Loading work.io
# ** Warning: (vsim-3009) [TSCALE] - Module 'io' does not have a `timescale directive in effect, but previous modules do.
# Region: /testDatamem/mem/io
# ** Warning: (vsim-3015) U:/lab4/dataMem.v(20): [PCDPC] - Port size (11 or 11) does not match connection size (32) for port 'addr'.
# Region: /testDatamem/mem/ram
# ** Warning: (vsim-3015) U:/lab4/sramblock2048.v(25): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'en'.
# Region: /testDatamem/mem/ram/tempBlock
run 100us
# should be equal to address 0 = 0, 32, 2048, 1
# Beginning Tests
# Writing to DP0
#
# Invalid Address Warning #4: Warning in testDatamem.mem.ram.tempBlock.inst at time 0: Block memory address x (xxxxxxxxxxx) invalid. Valid depth configured as 0 to 2047
# Writing to DP1
#
# Reading from DP0
#
# Reading from DP1
#
# Writing to ioBus
#
# Reading from ioBus
#
# Writing to dead memory
#
# Writing to dead memory
#
# Writing to dead memory
#
# Reading from dead memory
#
# Reading from dead memory
#
# Reading from dead memory
#
# Writing to memory
#
# Writing to memory
#
# Writing to memory
#
# Reading from memory
#
# Reading from memory
#
# Error at time 34: memory read failed.
#
# Reading from memory
#
# Error at time 36: memory read failed.
#
- testing of branchs is done
- it initialy did not work
# Reading C:/Modeltech_5.7d/tcl/vsim/pref.tcl
# Updating type .vhd file registration.
# Updating type .v file registration.
# Updating type .wlf file registration.
# // ModelSim SE Viewer 5.7d May 2 2003
# //
# // Copyright Model Technology, a Mentor Graphics Corporation company, 2003
# // All Rights Reserved.
# // UNPUBLISHED, LICENSED SOFTWARE.
# // CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# // PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
project open U:/ModSim.mpf
# Loading project ModSim
vsim work.testBranchControl
# vsim work.testBranchControl
# Loading work.testBranchControl
# Loading work.branchControl
# Loading work.alu
# ** Warning: (vsim-3010) [TSCALE] - Module 'alu' has a `timescale directive in effect, but previous modules do not.
# Region: /testBranchControl/a
run 20us
# Beginning Tests
# Testing beq
# x SUB x = x
# 1 SUB 1 = 0
# 1 SUB 0 = 1
# Testing bne
# 1 SUB 1 = 0
# 1 SUB 0 = 1
# Testing bgez
# 4294967295 SUB 0 = 4294967295
# ERROR at time 12: 4294967295 to 0 = 1, beq=0, bez=1, equal=0, rt=1, regA31=1
#
# Testing bltz
# 1 SUB 0 = 1
# ERROR at time 14: 1 to 0 = 1, beq=0, bez=1, equal=0, rt=0, regA31=0
#
# Testing bltz
# 0 SUB 0 = 0
# 4294967295 SUB 0 = 4294967295
# Tests Done
- i modified the code to diffentiat the bne better
vsim work.testBranchControl
# vsim work.testBranchControl
# Loading work.testBranchControl
# Loading work.branchControl
# Loading work.alu
# ** Warning: (vsim-3010) [TSCALE] - Module 'alu' has a `timescale directive in effect, but previous modules do not.
# Region: /testBranchControl/a
run 100us
# Beginning Tests
# Testing beq
# x SUB x = x
# 1 SUB 1 = 0
# 1 SUB 0 = 1
# Testing bne
# 1 SUB 1 = 0
# 1 SUB 0 = 1
# Testing bgez
# 4294967295 SUB 0 = 4294967295
# Testing bltz
# 1 SUB 0 = 1
# 0 SUB 0 = 0
# 4294967295 SUB 0 = 4294967295
# Tests Done
- slt is tested ok
vsim work.testSltControl
# vsim work.testSltControl
# Loading work.testSltControl
# Loading work.sltControl
# Loading work.alu
# ** Warning: (vsim-3010) [TSCALE] - Module 'alu' has a `timescale directive in effect, but previous modules do not.
# Region: /testSltControl/a
run 20us
# Beginning Tests
# Testing unsigned slt.
#
# x SUB x = x
# 1 SUB 1 = 0
# 1 SUB 2 = 4294967295
# 2 SUB 1 = 1
# Testing signed slt.
#
# 4294967295 SUB 1 = 4294967294
# 0 SUB 4294967294 = 2
# 4294967294 SUB 1 = 4294967293
# 4294967295 SUB 4294967295 = 0
# 0 SUB 4294967295 = 1
# Tests Done
- the adder is tested, the original test worked with no mods
vsim work.testAdder
# vsim work.testAdder
# Loading work.testAdder
# Loading work.adder
# ** Warning: (vsim-3015) U:/lab4/testAdder.v(10): [PCDPC] - Port size (30 or 30) does not match connection size (32) for port 'in0'.
# Region: /testAdder/adder
# ** Warning: (vsim-3015) U:/lab4/testAdder.v(10): [PCDPC] - Port size (30 or 30) does not match connection size (32) for port 'in1'.
# Region: /testAdder/adder
# ** Warning: (vsim-3015) U:/lab4/testAdder.v(10): [PCDPC] - Port size (30 or 30) does not match connection size (33) for port 'sum'.
# Region: /testAdder/adder
run 100us
# Testing 1000 Random Cases
# 0: 12153524 + c0895e81 = zZ29e93a5
# 1: 8484d609 + b1f05663 = zZ6752c6c
# 2: 06b97b0d + 46df998d = zZd99149a
# 3: b2c28465 + 89375212 = zZbf9d677
# 4: 00f3e301 + 06d7cd0d = zZ7cbb00e
# 5: 3b23f176 + 1e8dcd3d = zZ9b1beb3
# 6: 76d457ed + 462df78c = zZd024f79
# 7: 7cfde9f9 + e33724c6 = zZ0350ebf
# 8: e2f784c5 + d513d2aa = zZ80b576f
# 9: 72aff7e5 + bbd27277 = zZe826a5c
# 10: 8932d612 + 47ecdb8f = zZ11fb1a1
# 11: 793069f2 + e77696ce = zZ0a700c0
# 12: f4007ae8 + e2ca4ec5 = zZ6cac9ad
....
# 996: 1dc2173b + c3d11687 = zZ1932dc2
# 997: 81c9a603 + d0b432a1 = zZ27dd8a4
# 998: 76e9dfed + f68984ed = zZd7364da
# 999: eac812d5 + 3b726d76 = zZ63a804b
# End Random Tests
# Beginning Border Tests
# 1001: ffffffff + ffffffff = zZffffffe
# 1002: ffffffff + 00000000 = zZfffffff
# 1003: 00000000 + ffffffff = zZfffffff
# 1004: 0fffffff + 00000001 = zZ0000000
Thursday 2-5
- finished componnet testing. Added some random tests.
Fri 2-6:30 , 8 - 9
- began writing test cases for Cpu.
- wrote test for Forwarding, everything worked as per spec.
- began writing test cases for pipeline.