- it seems that we are implementing 8 word burst from the getgo ... right?
- if so does writeEnable stay high for 8 cycles?
- why is there a hit & a miss (hit = ~miss) i dont think there is anything in between....
- why does the cache not have a 32 bit input, how is the arbiter suposed to get data into the cache if there is a miss without input (do you want to dual porpose the address lines ???)
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///////////////////////////////////////////////
// my spec for this thing
//
//
// reads:
// - upon read going high the tag and valid will be checked and hit/miss will come async
// - one cycle later the data from that adress will arrive (ignore it if there was a miss)
//
// write
// - sync on cycle writeEnb goes high: data in will be written to the address iff the target
// block is valid, ow the data is ignored
//
// burst
// - sync on clock cycle burstEnb goes high and next 7 clocks : data will be written to each
// value in the target block, starting with the first word in the block
//
// dataIn : read on clock edges
//
// dataOut : passed from memory, output is from address of prev cycle
//
// miss : async : will be set as sson as addres is input to cache
//
// rst : will set all valid bit to zero -> no 1st time read to given addr should hit
//
// addr : there are 256 blocks before overlap
//
// things to test ?
// - try mixing reads, writes and burst ... it should handle em
// - try multiple bursts in sequence, the internal counter should reset.
// - see what happens if burst are broken off half way. the next burst should still work.
//
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# begin testing at time $t 2400
# Testing burst write to cache with 8 word
# writing to addr 000021, with data = 00000005 at time 2400000
# 2400000: addr = 4, tag = 2829, valid = 0.
# 2600000: address = 000021, ramAddr = 020, re = 0, we = 0, be = 1, din = 00000005, dout = 00000000, miss = 0.
#
# writing to addr 000022, with data = 00000006 at time 2800000
# 3000000: address = 000022, ramAddr = 021, re = 0, we = 0, be = 1, din = 00000006, dout = 00000005, miss = 0.
#
# writing to addr 000023, with data = 00000007 at time 3200000
# 3400000: address = 000023, ramAddr = 022, re = 0, we = 0, be = 1, din = 00000007, dout = 00000006, miss = 0.
#
# writing to addr 000024, with data = 00000008 at time 3600000
# 3800000: address = 000024, ramAddr = 023, re = 0, we = 0, be = 1, din = 00000008, dout = 00000007, miss = 0.
#
# writing to addr 000025, with data = 00000009 at time 4000000
run 2us
# 4200000: address = 000025, ramAddr = 024, re = 0, we = 0, be = 1, din = 00000009, dout = 00000008, miss = 0.
#
# writing to addr 000026, with data = 0000000a at time 4400000
# 4600000: address = 000026, ramAddr = 025, re = 0, we = 0, be = 1, din = 0000000a, dout = 00000009, miss = 0.
#
# writing to addr 000027, with data = 0000000b at time 4800000
# 5000000: address = 000027, ramAddr = 026, re = 0, we = 0, be = 1, din = 0000000b, dout = 0000000a, miss = 0.
#
# writing to addr 000028, with data = 0000000c at time 5200000
# 5400000: address = 000028, ramAddr = 02f, re = 0, we = 0, be = 1, din = 0000000c, dout = 0000000b, miss = 0.
#
# 5600000: addr = 5, tag = 2445, valid = 0.
# 5800000: address = 000028, ramAddr = 028, re = 0, we = 0, be = 0, din = 0000000d, dout = 0000000c, miss = 0.
#
# End of testing burst
# Testing read
# 6000000: addr = 5, tag = 2445, valid = 0.
run 2us
# 6200000: address = 000020, ramAddr = 020, re = 1, we = 0, be = 0, din = 0000000e, dout = 00000000, miss = 1.
#
# 6600000: address = 000021, ramAddr = 021, re = 1, we = 0, be = 0, din = 0000000f, dout = 00000005, miss = 1.
#
# 7000000: address = 000022, ramAddr = 022, re = 1, we = 0, be = 0, din = 00000010, dout = 00000006, miss = 1.
#
# 7400000: address = 000023, ramAddr = 023, re = 1, we = 0, be = 0, din = 00000011, dout = 00000007, miss = 1.
#
# 7800000: address = 000024, ramAddr = 024, re = 1, we = 0, be = 0, din = 00000012, dout = 00000008, miss = 1.
#
run 2us
# 8200000: address = 000025, ramAddr = 025, re = 1, we = 0, be = 0, din = 00000013, dout = 00000009, miss = 1.
#
# 8600000: address = 000026, ramAddr = 026, re = 1, we = 0, be = 0, din = 00000014, dout = 0000000a, miss = 1.
#
# 9000000: address = 000027, ramAddr = 027, re = 1, we = 0, be = 0, din = 00000015, dout = 0000000b, miss = 1.
#
# ERROR: i = 7 data out from memory = 00000000, data from buffer = 0000000c, miss = 1
# 9400000: address = 000020, ramAddr = 020, re = 1, we = 0, be = 0, din = 00000016, dout = 00000000, miss = 1.
#
# ERROR: miss = 1, should be low
# end of testing read burst
# 9800000: address = 000020, ramAddr = 020, re = 1, we = 0, be = 0, din = 00000017, dout = 00000005, miss = 1.
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PLease exstend ONLY the thread for the task whic hyou have information about
Write Cache
I have questions
- it seems that we are implementing 8 word burst from the getgo ... right?
- if so does writeEnable stay high for 8 cycles?
- why is there a hit & a miss (hit = ~miss) i dont think there is anything in between....
- why does the cache not have a 32 bit input, how is the arbiter suposed to get data into the cache if there is a miss without input (do you want to dual porpose the address lines ???)
Yes we are implementing 8 word burst READ.
yes.
Yes, it does seem redundant. If you do not see a need then please only keep MISS.
Yes I will update the design doc meomentarily. Please feel free to tell me modifications to the design doc as you run into issues.
For the 8 word burst, at the moment you receive a readEnable, you'll get a 256 bit package, which is byte alligned on whatever you're expecting.
Also, if you could make it so cache will return a the value of the address 1 cycle after a readenable, that might simplify the memory interface.
since the cache handles both writes of blocks and write of values being stored new signals are needed
- burstEnb : for bursts
- writeEnb : for regular single word writes
///////////////////////////////////////////////
// my spec for this thing
//
//
// reads:
// - upon read going high the tag and valid will be checked and hit/miss will come async
// - one cycle later the data from that adress will arrive (ignore it if there was a miss)
//
// write
// - sync on cycle writeEnb goes high: data in will be written to the address iff the target
// block is valid, ow the data is ignored
//
// burst
// - sync on clock cycle burstEnb goes high and next 7 clocks : data will be written to each
// value in the target block, starting with the first word in the block
//
// dataIn : read on clock edges
//
// dataOut : passed from memory, output is from address of prev cycle
//
// miss : async : will be set as sson as addres is input to cache
//
// rst : will set all valid bit to zero -> no 1st time read to given addr should hit
//
// addr : there are 256 blocks before overlap
//
// things to test ?
// - try mixing reads, writes and burst ... it should handle em
// - try multiple bursts in sequence, the internal counter should reset.
// - see what happens if burst are broken off half way. the next burst should still work.
//
- the miss signal will now be alligned with the output of the data from a memory read.
- if its a hit then the memory is good, o.w. the data is invalid.
- its exspected that the miss signal will stall the pipeline.
- when the miss clears, the data that is being output should be valid.
write 2-way Associativity
# begin testing at time $t 2400
# Testing burst write to cache with 8 word
# writing to addr 000021, with data = 00000005 at time 2400000
# 2400000: addr = 4, tag = 2829, valid = 0.
# 2600000: address = 000021, ramAddr = 020, re = 0, we = 0, be = 1, din = 00000005, dout = 00000000, miss = 0.
#
# writing to addr 000022, with data = 00000006 at time 2800000
# 3000000: address = 000022, ramAddr = 021, re = 0, we = 0, be = 1, din = 00000006, dout = 00000005, miss = 0.
#
# writing to addr 000023, with data = 00000007 at time 3200000
# 3400000: address = 000023, ramAddr = 022, re = 0, we = 0, be = 1, din = 00000007, dout = 00000006, miss = 0.
#
# writing to addr 000024, with data = 00000008 at time 3600000
# 3800000: address = 000024, ramAddr = 023, re = 0, we = 0, be = 1, din = 00000008, dout = 00000007, miss = 0.
#
# writing to addr 000025, with data = 00000009 at time 4000000
run 2us
# 4200000: address = 000025, ramAddr = 024, re = 0, we = 0, be = 1, din = 00000009, dout = 00000008, miss = 0.
#
# writing to addr 000026, with data = 0000000a at time 4400000
# 4600000: address = 000026, ramAddr = 025, re = 0, we = 0, be = 1, din = 0000000a, dout = 00000009, miss = 0.
#
# writing to addr 000027, with data = 0000000b at time 4800000
# 5000000: address = 000027, ramAddr = 026, re = 0, we = 0, be = 1, din = 0000000b, dout = 0000000a, miss = 0.
#
# writing to addr 000028, with data = 0000000c at time 5200000
# 5400000: address = 000028, ramAddr = 02f, re = 0, we = 0, be = 1, din = 0000000c, dout = 0000000b, miss = 0.
#
# 5600000: addr = 5, tag = 2445, valid = 0.
# 5800000: address = 000028, ramAddr = 028, re = 0, we = 0, be = 0, din = 0000000d, dout = 0000000c, miss = 0.
#
# End of testing burst
# Testing read
# 6000000: addr = 5, tag = 2445, valid = 0.
run 2us
# 6200000: address = 000020, ramAddr = 020, re = 1, we = 0, be = 0, din = 0000000e, dout = 00000000, miss = 1.
#
# 6600000: address = 000021, ramAddr = 021, re = 1, we = 0, be = 0, din = 0000000f, dout = 00000005, miss = 1.
#
# 7000000: address = 000022, ramAddr = 022, re = 1, we = 0, be = 0, din = 00000010, dout = 00000006, miss = 1.
#
# 7400000: address = 000023, ramAddr = 023, re = 1, we = 0, be = 0, din = 00000011, dout = 00000007, miss = 1.
#
# 7800000: address = 000024, ramAddr = 024, re = 1, we = 0, be = 0, din = 00000012, dout = 00000008, miss = 1.
#
run 2us
# 8200000: address = 000025, ramAddr = 025, re = 1, we = 0, be = 0, din = 00000013, dout = 00000009, miss = 1.
#
# 8600000: address = 000026, ramAddr = 026, re = 1, we = 0, be = 0, din = 00000014, dout = 0000000a, miss = 1.
#
# 9000000: address = 000027, ramAddr = 027, re = 1, we = 0, be = 0, din = 00000015, dout = 0000000b, miss = 1.
#
# ERROR: i = 7 data out from memory = 00000000, data from buffer = 0000000c, miss = 1
# 9400000: address = 000020, ramAddr = 020, re = 1, we = 0, be = 0, din = 00000016, dout = 00000000, miss = 1.
#
# ERROR: miss = 1, should be low
# end of testing read burst
# 9800000: address = 000020, ramAddr = 020, re = 1, we = 0, be = 0, din = 00000017, dout = 00000005, miss = 1.