Hey Brandon, I just looked over the design doc, you are making arbitrator too complicated as the smart controller. Stall should be detect by the hazardDetect, I will build mechanisms in the dataCache to generate the necessary signal to signal a stall. Since there are different types of stall, we will need someone else to test hazardDetect. It will simplify arbitractor a lot.
WriteBuffer is more complicated than I thought, it doesn't overwrite data if they are written to memory already, there is no reason to. It has to send out the address to memory also, writeBuffer has 2 additional ports, dataToMemory and addrToMemory. It can handle both a read and readNext at the same time, since readNext doesn't suppiled an address. It's more efficient this way and it will simplify arbitrator.
Essentially, the arbitrator is a conflict resolutor. It will decide who gets access to the memory. WriteBuffer, cache and hazardDetect will handle the rest. It will not take you a long time to design it.
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The arbitrater the data will feed into both dataCache and instCache. Arbiter will send a writeEnb sign to either data or inst. The writeEnb signal is coming from the memory and should remain high until the last cycle for 8 cycle. A writeDone should be send to the cache at that point. The signals will be AND with a signal from arbiter, that decides whether the signal is going to dataCache or instCache. This way, we don't have to mux the data, we only have to control the signal for writing to the cache.
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Jason is going to write directCache.
I will handle the writeBuffer.
It took me about 3 hours to write the basic version of writeBuffer, which is not very efficient. I need to go back to write a better writeBuffer.
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I started working on writeBuffer since 3 pm. It's still not done yet. I plan to spend another hour to implement writeBuffer to handle writing to the cache.
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started working on fixing bugs in writeBuffer
fixed wiring signals in dataMem
meeting with Brandon, Jason and Alan to discuss the overall design and interface
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# Testing burst write to cache with 8 word to address 000045
# i = 0,writing to addr 000045, with data = 0000001e at time 12400000
# i = 1,writing to addr 000045, with data = 0000001f at time 12800000
# i = 2,writing to addr 000045, with data = 00000020 at time 13200000
# i = 3,writing to addr 000045, with data = 00000021 at time 13600000
# i = 4,writing to addr 000045, with data = 00000022 at time 14000000
# i = 5,writing to addr 000045, with data = 00000023 at time 14400000
# i = 6,writing to addr 000045, with data = 00000024 at time 14800000
run 5us
# i = 7,writing to addr 000045, with data = 00000025 at time 15200000
# ERROR: data out from cache = 00000023, data from buffer = 0000001f, miss = 0
# Testing burst write to cache with 8 word to address 000042, which should be overwritten
# i = 0,writing to addr 000042, with data = 00000029 at time 16800000
# i = 1,writing to addr 000042, with data = 0000002a at time 17200000
# i = 2,writing to addr 000042, with data = 0000002b at time 17600000
# i = 3,writing to addr 000042, with data = 0000002c at time 18000000
# i = 4,writing to addr 000042, with data = 0000002d at time 18400000
# i = 5,writing to addr 000042, with data = 0000002e at time 18800000
# i = 6,writing to addr 000042, with data = 0000002f at time 19200000
# i = 7,writing to addr 000042, with data = 00000030 at time 19600000
run 5us
# ERROR: addr = 000042, data out from cache = 0000002b, expect = 0000002e, miss = 0
# ERROR: addr = 000042, data out from cache = 0000002b, expect = 00000020, miss = 0
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another thing we can do for arbitractor is have the datamem hold the address until miss goes low, so arbitrator don't need to latch in the value and since the cache is latching in the value anyway, we can save some registers and simplified the logic a little bit
To handle the situation when we have a sw to addr 4, and then a lw to addr 3. Notice they are in the same block, but different address within the block. When we do an update from memory, it will check with wrBuffer to see if the address coming in is already in the wrBuffer already, if it is we will use the data from wrBuffer to input to the cache.
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discuss the project design with Alan and Brandon
we layout the interface between cache and memory controller and write buffer
I have a good idea on how to implement write buffer and cache.
Brandon wants to do the read only part first. He didn't even want me to write the writeBuffer.
I think the hard part is to handle the write and read at the same time, and we should start working on them as early as possible.
start working on the cache and writeBuffer
finishe them before the end of today
Hey Brandon, I just looked over the design doc, you are making arbitrator too complicated as the smart controller. Stall should be detect by the hazardDetect, I will build mechanisms in the dataCache to generate the necessary signal to signal a stall. Since there are different types of stall, we will need someone else to test hazardDetect. It will simplify arbitractor a lot.
WriteBuffer is more complicated than I thought, it doesn't overwrite data if they are written to memory already, there is no reason to. It has to send out the address to memory also, writeBuffer has 2 additional ports, dataToMemory and addrToMemory. It can handle both a read and readNext at the same time, since readNext doesn't suppiled an address. It's more efficient this way and it will simplify arbitrator.
Essentially, the arbitrator is a conflict resolutor. It will decide who gets access to the memory. WriteBuffer, cache and hazardDetect will handle the rest. It will not take you a long time to design it.
backlog
I finished writing the skelton for directCache.
I wrote the basic writeBuffer, but I found a design fault. I need to go back and fix writeBuffer to handle write more efficiently.
The arbitrater the data will feed into both dataCache and instCache. Arbiter will send a writeEnb sign to either data or inst. The writeEnb signal is coming from the memory and should remain high until the last cycle for 8 cycle. A writeDone should be send to the cache at that point. The signals will be AND with a signal from arbiter, that decides whether the signal is going to dataCache or instCache. This way, we don't have to mux the data, we only have to control the signal for writing to the cache.
Jason is going to write directCache.
I will handle the writeBuffer.
It took me about 3 hours to write the basic version of writeBuffer, which is not very efficient. I need to go back to write a better writeBuffer.
I started working on writeBuffer since 3 pm. It's still not done yet. I plan to spend another hour to implement writeBuffer to handle writing to the cache.
I just finished the writeBuffer.v. Spec is in the module.
WriteBuffer can handle readNext to the memory and write at the same time, no need to stall the cpu.
I am going to start working on dataMem and instMem later.
Goal: wrapper files for dataMem and instMem
testBench for memController
currently the cache doesn't output the address to memory, who's going to handle that
address to memory is 23 bits wide, need to adjust tag file accordingly
who's inputting the address to cache
I just finished updating datamem and instmem
started working on fixing bugs in writeBuffer
fixed wiring signals in dataMem
meeting with Brandon, Jason and Alan to discuss the overall design and interface
just modified hazardDetect.v to handle the new hazards
found a bug in cache, the address feeding into the ram is not correct
direct cache failed the basic test, writing more complicated test cases
I just finished updating instMem and dataMem to handle burst mode and write back correctly
i found another bug in directCache
# Testing burst write to cache with 8 word to address 000045
# i = 0,writing to addr 000045, with data = 0000001e at time 12400000
# i = 1,writing to addr 000045, with data = 0000001f at time 12800000
# i = 2,writing to addr 000045, with data = 00000020 at time 13200000
# i = 3,writing to addr 000045, with data = 00000021 at time 13600000
# i = 4,writing to addr 000045, with data = 00000022 at time 14000000
# i = 5,writing to addr 000045, with data = 00000023 at time 14400000
# i = 6,writing to addr 000045, with data = 00000024 at time 14800000
run 5us
# i = 7,writing to addr 000045, with data = 00000025 at time 15200000
# ERROR: data out from cache = 00000023, data from buffer = 0000001f, miss = 0
# Testing burst write to cache with 8 word to address 000042, which should be overwritten
# i = 0,writing to addr 000042, with data = 00000029 at time 16800000
# i = 1,writing to addr 000042, with data = 0000002a at time 17200000
# i = 2,writing to addr 000042, with data = 0000002b at time 17600000
# i = 3,writing to addr 000042, with data = 0000002c at time 18000000
# i = 4,writing to addr 000042, with data = 0000002d at time 18400000
# i = 5,writing to addr 000042, with data = 0000002e at time 18800000
# i = 6,writing to addr 000042, with data = 0000002f at time 19200000
# i = 7,writing to addr 000042, with data = 00000030 at time 19600000
run 5us
# ERROR: addr = 000042, data out from cache = 0000002b, expect = 0000002e, miss = 0
# ERROR: addr = 000042, data out from cache = 0000002b, expect = 00000020, miss = 0
I am done with test cache.
finished datamem.v, instmem.v, writebuffer.v,
hazarddetect.v, testCache.v
another thing we can do for arbitractor is have the datamem hold the address until miss goes low, so arbitrator don't need to latch in the value and since the cache is latching in the value anyway, we can save some registers and simplified the logic a little bit
To handle the situation when we have a sw to addr 4, and then a lw to addr 3. Notice they are in the same block, but different address within the block. When we do an update from memory, it will check with wrBuffer to see if the address coming in is already in the wrBuffer already, if it is we will use the data from wrBuffer to input to the cache.
9 hours today working on the project
fixing datamem to handle miss properly
Jason is confused on the test cases
spent 2 hours fixing datamem, instmem and testCache.v
miss is still not working correctly from cache