I found another bug in the data path, we should be calculating the address of Pc+4 + immed, and pc +8. Since we pipeline the pc, we are seq to pc+8 for regular address.
The ori bug is fixed in the controller.
we can use luts to implement a shifter, but the CAD automatically does that for us.
a mux 4 is faster because of dedicated logic
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fixed the bug in monitor, fixed the jr after lw bug in hazardDetect, it now stalls the pipeline,
need to fix dataForwarding to get rid of the 2 extra signals.
fixed the bug the corner.s in simulatation
there is still a bug in corner.s on the board
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Goal finish design doc tonight by 8 pm
If possible, finish controller.
I still need to look at controller to double check
aluControl is done
design doc is done
working with the group to put everything together
we are behind the schedule
groups need to read the design doc and follow the design doc
correct the design doc to fix any errors in the input
shifter is not compilable
Jason, take a look at >>>
datapath, I need to go over the datapath with Brian, or we can just let the tester verify the datapath works.
I just fixed a bug in aluControl.v about the shift signal.
I found a bug in sltControl on sunday. fixed it with Jason. Need to update design doc, that sltControl now takes in cout as an input
Brandan found a bug in controller, need to fixed xor and update design doc.
I found another bug in the data path, we should be calculating the address of Pc+4 + immed, and pc +8. Since we pipeline the pc, we are seq to pc+8 for regular address.
The ori bug is fixed in the controller.
we can use luts to implement a shifter, but the CAD automatically does that for us.
a mux 4 is faster because of dedicated logic
We can't use monitor to verify the cpu unless we know monitor has been tested and function correctly.
some people are still not reading or following the design doc.
the design doc keeps everyone on the same sheet of music
it's confusing if everyone name their wires and signals not following the naming convention
the initial plan of testing without dataforwarding and hazardDetect is slowing us down considerably
so far we only found a lot of wiring errors and bugs, no logical bugs or controoler bugs yet.
we need to test stall and beq really good
we need to stall if
lw $5, 0($6)
sw $3, 4($5)
started working at 8:30 pm, helping the tester to do integration testing
wrote test cases to test lw after lw and lw
fixed monitor.v to fixed the pipe effect
wrote test caes to test break
fixed many errors in monitor.v
modified testBasicCpu.s to output the to io
wrote test cases to break
update on today's work back log
started working at 1 pm today
fixed the bug in monitor, fixed the jr after lw bug in hazardDetect, it now stalls the pipeline,
need to fix dataForwarding to get rid of the 2 extra signals.
fixed the bug the corner.s in simulatation
there is still a bug in corner.s on the board