Imported lab5 into the CVS.
Added: io.v, syntax checked, and should be functional. Now it has an internal counter that can be accessed by memAddress 0xfffffffc.
Took 15 minutes.
Next thing is adding the boot 0 ram.
This will probably go into IO.
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Added: boot0.s This is the .s file that should be our boot0. Right now I'm directly putting in label addresses. I'll probably put the hex values directly into io.v, to reduce actual hardware.
10 minutes.
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Added: testWriteBuffer.v. It's a skeleton right now, it handles intialization testing right now, still needa finish up corner testing and random cases.
30 minutes.
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Added: buffer.v a really stupid buffer, should probaby be replaced. Used by memController so that it interfaces with the cache correctly. Every cycle where the buffer isn't empty, it should write new data out.
Modified: memController.v has been changed so it writes singly, but reads multiple times. As it reads, it fills the buffer, and in theory shouldn't over flow the buffer because read commands are handled by the arbitrator which will not send more than one read signal.
1 hour.
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Modified: testWriteBuffer.v, and ran a few tests on writeBuffer.
Write buffer seems to be broken, full and empty do not work correctly, it appears some of the wiring is not done.
readEnb can't seem to find stuff that has been placed in buffer.
1.5 hours
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Fixed: memController.v: Tristate buffer was using non-existant enable signal, now linked to command==1.
Modified: memController.v now uses posedge clk instead of edge triggering for output generation. This solves simulation hold time violations.
2 hours
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Added: pulseSync.v, which helps get a pulse from one clock boundary to another.
Modified: memController.v Uses pulse sync and correctly passes readNext to the processor.
40 minutes
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Fixed: Toplevel.v is now our top level.
datamem.v now should properly select output based on address.
instmem.v width of ioOut wire should be 32 bits now.
30 minutes
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Modified: TopLevel.v now accesses cpu.v directly. Wires should be connected for all ram interfaces.
Also created clk off the dll clk of VE_CLK. Going out of TopLevel its negated, but going into cpu.v it should be the same.
25 Minutes.
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Modified: Arbitrator.v and memController.v so that they have handshaking. This also prevents memController.v from repeating the same instruction more than once. I don't think it'd be too hard to make memory controller able to fulfill all 3 requests given a long enough clock period.
1 hour
Debugging: Minor updates to get corner.v to around line 112.
8 hours
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Modified: memController.v now no longer goes into the waitForProc stage, it relies on the arbitrator to give a proper commands based on the arbitrators history.
This should allow the memController to perform all 3 possible requests in a single procClock cycle.
30 minutes
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Fixed: memController.v was not properly filling the buffer going to instMem, enable was going low 4 cycles into the write because of the constant assignment based on command which woulld change to a different command.
45 Minutes.
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Modified: topLevel.v, now has ramclock referencing video decoder clock which is 25 mhz, and uses the 2x clock.
Added: buffer2.v, which now has two new signals, bigRe, and bigOut, which is the 256 bit out which will be valid the cycle bigRe goes high.
Miscellaneous debugging:
Cpu now works correctly with ram 1x -8x faster in simulation.
5 hours
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More miscellaneous debugging, modifications to get more signals to the toplevel.
It looks like the problem is coming from memory into the buffer that reaches instmem.
Either the buffer, or the memory is changing the instruction memories.
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More miscellaneous debugging, modifications to get more signals to the toplevel.
It looks like the problem is coming from memory into the buffer that reaches instmem.
Either the buffer, or the memory is changing the instruction memories.
7 hours.
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Imported lab5 into the CVS.
Added: io.v, syntax checked, and should be functional. Now it has an internal counter that can be accessed by memAddress 0xfffffffc.
Took 15 minutes.
Next thing is adding the boot 0 ram.
This will probably go into IO.
Added: boot0.s This is the .s file that should be our boot0. Right now I'm directly putting in label addresses. I'll probably put the hex values directly into io.v, to reduce actual hardware.
10 minutes.
Updated: boot0.s now has comments for how the asm should look.
Added: boot0.mem should have all the proper assembly code.
30 Minutes
Updated: io.v Added boot0 instructions into the read of memory at the required addresses. Its very clunky, and could be optimized.
10 minutes.
Updated: memController.v to do 8 burst read. Now it takes 13 cycles for each read operation.
I'm sitll not sure on how to interface the memory with the cache, directCache.v seems incomplete.
As a note, it took me about 2 hours to do the modifications. I'm still not sure if its functionally correct.
Added: testWriteBuffer.v. It's a skeleton right now, it handles intialization testing right now, still needa finish up corner testing and random cases.
30 minutes.
Added: buffer.v a really stupid buffer, should probaby be replaced. Used by memController so that it interfaces with the cache correctly. Every cycle where the buffer isn't empty, it should write new data out.
Modified: memController.v has been changed so it writes singly, but reads multiple times. As it reads, it fills the buffer, and in theory shouldn't over flow the buffer because read commands are handled by the arbitrator which will not send more than one read signal.
1 hour.
Modified: testWriteBuffer.v, and ran a few tests on writeBuffer.
Write buffer seems to be broken, full and empty do not work correctly, it appears some of the wiring is not done.
readEnb can't seem to find stuff that has been placed in buffer.
1.5 hours
Modified: memController.v now incorporates arbiter. Also signals to cache/ readNext are buffered for the clock crossing.
However I HIGHLY doubt its fully functional, this is probably hard to test.
Modified: testWriteBuffer.v has problems in that it assumed fifo behavior. It can not assume this, so many test cases are void.
4 hours.
Separated memController.v and arbitrator.v so it'd be easier to test.
1 hour
Fixed: memController.v: Tristate buffer was using non-existant enable signal, now linked to command==1.
Modified: memController.v now uses posedge clk instead of edge triggering for output generation. This solves simulation hold time violations.
2 hours
Added: pulseSync.v, which helps get a pulse from one clock boundary to another.
Modified: memController.v Uses pulse sync and correctly passes readNext to the processor.
40 minutes
Fixed: Toplevel.v is now our top level.
datamem.v now should properly select output based on address.
instmem.v width of ioOut wire should be 32 bits now.
30 minutes
Fixed: arbitrator.v Address should now output correctly.
5 minutes.
Modified: TopLevel.v now accesses cpu.v directly. Wires should be connected for all ram interfaces.
Also created clk off the dll clk of VE_CLK. Going out of TopLevel its negated, but going into cpu.v it should be the same.
25 Minutes.
Modified: Arbitrator.v and memController.v so that they have handshaking. This also prevents memController.v from repeating the same instruction more than once. I don't think it'd be too hard to make memory controller able to fulfill all 3 requests given a long enough clock period.
1 hour
Debugging: Minor updates to get corner.v to around line 112.
8 hours
Fixed: arbitrator.v, memController.v miscellaneous bugs affecting their handsharke.
Specifically in arbitrator fixed the history determining mechanism.
2hours
Modified: memController.v now no longer goes into the waitForProc stage, it relies on the arbitrator to give a proper commands based on the arbitrators history.
This should allow the memController to perform all 3 possible requests in a single procClock cycle.
30 minutes
Fixed: memController.v was not properly filling the buffer going to instMem, enable was going low 4 cycles into the write because of the constant assignment based on command which woulld change to a different command.
45 Minutes.
Miscellaneous debugging
4 hours
Modified: topLevel.v, now has ramclock referencing video decoder clock which is 25 mhz, and uses the 2x clock.
Added: buffer2.v, which now has two new signals, bigRe, and bigOut, which is the 256 bit out which will be valid the cycle bigRe goes high.
Miscellaneous debugging:
Cpu now works correctly with ram 1x -8x faster in simulation.
5 hours
Miscellaneous debugging, modifications of topLevel/cpu.v to get more signals to the topLevel.
8 hours
More miscellaneous debugging, modifications to get more signals to the toplevel.
It looks like the problem is coming from memory into the buffer that reaches instmem.
Either the buffer, or the memory is changing the instruction memories.
More miscellaneous debugging, modifications to get more signals to the toplevel.
It looks like the problem is coming from memory into the buffer that reaches instmem.
Either the buffer, or the memory is changing the instruction memories.
7 hours.