By: alandtse ( Alan Tse )
Alan's Notebook
2003-09-30 16:54
Added m:\lab4 files into repository.
Added datamem.v, monitor.v, mux2.v to CVS.
Began work on io.v, which is wrapped by datamem.v.
Question: Specs state that we control writing to IO via high bit of address, however this implies we'd get any address > 0x80000000 mapped to io. I needa resolve it to fix datamem's structure.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-09-30 18:32
Added ioInput.v, modified dataMem.v syntax checked.
Lab4 was updated to answer my question.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-09-30 19:43
Modified io.v to match latest specs. ie. dout is based on addr.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-09-30 19:59
Added processor.v. Skeleton only, not syntax checked. Data path should go into this.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 21:43
Working on monitor.v.
Made the data all pipelined except for stuff which arrives in processor during mem stage.
For jal, I'm not sure how i'm gonna get $ra's new contents, I'm assuming aluOut.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 21:54
Multiply has the same issue. Basically any functions that change a register value, I'm assuming are aluOut.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 22:06
updated monitor.v. Fully pipelined and should have all the instructions we need. I'm assuming any registers being modified will be coming from aluOut, such as mfhi, mflo, jal...... Though now that I think about it, it might come from memAddress since lw is functionally eqivalent.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 22:40
added multiplier.v. I plan to use a coregen fast multiplier to handle this, and this shall serve as the wrapper just in case we needa use our slower multiplier.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 22:45
Fixed: multiplier.v now compiles.
I'm done for tonight.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Updated: multiplier.v, using aaahnold multiplier, which is a SUPER fast coregen multiplier. I'll also start working on modifying one of our 32 cycle multipliers just in case.
Also updated monitor.v to handle stalls.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Beginning fpga top modification. I'm gonna try to map everything I think to the top level of the board.
One worry Jason brought up is the fact that our current wiring INCLUDES datahazard/forwarding, so we needa have a datapath that doesn't to solve part1.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
10/9/2003 5:26PM
Fixed: instMem, now takes in reset, when it receives reset, it automatically outputs 0.
Updated: TopLevel.v syntax checked, and possibly functional.
Added following switches:
Switch 5 is reset
Switch 8 is release
Switch 7 chooses output of IO, 0 = DP0, 1 = DP1
Switch 4 sends a single clock pulse, which is half the frequency
Switch 9 is the inputs to the io, bottom 8 bits.
Switch 8[1] specifies if we're on single clock or not
Switch 8[2] specifies whether we output the values of IF stage, or IO. high = IO
Switch 8[3] chooses between address and instruction. high = address
10/9/2003 6:12PM
Modified: Debouncer now is a variable target counter, and outputs high only for 1 cycle.
Updated: processor.v, TopLevel.v to pass on instruction from IF.
10/9/2003 6:38PM
Fixed: debouncer.v behaves properly when switch is held a long time.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Disabled their DLL cause it was giving a problem.
Everything seems to work, including breaks, single step, and IO, except for it not reading executing mem 0.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
By: alandtse ( Alan Tse )
Alan's Notebook
2003-09-30 16:54
Added m:\lab4 files into repository.
Added datamem.v, monitor.v, mux2.v to CVS.
Began work on io.v, which is wrapped by datamem.v.
Question: Specs state that we control writing to IO via high bit of address, however this implies we'd get any address > 0x80000000 mapped to io. I needa resolve it to fix datamem's structure.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-09-30 17:35
Added io.v. Syntax checked.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-09-30 18:32
Added ioInput.v, modified dataMem.v syntax checked.
Lab4 was updated to answer my question.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-09-30 19:43
Modified io.v to match latest specs. ie. dout is based on addr.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-09-30 19:59
Added processor.v. Skeleton only, not syntax checked. Data path should go into this.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 21:43
Working on monitor.v.
Made the data all pipelined except for stuff which arrives in processor during mem stage.
For jal, I'm not sure how i'm gonna get $ra's new contents, I'm assuming aluOut.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 21:54
Multiply has the same issue. Basically any functions that change a register value, I'm assuming are aluOut.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 22:06
updated monitor.v. Fully pipelined and should have all the instructions we need. I'm assuming any registers being modified will be coming from aluOut, such as mfhi, mflo, jal...... Though now that I think about it, it might come from memAddress since lw is functionally eqivalent.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 22:40
added multiplier.v. I plan to use a coregen fast multiplier to handle this, and this shall serve as the wrapper just in case we needa use our slower multiplier.
By: alandtse ( Alan Tse )
RE: Alan's Notebook
2003-10-01 22:45
Fixed: multiplier.v now compiles.
I'm done for tonight.
Updated: multiplier.v, using aaahnold multiplier, which is a SUPER fast coregen multiplier. I'll also start working on modifying one of our 32 cycle multipliers just in case.
Also updated monitor.v to handle stalls.
Took Brian's multiplier from lab2 and incorporated it into lab4.
Added following files: multController.v, multMultiplicand.v, multProduct.v, multModule.v.
Updated:
multiplier.v to use BrianOnRoids as opposed to aaahnold.
Beginning fpga top modification. I'm gonna try to map everything I think to the top level of the board.
One worry Jason brought up is the fact that our current wiring INCLUDES datahazard/forwarding, so we needa have a datapath that doesn't to solve part1.
Updated multiplier with new signal done, which asserts when multiplier should be ready. I still think the last case is wrong.
Fixed: monitor.v properly identifies all instructions, and has proper output based on testing.
10/9/2003 5:26PM
Fixed: instMem, now takes in reset, when it receives reset, it automatically outputs 0.
Updated: TopLevel.v syntax checked, and possibly functional.
Added following switches:
Switch 5 is reset
Switch 8 is release
Switch 7 chooses output of IO, 0 = DP0, 1 = DP1
Switch 4 sends a single clock pulse, which is half the frequency
Switch 9 is the inputs to the io, bottom 8 bits.
Switch 8[1] specifies if we're on single clock or not
Switch 8[2] specifies whether we output the values of IF stage, or IO. high = IO
Switch 8[3] chooses between address and instruction. high = address
10/9/2003 6:12PM
Modified: Debouncer now is a variable target counter, and outputs high only for 1 cycle.
Updated: processor.v, TopLevel.v to pass on instruction from IF.
10/9/2003 6:38PM
Fixed: debouncer.v behaves properly when switch is held a long time.
Added: instBoardRam.v dataBoardRam.v, ram to be used for synthesis.
Fixed: instMem.v, dataMem.v with `ifdefs to handle synthesis.
Miscellaneous Fixes: Modified files so they gave fewer synthesis warnings.
Also fixed shifter.v with a new algorithm. Its tested.
Right now I'm having trouble with the clkDLL killing the translation in xilinx. I currently removed it, and will post timings.
Updated: ioInput.v now takes in rst signal, also will read from iotrace.txt.
Modified: processor.v so it can handle the 7 bit stat signal from stat as specified by Jack during lab lecture.
Much random shit to get it to run on the board.
Disabled their DLL cause it was giving a problem.
Everything seems to work, including breaks, single step, and IO, except for it not reading executing mem 0.
Added varReg2.v which resets to -4. This should handle the skipping of the first value in memory.
Also included Mike's synchronous signals for both reset and release.
Minor cosmetic errors. -4 appears as output, but its instruction doesn't matter.
FullHazard1 fails at beq r18, r19
at 0x1b8.
Fixed: monitor.v: regOutB was getting regOutA
testFullHazard1.v line 0x1b8 was a faulty branch test.
Board looks like it runs. We're using the -4 offset though.
Modified cpu.v, regfile.v so they pass out the value of register 12.
Imported the final working files into the cvs.
Switch 10[7] control stat or reg 12 output on leds.
We're running at 28 MHZ. Alu is still the crit path.