Search Results for "mining software linux"
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Showing 48 open source projects for "mining software linux"
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a... -
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AWS EC2 FPGA
AWS EC2 FPGA hardware and software development Kit
AWS EC2 FPGA Development Kit is a set of development and runtime tools to develop, simulate, debug, compile and run hardware-accelerated applications on Amazon EC2 F1 instances. It is distributed between this GitHub repository and FPGA Developer AMI - Centos/AL2 provided by AWS with no cost of development tools. After creating an FPGA design (also called CL - Custom logic), developers can create an Amazon FPGA Image (AFI) and easily deploy it to an F1 instance. AFIs are reusable, shareable... -
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openTPU
An open-source AI accelerator, developed by AI
openTPU is an open-source AI accelerator project that exposes an entire inference hardware stack in one readable repository. It includes SystemVerilog RTL, a custom instruction set, a bit-exact simulator, a kernel language, compiler tooling, host software, and profiling utilities. The hardware design runs on a Xilinx Kintex-7 PCIe FPGA card and has been demonstrated with modern language models including Qwen, LFM, Gemma, SmolLM, and Phi variants. Both int8 and compact 4-bit weight formats... -
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Gwyscope
Open hardware SPM controller with advanced sampling support.
Gwyscope is a low cost, open hardware, Digital Signal Processor (DSP) suitable for Scanning Probe Microscopy measurements, focusing on demonstrating the concept of adaptive scanning, general XYZ data acquisition and statistical data processing on the controller level. More details can be found in: M. Valtr et al., Scanning Probe Microscopy controller with advanced sampling support, HardwareX, Volume 15, e00451 https://www.hardware-x.com/article/S2468-0672(23)00058-5/fulltext It... -
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pyrpl
PyRPL turns your Red Pitaya into a powerful analog feedback device.
The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) implements many devices that are needed for optics experiments with the Red Pitaya. PyRPL implements various digital signal processing (DSP) modules (see features below). It allows... -
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Wheefun Computer Prototyping Kit
A Toolkit for Designing Computers
This package is designed for people who are a) interested in writing emulators or b) integrating this level of detain into their applications (e.g., a video game). The ability to do this is useful because a) it allows for tinkering far before physical implementation of the design is. In addition to a strong core, WFCPK will also include modules emulating various processors (e.g., the MOS 6502 and the Zilog Z80) as well as the Video-Audio Interface (a custom VGA-compatible display and... -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and the Wishbone bus are supported. ... -
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ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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Endpoint Management with Remote Control Built InSplashtop AEM handles patching, alerts, scripts, and inventory, and unattended remote control is included. When something needs hands-on work, you’re one click away instead of switching tools.
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Project 2306 IDE Rad MacOS MCU DeveR
Electronic design and programming tools suite like Eagle, MpLab
Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned Features : Similar with mainstream market tools IDE and GUI Wrapper like : LabView©, Proteus©, MPLab©, Eagle CAD©, Tools Suite for Most Market Microcontroller. ... -
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lpACLib
An Open-Source Library for Low-Power Approximate Computing Modules
The “lpACLib” library contains the VHDL description of accurate and approximate versions of several arithmetic modules (like adders and multiplier of different bit-widths) and accelerators. Moreover, it also provides the corresponding software behavioral models/implementations developed in C and MATLAB to enable quality characterization. Besides our novel designs, it also contains implementations for several state-of-the-art arithmetic modules and their approximate versions. This open-source... -
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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COFILOS
A Development Framework for Coldfire
Contains a framework for Coldfire MCUs like 52254. The framework supports a Command Line Interface (CLI) that may work from Serial port, USB or ENET. The framework uses Processor Expert and IDE requirement is MCU Eclipse 10.4 from Freescale. Includes the FunkOS Realtime Operating System by Funkenstein Software Consulting, available at http://funkos.sourceforge.net Mainly it is a support package for the development board Perseus, but I have ported also the RTOS to MCF52233DEMO... -
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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ApproxAdderLib
Library of Approximate Adders
We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as... -
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MatlabSimulink2CPP
Demo of Simulink to C++ C or HDL FGA for HFT potential
Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/ -
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Notepad++ Verilog Plugin
Verilog plugin for Notepad++
Verilog processor for Notepad++. Current features: - Instantiate a module - Insert registers/wires from a module - Generate a test bench template - Automatically inserts a default header for a test bench - Insert a clocked always block v1.2.0 now supports ANSI and non-ANSI module declarations. To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C. This selects the module and parses its components.... -
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A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.
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VHDT
VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation. -
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Partially Reconfigurable Hardware
Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs
This project introduces new FPGA architectural tools and Linux OS modifications that aid in supporting Dynamic Partial Reconfiguration (DPR) on FPGAs for concurrent control. It shows that control systems benefit from hardware concurrency, meaning that by moving the control intelligence into hardware, the negative effects inherent to threads and their scheduler are minimized. This leaves software with the role of a high-level administrator rather than an executor, thereby eliminating unnecessary bottlenecks. ... -
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation *... -
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This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.
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Application de fines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
