PyRPL turns your Red Pitaya into a powerful analog feedback device.
Tools and libraries for use with systemc and verilog
An operating system written in RTL
Verilog Finite State Machine (FSM) Code Generator
An Open-Source Library for Low-Power Approximate Computing Modules
A Development Framework for Coldfire
Demo of Simulink to C++ C or HDL FGA for HFT potential
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
Open implementation of the x86 architecture
Open architecture GPU simulator and implementation
PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e
Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs
The aim of FAZIA project is to build a 4Pi array for charged particles
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
SystemVerilog module to substitute Verilog PLA system tasks.
Simple AVR OS