Open hardware SPM controller with advanced sampling support.
PyRPL turns your Red Pitaya into a powerful analog feedback device.
Tools and libraries for use with systemc and verilog
Verilog Finite State Machine (FSM) Code Generator
An Open-Source Library for Low-Power Approximate Computing Modules
A Development Framework for Coldfire
Open implementation of the x86 architecture
PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e
The aim of FAZIA project is to build a 4Pi array for charged particles
SystemVerilog module to substitute Verilog PLA system tasks.