Open Source VHDL/Verilog Software - Page 3

VHDL/Verilog Software

Browse free open source VHDL/Verilog Software and projects below. Use the toggles on the left to filter open source VHDL/Verilog Software by OS, license, language, programming language, and project status.

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  • 1
    This is the award-winning FALCON I object recognition system! Capable of tracking up to 12 different objects simultaneously, and with over 6 times the raw resolution of the CMUCam, this is one of the most powerful vision systems in its class.
    Downloads: 0 This Week
    Last Update:
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  • 2
    FAZIA DAQ

    FAZIA DAQ

    The aim of FAZIA project is to build a 4Pi array for charged particles

    The FAZIA project groups together more than 10 institutions in Nuclear Physics, which are working in the domain of heavy-ion induced reactions around and below the Fermi energy (10-100AMeV). The aim of the project is to build a 4Pi array for charged particles, with high granularity and good energy resolution, with A and Z identification capability over the widest possible range. It will use the up-to-date techniques concerning detection, signal processing and data flow, with full digital electronics. Neutron detection is also foreseen via the collaboration with the NEUTROMANIA group. FAZIA is designed to operate at stable and radioactive beams facilities like LNL-Legnaro, LNS-Catania in Italy, GANIL-SPIRAL and SPIRAL2 in France, GSI-FAIR in Germany in the horizon 2010-2015. The availability of the european radioactive beam facility EURISOL expected in the period 2015-2020 will also be a major opportunity for the FAZIA community.
    Downloads: 0 This Week
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  • 3
    Automatic build management for VHDL and Verilog projects. The automatic dependency resolver finds the exact subset of sources, and the correct order they must appear in required to build a project. A Makefile automates the actual build itself.
    Downloads: 0 This Week
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  • 4
    The foosball game is implemented in VHDL for use with the Altera DE2 FPGA board with the visual interface in a VGA monitor and input interface in a PS/2 keyboard.
    Downloads: 0 This Week
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    See Project
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  • 5
    The aim of this project is to develop a Graphic Processing Unit core targeting FPGA implementation.
    Downloads: 0 This Week
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  • 6
    FPGA coprocessor floating point math lib
    libhdlfltp is a VHDL library of floating point operators, all of which are parametrized, synthesizable to FPGAs and cover a number of the core operators in math.h.
    Downloads: 0 This Week
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  • 7

    FPGA starterkit essentials

    basic debug tools while using FPGA boards

    Module 1: durchblicker: embedded Logicanalyzer with direct output on VGA-monitor
    Downloads: 0 This Week
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  • 8
    Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab.
    Downloads: 0 This Week
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  • 9
    FPGAmer is a framework to develop embedded games. Our development platform is the Xilinx University Program Virtex-II-Pro but not limited to that. FPGAmer includes custom hardware components plus a custom software framework and some sample games.
    Downloads: 0 This Week
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  • 10
    This project implements an On Screen Display for FPV (First Person View) for RC planes. Sends telemetry data from GPS & sensors embebed with video information.
    Downloads: 0 This Week
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  • 11
    FSMDesigner
    FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
    Downloads: 0 This Week
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  • 12
    FUI Audio DAC

    FUI Audio DAC

    FPGA-Based USB-Input Audio Digital to Analogue Converter

    An open-hardware and -firmware project that implements a USB-input fully-digital class-D audio amplifier. All processing is done on FPGA, including the USB-physical, USB-SIE, HID interface, clock-recovery, bus voltage regulation, noise-shaping and PWM output. A Microchip PIC based remote control is also included. The remote maps to the media buttons of the USB HID interface. The volume control, next track, previous track, stop and play/pause functions are supported.
    Downloads: 0 This Week
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  • 13
    the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol
    Downloads: 0 This Week
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  • 14
    GPS to Radio-controlled Clock

    GPS to Radio-controlled Clock

    GPS to Radio-controlled Clock

    The purpose of this simple DIY project is to build an electronic circuit that received the GPS time signal, convert it to the radio-controlled clock format, and transmit that signal to the clock. Once built, there is no need for setup and maintenance, all you need is put this unit close to the window to receive GPS signal, and it will transmit the time signal to your radio-controlled clock.
    Downloads: 0 This Week
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  • 15
    This project aims at creating an open-source SoC that will support the Google TV platform.
    Downloads: 0 This Week
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  • 16

    GalaxyIP

    Galaxy Intellectual Property Cores

    GalaxyIP (Galaxy Intellectual Property Cores) is a project devoted to accommodate a set of IP-Cores for embedded SoC development, based on the processor code named Voyager (StarTrek and the space probes).
    Downloads: 0 This Week
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  • 17
    Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs such as Xilinx' Spartan3 and Virtex FPGAs.
    Downloads: 0 This Week
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  • 18
    Este proyecto presenta GraphUIS, una implementación de un periférico de video en un FPGA como un diseño modular caracterizado por no tener memoria dedicada. Se desarrolló como un proyecto académico en la Universidad Industrial de Santander.
    Downloads: 0 This Week
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    See Project
  • 19
    Gwyscope

    Gwyscope

    Open hardware SPM controller with advanced sampling support.

    Gwyscope is a low cost, open hardware, Digital Signal Processor (DSP) suitable for Scanning Probe Microscopy measurements, focusing on demonstrating the concept of adaptive scanning, general XYZ data acquisition and statistical data processing on the controller level. More details can be found in: M. Valtr et al., Scanning Probe Microscopy controller with advanced sampling support, HardwareX, Volume 15, e00451 https://www.hardware-x.com/article/S2468-0672(23)00058-5/fulltext It is based on a low cost FPGA board Red Pitaya and additional high bit depth AD and DA converters. When put together with the AFM scanning hardware (sensor, scanner and their amplifiers) and user interface software it can serve as a standalone SPM system. Otherwise, it can serve as a sub-module for a custom built SPM system, e.g. providing the feedback loop mechanism only. Finally, it can be used as a board for developing advanced sampling techniques, which was the primary goal.
    Downloads: 0 This Week
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  • 20
    The H.264 VHDL core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. Simple, fully synchronous design with low gate count.
    Downloads: 0 This Week
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  • 21
    This project includes a set of tools and guidelines designed for rapid production of large-scale embedded systems projects. The tools enable quick generation of reusable, reconfigurable hardware, using a user-specified hardware description language.
    Downloads: 0 This Week
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  • 22
    Platform for advanced open source IP-Core development, i. e. dynamic memory controllers for FPGAs.
    Downloads: 0 This Week
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  • 23
    This project aims to develop a colour-based vision processing system for use in RoboCup. We are using a CCD camera for input to an FPGA. The system locates coloured objects and outputs detected corners.
    Downloads: 0 This Week
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  • 24
    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
    Downloads: 0 This Week
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  • 25
    This is an image coder with fixed sampling, at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with res. up to 352x288).
    Downloads: 0 This Week
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    See Project
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