Search Results for "verilog-a"
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21 projects for "verilog-a" with 2 filters applied:
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XLS
XLS: Accelerated HW Synthesis
XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA... -
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ALCHA
A New Programming Language for FPGA Projects
ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides. It will support an object oriented programming model, abstract data and signal types, and compile-time scripting. -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Wheefun Computer Prototyping Kit
A Toolkit for Designing Computers
This package is designed for people who are a) interested in writing emulators or b) integrating this level of detain into their applications (e.g., a video game). The ability to do this is useful because a) it allows for tinkering far before physical implementation of the design is. In addition to a strong core, WFCPK will also include modules emulating various processors (e.g., the MOS 6502 and the Zilog Z80) as well as the Video-Audio Interface (a custom VGA-compatible display and... -
MongoDB Atlas runs apps anywhereMongoDB Atlas gives you the freedom to build and run modern applications anywhere—across AWS, Azure, and Google Cloud. With global availability in over 115 regions, Atlas lets you deploy close to your users, meet compliance needs, and scale with confidence across any geography.
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Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
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DRAKON Editor
A free cross-platform editor for the DRAKON visual language.
DRAKON is a diagram language developed within the Russian space program. Its primary objective is presenting complex software systems in a way which is easy to understand by humans. DRAKON's motto: took a glance - understood at once. DRAKON Editor helps software architects, quality specialists and developers. Architects and quality assurers can express a high-level view of how their product works. DRAKON serves them to explain the dynamics of a software system. Software engineers can use... -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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ApproxAdderLib
Library of Approximate Adders
We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well... -
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Doxverilog is a nativ Verilog/SystemVerilog parser for the Doxygen documentation generator. This allows the production of advanced documentation from Verilog/SystemVerilog sourcecode.
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VHDT
VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation. -
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Application de fines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
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This tool compares Value Change Dump files, which is useful for regression testing of Verilog models. VCD files are dumpfiles generated by EDA logic simulation tools.
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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
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vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
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Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.
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HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
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This is an image coder with fixed sampling, at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with res. up to 352x288).
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Software to support the JTAG bus (IEEE 1149.1). Primary purpose is for a JTAG programmer/debugger using FPGA's to provide ability to test and program JTAG devices.
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The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.
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vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.
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