Search Results for "chip"
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22 projects for "chip" with 2 filters applied:
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Chipyard
An Agile RISC-V SoC Design Framework with in-order cores
...Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems. -
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OpenOCD - Open On-Chip Debugger
The Open On-Chip Debugger
The "Open On-Chip Debugger" provides JTAG/SWD access from GDB (or directly with TCL scripts) to processors with ARM and MIPS based cores. See website for full list of supported targets. -
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Zilog Z80
Z80 shared library including some nice test-projects
Another Zilog Z80 emulation. C++ class on a shared library. Simulates all pins of the Z80-Chip in a single function interface. Additionally are some Test-Projects added. 1. CP/M 2.2 emulator connectable by an telnet client. 2. An instruction set examiner. 3. An ZX-80 emulator. 4. An TK-80 emulator 5. An Z80 Dis-assembler driver for all supported instructions. -
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Rocket Chip
Rocket Chip Generator
Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. -
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HP41CX
HP-41cx Emulator
An Qt based HP-41cx Emulator first based on Eric's NSIM-0.61 Project. Ported to C++ and extended by an graphical Qt-based User-interface. Since Oct.2014 I developed my own NUT-Core implementation which is quite different from Eric's one. I called it NewT in fact of the existing NewT NUT Hardware revival. -
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Eclipse Embedded Systems Register View
displays special function Registers (SFRs) while debugging
...Modifications of peripheral registers values are possible via Editing in the Binary column via BitButtons, Editing in the Hex column, Choosing an interpretation from an ComboBox in the Hex column The EmbSysRegView works with any 32 bit target that stores data in little endian byte order and maps its register into memory adress space. In other words, if you find your registers in the CDT Memory View, the RegisterView will also work with that device assumin that a chip xml description is available. -
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Open On-Chip Debug Solution for Embedded Target Systems based primarily on ARM cores. This project has moved to sourceforge: https://sourceforge.net/projects/openocd/
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BASIC interpreter for the 16bit PIC microcontroller 24FJ64GA002. The interpreter runs on the chip only, no compiler/tokenizer is needed. Communication with PC is done by USB-to-serial converter cable.
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A phrase to phoneme code converter for the SpeakJet chip by Magnevation. Speakalator runs on Unix type operating systems.
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eProcurement SoftwareeBuyerAssist by Eyvo is a cloud-based procurement solution designed for businesses of all sizes and industries. Fully modular and scalable, it streamlines the entire procurement lifecycle—from requisition to fulfillment. The platform includes powerful tools for strategic sourcing, supplier management, warehouse operations, and contract oversight. Additional modules cover purchase orders, approval workflows, inventory and asset management, customer orders, budget control, cost accounting, invoice matching, vendor credit checks, and risk analysis. eBuyerAssist centralizes all procurement functions into a single, easy-to-use system—improving visibility, control, and efficiency across your organization. Whether you're aiming to reduce costs, enhance compliance, or align procurement with broader business goals, eBuyerAssist helps you get there faster, smarter, and with measurable results.
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Weeno is an software-only extension of Wiring / Arduino for potentially all and any Atmel AVR MCUs. And potentially all chip architectures from all companies, whether Freescale, SiLabs, TI, even ARM. Basically, the goal is to make AVR-Weeno, ARM-Weeno, 8
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The m6800 Simulator is a teaching tool to introduce students to microprocessors. It is based on a cut-down version of the M6800 chip, and a reduced instruction set. The simulator assembles and simulates execution of the users code on a GUI
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ChIPOTle 2.0 is a user friendly tool for performing peak detection in ChIP-chip signal. The tool also has functions for probe sorting, signal normalization, replication merging, and multiple correction testing in a windows interface or *nix command line.
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neochip is a collection of algorithms for high-density oligonucleotide microarrays. The current version contains heuristic algorithms that attempt to improve the quality of arrays by re-designing their layout (the location of the probes on the chip).
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C into assembly language converter producing asm files, specific optimizations for different chip manufacturers (Intel, AMD and Transmeta), written in C/C++ with OOP design, designed to be multiplatform
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The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.
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IMAVR is Atmel AVR 8-bit RISC chip emulator for UNIX. You can run your code before programming to chip. Embedded simple debugger and disassembler. Emulate wide range of AVR chip, wide range of their modules: EEPROM,USART, timers and so on.
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The JavaBluetooth Stack is a 100% Java implementation of the Bluetooth Specifications Version 1.1. It uses the javax.comm package to address the Bluetooth chip, and implements the JSR-82 (javax.bluetooth) API. Deployment on TINI is possible.
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The Ogg Vorbis Player (http://www.xiph.org/ogg/vorbis/index.html) shall be implemented in form of a system-on-a-chip by using hardware/software co-design techniques using prototyping board with the open source LEON processor (http://www.gaisler.com).
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Gnu Digital Signal Processor Simulator. The goal is to develop a DSP Simulator for Linux. The first chip supported will be the TMS320C54x.
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This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
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