Search Results for "processor"

SimThyr is a continuous simulation program for the human pituitary-thyroid feedback control system. Applications of this program cover research, including development of hypotheses, and education of students in biology and medicine, nurses and patients.

ModelRunner is a simple batch processor to run Lisflood models.

...Simple environment to run and debug firmware for AVR 8-bit microprocessors. Able to run arduino firmware. Internally this program uses the open source Simavr AVR Processor Simulator (https://github.com/buserror/simavr) and wraps all its functions in a GUI shell. Setups for firmware debugging scenarios can be created dynamically. Able to run 16MHz MCU with decent set of external parts in real time. In particular this can be used for development of CNC firmware in conjuction with its CAM frontend without access to the real hardware. ...

A spring-based 3D graph layout tool written in Java. Rendering is performed in OpenGL via the JOGL library.

MDcore is an Open-Source library implementing the core functionality of a Molecular Dynamics engine. The engine is inherently multi-threaded and runs efficiently on multi-processor/multi-core shared-memory architectures.

Impact is an explicit Finite Element Program Suite which simulates dynamic impact events. It has a range of elements, contact handling and different material laws. Models can be created, solved and analyzed with the included pre- and postprocessor. Impact is based on an Explicit Time stepping algorithm. These kind of codes are used to simulate dynamic phenomena such as car crashes and similar, usually involving large deformations.

openDLX is a DLX/MIPS ISA compatible pipeline simulator. (Visit https://github.com/smetzlaff/openDLX for the latest development version or if You want to contribute.)

...The output of simulation will vary from machine to machine depending upon the underlying hardware, for e.g., the timings will be different on a dual core and a quad core processor. Feel free to reach out to me if you have any suggestions or queries.

SCHEDuler SIMULAtor (originally sched_sim) is a simple C++ event driven simulator of scheduling policies (single processor). Currently supported scheduling policies are: FIFO, LIFO, EDF, LST, RM, DM.

lilpM32 is a MIPS-like processor designed in Logisim, assembler program and documentation for them. Complete assembler and fully functional instruction set with I/O and subroutines features allow to write full-blown complicated programs.

The Daedalus Design framework is a complete design flow for multi-media embedded Multi-processor System-on-Chip (MPSoC) platforms. It transforms a high level system description into an FPGA prototype in a largely automated way in only a matter of hours.

This project is started out of the idea to simulate simple creatures like game of live. The goal is to build up an multi processor/host environment to simulate the building of simple live in given world environments.

The MuDiSP3 is a set of C++ classes acting as a framework for the execution of Digital Signal Processing (DSP) simulations. The entire simulated system is represented by a "System" class which inherits his properties from a general purpose DSP. The user c

DSPemu emule a digital signal processor TMS320F243, with console interface showing the registers and memory. With DSPemu is possible test algorithms such as Filter, FFT/IFFT. This can be integrate and used with a circuit simulator.

QUASI is stand-alone AVR RISC processor simulator with debugging features, EDA-like GUI and plugin interface.