Search Results for "mips pipeline simulator"
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Showing 25 open source projects for "mips pipeline simulator"
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Halide
A language for fast, portable data-parallel computation
...It was designed to make writing high-performance image and array processing code much easier on modern machines. It works on all major operating systems and with several CPU architectures (X86, ARM, MIPS, Hexagon, PowerPC) and GPU Compute APIs (CUDA, OpenCL, OpenGL, among others). It isn't a standalone programming language however; rather it is embedded in C++ which means that you write C++ code, building an in-memory representation of a Halide pipeline using Halide's C++ API. This representation can then be compiled to an object file, or a JIT-compile and run in the same process. ... -
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StereoKit
An easy-to-use mixed reality library for building VR applications
StereoKit is an easy-to-use open source mixed reality library for building HoloLens and VR applications with C# and OpenXR! Inspired by libraries like XNA and Processing, StereoKit is meant to be fun to use and easy to develop with, yet still quite capable of creating professional and business-ready software. HoloLens 2, Oculus Quest, Windows Mixed Reality, Oculus Desktop, SteamVR, Monado (Linux), and eventually everywhere OpenXR is! Flat screen MR simulator with input emulation for easy... -
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QuadRay-engine
Realtime raytracer using SIMD on ARM, MIPS, PPC and x86
QuadRay engine is a realtime raytracing project aimed at full SIMD utilization on ARM, MIPS, POWER and x86 architectures. The efficient use of SIMD is achieved by processing four rays at a time to match SIMD register width (hence the name). The rendering core of the engine is written in a unified SIMD assembler allowing single assembler code to be compatible with different processor architectures, thus reducing the need to maintain multiple parallel versions. At present, Intel... -
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Parallel and Distributed Process System
NOTICE OF CONSOLIDATION & PARTNERSHIP PENDING As of April 2026, the 20
NOTICE OF CONSOLIDATION & PARTNERSHIP PENDING As of April 2026, the 20 pipelines of the QCAUS/PDPBioGen suites are undergoing consolidation for high-scale institutional research. Core 'Ford 2026' algorithms remain the proprietary IP of the Ford Peace and Justice Foundation. Academic users at partner institutions are currently performing validation; all other commercial inquiries must contact the author Computational Neuroscience: Large-scale neural population dynamics, brain-inspired... -
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spim is a self-contained simulator that runs MIPS32 assembly language programs. spim also provides a simple debugger and minimal set of operating system services.
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EduMIPS64 (aka edumips) is a cross-platform MIPS 64 ISA simulator. It can be used to run and debug MIPS programs that are written using the MIPS64 instruction set. It supports visual debugging and lets you see what instructions do in the pipeline.
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gem5-STNoC
Cycle-approximate STNoC instance in gem5
The gem5-STNoC model available here (https://sourceforge.net/projects/gem5-stnoc) in alpha version is adapted from the gem5 Garnet Fixed Pipeline as a cycle-approximate NoC model based on STMicroelectronics STNoC backbone specifications. It supports several mechanisms implemented at the STNoC Network Interface, such as NoC Firewall and preliminary Memory Interleaving. The model is freeware covered by standard gem5 license. Development has been partly supported by EU-ICT projects DREAMS and TRESCCA. -
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DigMIPS
A simple MIPS processor for Chipmunk DigLog circuit simulator
- DigMIPS is a simple 1-cycle-per-instruction MIPS processor working under DigLog circuit simulator. - DigMIPS is provided with an assembler and a C compiler. - DigMIPS serve as a nice support to teach the basics of computer architecture. Features: - 8 instructions - 8K RAM + 8K ROM - I/O periphals (keyboard and teletype screen) Software: - DigASM (assembler) - DigCC (C compiler) -
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SkyEye
a very fast full system simulator
SkyEye is a very fast full system simulator which takes llvm as IR of dynmic compiled framework.. It can simulate series ARM, Coldfire,Mips, Powerpc, Sparc, x86, TI DSP and Blackfin DSP Processor. Also can simulate multicore system by the multicore of host. The commercial support is provided by DigiProto Co. (http://www.digiproto.com) -
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openDLX
A DLX/MIPS processor simulator
openDLX is a DLX/MIPS ISA compatible pipeline simulator. (Visit https://github.com/smetzlaff/openDLX for the latest development version or if You want to contribute.) -
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DASiT
DASiT (DLX-Altivec Simulator Tool)
DASiT is a simulation teaching tool based on DLX processor that includes multimedia set-instructions by incorporating AltiVec SIMD extensions. The tool developed in Java displays DLX pipeline execution with its data path that incorporates visualization of memory and register. It is considered as a complement in undergraduate computer design and computer architecture subjects. -
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MIPS Interactive Learning Environment
MILE - MIPS Interactive Learning Environment
MILE is a user-friendly MIPS simulator. It offers users a GUI in which they can develop and run programs written in MIPS assembly language. It is intended to be used as an instructional tool. MILE is still in early development. It lucks certain features and functionality. Please be patient until the beta version is released. -
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YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
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Operating System Framework for a MIPS Simulator. The project includes a multi-threaded MIPS Simulator and a naive Operating System and an Assembler for the simulated architecture, intended to be used for instructional and educational purpose.
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Fully graphical mips simulator, with a simple text editor. The aim is to not only have the entire mips isa implemented and simulated, but to have a mips ide. The text highlighting for the mips instructions set is currently underway. Version 3 Available.
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A Java-written MIPS simulator developed to stimulate people learning the Assembly language. It adds graphics, sounds and user interation to make writing assembly programs more interesting.
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A multi-ISA "assembly debugger" with graphical and terminal frontends. Currently sporting LC-3, Georgia Tech's LC-2200, and brain*. MIPS support is in the making, to compete with SPIM. (Windows, Linux, MacOSX; LC-3 simulator and LC-2200 simulator)
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Fast instruction-set simulators for MIPS32. Includes an interpreter, static-compiled simulator builder, and a dynamic-compiled simulator that optionally uses multiprocessing. Runs statically-linked binary from cross-gcc. Supports GDB remote debugging.
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Superscalar processor simulator for in-order and out-of-order processors. It also simulates several configurations of multiprocessors. Currently only supports the MIPS instructions set.
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A basic MIPS simulator based on DEVS (Discrete Event System Specification). This project aims to develop the behavior of some components of the MIPS architecture (Registers, Memory, Muxs) including only seven instructions (add, sub, and, or, lw, sw, beq)
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