2 projects for "clock" with 2 filters applied:

  • Veeam Data Platform v13.1 Icon
    Veeam Data Platform v13.1

    Move workloads across hypervisors and clouds with no vendor lock-in. Try VDP free today.

    Try Veeam Data Platform today. Experience the unified platform that's secure by design, portable by default, and proven to recover clean, fast, and anywhere.
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  • Paessler - Monitor Your Whole Network in Minutes Icon
    Paessler - Monitor Your Whole Network in Minutes

    Auto-discovery finds your devices and deploys pre-configured sensors instantly. No project plan required, just visibility from day one.

    Waiting weeks for a monitoring rollout isn't an option when infrastructure doesn't stop running. PRTG's auto-discovery scans your network and suggests from over 200 pre-configured sensor types, so you're watching servers, applications and devices within minutes, not after a multi-week deployment. Enterprise-strength monitoring, without the enterprise complexity. Start your free trial today.
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  • 1
    Eagle Mode

    Eagle Mode

    Zoomable user interface (ZUI) with file manager, file viewers and more

    ...It integrates file viewers for most of the common file types, as well as an audio and video player. Furthermore, the virtual cosmos contains a chess game, a netwalk game, a 3D minesweeper game, a multi-function clock, a stock watchlist, some fractals, and a Linux kernel configurator in form of a kernel patch.
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    Downloads: 39 This Week
    Last Update:
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  • 2

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 0 This Week
    Last Update:
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