Search Results for "compiler design"
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Showing 29 open source projects for "compiler design"
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. ... -
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Swift Numerics
Advanced mathematical types and functions for Swift
...The package includes RealModule utilities and a full Complex type with the expected arithmetic and transcendental functions, bridging a long-standing gap for numerics in Swift. API design follows Swift’s emphasis on value semantics and protocol-oriented programming, enabling compiler optimizations and predictable performance. The modules are factored to keep dependencies minimal and to allow adopters to pull in only what they need. As a result, Swift Numerics underpins higher-level libraries in simulation, signal processing, and machine learning written in pure Swift. -
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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Snap7
32/64 bit multi-platform Ethernet S7 PLC communication suite
Snap7, through three specialized components: Client and the inedited Server and Partner, allows you to definitively integrate your PC based systems into a PLC automation chain. Designed to transfer large amounts of hi-speed data in industrial facilities, it scales easily, down to small Linux Arm boards such as Raspberry PI. Hi level object oriented wrappers are provided, currently C/C++, .NET/Mono, Pascal, LabVIEW, Python with many source code examples. Very easy to use, a full... -
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IEC 60870-5 104 Protocol download
IEC 104 RTU Server Client Simulator Source Code Library Win Linux
v21.06.022 Complete implementation of iec 104 protocol standard including File transfer. Make your RTU, protocol converter, Gateway, HMI, Data concentrator compatible with iec 104. *Industry Proved * Worldwide Customers Download Evaluation Kit - IEC 104 Development Bundle In the Development Bundle, We included IEC 104 Server & Client Simulator, Windows & Linux... -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So,... -
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GeckoCIRCUITS
GeckoCIRCUITS is THE circuit simulator for modeling power electronics
GeckoCIRCUITS is THE circuit simulator for modeling power electronics systems. Besides its fast circuit simulation capability, GeckoCIRCUITS combines control modelling and thermal simulations via equivalent networks in an easy-to-use software package. GeckoCIRCUITS has its strengths in the extremely high simulation speed and its open interface. The software can be integrated into MATLAB/Simulink or other programming environments. -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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MathFu
C++ math library developed primarily for games focused on simplicity
...Implementations are carefully tuned to leverage SIMD instruction sets such as SSE and NEON while preserving a clean fallback path for portability. Because types are fixed at compile time, the compiler can aggressively inline and unroll code, producing predictable performance and tiny binaries. The design emphasizes minimal dependencies and clear ownership so the library can be embedded into engines without dragging in heavyweight frameworks. It fits equally well in rendering math, physics helpers, animation blending, and camera control logic where determinism and speed matter. -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
...VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. We believe the use of an HDL is also the way of the future when it comes to PCB design. The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool. -
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numericstream
tools to take data from instruments to networks
...Subsequently client applications can take this data to display on webpages, export to text file, and almost anything else. The driver has been written using the mingw port of the gcc compiler, currently the system runs on Windows XP, however the design is deliberately cross platform, and linux based serial port interfaces will be added. The first client is written in php, and tested using the Apache web server. The client is currently a proof of concept, and needs some work! -
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The KontrollerLab is an IDE for developing software for Atmel(r) AVR(c) microcontrollers using the avr-gcc compiler, the uisp and the avrdude upload software.
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FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki.
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ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.
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Digital Signal Processing Block Diagram Compiler - user extendable to all DSP's, but presently supports only the TI C2000 family. Rich support for fixed point arithmetic, both saturated and unsaturated. Block diagram entry is via TinyCAD (included).
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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
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s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
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BuddyScout is an interface between BuDDy (Binary Decision Diagram library) and GHC (Glasgow Haskell Compiler). It enables you to use the BDD library from within Haskell programs.
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vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd
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MEDDAC is the seeding point for designing a new approach to Operating System design itself. It is an Open Source project with roots in mainframe design and development the author began in 1979. Monitor Editor Disassembler Decompiler Assembler Compiler
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SDL REFLEX is the micro kernel of a real time operating system for the AVR microcontroller family. The kernel is especially designed to implement systems described in SDL The Specification and Description Language . Compiler GNU ANSI-C for AVR v.3.3
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Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com, and test reports are collected from that project.
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DGC is a tool for the creation of digital netlists. DGC does an optimization and technology mapping for an abstract description of boolean functions and state machines. Output formats are EDIF, XNF and VHDL. Input formats are KISS, PLA and others. See also: http://gitorious.org/dgc-gtk/
