Search Results for "cpu chip"

Chipyard is a framework and generator for constructing custom RISC‑V SoC hardware. Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems.

Simple source files and compiled JAR Java programs, for benchmark 50 000 000 cycle finding prime numbers. On Intel(R) Core(TM) i5-8600K CPU, Windows 10 20H2, i have 39 second on single core and 7,6 second on multi core. (PS: C++ multicore 6 second). Added C files for gcc compiler in Windows 10 and for Xcode C command line project in MacOS ( tested on Mac mini M2 with single core 16 to 25 sec and multicore 2,3 to 5 second by compiler -O switch). Surprise, same code in JavaScript for M2 chip in Safari: 12,5 sec single core and 3,3 sec multi core. ...

Mobile AI Compute Engine (or MACE for short) is a deep learning inference framework optimized for mobile heterogeneous computing on Android, iOS, Linux and Windows devices. Runtime is optimized with NEON, OpenCL and Hexagon, and Winograd algorithm is introduced to speed up convolution operations. The initialization is also optimized to be faster. Chip-dependent power options like big.LITTLE scheduling, Adreno GPU hints are included as advanced APIs. UI responsiveness guarantee is sometimes...

SC_CoSiM is a platform which focuses on validating a full system, by performing near real-time, command-to-command co-simulation of the hardware DUT implemented on FPGA as a full system prototype (with CPU, on-chip interconnect, memory, application, drivers, and OS, typically Linux) against its equivalent cycle-approximate system-level model of the DUT. Our work presented at DVCon-Europe 2018 extended the technology demonstrator from David C Black(https://github.com/dcblack/technology_demonstrator). To reference this work: A. Papagrigoriou, M.D. ...

Beagleboard-xm is a powerful chip with a cortex-A8 CPU and a DSP. I have the plan to build an OCR gadget using it with Linux. As a by product I will post my tailored Linux kernel and u-boot, and all relevant stuff here, from now on. I was shocked by the blocking of Chinese citizens from accessing some of the contents on sourceforge. I deeply regret the outrageous action initiated, even though I fully understand the reasoning behind it.

This littre tracker has a special player which only needs around 65 CPU cycles (1 rasterline) to produce music on the Commodore 64's SID sound-chip. Due to the rastertime-limit there are some restrictions but with clever solutions you can tweak good sound out of it... check out the included example-tunes to learn how... NOTE: I left SourceForge for reasons not ethical to mention here. You can find me and my further work at these locations: http://hermit.sidrip.com http://csdb.dk/scener/?...

Library which allows developper to access the hardware features of GP2X (personal entertainment player created by a Korean company: GPH). Software emulation is provided on PC through SDL.

This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.

Yet Another DLX based Architecture System On a Chip (YADASOC) is a RTL Verilog implenetation of a DLX based CPU and subsystems.