Search Results for "verilog code ofdm" - Page 3

gscc stands for GNU SystemC Compiler Collection, witch is a set of tools to manipulate systemc code ( systemc is a hardware description language www.systemc.org ). The most notable tool is called gsc, witch is a systemc to verilog translator.

Veri-indent is a verilog source code Parser,Analyzer and Beautifier. (similar to c 'indent' , but more than that). Verilog source can be formatted and Symbol table, list of registers,wires,pli calls in source code can be extracted.

The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed.

RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.

pprint - cross referencing postscript pretty-printer for C/C++/Verilog source code

Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.

This project contains the material discussed in my PhD dissertation, entitled "Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems." The source code is available in the SVN repository: https://sourceforge.net/p/xrt/code/6/tree/trunk/ and consists in two folders: 1) /X-RT : A portable multiprocessor scheduling framework supporting scheduling periodic real-time tasks according to the G-EDF (Global Earliest Deadline First) scheduling platform...

This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.

This program converts assembly code to verilog implementation