Search Results for "netlist" - Page 2
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Showing 32 open source projects for "netlist"
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Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.
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A UNIX/X11 circuit drawing application with schematic capture. Features user-definable parts libraries and fully hierarchical SPICE netlist generation.
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Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.
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The ISCAS-VHDL-CIR netlist converting tool. The NLK software is a part of a project named "Softwarepraktikum" of the 'BTU Cottbus' university in germany. The NLK is written in C++ as a Linux console application.
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The purpose of this tool is creation of tcl/tk - based environment for convenient Verilog netlist viewing and editing. This tool will allow development of TCL scripts in order to make structural changes in verilog netlist.
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This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
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Provide a set of circuit design wizards to assist in electronic design. The wizards should initially provide a graphical output of the circuit, the values of components and a SPICE netlist for simulation. This project is in the early stages.
